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-rw-r--r--MAINTAINERS10
-rw-r--r--Makefile24
-rw-r--r--README24
-rw-r--r--arch/arc/Makefile8
-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/Makefile29
-rw-r--r--arch/arm/cpu/armv7/Makefile1
-rw-r--r--arch/arm/cpu/armv7/exynos/Kconfig7
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c19
-rw-r--r--arch/arm/cpu/armv7/exynos/clock_init_exynos5.c2
-rw-r--r--arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c29
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c2
-rw-r--r--arch/arm/cpu/armv7/exynos/power.c27
-rw-r--r--arch/arm/cpu/armv7/exynos/spl_boot.c10
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c17
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c9
-rw-r--r--arch/arm/cpu/armv7/omap5/Kconfig4
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c12
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c3
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c2
-rw-r--r--arch/arm/cpu/armv7/stv0991/Makefile9
-rw-r--r--arch/arm/cpu/armv7/stv0991/clock.c41
-rw-r--r--arch/arm/cpu/armv7/stv0991/lowlevel.S12
-rw-r--r--arch/arm/cpu/armv7/stv0991/pinmux.c62
-rw-r--r--arch/arm/cpu/armv7/stv0991/reset.c26
-rw-r--r--arch/arm/cpu/armv7/stv0991/timer.c114
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun4i.c27
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun6i.c29
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_sun4i.c4
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_sun6i.c3
-rw-r--r--arch/arm/cpu/armv7/uniphier/Kconfig31
-rw-r--r--arch/arm/cpu/armv7/uniphier/Makefile1
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_early_init_r.c15
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_late_init.c38
-rw-r--r--arch/arm/cpu/armv7/uniphier/init_page_table.c7
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile2
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile2
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c20
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile2
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c1
-rw-r--r--arch/arm/cpu/armv7/uniphier/support_card.c125
-rw-r--r--arch/arm/dts/Makefile8
-rw-r--r--arch/arm/dts/exynos4412-odroid.dts11
-rw-r--r--arch/arm/dts/exynos5250-snow.dts4
-rw-r--r--arch/arm/dts/exynos5800-peach-pi.dts157
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4-ref.dts61
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4.dtsi120
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4-ref.dts63
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4.dtsi140
-rw-r--r--arch/arm/dts/uniphier-ph1-sld3-ref.dts60
-rw-r--r--arch/arm/dts/uniphier-ph1-sld3.dtsi125
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8-ref.dts61
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8.dtsi120
-rw-r--r--arch/arm/include/asm/arch-am33xx/spl.h1
-rw-r--r--arch/arm/include/asm/arch-bcm2835/mbox.h33
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h10
-rw-r--r--arch/arm/include/asm/arch-exynos/dmc.h1
-rw-r--r--arch/arm/include/asm/arch-exynos/ehci.h13
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h4
-rw-r--r--arch/arm/include/asm/arch-exynos/power.h7
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h8
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h5
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h12
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h4
-rw-r--r--arch/arm/include/asm/arch-rmobile/mmc.h14
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7790.h13
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7791.h13
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7793.h14
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7794.h13
-rw-r--r--arch/arm/include/asm/arch-rmobile/rcar-base.h39
-rw-r--r--arch/arm/include/asm/arch-rmobile/rcar-mstp.h109
-rw-r--r--arch/arm/include/asm/arch-s3c24x0/s3c2410.h4
-rw-r--r--arch/arm/include/asm/arch-s3c24x0/s3c2440.h4
-rw-r--r--arch/arm/include/asm/arch-s3c24x0/s3c24x0.h31
-rw-r--r--arch/arm/include/asm/arch-stv0991/gpio.h22
-rw-r--r--arch/arm/include/asm/arch-stv0991/hardware.h73
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_cgu.h116
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_creg.h95
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_defs.h16
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_gpt.h43
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_periph.h44
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_wdru.h28
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h47
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h67
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/display.h187
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h1
-rw-r--r--arch/arm/include/asm/arch-uniphier/board.h7
-rw-r--r--arch/arm/include/asm/arch-uniphier/gpio.h6
-rw-r--r--arch/arm/include/asm/global_data.h8
-rw-r--r--arch/arm/include/asm/omap_common.h3
-rw-r--r--arch/avr32/Makefile8
-rw-r--r--arch/blackfin/Makefile8
-rw-r--r--arch/blackfin/include/asm/io.h3
-rw-r--r--arch/m68k/Makefile8
-rw-r--r--arch/microblaze/Makefile8
-rw-r--r--arch/mips/Makefile8
-rw-r--r--arch/mips/cpu/mips32/start.S7
-rw-r--r--arch/mips/cpu/mips64/start.S7
-rw-r--r--arch/mips/include/asm/unaligned.h2
-rw-r--r--arch/mips/lib/Makefile3
-rw-r--r--arch/mips/lib/board.c320
-rw-r--r--arch/mips/lib/bootm.c23
-rw-r--r--arch/nds32/Makefile8
-rw-r--r--arch/nios2/Makefile8
-rw-r--r--arch/nios2/cpu/fdt.c8
-rw-r--r--arch/openrisc/Makefile8
-rw-r--r--arch/powerpc/Makefile11
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig10
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile4
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_serdes.c19
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c16
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/p2041_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/p3041_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/p4080_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5020_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5040_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c35
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1024_ids.c82
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1024_serdes.c52
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1040_ids.c30
-rw-r--r--arch/powerpc/cpu/mpc85xx/t2080_ids.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/t2080_serdes.c1
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc8xx/Kconfig4
-rw-r--r--arch/powerpc/cpu/mpc8xx/cpu_init.c3
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c4
-rw-r--r--arch/powerpc/cpu/ppc4xx/fdt.c7
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h48
-rw-r--r--arch/powerpc/include/asm/fsl_errata.h51
-rw-r--r--arch/powerpc/include/asm/fsl_liodn.h4
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h4
-rw-r--r--arch/powerpc/include/asm/fsl_serdes.h16
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h22
-rw-r--r--arch/powerpc/include/asm/processor.h4
-rw-r--r--arch/powerpc/lib/board.c12
-rw-r--r--arch/sandbox/Makefile8
-rw-r--r--arch/sandbox/cpu/os.c1
-rw-r--r--arch/sandbox/cpu/start.c3
-rw-r--r--arch/sh/Makefile8
-rw-r--r--arch/sh/include/asm/unaligned.h2
-rw-r--r--arch/sparc/Makefile8
-rw-r--r--arch/x86/Kconfig149
-rw-r--r--arch/x86/Makefile12
-rw-r--r--arch/x86/cpu/Makefile4
-rw-r--r--arch/x86/cpu/config.mk5
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c11
-rw-r--r--arch/x86/cpu/coreboot/ipchecksum.c3
-rw-r--r--arch/x86/cpu/cpu.c17
-rw-r--r--arch/x86/cpu/interrupts.c54
-rw-r--r--arch/x86/cpu/ivybridge/Makefile8
-rw-r--r--arch/x86/cpu/ivybridge/bd82x6x.c146
-rw-r--r--arch/x86/cpu/ivybridge/gma.c756
-rw-r--r--arch/x86/cpu/ivybridge/gma.h156
-rw-r--r--arch/x86/cpu/ivybridge/lpc.c523
-rw-r--r--arch/x86/cpu/ivybridge/model_206ax.c514
-rw-r--r--arch/x86/cpu/ivybridge/northbridge.c188
-rw-r--r--arch/x86/cpu/ivybridge/pch.c123
-rw-r--r--arch/x86/cpu/ivybridge/pci.c40
-rw-r--r--arch/x86/cpu/ivybridge/sata.c225
-rw-r--r--arch/x86/cpu/ivybridge/usb_ehci.c29
-rw-r--r--arch/x86/cpu/ivybridge/usb_xhci.c32
-rw-r--r--arch/x86/cpu/lapic.c57
-rw-r--r--arch/x86/cpu/pci.c12
-rw-r--r--arch/x86/cpu/turbo.c98
-rw-r--r--arch/x86/cpu/u-boot.lds18
-rw-r--r--arch/x86/dts/link.dts54
-rw-r--r--arch/x86/include/asm/acpi.h24
-rw-r--r--arch/x86/include/asm/arch-coreboot/sysinfo.h2
-rw-r--r--arch/x86/include/asm/arch-coreboot/tables.h2
-rw-r--r--arch/x86/include/asm/arch-ivybridge/bd82x6x.h23
-rw-r--r--arch/x86/include/asm/arch-ivybridge/model_206ax.h4
-rw-r--r--arch/x86/include/asm/arch-ivybridge/pch.h120
-rw-r--r--arch/x86/include/asm/arch-ivybridge/sandybridge.h13
-rw-r--r--arch/x86/include/asm/i8259.h2
-rw-r--r--arch/x86/include/asm/interrupt.h11
-rw-r--r--arch/x86/include/asm/io.h2
-rw-r--r--arch/x86/include/asm/ioapic.h38
-rw-r--r--arch/x86/include/asm/lapic.h124
-rw-r--r--arch/x86/include/asm/msr-index.h2
-rw-r--r--arch/x86/include/asm/msr.h11
-rw-r--r--arch/x86/include/asm/pci.h3
-rw-r--r--arch/x86/include/asm/post.h1
-rw-r--r--arch/x86/include/asm/processor.h31
-rw-r--r--arch/x86/include/asm/speedstep.h89
-rw-r--r--arch/x86/include/asm/turbo.h31
-rw-r--r--arch/x86/include/asm/u-boot-x86.h2
-rw-r--r--arch/x86/lib/Makefile3
-rw-r--r--arch/x86/lib/bios.c347
-rw-r--r--arch/x86/lib/bios.h98
-rw-r--r--arch/x86/lib/bios_asm.S281
-rw-r--r--arch/x86/lib/bios_interrupts.c217
-rw-r--r--arch/x86/lib/pcat_interrupts.c42
-rw-r--r--arch/x86/lib/relocate.c3
-rw-r--r--arch/x86/lib/string.c4
-rw-r--r--board/a3m071/a3m071.c4
-rw-r--r--board/a4m072/a4m072.c5
-rw-r--r--board/amcc/canyonlands/canyonlands.c6
-rw-r--r--board/amcc/sequoia/sequoia.c19
-rw-r--r--board/cm5200/cm5200.c4
-rw-r--r--board/comelit/dig297/dig297.c5
-rw-r--r--board/compulab/cm_fx6/cm_fx6.c4
-rw-r--r--board/compulab/cm_t35/cm_t35.c7
-rw-r--r--board/compulab/cm_t54/cm_t54.c4
-rw-r--r--board/corscience/tricorder/tricorder.c7
-rw-r--r--board/davedenx/aria/aria.c4
-rw-r--r--board/esd/cpci405/cpci405.c4
-rw-r--r--board/esd/mecp5123/mecp5123.c4
-rw-r--r--board/esd/pmc405de/pmc405de.c4
-rw-r--r--board/esd/pmc440/pmc440.c4
-rw-r--r--board/esd/vme8349/vme8349.c4
-rw-r--r--board/freescale/b4860qds/b4860qds.c99
-rw-r--r--board/freescale/b4860qds/eth_b4860qds.c127
-rw-r--r--board/freescale/b4860qds/law.c3
-rw-r--r--board/freescale/bsc9131rdb/bsc9131rdb.c4
-rw-r--r--board/freescale/bsc9132qds/bsc9132qds.c4
-rw-r--r--board/freescale/c29xpcie/c29xpcie.c4
-rw-r--r--board/freescale/common/Makefile1
-rw-r--r--board/freescale/common/cds_pci_ft.c5
-rw-r--r--board/freescale/common/sys_eeprom.c4
-rw-r--r--board/freescale/common/vid.c491
-rw-r--r--board/freescale/common/vid.h20
-rw-r--r--board/freescale/common/vsc3316_3308.c108
-rw-r--r--board/freescale/common/vsc3316_3308.h4
-rw-r--r--board/freescale/corenet_ds/corenet_ds.c4
-rw-r--r--board/freescale/corenet_ds/eth_hydra.c7
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c22
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c27
-rw-r--r--board/freescale/ls2085a/ls2085a.c4
-rw-r--r--board/freescale/mpc5121ads/mpc5121ads.c4
-rw-r--r--board/freescale/mpc7448hpc2/mpc7448hpc2.c5
-rw-r--r--board/freescale/mpc8308rdb/mpc8308rdb.c4
-rw-r--r--board/freescale/mpc8313erdb/mpc8313erdb.c4
-rw-r--r--board/freescale/mpc8315erdb/mpc8315erdb.c4
-rw-r--r--board/freescale/mpc8323erdb/mpc8323erdb.c4
-rw-r--r--board/freescale/mpc832xemds/mpc832xemds.c4
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c4
-rw-r--r--board/freescale/mpc8349itx/mpc8349itx.c4
-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c4
-rw-r--r--board/freescale/mpc8360erdk/mpc8360erdk.c4
-rw-r--r--board/freescale/mpc837xemds/mpc837xemds.c4
-rw-r--r--board/freescale/mpc837xerdb/mpc837xerdb.c4
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c3
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c5
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c4
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c5
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c4
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c4
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c4
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c5
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c12
-rw-r--r--board/freescale/p1010rdb/p1010rdb.c4
-rw-r--r--board/freescale/p1022ds/p1022ds.c4
-rw-r--r--board/freescale/p1023rdb/p1023rdb.c4
-rw-r--r--board/freescale/p1_p2_rdb/p1_p2_rdb.c40
-rw-r--r--board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c35
-rw-r--r--board/freescale/p1_twr/p1_twr.c4
-rw-r--r--board/freescale/p2020come/p2020come.c4
-rw-r--r--board/freescale/p2020ds/p2020ds.c4
-rw-r--r--board/freescale/p2041rdb/p2041rdb.c4
-rw-r--r--board/freescale/qemu-ppce500/qemu-ppce500.c4
-rw-r--r--board/freescale/t102xqds/Kconfig12
-rw-r--r--board/freescale/t102xqds/MAINTAINERS12
-rw-r--r--board/freescale/t102xqds/Makefile17
-rw-r--r--board/freescale/t102xqds/README328
-rw-r--r--board/freescale/t102xqds/ddr.c170
-rw-r--r--board/freescale/t102xqds/eth_t102xqds.c442
-rw-r--r--board/freescale/t102xqds/law.c32
-rw-r--r--board/freescale/t102xqds/pci.c23
-rw-r--r--board/freescale/t102xqds/spl.c151
-rw-r--r--board/freescale/t102xqds/t1024_pbi.cfg26
-rw-r--r--board/freescale/t102xqds/t1024_rcw.cfg10
-rw-r--r--board/freescale/t102xqds/t102xqds.c408
-rw-r--r--board/freescale/t102xqds/t102xqds.h14
-rw-r--r--board/freescale/t102xqds/t102xqds_qixis.h64
-rw-r--r--board/freescale/t102xqds/tlb.c117
-rw-r--r--board/freescale/t102xrdb/Kconfig12
-rw-r--r--board/freescale/t102xrdb/MAINTAINERS10
-rw-r--r--board/freescale/t102xrdb/Makefile17
-rw-r--r--board/freescale/t102xrdb/README258
-rw-r--r--board/freescale/t102xrdb/cpld.c103
-rw-r--r--board/freescale/t102xrdb/cpld.h45
-rw-r--r--board/freescale/t102xrdb/ddr.c154
-rw-r--r--board/freescale/t102xrdb/eth_t102xrdb.c100
-rw-r--r--board/freescale/t102xrdb/law.c32
-rw-r--r--board/freescale/t102xrdb/pci.c23
-rw-r--r--board/freescale/t102xrdb/spl.c107
-rw-r--r--board/freescale/t102xrdb/t1024_pbi.cfg26
-rw-r--r--board/freescale/t102xrdb/t1024_rcw.cfg8
-rw-r--r--board/freescale/t102xrdb/t102xrdb.c144
-rw-r--r--board/freescale/t102xrdb/t102xrdb.h13
-rw-r--r--board/freescale/t102xrdb/tlb.c117
-rw-r--r--board/freescale/t1040qds/t1040qds.c4
-rw-r--r--board/freescale/t104xrdb/spl.c26
-rw-r--r--board/freescale/t104xrdb/t104xrdb.c4
-rwxr-xr-xboard/freescale/t208xqds/README274
-rw-r--r--board/freescale/t208xqds/ddr.h15
-rw-r--r--board/freescale/t208xqds/eth_t208xqds.c173
-rw-r--r--board/freescale/t208xqds/t2080_rcw.cfg16
-rw-r--r--board/freescale/t208xqds/t208xqds.c17
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650 files changed, 20026 insertions, 3826 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index c8386ab..6041936 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -128,6 +128,12 @@ T: git git://git.denx.de/u-boot-stm.git
F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
+ARM STM STV0991
+M: Vikas Manocha <vikas.manocha@st.com>
+S: Maintained
+F: arch/arm/cpu/armv7/stv0991/
+F: arch/arm/include/asm/arch-stv0991/
+
ARM SUNXI
M: Ian Campbell <ijc@hellion.org.uk>
M: Hans De Goede <hdegoede@redhat.com>
@@ -196,7 +202,8 @@ F: drivers/mtd/cfi_flash.c
F: drivers/mtd/jedec_flash.c
COLDFIRE
-M: Jason Jin <jason.jin@freescale.com>
+M: Huan Wang <alison.wang@freescale.com>
+M: Angelo Dureghello <angelo@sysam.it>
S: Maintained
T: git git://git.denx.de/u-boot-coldfire.git
F: arch/m68k/
@@ -390,6 +397,7 @@ T: git git://git.denx.de/u-boot-tq-group.git
UBI
M: Kyungmin Park <kmpark@infradead.org>
+M: Heiko Schocher <hs@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-ubi.git
F: drivers/mtd/ubi/
diff --git a/Makefile b/Makefile
index 79cb45c..2308828 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
VERSION = 2015
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -503,6 +503,7 @@ autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \
-path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
ifneq ($(autoconf_is_current),)
include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
endif
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
@@ -601,17 +602,11 @@ c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
-head-y := $(CPUDIR)/start.o
-head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
-head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
-
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
libs-y += lib/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-libs-y += $(CPUDIR)/
libs-$(CONFIG_OF_EMBED) += dts/
-libs-y += arch/$(ARCH)/lib/
libs-y += fs/
libs-y += net/
libs-y += disk/
@@ -645,23 +640,11 @@ libs-y += drivers/usb/musb-new/
libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
libs-y += common/
-libs-y += lib/libfdt/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
libs-y += test/dm/
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-libs-y += arch/$(ARCH)/imx-common/
-endif
-
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
-libs-y += arch/$(ARCH)/mvebu-common/
-endif
-
-libs-$(CONFIG_ARM) += arch/arm/cpu/
-libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-y := $(sort $(libs-y))
@@ -980,6 +963,9 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
$(objtree)/tools/ifdtool -w \
$(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \
+ u-boot.tmp
mv u-boot.tmp $@
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
diff --git a/README b/README
index e7cd1bc..4ca04d0 100644
--- a/README
+++ b/README
@@ -409,6 +409,10 @@ The following options need to be configured:
Enables a workaround for IFC erratum A003399. It is only
requred during NOR boot.
+ CONFIG_A008044_WORKAROUND
+ Enables a workaround for T1040/T1042 erratum A008044. It is only
+ requred during NAND boot and valid for Rev 1.0 SoC revision
+
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
@@ -783,6 +787,13 @@ The following options need to be configured:
Board code has addition modification that it wants to make
to the flat device tree before handing it off to the kernel
+ CONFIG_OF_SYSTEM_SETUP
+
+ Other code has addition modification that it wants to make
+ to the flat device tree before handing it off to the kernel.
+ This causes ft_system_setup() to be called before booting
+ the kernel.
+
CONFIG_OF_BOOT_CPU
This define fills in the correct boot CPU in the boot
@@ -3510,7 +3521,7 @@ FIT uImage format:
to 128 or 256, although it does not have to be power of 2).
default: 4096
-
+
CONFIG_MTD_UBI_BEB_LIMIT
This option specifies the maximum bad physical eraseblocks UBI
expects on the MTD device (per 1024 eraseblocks). If the
@@ -3650,10 +3661,13 @@ FIT uImage format:
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
- Address, size and partition on the MMC to load U-Boot from
+ Address and partition on the MMC to load U-Boot from
when the MMC is being used in raw mode.
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in raw mode
+
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
Sector to load kernel uImage from when MMC is being
used in raw mode (for Falcon mode)
@@ -3664,6 +3678,10 @@ FIT uImage format:
parameters from when MMC is being used in raw mode
(for falcon mode)
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in fs mode
+
CONFIG_SPL_FAT_SUPPORT
Support for fs/fat/libfat.o in SPL binary
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
new file mode 100644
index 0000000..de25cc9
--- /dev/null
+++ b/arch/arc/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/arc/cpu/$(CPU)/start.o
+
+libs-y += arch/arc/cpu/$(CPU)/
+libs-y += arch/arc/lib/
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index be703af..c0b68cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -341,6 +341,10 @@ config TARGET_SPEAR600
bool "Support spear600"
select CPU_ARM926EJS
+config TARGET_STV0991
+ bool "Support stv0991"
+ select CPU_V7
+
config TARGET_X600
bool "Support x600"
select CPU_ARM926EJS
@@ -396,8 +400,8 @@ config TARGET_MX35PDK
bool "Support mx35pdk"
select CPU_ARM1136
-config TARGET_RPI_B
- bool "Support rpi_b"
+config TARGET_RPI
+ bool "Support rpi"
select CPU_ARM1176
config TARGET_TNETV107X_EVM
@@ -794,6 +798,7 @@ config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
select CPU_V7
select SUPPORT_SPL
+ select OF_CONTROL if !SPL_BUILD
endchoice
@@ -931,7 +936,7 @@ source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
-source "board/raspberrypi/rpi_b/Kconfig"
+source "board/raspberrypi/rpi/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
@@ -953,6 +958,7 @@ source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
+source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
new file mode 100644
index 0000000..ebb7dc3
--- /dev/null
+++ b/arch/arm/Makefile
@@ -0,0 +1,29 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/arm/cpu/$(CPU)/start.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
+libs-y += arch/arm/cpu/$(CPU)/
+libs-y += arch/arm/cpu/
+libs-y += arch/arm/lib/
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+libs-y += arch/arm/imx-common/
+endif
+else
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+libs-y += arch/arm/imx-common/
+endif
+endif
+
+ifneq (,$(filter $(SOC), armada-xp kirkwood))
+libs-y += arch/arm/mvebu-common/
+endif
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index e419716..409e6f5 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(CONFIG_SOCFPGA) += socfpga/
+obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_U8500) += u8500/
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index e9a102c..f3eadb4 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -46,11 +46,16 @@ config TARGET_SMDK5420
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
-config TARGET_PEACH_PIT
+config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
+config TARGET_PEACH_PIT
+ bool "Peach Pit board"
+ select SUPPORT_SPL
+ select OF_CONTROL if !SPL_BUILD
+
endchoice
config SYS_SOC
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index c0c95fb..8fab135 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
- else if (proid_is_exynos5250() || proid_is_exynos5420())
+ else if (proid_is_exynos5250() || proid_is_exynos5420()
+ || proid_is_exynos5800())
div = PLL_DIV_65536;
else
return 0;
@@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void)
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
@@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
@@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
} else {
@@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
} else {
@@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
@@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_lcd_clk();
else
return exynos5_get_lcd_clk();
@@ -1682,7 +1683,7 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420())
+ else if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_lcd_clk();
}
}
@@ -1696,7 +1697,7 @@ void set_mipi_clk(void)
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
} else {
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b6a9bc1..0aff3d0 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
void system_clock_init(void)
{
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_system_clock_init();
else
exynos5250_system_clock_init();
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index b86dd2d..7c0b12a 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
+ if (CONFIG_NR_DRAM_BANKS > 4) {
+ /* Need both controllers. */
+ mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+ mem->chips_per_channel = 2;
+ mem->chips_to_configure = 2;
+ } else {
+ /* 2GB requires a single controller */
+ mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+ }
+
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);
@@ -832,6 +842,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+ /*
+ * As per Exynos5800 UM ver 0.00 section 17.13.2.1
+ * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
+ * support the PHY initiated update. And it is recommended to set
+ * this field to 1'b1 during initialization
+ *
+ * When we apply PHY-initiated mode, DLL lock value is determined
+ * once at DMC init time and not updated later when we change the MIF
+ * voltage based on ASV group in kernel. Applying MC-initiated mode
+ * makes sure that DLL tracing is ON so that silicon is able to
+ * compensate the voltage variation.
+ */
+ val = readl(&drex0->concontrol);
+ val |= CONCONTROL_UPDATE_MODE;
+ writel(val , &drex0->concontrol);
+ val = readl(&drex1->concontrol);
+ val |= CONCONTROL_UPDATE_MODE;
+ writel(val , &drex1->concontrol);
+
return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 3d95dc3..94d0297 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -837,7 +837,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_pinmux_config(peripheral, flags);
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index e1ab3d6..1520d64 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -53,10 +53,37 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
}
}
+void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
+{
+ struct exynos4412_power *power =
+ (struct exynos4412_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBHOST_PHY */
+ setbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&power->hsic1_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&power->hsic2_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBHOST_PHY */
+ clrbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ clrbits_le32(&power->hsic1_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ clrbits_le32(&power->hsic2_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
void set_usbhost_phy_ctrl(unsigned int enable)
{
if (cpu_is_exynos5())
exynos5_set_usbhost_phy_ctrl(enable);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_set_usbhost_phy_ctrl(enable);
}
static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index ae3ad01..bc237c9 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -195,10 +195,16 @@ void copy_uboot_to_ram(void)
void (*end_bootop_from_emmc)(void);
#endif
#ifdef CONFIG_USB_BOOTING
- u32 (*usb_copy)(void);
int is_cr_z_set;
unsigned int sec_boot_check;
+ /*
+ * Note that older hardware (before Exynos5800) does not expect any
+ * arguments, but it does not hurt to pass them, so a common function
+ * prototype is used.
+ */
+ u32 (*usb_copy)(u32 num_of_block, u32 *dst);
+
/* Read iRAM location to check for secondary USB boot mode */
sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
@@ -240,7 +246,7 @@ void copy_uboot_to_ram(void)
*/
is_cr_z_set = config_branch_prediction(0);
usb_copy = get_irom_func(USB_INDEX);
- usb_copy();
+ usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
config_branch_prediction(is_cr_z_set);
break;
#endif
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index fb535eb..cb18908 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -33,8 +33,19 @@ void save_omap_boot_params(void)
* used. But it not correct to assume that romcode structure
* encoding would be same as u-boot. So use the defined offsets.
*/
- gd->arch.omap_boot_params.omap_bootdevice = boot_device =
- *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+ boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+#if defined(BOOT_DEVICE_NAND_I2C)
+ /*
+ * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
+ * Otherwise the SPL boot IF can't handle this device correctly.
+ * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
+ * Draco leads to this boot-device passed to SPL from the BootROM.
+ */
+ if (boot_device == BOOT_DEVICE_NAND_I2C)
+ boot_device = BOOT_DEVICE_NAND;
+#endif
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device;
gd->arch.omap_boot_params.ch_flags =
*((u8 *)(rom_params + CH_FLAGS_OFFSET));
@@ -57,7 +68,7 @@ void save_omap_boot_params(void)
}
}
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/*
* We get different values for QSPI_1 and QSPI_4 being used, but
* don't actually care about this difference. Rather than
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index c8e9bc8..e601ba1 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1226,13 +1226,14 @@ void dmm_init(u32 base)
emif1_enabled = 1;
emif2_enabled = 1;
break;
- } else if (valid == 1) {
+ }
+
+ if (valid == 1)
emif1_enabled = 1;
- } else if (valid == 2) {
+
+ if (valid == 2)
emif2_enabled = 1;
- }
}
-
}
static void do_bug0039_workaround(u32 base)
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 129982c..aca862d 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM
config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
+config TARGET_BEAGLE_X15
+ bool "BeagleBoard X15"
+
endchoice
config SYS_SOC
@@ -20,5 +23,6 @@ config SYS_SOC
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
+source "board/ti/beagle_x15/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 0257383..95f1686 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,31 +365,31 @@ struct vcores_data dra752_volts = {
.mpu.value = VDD_MPU_DRA752,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA752,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.gpu.value = VDD_GPU_DRA752,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.core.value = VDD_CORE_DRA752,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value = VDD_IVA_DRA752,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
};
@@ -593,7 +593,7 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
-void hw_data_init(void)
+void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index ff08ef4..0745d42 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134,
+ .control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
@@ -800,6 +801,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
+ .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */
@@ -906,6 +908,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
+ .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 065199b..7d8cec0 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -513,7 +513,7 @@ const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
const u32 **regs,
u32 *size)
{
diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile
new file mode 100644
index 0000000..95641d3
--- /dev/null
+++ b/arch/arm/cpu/armv7/stv0991/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := timer.o clock.o pinmux.o reset.o
+obj-y += lowlevel.o
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c
new file mode 100644
index 0000000..70b8a8d
--- /dev/null
+++ b/arch/arm/cpu/armv7/stv0991/clock.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/stv0991_cgu.h>
+#include<asm/arch/stv0991_periph.h>
+
+static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
+ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
+
+void enable_pll1(void)
+{
+ /* pll1 already configured for 1000Mhz, just need to enable it */
+ writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
+ &stv0991_cgu_regs->pll1_ctrl);
+}
+
+void clock_setup(int peripheral)
+{
+ switch (peripheral) {
+ case UART_CLOCK_CFG:
+ writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
+ break;
+ case ETH_CLOCK_CFG:
+ enable_pll1();
+ writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
+
+ /* Clock selection for ethernet tx_clk & rx_clk*/
+ writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
+ | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
+
+ break;
+ default:
+ break;
+ }
+}
diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S
new file mode 100644
index 0000000..6dafba3
--- /dev/null
+++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 stmicroelectronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ mov pc, lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c
new file mode 100644
index 0000000..1d086a2
--- /dev/null
+++ b/arch/arm/cpu/armv7/stv0991/pinmux.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/stv0991_creg.h>
+#include <asm/arch/stv0991_periph.h>
+#include <asm/arch/hardware.h>
+
+static struct stv0991_creg *const stv0991_creg = \
+ (struct stv0991_creg *)CREG_BASE_ADDR;
+
+int stv0991_pinmux_config(int peripheral)
+{
+ switch (peripheral) {
+ case UART_GPIOC_30_31:
+ /* SSDA/SSCL pad muxing to UART Rx/Dx */
+ writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
+ CFG_GPIOC_31_UART_RX,
+ &stv0991_creg->mux12);
+ writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
+ CFG_GPIOC_30_UART_TX,
+ &stv0991_creg->mux12);
+ /* SSDA/SSCL pad config to push pull*/
+ writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
+ CFG_GPIOC_31_MODE_PP,
+ &stv0991_creg->cfg_pad6);
+ writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
+ CFG_GPIOC_30_MODE_HIGH,
+ &stv0991_creg->cfg_pad6);
+ break;
+ case UART_GPIOB_16_17:
+ /* ethernet rx_6/7 to UART Rx/Dx */
+ writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
+ CFG_GPIOB_17_UART_RX,
+ &stv0991_creg->mux7);
+ writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
+ CFG_GPIOB_16_UART_TX,
+ &stv0991_creg->mux7);
+ break;
+ case ETH_GPIOB_10_31_C_0_4:
+ writel(readl(&stv0991_creg->mux6) & 0x000000FF,
+ &stv0991_creg->mux6);
+ writel(0x00000000, &stv0991_creg->mux7);
+ writel(0x00000000, &stv0991_creg->mux8);
+ writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
+ &stv0991_creg->mux9);
+ /* Ethernet Voltage configuration to 1.8V*/
+ writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
+ ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
+ writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
+ ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c
new file mode 100644
index 0000000..3384b32
--- /dev/null
+++ b/arch/arm/cpu/armv7/stv0991/reset.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stv0991_wdru.h>
+void reset_cpu(ulong ignored)
+{
+ puts("System is going to reboot ...\n");
+ /*
+ * This 1 second delay will allow the above message
+ * to be printed before reset
+ */
+ udelay((1000 * 1000));
+
+ /* Setting bit 1 of the WDRU unit will reset the SoC */
+ writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
+
+ /* system will restart */
+ while (1)
+ ;
+}
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
new file mode 100644
index 0000000..8654b8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/stv0991/timer.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-stv0991/hardware.h>
+#include <asm/arch-stv0991/stv0991_cgu.h>
+#include <asm/arch-stv0991/stv0991_gpt.h>
+
+static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
+ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
+
+#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
+#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init(void)
+{
+ /* Timer1 clock configuration */
+ writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
+ writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
+ TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
+
+ /* Stop the timer */
+ writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
+ writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
+ /* Configure timer for auto-reload */
+ writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
+ &gpt1_regs_ptr->cr1);
+
+ /* load value for free running */
+ writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
+
+ /* start timer */
+ writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
+ &gpt1_regs_ptr->cr1);
+
+ /* Reset the timer */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer_masked();
+ ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
+ ulong rndoff;
+
+ rndoff = (usec % 10) ? 1 : 0;
+
+ /* tenudelcnt timer tick gives 10 microsecconds delay */
+ tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+ while ((ulong) (get_timer_masked() - start) < tmo)
+ ;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (now >= lastdec) {
+ /* normal mode */
+ timestamp += now - lastdec;
+ } else {
+ /* we have an overflow ... */
+ timestamp += now + GPT_FREE_RUNNING - lastdec;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+ return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_STV0991_HZ;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index a0e49d1..49f4032 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -180,6 +180,21 @@ void clock_set_pll1(unsigned int hz)
}
#endif
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 3000000 * m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
+}
+
unsigned int clock_get_pll5p(void)
{
struct sunxi_ccm_reg *const ccm =
@@ -200,3 +215,15 @@ unsigned int clock_get_pll6(void)
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll5p();
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
+ CCM_DE_CTRL_M(div), clk_cfg);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 16ab6f3..8e949c6 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -127,6 +127,23 @@ void clock_set_pll1(unsigned int clk)
}
#endif
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 24000000 * n / m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
+ &ccm->pll3_cfg);
+}
+
void clock_set_pll5(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -151,3 +168,15 @@ unsigned int clock_get_pll6(void)
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll6() * 2;
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
+ clk_cfg);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
index dc9fdb9..ec8aaa7 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
@@ -428,9 +428,9 @@ static void dramc_clock_output_en(u32 on)
#ifdef CONFIG_MACH_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
- setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
else
- clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
#endif
}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
index 10a6241..699173c 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -142,9 +142,6 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
&mctl_phy->ptr0);
- /* Unknown magic performed by boot0 */
- if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2)
- setbits_le32(&mctl_phy->ptr0, 1 << 18);
writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 36b7f11..9760299 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -5,15 +5,17 @@ config SYS_SOC
default "uniphier"
config SYS_CONFIG_NAME
- default "ph1_pro4" if MACH_PH1_PRO4
- default "ph1_ld4" if MACH_PH1_LD4
- default "ph1_sld8" if MACH_PH1_SLD8
+ default "uniphier"
+
+config UNIPHIER_SMP
+ bool
choice
prompt "UniPhier SoC select"
config MACH_PH1_PRO4
bool "PH1-Pro4"
+ select UNIPHIER_SMP
config MACH_PH1_LD4
bool "PH1-LD4"
@@ -23,6 +25,29 @@ config MACH_PH1_SLD8
endchoice
+choice
+ prompt "UniPhier Support Card select"
+ optional
+
+config PFC_MICRO_SUPPORT_CARD
+ bool "Support card with PFC CPLD"
+ help
+ This option provides support for the expansion board with PFC
+ original address mapping.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+config DCC_MICRO_SUPPORT_CARD
+ bool "Support card with DCC CPLD"
+ help
+ This option provides support for the expansion board with DCC-
+ arranged address mapping that is compatible with legacy UniPhier
+ reference boards.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+endchoice
+
config CMD_PINMON
bool "Enable boot mode pins monitor command"
depends on !SPL_BUILD
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index 0f64d25..4a7b8a9 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -11,6 +11,7 @@ obj-y += cache_uniphier.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
new file mode 100644
index 0000000..cb7e04f
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int board_early_init_r(void)
+{
+ uniphier_board_late_init();
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c
index 3730020..0622a1e 100644
--- a/arch/arm/cpu/armv7/uniphier/board_late_init.c
+++ b/arch/arm/cpu/armv7/uniphier/board_late_init.c
@@ -26,42 +26,6 @@ static void nand_denali_wp_disable(void)
#endif
}
-static void nand_denali_fixup(void)
-{
-#if defined(CONFIG_NAND_DENALI) && \
- (defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
- /*
- * The Denali NAND controller on some of UniPhier SoCs does not
- * automatically query the device parameters. For those SoCs,
- * some registers must be set after the device is probed.
- */
- void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- struct mtd_info *mtd;
- struct nand_chip *chip;
-
- if (nand_curr_device < 0 ||
- nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
- /* NAND was not detected. Just return. */
- return;
- }
-
- mtd = &nand_info[nand_curr_device];
- chip = mtd->priv;
-
- writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
- writel(0, denali_reg + DEVICE_WIDTH);
- writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
- writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
- writel(1, denali_reg + DEVICES_CONNECTED);
-
- /*
- * chip->scan_bbt in nand_scan_tail() has been skipped.
- * It should be done in here.
- */
- chip->scan_bbt(mtd);
-#endif
-}
-
int board_late_init(void)
{
puts("MODE: ");
@@ -70,7 +34,6 @@ int board_late_init(void)
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
- nand_denali_fixup();
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot\n");
@@ -80,7 +43,6 @@ int board_late_init(void)
case BOOT_DEVICE_NOR:
printf("NOR Boot\n");
setenv("bootmode", "norboot");
- nand_denali_fixup();
break;
default:
printf("Unsupported Boot Mode\n");
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c
index d273835..a0d10a9 100644
--- a/arch/arm/cpu/armv7/uniphier/init_page_table.c
+++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c
@@ -28,7 +28,12 @@
#define IS_SSC(x) ((IS_SPL_TEXT_AREA(x)) || \
(IS_INIT_STACK_AREA(x)))
#define IS_EXT(x) ((x) < 0x100)
-#define IS_REG(x) (0x500 <= (x) && (x) < 0x700)
+
+/* 0x20000000-0x2fffffff, 0xf0000000-0xffffffff are only used by PH1-sLD3 */
+#define IS_REG(x) (0x200 <= (x) && (x) < 0x300) || \
+ (0x500 <= (x) && (x) < 0x700) || \
+ (0xf00 <= (x))
+
#define IS_DDR(x) (0x800 <= (x) && (x) < 0xf00)
#define MMU_FLAGS(x) (IS_SSC(x)) ? SSC : \
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index fba1cc7..5d682d3 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
index 62f5b01..9d51299 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
@@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 74129bc..fd1c432 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
index 1843d04..31ee2a2 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
@@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
index f113db5..3c82a1a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
@@ -22,16 +22,7 @@ void sbc_init(void)
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
- if (readl(SBBASE0) & 0x1) {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x3effffff: memory bank (31MB)
- * 0x03f00000-0x3fffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- } else {
+ if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
@@ -40,6 +31,15 @@ void sbc_init(void)
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x00000000-0x01ffffff: mask ROM
+ * 0x02000000-0x3effffff: memory bank (31MB)
+ * 0x03f00000-0x3fffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index fba1cc7..5d682d3 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
index 72ec599..ea0691d 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
@@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c
index 40d4940..419012e 100644
--- a/arch/arm/cpu/armv7/uniphier/support_card.c
+++ b/arch/arm/cpu/armv7/uniphier/support_card.c
@@ -83,6 +83,12 @@ static int support_card_show_revision(void)
}
#endif
+int check_support_card(void)
+{
+ printf("SC: Micro Support Card ");
+ return support_card_show_revision();
+}
+
void support_card_init(void)
{
/*
@@ -94,12 +100,6 @@ void support_card_init(void)
support_card_reset_deassert();
}
-int check_support_card(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
#if defined(CONFIG_SMC911X)
#include <netdev.h>
@@ -112,18 +112,14 @@ int board_eth_init(bd_t *bis)
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
+#include <asm/arch/sbc-regs.h>
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
-static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
- CONFIG_SYS_FLASH_BANKS_LIST;
+struct memory_bank {
+ phys_addr_t base;
+ unsigned long size;
+};
-phys_addr_t cfi_flash_bank_addr(int i)
-{
- return flash_banks_list[i];
-}
-#endif
-
-int mem_is_flash(phys_addr_t base)
+static int mem_is_flash(const struct memory_bank *mem)
{
const int loop = 128;
u32 *scratch_addr;
@@ -131,8 +127,9 @@ int mem_is_flash(phys_addr_t base)
int ret = 1;
int i;
- scratch_addr = map_physmem(base + 0x01e00000,
- sizeof(u32) * loop, MAP_NOCACHE);
+ /* just in case, use the tail of the memory bank */
+ scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
+ sizeof(u32) * loop, MAP_NOCACHE);
for (i = 0; i < loop; i++, scratch_addr++) {
saved_value = readl(scratch_addr);
@@ -150,31 +147,79 @@ int mem_is_flash(phys_addr_t base)
return ret;
}
-int board_flash_wp_on(void)
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+ /* {address, size} */
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x02000000, 0x01f00000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x01f00000},
+};
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x04000000, 0x04000000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x04000000},
+ {0x04000000, 0x04000000},
+};
+#endif
+
+static const struct memory_bank
+*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
+
+phys_addr_t cfi_flash_bank_addr(int i)
{
- int i;
- int ret = 1;
+ return flash_banks_list[i]->base;
+}
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- if (mem_is_flash(cfi_flash_bank_addr(i))) {
- /*
- * We found at least one flash.
- * We need to return 0 and call flash_init().
- */
- ret = 0;
- }
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
- else {
- /*
- * We might have a SRAM here.
- * To prevent SRAM data from being destroyed,
- * we set dummy address (SDRAM).
- */
- flash_banks_list[i] = 0x80000000 + 0x10000 * i;
+unsigned long cfi_flash_bank_size(int i)
+{
+ return flash_banks_list[i]->size;
+}
+
+static void detect_num_flash_banks(void)
+{
+ const struct memory_bank *memory_bank, *end;
+
+ cfi_flash_num_flash_banks = 0;
+
+ if (boot_is_swapped()) {
+ memory_bank = memory_banks_boot_swap_on;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
+ } else {
+ memory_bank = memory_banks_boot_swap_off;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
+ }
+
+ for (; memory_bank < end; memory_bank++) {
+ if (cfi_flash_num_flash_banks >=
+ CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+ break;
+
+ if (mem_is_flash(memory_bank)) {
+ flash_banks_list[cfi_flash_num_flash_banks] =
+ memory_bank;
+
+ debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
+ memory_bank->base, memory_bank->size);
+ cfi_flash_num_flash_banks++;
}
-#endif
}
- return ret;
+ debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
+}
+#else /* ONFIG_SYS_NO_FLASH */
+void detect_num_flash_banks(void)
+{
+};
+#endif /* ONFIG_SYS_NO_FLASH */
+
+void support_card_late_init(void)
+{
+ detect_num_flash_banks();
}
-#endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba6dec9..187d58c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
- exynos5420-peach-pit.dtb
+ exynos5420-peach-pit.dtb \
+ exynos5800-peach-pi.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@@ -31,6 +32,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
+dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ uniphier-ph1-sld3-ref.dtb \
+ uniphier-ph1-pro4-ref.dtb \
+ uniphier-ph1-ld4-ref.dtb \
+ uniphier-ph1-sld8-ref.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index 2a1f1dd..c78efec 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -67,4 +67,15 @@
div = <0x3>;
index = <4>;
};
+
+ ehci@12580000 {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12580000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ phy {
+ compatible = "samsung,exynos-usb-phy";
+ reg = <0x125B0000 0x100>;
+ };
+ };
};
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 6fd9275..95af025 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -131,11 +131,11 @@
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
+ samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
+ samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
};
tmu@10060000 {
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
new file mode 100644
index 0000000..8aedf8e
--- /dev/null
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -0,0 +1,157 @@
+/*
+ * SAMSUNG/GOOGLE Peach-Pit board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "exynos54xx.dtsi"
+
+/ {
+ model = "Samsung/Google Peach Pi board based on Exynos5800";
+
+ compatible = "google,pit-rev#", "google,pit",
+ "google,peach", "samsung,exynos5800", "samsung,exynos5";
+
+ config {
+ google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+ hwid = "PIT TEST A-A 7848";
+ lazy-init = <1>;
+ };
+
+ aliases {
+ serial0 = "/serial@12C30000";
+ console = "/serial@12C30000";
+ pmic = "/i2c@12ca0000";
+ };
+
+ dmc {
+ mem-manuf = "samsung";
+ mem-type = "ddr3";
+ clock-frequency = <800000000>;
+ arm-frequency = <1700000000>;
+ };
+
+ tmu@10060000 {
+ samsung,min-temp = <25>;
+ samsung,max-temp = <125>;
+ samsung,start-warning = <95>;
+ samsung,start-tripping = <105>;
+ samsung,hw-tripping = <110>;
+ samsung,efuse-min-value = <40>;
+ samsung,efuse-value = <55>;
+ samsung,efuse-max-value = <100>;
+ samsung,slope = <274761730>;
+ samsung,dc-value = <25>;
+ };
+
+ /* MAX77802 is on i2c bus 4 */
+ i2c@12ca0000 {
+ clock-frequency = <400000>;
+ power-regulator@9 {
+ compatible = "maxim,max77802-pmic";
+ reg = <0x9>;
+ };
+ };
+
+ i2c@12cd0000 { /* i2c7 */
+ clock-frequency = <100000>;
+ soundcodec@20 {
+ reg = <0x20>;
+ compatible = "maxim,max98090-codec";
+ };
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
+ };
+
+ sound@3830000 {
+ samsung,codec-type = "max98090";
+ };
+
+ i2c@12e10000 { /* i2c9 */
+ clock-frequency = <400000>;
+ tpm@20 {
+ compatible = "infineon,slb9645-tpm";
+ reg = <0x20>;
+ };
+ };
+
+ spi@12d30000 { /* spi1 */
+ spi-max-frequency = <50000000>;
+ firmware_storage_spi: flash@0 {
+ reg = <0>;
+
+ /*
+ * A region for the kernel to store a panic event
+ * which the firmware will add to the log.
+ */
+ elog-panic-event-offset = <0x01e00000 0x100000>;
+
+ elog-shrink-size = <0x400>;
+ elog-full-threshold = <0xc00>;
+ };
+ };
+
+ spi@12d40000 { /* spi2 */
+ spi-max-frequency = <4000000>;
+ spi-deactivate-delay = <200>;
+ cros-ec@0 {
+ reg = <0>;
+ compatible = "google,cros-ec";
+ spi-half-duplex;
+ spi-max-timeout-ms = <1100>;
+ spi-frame-header = <0xec>;
+ ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+
+ /*
+ * This describes the flash memory within the EC. Note
+ * that the STM32L flash erases to 0, not 0xff.
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0>;
+ };
+ };
+ };
+
+ xhci@12000000 {
+ samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+ };
+
+ xhci@12400000 {
+ samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+ };
+
+ fimd@14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1920>;
+ samsung,vl-row = <1080>;
+ samsung,vl-width = <1920>;
+ samsung,vl-height = <1080>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <80>;
+ samsung,vl-hbpd = <172>;
+ samsung,vl-hfpd = <60>;
+ samsung,vl-vspw = <10>;
+ samsung,vl-vbpd = <25>;
+ samsung,vl-vfpd = <10>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
new file mode 100644
index 0000000..08bbd03
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -0,0 +1,61 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld4.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-LD4 Reference Board";
+ compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
new file mode 100644
index 0000000..2a3dd73
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-ld4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
new file mode 100644
index 0000000..23add7c
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -0,0 +1,63 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-Pro4 Reference Board";
+ compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
new file mode 100644
index 0000000..49e375e
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -0,0 +1,140 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-pro4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58780000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58781000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58782000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58783000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ /* i2c4 does not exist */
+
+ i2c5: i2c@58785000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58785000 0x80>;
+ clock-frequency = <400000>;
+ status = "ok";
+ };
+
+ i2c6: i2c@58786000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58786000 0x80>;
+ clock-frequency = <400000>;
+ status = "ok";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
new file mode 100644
index 0000000..91b4dbe
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -0,0 +1,60 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld3.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-sLD3 Reference Board";
+ compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
new file mode 100644
index 0000000..f5529d2
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -0,0 +1,125 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-sld3";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ usb3: usb@5a830100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a830100 0x100>;
+ };
+
+ nand: nand@f8000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
new file mode 100644
index 0000000..a8ce049
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -0,0 +1,61 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld8.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-sLD8 Reference Board";
+ compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
new file mode 100644
index 0000000..0ea76e5
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-sld8";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 8543f43..e756418 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -25,6 +25,7 @@
#else
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
+#define BOOT_DEVICE_NAND_I2C 6
#if defined(CONFIG_AM33XX)
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 61f427d..0289ba6 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -119,6 +119,39 @@ struct bcm2835_mbox_tag_hdr {
* };
*/
+#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
+
+/*
+ * 0x2..0xf from:
+ * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733
+ * 0x10, 0x11 from swarren's testing
+ */
+#define BCM2835_BOARD_REV_B_I2C0_2 0x2
+#define BCM2835_BOARD_REV_B_I2C0_3 0x3
+#define BCM2835_BOARD_REV_B_I2C1_4 0x4
+#define BCM2835_BOARD_REV_B_I2C1_5 0x5
+#define BCM2835_BOARD_REV_B_I2C1_6 0x6
+#define BCM2835_BOARD_REV_A_7 0x7
+#define BCM2835_BOARD_REV_A_8 0x8
+#define BCM2835_BOARD_REV_A_9 0x9
+#define BCM2835_BOARD_REV_B_REV2_d 0xd
+#define BCM2835_BOARD_REV_B_REV2_e 0xe
+#define BCM2835_BOARD_REV_B_REV2_f 0xf
+#define BCM2835_BOARD_REV_B_PLUS 0x10
+#define BCM2835_BOARD_REV_CM 0x11
+
+struct bcm2835_mbox_tag_get_board_rev {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ } req;
+ struct {
+ u32 rev;
+ } resp;
+ } body;
+};
+
#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
struct bcm2835_mbox_tag_get_mac_address {
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 78aceef..29674ad 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -227,6 +227,13 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5420 */
s5p_cpu_id = 0x5420;
break;
+ case 0x422:
+ /*
+ * Exynos5800 is a variant of Exynos5420
+ * and has product id 0x5422
+ */
+ s5p_cpu_id = 0x5800;
+ break;
}
}
@@ -255,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
IS_EXYNOS_TYPE(exynos5420, 0x5420)
+IS_EXYNOS_TYPE(exynos5800, 0x5800)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@@ -265,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
- if (proid_is_exynos5420()) \
+ if (proid_is_exynos5420() || proid_is_exynos5800()) \
return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index ec3f9b6..4990a1a 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -450,6 +450,7 @@ enum mem_manuf {
#define CONCONTROL_RD_FETCH_SHIFT 12
#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
#define CONCONTROL_AREF_EN_SHIFT 5
+#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */
#define PRECHCONFIG_TP_CNT_SHIFT 24
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
index d2d70bd..3800fa9 100644
--- a/arch/arm/include/asm/arch-exynos/ehci.h
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -12,6 +12,13 @@
#define CLK_24MHZ 5
+#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
+#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
+#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
+#define RSTCON_HOSTPHY_SWRST (0xf << 3)
+#define RSTCON_SWRST (0x1 << 0)
+
#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
#define HOST_CTRL0_COMMONON_N (1 << 9)
#define HOST_CTRL0_SIDDQ (1 << 6)
@@ -61,6 +68,12 @@ struct exynos_usb_phy {
unsigned int usbotgtune;
};
+struct exynos4412_usb_phy {
+ unsigned int usbphyctrl;
+ unsigned int usbphyclk;
+ unsigned int usbphyrstcon;
+};
+
/* Switch on the VBUS power. */
int board_usb_vbus_init(void);
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 02287de..9699954 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_gpio_data;
else
return exynos5_gpio_data;
@@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return EXYNOS5420_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index e8a98a5..3f97b31 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -210,6 +210,13 @@ struct exynos4_power {
unsigned int gps_alive_option;
};
+struct exynos4412_power {
+ unsigned char res1[0x0704];
+ unsigned int usbhost_phy_control;
+ unsigned int hsic1_phy_control;
+ unsigned int hsic2_phy_control;
+};
+
struct exynos5_power {
unsigned int om_stat;
unsigned char res1[0x18];
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index f2c9687..ba86eea 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -27,7 +27,10 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
@@ -72,6 +75,10 @@
#define DCU_LAYER_MAX_NUM 16
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+
#define CONFIG_SYS_FSL_SRDS_1
#ifdef CONFIG_LS102XA
@@ -80,6 +87,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b0c267c 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -95,8 +95,6 @@ struct ccsr_gur {
u32 sdhcpcr;
};
-#define SCFG_SCFGREVCR_REV 0xffffffff
-#define SCFG_SCFGREVCR_NOREV 0
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
@@ -182,7 +180,7 @@ struct ccsr_scfg {
u32 etsecmcr;
u32 sdhciovserlcr;
u32 resv14[61];
- u32 sparecr;
+ u32 sparecr[8];
};
/* Clocking */
@@ -448,6 +446,7 @@ struct ccsr_ddr {
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
+#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
/* CCI-400 registers */
struct ccsr_cci400 {
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 30d9de2..0dc584b 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -278,11 +278,11 @@
/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
+#define TPS659038_REG_ADDR_SMPS12 0x23
+#define TPS659038_REG_ADDR_SMPS45 0x2B
+#define TPS659038_REG_ADDR_SMPS6 0x2F
+#define TPS659038_REG_ADDR_SMPS7 0x33
+#define TPS659038_REG_ADDR_SMPS8 0x37
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
@@ -314,7 +314,7 @@
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#define V_OSCK 19200000 /* Clock output from T2 */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index b9600cf..e218159 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -27,7 +27,7 @@
#define CONTROL_CORE_ID_CODE 0x4A002204
#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
#else
#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
@@ -163,7 +163,7 @@ struct s32ktimer {
* much larger) and do not, at this time, make use of the additional
* space.
*/
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#else
diff --git a/arch/arm/include/asm/arch-rmobile/mmc.h b/arch/arm/include/asm/arch-rmobile/mmc.h
new file mode 100644
index 0000000..4e0fef1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/mmc.h
@@ -0,0 +1,14 @@
+/*
+ * Renesas SuperH MMCIF driver.
+ *
+ * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _RMOBILE_MMC_H_
+#define _RMOBILE_MMC_H_
+
+int mmcif_mmc_init(void);
+
+#endif /* _RMOBILE_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index de14869..132d58c 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -15,6 +15,19 @@
#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00640801
+#define MSTP1_BITS 0xDB6E9BDF
+#define MSTP2_BITS 0x300DA1FC
+#define MSTP3_BITS 0xF08CF831
+#define MSTP4_BITS 0x80000184
+#define MSTP5_BITS 0x44C00046
+#define MSTP7_BITS 0x07F30718
+#define MSTP8_BITS 0x01F0FF84
+#define MSTP9_BITS 0xF5979FCF
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x00000000
+
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index 26a0bd5..d2cbcd7 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -51,6 +51,19 @@
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_1_DBADJ2 0xE67A00C8
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00640801
+#define MSTP1_BITS 0x9B6C9B5A
+#define MSTP2_BITS 0x100D21FC
+#define MSTP3_BITS 0xF08CD810
+#define MSTP4_BITS 0x800001C4
+#define MSTP5_BITS 0x44C00046
+#define MSTP7_BITS 0x05BFE618
+#define MSTP8_BITS 0x40C0FE85
+#define MSTP9_BITS 0xFF979FFF
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x000001C0
+
#define R8A7791_CUT_ES2X 2
#define IS_R8A7791_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h
index 778812e..1abdeb7 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h
@@ -56,6 +56,20 @@
/*
* R8A7793 I/O Product Information
*/
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00640801
+#define MSTP1_BITS 0x9B6C9B5A
+#define MSTP2_BITS 0x100D21FC
+#define MSTP3_BITS 0xF08CD810
+#define MSTP4_BITS 0x800001C4
+#define MSTP5_BITS 0x44C00046
+#define MSTP7_BITS 0x05BFE618
+#define MSTP8_BITS 0x40C0FE85
+#define MSTP9_BITS 0xFF979FFF
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x000001C0
+
#define R8A7793_CUT_ES2X 2
#define IS_R8A7793_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h
index 66d5a29..d7c9004 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h
@@ -14,4 +14,17 @@
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00440801
+#define MSTP1_BITS 0x936899DA
+#define MSTP2_BITS 0x100D21FC
+#define MSTP3_BITS 0xE084D810
+#define MSTP4_BITS 0x800001C4
+#define MSTP5_BITS 0x40C00044
+#define MSTP7_BITS 0x013FE618
+#define MSTP8_BITS 0x40803C05
+#define MSTP9_BITS 0xFB879FEE
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x000001C0
+
#endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index dbbebcf..23c4bba 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -29,6 +29,45 @@
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
+/* Module stop status register */
+#define MSTPSR0 0xE6150030
+#define MSTPSR1 0xE6150038
+#define MSTPSR2 0xE6150040
+#define MSTPSR3 0xE6150048
+#define MSTPSR4 0xE615004C
+#define MSTPSR5 0xE615003C
+#define MSTPSR7 0xE61501C4
+#define MSTPSR8 0xE61509A0
+#define MSTPSR9 0xE61509A4
+#define MSTPSR10 0xE61509A8
+#define MSTPSR11 0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0 0xE6150110
+#define RMSTPCR1 0xE6150114
+#define RMSTPCR2 0xE6150118
+#define RMSTPCR3 0xE615011C
+#define RMSTPCR4 0xE6150120
+#define RMSTPCR5 0xE6150124
+#define RMSTPCR7 0xE615012C
+#define RMSTPCR8 0xE6150980
+#define RMSTPCR9 0xE6150984
+#define RMSTPCR10 0xE6150988
+#define RMSTPCR11 0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0 0xE6150130
+#define SMSTPCR1 0xE6150134
+#define SMSTPCR2 0xE6150138
+#define SMSTPCR3 0xE615013C
+#define SMSTPCR4 0xE6150140
+#define SMSTPCR5 0xE6150144
+#define SMSTPCR7 0xE615014C
+#define SMSTPCR8 0xE6150990
+#define SMSTPCR9 0xE6150994
+#define SMSTPCR10 0xE6150998
+#define SMSTPCR11 0xE615099C
+
/*
* SH-I2C
* Ch2 and ch3 are different address. These are defined
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
new file mode 100644
index 0000000..9a564f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
+ *
+ * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_RCAR_MSTP_H
+#define __ASM_ARCH_RCAR_MSTP_H
+
+#define mstp_setbits(type, addr, saddr, set) \
+ out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+ out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setclrbits(type, addr, set, clear) \
+ out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+ mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+ mstp_clrbits(le32, addr, saddr, clear)
+#define mstp_setclrbits_le32(addr, set, clear) \
+ mstp_setclrbits(le32, addr, set, clear)
+
+#ifndef CONFIG_SMSTP0_ENA
+#define CONFIG_SMSTP0_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP1_ENA
+#define CONFIG_SMSTP1_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP2_ENA
+#define CONFIG_SMSTP2_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP3_ENA
+#define CONFIG_SMSTP3_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP4_ENA
+#define CONFIG_SMSTP4_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP5_ENA
+#define CONFIG_SMSTP5_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP6_ENA
+#define CONFIG_SMSTP6_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP7_ENA
+#define CONFIG_SMSTP7_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP8_ENA
+#define CONFIG_SMSTP8_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP9_ENA
+#define CONFIG_SMSTP9_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP10_ENA
+#define CONFIG_SMSTP10_ENA 0x00
+#endif
+#ifndef CONFIG_SMSTP11_ENA
+#define CONFIG_SMSTP11_ENA 0x00
+#endif
+
+#ifndef CONFIG_RMSTP0_ENA
+#define CONFIG_RMSTP0_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP1_ENA
+#define CONFIG_RMSTP1_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP2_ENA
+#define CONFIG_RMSTP2_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP3_ENA
+#define CONFIG_RMSTP3_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP4_ENA
+#define CONFIG_RMSTP4_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP5_ENA
+#define CONFIG_RMSTP5_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP6_ENA
+#define CONFIG_RMSTP6_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP7_ENA
+#define CONFIG_RMSTP7_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP8_ENA
+#define CONFIG_RMSTP8_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP9_ENA
+#define CONFIG_RMSTP9_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP10_ENA
+#define CONFIG_RMSTP10_ENA 0x00
+#endif
+#ifndef CONFIG_RMSTP11_ENA
+#define CONFIG_RMSTP11_ENA 0x00
+#endif
+
+struct mstp_ctl {
+ u32 s_addr;
+ u32 s_dis;
+ u32 s_ena;
+ u32 r_addr;
+ u32 r_dis;
+ u32 r_ena;
+};
+
+#endif /* __ASM_ARCH_RCAR_MSTP_H */
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
index ce4186f..8773ce3 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
@@ -83,9 +83,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
-static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
+static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void)
{
- return (struct s3c2410_nand *)S3C2410_NAND_BASE;
+ return (struct s3c24x0_nand *)S3C2410_NAND_BASE;
}
static inline struct s3c24x0_uart
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
index 3f44bdc..7a525f2 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -81,9 +81,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
-static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void)
{
- return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+ return (struct s3c24x0_nand *)S3C2440_NAND_BASE;
}
static inline struct s3c24x0_uart
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index ed9df34..2dae9fc 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -135,34 +135,33 @@ struct s3c24x0_lcd {
};
-#ifdef CONFIG_S3C2410
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
- u32 nfconf;
- u32 nfcmd;
- u32 nfaddr;
- u32 nfdata;
- u32 nfstat;
- u32 nfecc;
-};
-#endif
-#ifdef CONFIG_S3C2440
-/* NAND FLASH (see S3C2440 manual chapter 6) */
-struct s3c2440_nand {
+/* NAND FLASH (see manual chapter 6) */
+struct s3c24x0_nand {
u32 nfconf;
+#ifndef CONFIG_S3C2410
u32 nfcont;
+#endif
u32 nfcmd;
u32 nfaddr;
u32 nfdata;
+#ifndef CONFIG_S3C2410
u32 nfeccd0;
u32 nfeccd1;
u32 nfeccd;
+#endif
u32 nfstat;
+#ifdef CONFIG_S3C2410
+ u32 nfecc;
+#else
u32 nfstat0;
u32 nfstat1;
-};
+ u32 nfmecc0;
+ u32 nfmecc1;
+ u32 nfsecc;
+ u32 nfsblk;
+ u32 nfeblk;
#endif
-
+};
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h
new file mode 100644
index 0000000..9131ded
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/gpio.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_STV0991_GPIO_H
+#define __ASM_ARCH_STV0991_GPIO_H
+
+enum gpio_direction {
+ GPIO_DIRECTION_IN,
+ GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+ u32 data; /* offset 0x0 */
+ u32 reserved[0xff]; /* 0x4--0x3fc */
+ u32 dir; /* offset 0x400 */
+};
+
+#endif /* __ASM_ARCH_STV0991_GPIO_H */
diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h
new file mode 100644
index 0000000..3f6bcaf
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/hardware.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/* STV0991 */
+#define SRAM0_BASE_ADDR 0x00000000UL
+#define SRAM1_BASE_ADDR 0x00068000UL
+#define SRAM2_BASE_ADDR 0x000D0000UL
+#define SRAM3_BASE_ADDR 0x00138000UL
+#define CFS_SRAM0_BASE_ADDR 0x00198000UL
+#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
+#define FAST_SRAM_BASE_ADDR 0x001D8000UL
+#define FLASH_BASE_ADDR 0x40000000UL
+#define PL310_BASE_ADDR 0x70000000UL
+#define HSAXIM_BASE_ADDR 0x70100000UL
+#define IMGSS_BASE_ADDR 0x70200000UL
+#define ADC_BASE_ADDR 0x80000000UL
+#define GPIOA_BASE_ADDR 0x80001000UL
+#define GPIOB_BASE_ADDR 0x80002000UL
+#define GPIOC_BASE_ADDR 0x80003000UL
+#define HDM_BASE_ADDR 0x80004000UL
+#define THSENS_BASE_ADDR 0x80200000UL
+#define GPTIMER2_BASE_ADDR 0x80201000UL
+#define GPTIMER1_BASE_ADDR 0x80202000UL
+#define QSPI_BASE_ADDR 0x80203000UL
+#define CGU_BASE_ADDR 0x80204000UL
+#define CREG_BASE_ADDR 0x80205000UL
+#define PEC_BASE_ADDR 0x80206000UL
+#define WDRU_BASE_ADDR 0x80207000UL
+#define BSEC_BASE_ADDR 0x80208000UL
+#define DAP_ROM_BASE_ADDR 0x80210000UL
+#define SOC_CTI_BASE_ADDR 0x80211000UL
+#define TPIU_BASE_ADDR 0x80212000UL
+#define TMC_ETF_BASE_ADDR 0x80213000UL
+#define R4_ETM_BASE_ADDR 0x80214000UL
+#define R4_CTI_BASE_ADDR 0x80215000UL
+#define R4_DBG_BASE_ADDR 0x80216000UL
+#define GMAC_BASE_ADDR 0x80300000UL
+#define RNSS_BASE_ADDR 0x80302000UL
+#define CRYP_BASE_ADDR 0x80303000UL
+#define HASH_BASE_ADDR 0x80304000UL
+#define GPDMA_BASE_ADDR 0x80305000UL
+#define ISA_BASE_ADDR 0x8032A000UL
+#define HCI_BASE_ADDR 0x80400000UL
+#define I2C1_BASE_ADDR 0x80401000UL
+#define I2C2_BASE_ADDR 0x80402000UL
+#define SAI_BASE_ADDR 0x80403000UL
+#define USI_BASE_ADDR 0x80404000UL
+#define SPI1_BASE_ADDR 0x80405000UL
+#define UART_BASE_ADDR 0x80406000UL
+#define SPI2_BASE_ADDR 0x80500000UL
+#define CAN_BASE_ADDR 0x80501000UL
+#define USART1_BASE_ADDR 0x80502000UL
+#define USART2_BASE_ADDR 0x80503000UL
+#define USART3_BASE_ADDR 0x80504000UL
+#define USART4_BASE_ADDR 0x80505000UL
+#define USART5_BASE_ADDR 0x80506000UL
+#define USART6_BASE_ADDR 0x80507000UL
+#define SDI2_BASE_ADDR 0x80600000UL
+#define SDI1_BASE_ADDR 0x80601000UL
+#define VICA_BASE_ADDR 0x81000000UL
+#define VICB_BASE_ADDR 0x81001000UL
+#define STM_CHANNELS_BASE_ADDR 0x81100000UL
+#define STM_BASE_ADDR 0x81110000UL
+#define SROM_BASE_ADDR 0xFFFF0000UL
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
new file mode 100644
index 0000000..ddcbb57
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STV0991_CGU_H
+#define _STV0991_CGU_H
+
+struct stv0991_cgu_regs {
+ u32 cpu_freq; /* offset 0x0 */
+ u32 icn2_freq; /* offset 0x4 */
+ u32 dma_freq; /* offset 0x8 */
+ u32 isp_freq; /* offset 0xc */
+ u32 h264_freq; /* offset 0x10 */
+ u32 osif_freq; /* offset 0x14 */
+ u32 ren_freq; /* offset 0x18 */
+ u32 tim_freq; /* offset 0x1c */
+ u32 sai_freq; /* offset 0x20 */
+ u32 eth_freq; /* offset 0x24 */
+ u32 i2c_freq; /* offset 0x28 */
+ u32 spi_freq; /* offset 0x2c */
+ u32 uart_freq; /* offset 0x30 */
+ u32 qspi_freq; /* offset 0x34 */
+ u32 sdio_freq; /* offset 0x38 */
+ u32 usi_freq; /* offset 0x3c */
+ u32 can_line_freq; /* offset 0x40 */
+ u32 debug_freq; /* offset 0x44 */
+ u32 trace_freq; /* offset 0x48 */
+ u32 stm_freq; /* offset 0x4c */
+ u32 eth_ctrl; /* offset 0x50 */
+ u32 reserved[3]; /* offset 0x54 */
+ u32 osc_ctrl; /* offset 0x60 */
+ u32 pll1_ctrl; /* offset 0x64 */
+ u32 pll1_freq; /* offset 0x68 */
+ u32 pll1_fract; /* offset 0x6c */
+ u32 pll1_spread; /* offset 0x70 */
+ u32 pll1_status; /* offset 0x74 */
+ u32 pll2_ctrl; /* offset 0x78 */
+ u32 pll2_freq; /* offset 0x7c */
+ u32 pll2_fract; /* offset 0x80 */
+ u32 pll2_spread; /* offset 0x84 */
+ u32 pll2_status; /* offset 0x88 */
+ u32 cgu_enable_1; /* offset 0x8c */
+ u32 cgu_enable_2; /* offset 0x90 */
+ u32 cgu_isp_pulse; /* offset 0x94 */
+ u32 cgu_h264_pulse; /* offset 0x98 */
+ u32 cgu_osif_pulse; /* offset 0x9c */
+ u32 cgu_ren_pulse; /* offset 0xa0 */
+
+};
+
+/* CGU Timer */
+#define CLK_TMR_OSC 0
+#define CLK_TMR_MCLK 1
+#define CLK_TMR_PLL1 2
+#define CLK_TMR_PLL2 3
+#define MDIV_SHIFT_TMR 3
+#define DIV_SHIFT_TMR 6
+
+#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
+ | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
+
+/* Clock Enable/Disable */
+
+#define TIMER1_CLK_EN (1 << 15)
+
+/* CGU Uart config */
+#define CLK_UART_MCLK 0
+#define CLK_UART_PLL1 1
+#define CLK_UART_PLL2 2
+
+#define MDIV_SHIFT_UART 3
+#define DIV_SHIFT_UART 6
+
+#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
+ | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
+
+/* CGU Ethernet clock config */
+#define CLK_ETH_MCLK 0
+#define CLK_ETH_PLL1 1
+#define CLK_ETH_PLL2 2
+
+#define MDIV_SHIFT_ETH 3
+#define DIV_SHIFT_ETH 6
+#define DIV_ETH_125 9
+#define DIV_ETH_50 12
+#define DIV_ETH_P2P 15
+
+#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
+ | 1 << DIV_ETH_125 \
+ | 0 << DIV_SHIFT_ETH \
+ | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
+ /* CGU Ethernet control */
+
+#define ETH_CLK_TX_EXT_PHY 0
+#define ETH_CLK_TX_125M 1
+#define ETH_CLK_TX_25M 2
+#define ETH_CLK_TX_2M5 3
+#define ETH_CLK_TX_DIS 7
+
+#define ETH_CLK_RX_EXT_PHY 0
+#define ETH_CLK_RX_25M 1
+#define ETH_CLK_RX_2M5 2
+#define ETH_CLK_RX_DIS 3
+#define RX_CLK_SHIFT 3
+#define ETH_CLK_MASK ~(0x1F)
+
+#define ETH_PHY_MODE_GMII 0
+#define ETH_PHY_MODE_RMII 1
+#define ETH_PHY_CLK_DIS 1
+
+#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
+ | ETH_CLK_TX_EXT_PHY)
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
new file mode 100644
index 0000000..c804eb5
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STV0991_CREG_H
+#define _STV0991_CREG_H
+
+struct stv0991_creg {
+ u32 version; /* offset 0x0 */
+ u32 hdpctl; /* offset 0x4 */
+ u32 hdpval; /* offset 0x8 */
+ u32 hdpgposet; /* offset 0xc */
+ u32 hdpgpoclr; /* offset 0x10 */
+ u32 hdpgpoval; /* offset 0x14 */
+ u32 stm_mux; /* offset 0x18 */
+ u32 sysctrl_1; /* offset 0x1c */
+ u32 sysctrl_2; /* offset 0x20 */
+ u32 sysctrl_3; /* offset 0x24 */
+ u32 sysctrl_4; /* offset 0x28 */
+ u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
+ u32 mux1; /* offset 0x100 */
+ u32 mux2; /* offset 0x104 */
+ u32 mux3; /* offset 0x108 */
+ u32 mux4; /* offset 0x10c */
+ u32 mux5; /* offset 0x110 */
+ u32 mux6; /* offset 0x114 */
+ u32 mux7; /* offset 0x118 */
+ u32 mux8; /* offset 0x11c */
+ u32 mux9; /* offset 0x120 */
+ u32 mux10; /* offset 0x124 */
+ u32 mux11; /* offset 0x128 */
+ u32 mux12; /* offset 0x12c */
+ u32 mux13; /* offset 0x130 */
+ u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
+ u32 cfg_pad1; /* offset 0x200 */
+ u32 cfg_pad2; /* offset 0x204 */
+ u32 cfg_pad3; /* offset 0x208 */
+ u32 cfg_pad4; /* offset 0x20c */
+ u32 cfg_pad5; /* offset 0x210 */
+ u32 cfg_pad6; /* offset 0x214 */
+ u32 cfg_pad7; /* offset 0x218 */
+ u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
+ u32 vdd_pad1; /* offset 0x300 */
+ u32 vdd_pad2; /* offset 0x304 */
+ u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
+ u32 vdd_comp1; /* offset 0x400 */
+};
+
+/* CREG MUX 12 register */
+#define GPIOC_30_MUX_SHIFT 24
+#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
+#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
+
+#define GPIOC_31_MUX_SHIFT 28
+#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
+#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
+
+/* CREG MUX 7 register */
+#define GPIOB_16_MUX_SHIFT 0
+#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
+#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
+
+#define GPIOB_17_MUX_SHIFT 4
+#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
+#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
+
+/* CREG CFG_PAD6 register */
+
+#define GPIOC_31_MODE_SHIFT 30
+#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
+#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
+#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
+
+#define GPIOC_30_MODE_SHIFT 28
+#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
+#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
+#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
+
+/* CREG Ethernet pad config */
+
+#define VDD_ETH_PS_1V8 0
+#define VDD_ETH_PS_2V5 2
+#define VDD_ETH_PS_3V3 3
+#define VDD_ETH_PS_MASK 0x3
+
+#define VDD_ETH_PS_SHIFT 12
+#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
+
+#define VDD_ETH_M_PS_SHIFT 28
+#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
new file mode 100644
index 0000000..1151378
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STV0991_DEFS_H__
+#define __STV0991_DEFS_H__
+#include <asm/arch/stv0991_periph.h>
+
+extern int stv0991_pinmux_config(enum periph_id);
+extern int clock_setup(enum periph_clock);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
new file mode 100644
index 0000000..abd7257
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STV0991_GPT_H
+#define _STV0991_GPT_H
+
+#include <asm/arch-stv0991/hardware.h>
+
+struct gpt_regs {
+ u32 cr1;
+ u32 cr2;
+ u32 reserved_1;
+ u32 dier; /* dma_int_en */
+ u32 sr; /* status reg */
+ u32 egr; /* event gen */
+ u32 reserved_2[3]; /* offset 0x18--0x20*/
+ u32 cnt;
+ u32 psc;
+ u32 arr;
+};
+
+struct gpt_regs *const gpt1_regs_ptr =
+ (struct gpt_regs *) GPTIMER1_BASE_ADDR;
+
+/* Timer control1 register */
+#define GPT_CR1_CEN 0x0001
+#define GPT_MODE_AUTO_RELOAD (1 << 7)
+
+/* Timer prescalar reg */
+#define GPT_PRESCALER_128 0x128
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING 0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_STV0991_HZ 1000
+#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
new file mode 100644
index 0000000..f728c83
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+ UART_GPIOC_30_31 = 0,
+ UART_GPIOB_16_17,
+ ETH_GPIOB_10_31_C_0_4,
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_SPI0,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SDMMC0,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_I2S1,
+};
+
+enum periph_clock {
+ UART_CLOCK_CFG = 0,
+ ETH_CLOCK_CFG,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
new file mode 100644
index 0000000..7e555a2
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STV0991_WD_RST_H
+#define _STV0991_WD_RST_H
+#include <asm/arch-stv0991/hardware.h>
+
+struct stv0991_wd_ru {
+ u32 wdru_config;
+ u32 wdru_ctrl1;
+ u32 wdru_ctrl2;
+ u32 wdru_tim;
+ u32 wdru_count;
+ u32 wdru_stat;
+ u32 wdru_wrlock;
+};
+
+struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
+ (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
+
+/* Watchdog control register */
+#define WDRU_RST_SYS 0x1
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index b40c16b..64acff3 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -25,9 +25,11 @@
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_uart(void);
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 9dca800..eb88969 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -62,7 +62,7 @@ struct sunxi_ccm_reg {
u32 gps_clk_cfg; /* 0xd0 */
u32 spi3_clk_cfg; /* 0xd4 */
u8 res5[0x28];
- u32 dram_clk_cfg; /* 0x100 */
+ u32 dram_clk_gate; /* 0x100 */
u32 be0_clk_cfg; /* 0x104 */
u32 be1_clk_cfg; /* 0x108 */
u32 fe0_clk_cfg; /* 0x10c */
@@ -186,12 +186,20 @@ struct sunxi_ccm_reg {
/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_DE_BE0 12
+#define AHB_GATE_OFFSET_HDMI 11
+#define AHB_GATE_OFFSET_LCD1 5
+#define AHB_GATE_OFFSET_LCD0 4
#define CCM_AHB_GATE_GPS (0x1 << 26)
#define CCM_AHB_GATE_SDRAM (0x1 << 14)
#define CCM_AHB_GATE_DLL (0x1 << 15)
#define CCM_AHB_GATE_ACE (0x1 << 16)
+#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0)
+#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15)
+#define CCM_PLL3_CTRL_EN (0x1 << 31)
+
#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
@@ -253,6 +261,34 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+
+#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH0_CTRL_RST (0x1 << 30)
+#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+/* We leave bit 11 set to 0, so sclk1 == sclk2 */
+#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
+/* Enable / disable both ch1 sclk1 and sclk2 at the same time */
+#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15)
+
+#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
+#define CCM_HDMI_CTRL_PLL3 (0 << 24)
+#define CCM_HDMI_CTRL_PLL7 (1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
+/* No separate ddc gate on sun4i, sun5i and sun7i */
+#define CCM_HDMI_CTRL_DDC_GATE 0
+#define CCM_HDMI_CTRL_GATE (0x1 << 31)
+
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
@@ -266,4 +302,13 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY1_CLK 0
#define CCM_USB_CTRL_PHY2_CLK 0
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK (3 << 24)
+#define CCM_DE_CTRL_PLL3 (0 << 24)
+#define CCM_DE_CTRL_PLL7 (1 << 24)
+#define CCM_DE_CTRL_PLL5P (2 << 24)
+#define CCM_DE_CTRL_RST (1 << 30)
+#define CCM_DE_CTRL_GATE (1 << 31)
+
#endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index e16a764..3599054 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -176,13 +176,18 @@ struct sunxi_ccm_reg {
#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
+#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
+#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
+#define CCM_PLL3_CTRL_EN (0x1 << 31)
+
#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL5_CTRL_UPD (0x1 << 20)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
-#define PLL6_CFG_DEFAULT 0x90041811
+#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
@@ -193,17 +198,26 @@ struct sunxi_ccm_reg {
#define AXI_GATE_OFFSET_DRAM 0
+/* ahb_gate0 offsets */
#define AHB_GATE_OFFSET_USB_OHCI1 30
#define AHB_GATE_OFFSET_USB_OHCI0 29
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#define AHB_GATE_OFFSET_MCTL 14
+#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+/* ahb_gate1 offsets */
+#define AHB_GATE_OFFSET_DRC0 25
+#define AHB_GATE_OFFSET_DE_BE0 12
+#define AHB_GATE_OFFSET_HDMI 11
+#define AHB_GATE_OFFSET_LCD1 5
+#define AHB_GATE_OFFSET_LCD0 4
+
#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
@@ -216,6 +230,12 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
@@ -223,8 +243,35 @@ struct sunxi_ccm_reg {
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
+#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+
+#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
+#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
+
+#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
+#define CCM_HDMI_CTRL_PLL3 (0 << 24)
+#define CCM_HDMI_CTRL_PLL7 (1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
+#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
+#define CCM_HDMI_CTRL_GATE (0x1 << 31)
+
#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
#define AHB_RESET_OFFSET_MMC2 10
@@ -232,10 +279,28 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_MMC0 8
#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_DRC0 25
+#define AHB_RESET_OFFSET_DE_BE0 12
+#define AHB_RESET_OFFSET_HDMI 11
+#define AHB_RESET_OFFSET_LCD1 5
+#define AHB_RESET_OFFSET_LCD0 4
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
#define APB2_RESET_TWI_SHIFT (0)
#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK (0xf << 24)
+#define CCM_DE_CTRL_PLL3 (0 << 24)
+#define CCM_DE_CTRL_PLL7 (1 << 24)
+#define CCM_DE_CTRL_PLL6_2X (2 << 24)
+#define CCM_DE_CTRL_PLL8 (3 << 24)
+#define CCM_DE_CTRL_PLL9 (4 << 24)
+#define CCM_DE_CTRL_PLL10 (5 << 24)
+#define CCM_DE_CTRL_GATE (1 << 31)
+
#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index bdee89e..2c92b5c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -99,9 +99,13 @@
#define SUNXI_SCR_BASE 0x01c2c400
+#ifndef CONFIG_MACH_SUN6I
#define SUNXI_GPS_BASE 0x01c30000
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
+#else
+#define SUNXI_GMAC_BASE 0x01c30000
+#endif
#define SUNXI_DRAM_COM_BASE 0x01c62000
#define SUNXI_DRAM_CTL0_BASE 0x01c63000
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
new file mode 100644
index 0000000..ddb71c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -0,0 +1,187 @@
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DISPLAY_H
+#define _SUNXI_DISPLAY_H
+
+struct sunxi_de_be_reg {
+ u8 res0[0x800]; /* 0x000 */
+ u32 mode; /* 0x800 */
+ u32 backcolor; /* 0x804 */
+ u32 disp_size; /* 0x808 */
+ u8 res1[0x4]; /* 0x80c */
+ u32 layer0_size; /* 0x810 */
+ u32 layer1_size; /* 0x814 */
+ u32 layer2_size; /* 0x818 */
+ u32 layer3_size; /* 0x81c */
+ u32 layer0_pos; /* 0x820 */
+ u32 layer1_pos; /* 0x824 */
+ u32 layer2_pos; /* 0x828 */
+ u32 layer3_pos; /* 0x82c */
+ u8 res2[0x10]; /* 0x830 */
+ u32 layer0_stride; /* 0x840 */
+ u32 layer1_stride; /* 0x844 */
+ u32 layer2_stride; /* 0x848 */
+ u32 layer3_stride; /* 0x84c */
+ u32 layer0_addr_low32b; /* 0x850 */
+ u32 layer1_addr_low32b; /* 0x854 */
+ u32 layer2_addr_low32b; /* 0x858 */
+ u32 layer3_addr_low32b; /* 0x85c */
+ u32 layer0_addr_high4b; /* 0x860 */
+ u32 layer1_addr_high4b; /* 0x864 */
+ u32 layer2_addr_high4b; /* 0x868 */
+ u32 layer3_addr_high4b; /* 0x86c */
+ u32 reg_ctrl; /* 0x870 */
+ u8 res3[0xc]; /* 0x874 */
+ u32 color_key_max; /* 0x880 */
+ u32 color_key_min; /* 0x884 */
+ u32 color_key_config; /* 0x888 */
+ u8 res4[0x4]; /* 0x88c */
+ u32 layer0_attr0_ctrl; /* 0x890 */
+ u32 layer1_attr0_ctrl; /* 0x894 */
+ u32 layer2_attr0_ctrl; /* 0x898 */
+ u32 layer3_attr0_ctrl; /* 0x89c */
+ u32 layer0_attr1_ctrl; /* 0x8a0 */
+ u32 layer1_attr1_ctrl; /* 0x8a4 */
+ u32 layer2_attr1_ctrl; /* 0x8a8 */
+ u32 layer3_attr1_ctrl; /* 0x8ac */
+};
+
+struct sunxi_lcdc_reg {
+ u32 ctrl; /* 0x00 */
+ u32 int0; /* 0x04 */
+ u32 int1; /* 0x08 */
+ u8 res0[0x04]; /* 0x0c */
+ u32 frame_ctrl; /* 0x10 */
+ u8 res1[0x2c]; /* 0x14 */
+ u32 tcon0_ctrl; /* 0x40 */
+ u32 tcon0_dclk; /* 0x44 */
+ u32 tcon0_basic_timing0; /* 0x48 */
+ u32 tcon0_basic_timing1; /* 0x4c */
+ u32 tcon0_basic_timing2; /* 0x50 */
+ u32 tcon0_basic_timing3; /* 0x54 */
+ u32 tcon0_hv_intf; /* 0x58 */
+ u8 res2[0x04]; /* 0x5c */
+ u32 tcon0_cpu_intf; /* 0x60 */
+ u32 tcon0_cpu_wr_dat; /* 0x64 */
+ u32 tcon0_cpu_rd_dat0; /* 0x68 */
+ u32 tcon0_cpu_rd_dat1; /* 0x6c */
+ u32 tcon0_ttl_timing0; /* 0x70 */
+ u32 tcon0_ttl_timing1; /* 0x74 */
+ u32 tcon0_ttl_timing2; /* 0x78 */
+ u32 tcon0_ttl_timing3; /* 0x7c */
+ u32 tcon0_ttl_timing4; /* 0x80 */
+ u32 tcon0_lvds_intf; /* 0x84 */
+ u32 tcon0_io_polarity; /* 0x88 */
+ u32 tcon0_io_tristate; /* 0x8c */
+ u32 tcon1_ctrl; /* 0x90 */
+ u32 tcon1_timing_source; /* 0x94 */
+ u32 tcon1_timing_scale; /* 0x98 */
+ u32 tcon1_timing_out; /* 0x9c */
+ u32 tcon1_timing_h; /* 0xa0 */
+ u32 tcon1_timing_v; /* 0xa4 */
+ u32 tcon1_timing_sync; /* 0xa8 */
+ u8 res3[0x44]; /* 0xac */
+ u32 tcon1_io_polarity; /* 0xf0 */
+ u32 tcon1_io_tristate; /* 0xf4 */
+};
+
+struct sunxi_hdmi_reg {
+ u32 version_id; /* 0x000 */
+ u32 ctrl; /* 0x004 */
+ u32 irq; /* 0x008 */
+ u32 hpd; /* 0x00c */
+ u32 video_ctrl; /* 0x010 */
+ u32 video_size; /* 0x014 */
+ u32 video_bp; /* 0x018 */
+ u32 video_fp; /* 0x01c */
+ u32 video_spw; /* 0x020 */
+ u32 video_polarity; /* 0x024 */
+ u8 res0[0x1d8]; /* 0x028 */
+ u32 pad_ctrl0; /* 0x200 */
+ u32 pad_ctrl1; /* 0x204 */
+ u32 pll_ctrl; /* 0x208 */
+ u32 pll_dbg0; /* 0x20c */
+};
+
+/*
+ * DE-BE register constants.
+ */
+#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
+#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
+#define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
+#define SUNXI_DE_BE_MODE_START (1 << 1)
+#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
+#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
+#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
+#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
+
+/*
+ * LCDC register constants.
+ */
+#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
+#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
+#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
+#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
+#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
+
+/*
+ * HDMI register constants.
+ */
+#define SUNXI_HDMI_X(x) (((x) - 1) << 0)
+#define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
+#define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
+#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
+#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
+#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
+#define SUNXI_HDMI_HPD_DETECT (1 << 0)
+#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
+#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
+#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
+#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
+#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
+#else
+#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
+#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
+#endif
+
+#ifdef CONFIG_MACH_SUN4I
+#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
+#elif defined CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PAD_CTRL1 0x01ded030
+#else
+#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
+#endif
+#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PLL_CTRL 0xba48a308
+#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
+#else
+#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
+#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
+#endif
+#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
+
+#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
+#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
+
+int sunxi_simplefb_setup(void *blob);
+
+#endif /* _SUNXI_DISPLAY_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index c734cf0..366c0dc 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -134,6 +134,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_OUTPUT 1
#define SUNXI_GPA0_EMAC 2
+#define SUN6I_GPA0_GMAC 2
#define SUN7I_GPA0_GMAC 5
#define SUNXI_GPB0_TWI0 2
diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h
index e6ba4e4..e3cba5b 100644
--- a/arch/arm/include/asm/arch-uniphier/board.h
+++ b/arch/arm/include/asm/arch-uniphier/board.h
@@ -12,10 +12,12 @@
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
+void support_card_late_init(void);
int check_support_card(void);
#else
#define support_card_reset() do {} while (0)
#define support_card_init() do {} while (0)
+#define support_card_late_init() do {} while (0)
static inline int check_support_card(void)
{
return 0;
@@ -32,4 +34,9 @@ static inline void uniphier_board_init(void)
support_card_init();
}
+static inline void uniphier_board_late_init(void)
+{
+ support_card_late_init();
+}
+
#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h
new file mode 100644
index 0000000..1fc4e19
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/gpio.h
@@ -0,0 +1,6 @@
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
+ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c69d064..438f128 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -17,6 +17,14 @@ struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+
+#if defined(CONFIG_U_QE)
+ u32 qe_clk;
+ u32 brg_clk;
+ uint mp_alloc_base;
+ uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 1838234..323952f 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -540,6 +540,7 @@ extern struct prcm_regs const omap5_es2_prcm;
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
+extern struct dplls dra7xx_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
@@ -547,6 +548,8 @@ extern struct omap_sys_ctrl_regs const omap4_ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+extern struct pmic_data tps659038;
+
void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
new file mode 100644
index 0000000..e9b3184
--- /dev/null
+++ b/arch/avr32/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/avr32/cpu/start.o
+
+libs-y += arch/avr32/cpu/
+libs-y += arch/avr32/lib/
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
new file mode 100644
index 0000000..787475e
--- /dev/null
+++ b/arch/blackfin/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/blackfin/cpu/start.o
+
+libs-y += arch/blackfin/cpu/
+libs-y += arch/blackfin/lib/
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 69f08bc..aadb0d2 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -11,10 +11,9 @@
#ifdef __KERNEL__
+#include <linux/compiler.h>
#include <asm/blackfin.h>
-#define __iomem
-
static inline void sync(void)
{
SSYNC();
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
new file mode 100644
index 0000000..aa3d2fa
--- /dev/null
+++ b/arch/m68k/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/m68k/cpu/$(CPU)/start.o
+
+libs-y += arch/m68k/cpu/$(CPU)/
+libs-y += arch/m68k/lib/
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
new file mode 100644
index 0000000..ae4adc2
--- /dev/null
+++ b/arch/microblaze/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/microblaze/cpu/start.o
+
+libs-y += arch/microblaze/cpu/
+libs-y += arch/microblaze/lib/
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
new file mode 100644
index 0000000..1907b57
--- /dev/null
+++ b/arch/mips/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/mips/cpu/$(CPU)/start.o
+
+libs-y += arch/mips/cpu/$(CPU)/
+libs-y += arch/mips/lib/
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 68e59b5..384ea26 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -136,10 +136,11 @@ reset:
/* Set up temporary stack */
li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ move fp, sp
la t9, board_init_f
jr t9
- nop
+ move ra, zero
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -155,6 +156,7 @@ reset:
.ent relocate_code
relocate_code:
move sp, a0 # set new stack pointer
+ move fp, sp
move s0, a1 # save gd in s0
move s2, a2 # save destination address in s2
@@ -260,8 +262,9 @@ in_ram:
addi t1, 4
move a0, s0 # a0 <-- gd
+ move a1, s2
la t9, board_init_r
jr t9
- move a1, s2
+ move ra, zero
.end relocate_code
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 92954e1..6ff714e 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -130,10 +130,11 @@ reset:
/* Set up temporary stack */
dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ move fp, sp
dla t9, board_init_f
jr t9
- nop
+ move ra, zero
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -149,6 +150,7 @@ reset:
.ent relocate_code
relocate_code:
move sp, a0 # set new stack pointer
+ move fp, sp
move s0, a1 # save gd in s0
move s2, a2 # save destination address in s2
@@ -254,8 +256,9 @@ in_ram:
daddi t1, 8
move a0, s0 # a0 <-- gd
+ move a1, s2
dla t9, board_init_r
jr t9
- move a1, s2
+ move ra, zero
.end relocate_code
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
index 1d5112e..c25a846 100644
--- a/arch/mips/include/asm/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
@@ -8,7 +8,7 @@
#ifndef _ASM_MIPS_UNALIGNED_H
#define _ASM_MIPS_UNALIGNED_H
-#include <compiler.h>
+#include <linux/compiler.h>
#if defined(__MIPSEB__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index e483e86..7f9b653 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -5,9 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y += board.o
-endif
obj-y += io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
deleted file mode 100644
index 3feb020..0000000
--- a/arch/mips/lib/board.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <serial.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-#include <environment.h>
-#include <nand.h>
-#include <onenand_uboot.h>
-#include <spi.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ulong monitor_flash_len;
-
-static char *failed = "*** failed ***\n";
-
-int __board_early_init_f(void)
-{
- /*
- * Nothing to do in this dummy implementation
- */
- return 0;
-}
-int board_early_init_f(void)
- __attribute__((weak, alias("__board_early_init_f")));
-
-static int init_func_ram(void)
-{
-#ifdef CONFIG_BOARD_TYPES
- int board_type = gd->board_type;
-#else
- int board_type = 0; /* use dummy arg */
-#endif
- puts("DRAM: ");
-
- gd->ram_size = initdram(board_type);
- if (gd->ram_size > 0) {
- print_size(gd->ram_size, "\n");
- return 0;
- }
- puts(failed);
- return 1;
-}
-
-static int display_banner(void)
-{
-
- printf("\n\n%s\n\n", version_string);
- return 0;
-}
-
-#ifndef CONFIG_SYS_NO_FLASH
-static void display_flash_config(ulong size)
-{
- puts("Flash: ");
- print_size(size, "\n");
-}
-#endif
-
-static int init_baudrate(void)
-{
- gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
- return 0;
-}
-
-
-/*
- * Breath some life into the board...
- *
- * The first part of initialization is running from Flash memory;
- * its main purpose is to initialize the RAM so that we
- * can relocate the monitor code to RAM.
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t)(void);
-
-init_fnc_t *init_sequence[] = {
- board_early_init_f,
- timer_init,
- env_init, /* initialize environment */
- init_baudrate, /* initialize baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f,
- display_banner, /* say that we are here */
- checkboard,
- init_func_ram,
- NULL,
-};
-
-
-void board_init_f(ulong bootflag)
-{
- gd_t gd_data, *id;
- bd_t *bd;
- init_fnc_t **init_fnc_ptr;
- ulong addr, addr_sp, len;
- ulong *s;
-
- /* Pointer is writable since we allocated a register for it.
- */
- gd = &gd_data;
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- memset((void *)gd, 0, sizeof(gd_t));
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr)() != 0)
- hang();
- }
-
- /*
- * Now that we have DRAM mapped and working, we can
- * relocate the code and continue running from DRAM.
- */
- addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-
- /* We can reserve some RAM "on top" here.
- */
-
- /* round down to next 4 kB limit.
- */
- addr &= ~(4096 - 1);
- debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
- /* Reserve memory for U-Boot code, data & bss
- * round down to next 16 kB limit
- */
- len = bss_end() - CONFIG_SYS_MONITOR_BASE;
- addr -= len;
- addr &= ~(16 * 1024 - 1);
-
- debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
-
- /* Reserve memory for malloc() arena.
- */
- addr_sp = addr - TOTAL_MALLOC_LEN;
- debug("Reserving %dk for malloc() at: %08lx\n",
- TOTAL_MALLOC_LEN >> 10, addr_sp);
-
- /*
- * (permanently) allocate a Board Info struct
- * and a permanent copy of the "global" data
- */
- addr_sp -= sizeof(bd_t);
- bd = (bd_t *)addr_sp;
- gd->bd = bd;
- debug("Reserving %zu Bytes for Board Info at: %08lx\n",
- sizeof(bd_t), addr_sp);
-
- addr_sp -= sizeof(gd_t);
- id = (gd_t *)addr_sp;
- debug("Reserving %zu Bytes for Global Data at: %08lx\n",
- sizeof(gd_t), addr_sp);
-
- /* Reserve memory for boot params.
- */
- addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN;
- bd->bi_boot_params = addr_sp;
- debug("Reserving %dk for boot params() at: %08lx\n",
- CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp);
-
- /*
- * Finally, we set up a new (bigger) stack.
- *
- * Leave some safety gap for SP, force alignment on 16 byte boundary
- * Clear initial stack frame
- */
- addr_sp -= 16;
- addr_sp &= ~0xF;
- s = (ulong *)addr_sp;
- *s-- = 0;
- *s-- = 0;
- addr_sp = (ulong)s;
- debug("Stack Pointer at: %08lx\n", addr_sp);
-
- /*
- * Save local variables to board info struct
- */
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */
- bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */
-
- memcpy(id, (void *)gd, sizeof(gd_t));
-
- relocate_code(addr_sp, id, addr);
-
- /* NOTREACHED - relocate_code() does not return */
-}
-
-/*
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- */
-
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-#ifndef CONFIG_SYS_NO_FLASH
- ulong size;
-#endif
- bd_t *bd;
-
- gd = id;
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-
- debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
- gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
-
- monitor_flash_len = image_copy_end() - dest_addr;
-
- serial_initialize();
-
- bd = gd->bd;
-
- /* The Malloc area is immediately below the monitor copy in DRAM */
- mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
- TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
- /* configure available FLASH banks */
- size = flash_init();
- display_flash_config(size);
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
- bd->bi_flashsize = size;
-
-#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
- bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */
-#else
- bd->bi_flashoffset = 0;
-#endif
-#else
- bd->bi_flashstart = 0;
- bd->bi_flashsize = 0;
- bd->bi_flashoffset = 0;
-#endif
-
-#ifdef CONFIG_CMD_NAND
- puts("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
- onenand_init();
-#endif
-
- /* relocate environment function pointers etc. */
- env_relocate();
-
-#if defined(CONFIG_PCI)
- /*
- * Do pci configuration
- */
- pci_init();
-#endif
-
-/** leave this here (after malloc(), environment and PCI are working) **/
- /* Initialize stdio devices */
- stdio_init();
-
- jumptable_init();
-
- /* Initialize the console (after the relocation and devices init) */
- console_init_r();
-/** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/
-
- /* Initialize from environment */
- load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_CMD_SPI
- puts("SPI: ");
- spi_init(); /* go init the SPI */
- puts("ready\n");
-#endif
-
-#if defined(CONFIG_MISC_INIT_R)
- /* miscellaneous platform dependent initialisations */
- misc_init_r();
-#endif
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
- puts("Net: ");
- eth_initialize(gd->bd);
-#endif
-
- /* main_loop() can return to retry autoboot, if so just run it again. */
- for (;;)
- main_loop();
-
- /* NOTREACHED - no way out of command loop except booting */
-}
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 71bb0d2..e0722d2 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -6,10 +6,7 @@
*/
#include <common.h>
-#include <command.h>
#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
#include <asm/addrspace.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +49,20 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp);
}
+static int boot_setup_linux(bootm_headers_t *images)
+{
+ int ret;
+ ulong rd_len;
+
+ rd_len = images->rd_end - images->rd_start;
+ ret = boot_ramdisk_high(&images->lmb, images->rd_start,
+ rd_len, &images->initrd_start, &images->initrd_end);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static void linux_cmdline_init(void)
{
linux_argc = 1;
@@ -224,6 +235,8 @@ static void boot_jump_linux(bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
+ int ret;
+
/* No need for those on MIPS */
if (flag & BOOTM_STATE_OS_BD_T)
return -1;
@@ -243,6 +256,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
return 0;
}
+ ret = boot_setup_linux(images);
+ if (ret)
+ return ret;
+
boot_cmdline_linux(images);
boot_prep_linux(images);
boot_jump_linux(images);
diff --git a/arch/nds32/Makefile b/arch/nds32/Makefile
new file mode 100644
index 0000000..e1eccba
--- /dev/null
+++ b/arch/nds32/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/nds32/cpu/$(CPU)/start.o
+
+libs-y += arch/nds32/cpu/$(CPU)/
+libs-y += arch/nds32/lib/
diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile
new file mode 100644
index 0000000..18685a9
--- /dev/null
+++ b/arch/nios2/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/nios2/cpu/start.o
+
+libs-y += arch/nios2/cpu/
+libs-y += arch/nios2/lib/
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index 4d88f16..5024682 100644
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
@@ -18,11 +18,13 @@
DECLARE_GLOBAL_DATA_PTR;
-void __ft_board_setup(void *blob, bd_t *bd)
+int __ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
-void ft_board_setup(void *blob, bd_t *bd) \
+int ft_board_setup(void *blob, bd_t *bd)
__attribute__((weak, alias("__ft_board_setup")));
void ft_cpu_setup(void *blob, bd_t *bd)
@@ -32,5 +34,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
* Note: aliases in the dts are required for this
*/
fdt_fixup_ethernet(blob);
+
+ return 0;
}
#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
new file mode 100644
index 0000000..c4da3ce
--- /dev/null
+++ b/arch/openrisc/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/openrisc/cpu/start.o
+
+libs-y += arch/openrisc/cpu/
+libs-y += arch/openrisc/lib/
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
new file mode 100644
index 0000000..8aa1d60
--- /dev/null
+++ b/arch/powerpc/Makefile
@@ -0,0 +1,11 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/powerpc/cpu/$(CPU)/start.o
+head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
+head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
+
+libs-y += arch/powerpc/cpu/$(CPU)/
+libs-y += arch/powerpc/cpu/
+libs-y += arch/powerpc/lib/
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7b42d06..7501eb4 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -110,6 +110,14 @@ config TARGET_P2041RDB
config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
+config TARGET_T102XQDS
+ bool "Support T102xQDS"
+ select SUPPORT_SPL
+
+config TARGET_T102XRDB
+ bool "Support T102xRDB"
+ select SUPPORT_SPL
+
config TARGET_T1040QDS
bool "Support T1040QDS"
@@ -183,6 +191,8 @@ source "board/freescale/p2020come/Kconfig"
source "board/freescale/p2020ds/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
+source "board/freescale/t102xqds/Kconfig"
+source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index ad26b43..b93158b 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -51,6 +51,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o
obj-$(CONFIG_PPC_T1042) += t1040_ids.o
obj-$(CONFIG_PPC_T1020) += t1040_ids.o
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
+obj-$(CONFIG_PPC_T1023) += t1024_ids.o
+obj-$(CONFIG_PPC_T1024) += t1024_ids.o
obj-$(CONFIG_PPC_T2080) += t2080_ids.o
obj-$(CONFIG_PPC_T2081) += t2080_ids.o
@@ -97,6 +99,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
+obj-$(CONFIG_PPC_T1023) += t1024_serdes.o
+obj-$(CONFIG_PPC_T1024) += t1024_serdes.o
obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 1a30f1c..598f7bd 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -59,8 +59,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
- SET_DMA_LIODN(1, 147),
- SET_DMA_LIODN(2, 227),
+ SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
+ SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
#ifndef CONFIG_PPC_B4420
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index cf18be5..63172de 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,8 @@ struct serdes_config {
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
+ {0x01, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x02, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x06, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x07, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x08, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, NONE, NONE} },
{0x0F, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
+ {0x17, {NONE, NONE,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x18, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x1B, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x1D, {NONE, NONE, AURORA, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x1E, {NONE, NONE, AURORA, AURORA,
NONE, NONE, NONE, NONE} },
{0x21, {NONE, NONE, AURORA, AURORA,
@@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
+ {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
+ {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
+ {0x99, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x9A, {PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+ NONE, NONE, NONE, NONE} },
{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
NONE, NONE, NONE, NONE} },
{}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3a04a89..2d5ddf0 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -9,6 +9,7 @@
#include <linux/compiler.h>
#include <asm/fsl_errata.h>
#include <asm/processor.h>
+#include <fsl_usb.h>
#include "fsl_corenet_serdes.h"
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
@@ -270,7 +271,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
puts("Work-around for Erratum USB14 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
- puts("Work-around for Erratum A007186 enabled\n");
+ if (has_erratum_a007186())
+ puts("Work-around for Erratum A007186 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
@@ -293,6 +295,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (has_erratum_a007075())
puts("Work-around for Erratum A007075 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
+ if (has_erratum_a007798())
+ puts("Work-around for Erratum A007798 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
@@ -308,6 +314,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
puts("Work-around for Erratum A-005434 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
+ defined(CONFIG_A008044_WORKAROUND)
+ if (IS_SVR_REV(svr, 1, 0))
+ puts("Work-around for Erratum A-008044 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
+ puts("Work-around for Erratum XFI on B4860QDS enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 8edf5bb..5cfae47 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -11,6 +11,7 @@
#include <asm/processor.h>
#include <asm/fsl_law.h>
#include <asm/errno.h>
+#include <asm/fsl_errata.h>
#include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1
@@ -203,7 +204,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
- if (sel == 0x01 || sel == 0x02) {
+ if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
debug("A007186: pll_num=%x pllcr0=%x\n",
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index 488e078..6e3cddd 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -50,8 +50,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
- SET_DMA_LIODN(1, 197),
- SET_DMA_LIODN(2, 198),
+ SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
+ SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index 7d98870..2b57703 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
- SET_DMA_LIODN(1, 197),
- SET_DMA_LIODN(2, 198),
+ SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
+ SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index b2a23c0..94a5143 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -40,8 +40,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
- SET_DMA_LIODN(1, 196),
- SET_DMA_LIODN(2, 197),
+ SET_DMA_LIODN(1, "fsl,eloplus-dma", 196),
+ SET_DMA_LIODN(2, "fsl,eloplus-dma", 197),
SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000),
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index b5d787c..0f292cf 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
- SET_DMA_LIODN(1, 197),
- SET_DMA_LIODN(2, 198),
+ SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
+ SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
index 990f179..d4343ef 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -42,8 +42,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
- SET_DMA_LIODN(1, 193),
- SET_DMA_LIODN(2, 194),
+ SET_DMA_LIODN(1, "fsl,eloplus-dma", 193),
+ SET_DMA_LIODN(2, "fsl,eloplus-dma", 194),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 8426b1a..7e69873 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -37,6 +37,7 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
+ __maybe_unused u32 svr;
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
@@ -122,11 +123,27 @@ void get_sys_info(sys_info_t *sys_info)
/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
+ * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
- if (SVR_MAJ(get_svr()) >= 2)
- mem_pll_rat *= 2;
+ defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
+ svr = get_svr();
+ switch (SVR_SOC_VER(svr)) {
+ case SVR_T4240:
+ case SVR_T4160:
+ case SVR_T4120:
+ case SVR_T4080:
+ if (SVR_MAJ(svr) >= 2)
+ mem_pll_rat *= 2;
+ break;
+ case SVR_T2080:
+ case SVR_T2081:
+ if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
+ mem_pll_rat *= 2;
+ break;
+ default:
+ break;
+ }
#endif
if (mem_pll_rat > 2)
sys_info->freq_ddrbus *= mem_pll_rat;
@@ -168,6 +185,9 @@ void get_sys_info(sys_info_t *sys_info)
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#define FM1_CLK_SEL 0x00000007
+#define FM1_CLK_SHIFT 0
#else
#define PME_CLK_SEL 0xe0000000
#define PME_CLK_SHIFT 29
@@ -175,8 +195,12 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+ rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
+#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif
+#endif
#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
@@ -213,7 +237,10 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- sys_info->freq_qman = sys_info->freq_systembus / 2;
+#ifndef CONFIG_QBMAN_CLK_DIV
+#define CONFIG_QBMAN_CLK_DIV 2
+#endif
+ sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
new file mode 100644
index 0000000..132689b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 27, 1, 0),
+ SET_QP_INFO(2, 28, 1, 0),
+ SET_QP_INFO(3, 29, 1, 1),
+ SET_QP_INFO(4, 30, 1, 1),
+ SET_QP_INFO(5, 31, 1, 2),
+ SET_QP_INFO(6, 32, 1, 2),
+ SET_QP_INFO(7, 33, 1, 3),
+ SET_QP_INFO(8, 34, 1, 3),
+ SET_QP_INFO(9, 35, 1, 0),
+ SET_QP_INFO(10, 36, 1, 0),
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(62),
+ SET_BMAN_LIODN(63),
+#endif
+
+ SET_SDHC_LIODN(1, 552),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+ SET_SATA_LIODN(1, 555),
+
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+
+ SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
+ SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
+ SET_QE_LIODN(559),
+ SET_TDM_LIODN(560),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
new file mode 100644
index 0000000..7dc8385
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+
+static u8 serdes_cfg_tbl[][4] = {
+ [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
+ [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
+ [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
+ [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
+ [0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
+ [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
+ [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
+ [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
+ [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+ [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
+ [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+ [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC1},
+ [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
+ [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC1},
+ [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
+ [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < 4; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index a5dfb81..8091722 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -24,12 +24,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
};
#endif
-struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
-};
-int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
-
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(62),
@@ -38,12 +32,21 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 552),
+ SET_PME_LIODN(117),
+
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 554),
- SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148),
+ SET_SATA_LIODN(1, 555),
+ SET_SATA_LIODN(2, 556),
- SET_DMA_LIODN(1, 147),
- SET_DMA_LIODN(2, 227),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+ SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
+ SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
@@ -74,6 +77,12 @@ struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_RTIC_LIODN_ENTRY(d, 551),
SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
@@ -82,4 +91,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
+#endif
};
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
index 0bfd447..eda7f59 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
@@ -63,9 +63,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
- SET_DMA_LIODN(1, 147),
- SET_DMA_LIODN(2, 227),
- SET_DMA_LIODN(3, 226),
+ SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
+ SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
+ SET_DMA_LIODN(3, "fsl,elo3-dma", 226),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index 7138bb4..c65f41d 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -169,6 +169,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index 1a3cb33..470b080 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -93,8 +93,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
- SET_DMA_LIODN(1, 147),
- SET_DMA_LIODN(2, 227),
+ SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
+ SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index e447748e..99420ab 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_COGENT_MPC8XX
config TARGET_ESTEEM192E
bool "Support ESTEEM192E"
-config TARGET_HERMES
- bool "Support hermes"
-
config TARGET_IP860
bool "Support IP860"
@@ -112,7 +109,6 @@ source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
-source "board/hermes/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 60c401e..6a1cd46 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -125,8 +125,7 @@ void cpu_init_f (volatile immap_t * immr)
* I owe him a free beer. - wd]
*/
-#if defined(CONFIG_HERMES) || \
- defined(CONFIG_IP860) || \
+#if defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 84fec5e..2d28eb2 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -76,6 +76,10 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T1020, T1020, 0),
CPU_TYPE_ENTRY(T1021, T1021, 0),
CPU_TYPE_ENTRY(T1022, T1022, 0),
+ CPU_TYPE_ENTRY(T1024, T1024, 0),
+ CPU_TYPE_ENTRY(T1023, T1023, 0),
+ CPU_TYPE_ENTRY(T1014, T1014, 0),
+ CPU_TYPE_ENTRY(T1013, T1013, 0),
CPU_TYPE_ENTRY(T2080, T2080, 0),
CPU_TYPE_ENTRY(T2081, T2081, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index bd905d1..eef9c5a 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -18,7 +18,7 @@
DECLARE_GLOBAL_DATA_PTR;
-void __ft_board_setup(void *blob, bd_t *bd)
+int __ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int i;
@@ -60,8 +60,11 @@ void __ft_board_setup(void *blob, bd_t *bd)
printf("Unable to update property EBC mappings, err=%s\n",
fdt_strerror(rc));
}
+
+ return 0;
}
-void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
+int ft_board_setup(void *blob, bd_t *bd)
+ __attribute__((weak, alias("__ft_board_setup")));
/*
* Fixup all PCIe nodes by setting the device_type property
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4c1774f..01b0905 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -678,6 +678,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007798
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -768,6 +769,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FSL_ERRATUM_A008044
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
@@ -785,6 +787,52 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
+defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_SYS_FMAN_V3
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#endif
+#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define CONFIG_MAX_CPUS 1
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLL 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CONFIG_SYS_SDHC_CLOCK 0
+#define CONFIG_SYS_FSL_NUM_LAWS 16
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_QBMAN_CLK_DIV 1
+#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index 64da4bb..61c6d70 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -26,59 +26,28 @@ static inline bool has_erratum_a006379(void)
return false;
}
#endif
+#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
-static inline bool has_erratum_a006261(void)
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+static inline bool has_erratum_a007186(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
- case SVR_P1010:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P2041:
- case SVR_P2040:
- return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
- case SVR_P3041:
- return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 1, 1) ||
- IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
- case SVR_P5010:
- case SVR_P5020:
- case SVR_P5021:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
+ return IS_SVR_REV(svr, 2, 0);
case SVR_T4160:
- case SVR_T4080:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_T1040:
- return IS_SVR_REV(svr, 1, 0);
- case SVR_T2080:
- case SVR_T2081:
- return IS_SVR_REV(svr, 1, 0);
- case SVR_P5040:
- return IS_SVR_REV(svr, 1, 0);
- }
-
- return false;
-}
-#endif
-
-static inline bool has_erratum_a007075(void)
-{
- u32 svr = get_svr();
- u32 soc = SVR_SOC_VER(svr);
-
- switch (soc) {
+ return IS_SVR_REV(svr, 2, 0);
case SVR_B4860:
+ return IS_SVR_REV(svr, 2, 0);
case SVR_B4420:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P1010:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_T2081:
+ case SVR_T2080:
return IS_SVR_REV(svr, 1, 0);
- case SVR_P4080:
- return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
}
+
return false;
}
#endif
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index adfbb66..811f034 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -91,8 +91,8 @@ extern void fdt_fixup_liodn(void *blob);
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
/* reg nodes for DMA start @ 0x300 */
-#define SET_DMA_LIODN(dmaNum, liodn) \
- SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
+#define SET_DMA_LIODN(dmaNum, compat, liodn) \
+ SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
#define SET_SDHC_LIODN(sdhcNum, liodn) \
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 74c5d8f..14c6fc3 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -22,7 +22,9 @@
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T104xRDB)
+ defined(CONFIG_T104xRDB) || \
+ defined(CONFIG_PPC_T1023) || \
+ defined(CONFIG_PPC_T1024)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index f60cb0a..8e0e190 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -71,6 +71,22 @@ enum srds_prtcl {
INTERLAKEN,
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
QSGMII_SW1_B,
+ SGMII_2500_FM1_DTSEC1,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC3,
+ SGMII_2500_FM1_DTSEC4,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC6,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM2_DTSEC1,
+ SGMII_2500_FM2_DTSEC2,
+ SGMII_2500_FM2_DTSEC3,
+ SGMII_2500_FM2_DTSEC4,
+ SGMII_2500_FM2_DTSEC5,
+ SGMII_2500_FM2_DTSEC6,
+ SGMII_2500_FM2_DTSEC9,
+ SGMII_2500_FM2_DTSEC10,
};
enum srds {
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0264523..ace1d12 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1626,10 +1626,15 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
+#else
#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
+#endif
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
@@ -1787,6 +1792,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
+ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
+#define FSL_CORENET_RCWSR13_EC2 0x0c000000
+#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
+#define PXCKEN_MASK 0x80000000
+#define PXCK_MASK 0x00FF0000
+#define PXCK_BITS_START 16
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
@@ -2971,6 +2991,8 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+ (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1b98e0f..2ed51b1 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1133,6 +1133,10 @@
#define SVR_T1020 0x852100
#define SVR_T1021 0x852101
#define SVR_T1022 0x852102
+#define SVR_T1024 0x854000
+#define SVR_T1023 0x854100
+#define SVR_T1014 0x854400
+#define SVR_T1013 0x854500
#define SVR_T2080 0x853000
#define SVR_T2081 0x853100
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 6eaab88..e6d5355 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -820,13 +820,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
mac_read_from_eeprom();
#endif
-#ifdef CONFIG_HERMES
- if ((gd->board_type >> 16) == 2)
- bd->bi_ethspeed = gd->board_type & 0xFFFF;
- else
- bd->bi_ethspeed = 0xFFFF;
-#endif
-
#ifdef CONFIG_CMD_NET
/* kept around for legacy kernels only ... ignore the next section */
eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
@@ -876,11 +869,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
misc_init_r();
#endif
-#ifdef CONFIG_HERMES
- if (bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980((int) bd->bi_ethspeed);
-#endif
-
#if defined(CONFIG_CMD_KGDB)
WATCHDOG_RESET();
puts("KGDB: ");
diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile
new file mode 100644
index 0000000..23fdcdb
--- /dev/null
+++ b/arch/sandbox/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sandbox/cpu/start.o
+
+libs-y += arch/sandbox/cpu/
+libs-y += arch/sandbox/lib/
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 31c9344..4d5f805 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -367,6 +367,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp)
done:
closedir(dir);
+ free(fname);
return ret;
}
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 0df7770..42353d8 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -130,7 +130,8 @@ static int sandbox_cmdline_cb_memory(struct sandbox_state *state,
state->write_ram_buf = true;
state->ram_buf_fname = arg;
- if (os_read_ram_buf(arg)) {
+ err = os_read_ram_buf(arg);
+ if (err) {
printf("Failed to read RAM buffer\n");
return err;
}
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
new file mode 100644
index 0000000..ca55fac
--- /dev/null
+++ b/arch/sh/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sh/cpu/$(CPU)/start.o
+
+libs-y += arch/sh/cpu/$(CPU)/
+libs-y += arch/sh/lib/
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
index 2e0d164..06096ee 100644
--- a/arch/sh/include/asm/unaligned.h
+++ b/arch/sh/include/asm/unaligned.h
@@ -8,7 +8,7 @@
#include <asm/unaligned-sh4a.h>
#else
/* Otherwise, SH can't handle unaligned accesses. */
-#include <compiler.h>
+#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
new file mode 100644
index 0000000..2d4c971
--- /dev/null
+++ b/arch/sparc/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sparc/cpu/$(CPU)/start.o
+
+libs-y += arch/sparc/cpu/$(CPU)/
+libs-y += arch/sparc/lib/
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 6e29868..4f5ce38 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -83,6 +83,155 @@ config X86_RAMTEST
to work correctly. It is not exhaustive but can save time by
detecting obvious failures.
+config MARK_GRAPHICS_MEM_WRCOMB
+ bool "Mark graphics memory as write-combining."
+ default n
+ help
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
+
+menu "Display"
+
+config FRAMEBUFFER_SET_VESA_MODE
+ prompt "Set framebuffer graphics resolution"
+ bool
+ help
+ Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
+
+choice
+ prompt "framebuffer graphics resolution"
+ default FRAMEBUFFER_VESA_MODE_117
+ depends on FRAMEBUFFER_SET_VESA_MODE
+ help
+ This option sets the resolution used for the coreboot framebuffer (and
+ bootsplash screen).
+
+config FRAMEBUFFER_VESA_MODE_100
+ bool "640x400 256-color"
+
+config FRAMEBUFFER_VESA_MODE_101
+ bool "640x480 256-color"
+
+config FRAMEBUFFER_VESA_MODE_102
+ bool "800x600 16-color"
+
+config FRAMEBUFFER_VESA_MODE_103
+ bool "800x600 256-color"
+
+config FRAMEBUFFER_VESA_MODE_104
+ bool "1024x768 16-color"
+
+config FRAMEBUFFER_VESA_MODE_105
+ bool "1024x7686 256-color"
+
+config FRAMEBUFFER_VESA_MODE_106
+ bool "1280x1024 16-color"
+
+config FRAMEBUFFER_VESA_MODE_107
+ bool "1280x1024 256-color"
+
+config FRAMEBUFFER_VESA_MODE_108
+ bool "80x60 text"
+
+config FRAMEBUFFER_VESA_MODE_109
+ bool "132x25 text"
+
+config FRAMEBUFFER_VESA_MODE_10A
+ bool "132x43 text"
+
+config FRAMEBUFFER_VESA_MODE_10B
+ bool "132x50 text"
+
+config FRAMEBUFFER_VESA_MODE_10C
+ bool "132x60 text"
+
+config FRAMEBUFFER_VESA_MODE_10D
+ bool "320x200 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_10E
+ bool "320x200 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_10F
+ bool "320x200 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_110
+ bool "640x480 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_111
+ bool "640x480 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_112
+ bool "640x480 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_113
+ bool "800x600 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_114
+ bool "800x600 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_115
+ bool "800x600 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_116
+ bool "1024x768 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_117
+ bool "1024x768 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_118
+ bool "1024x768 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_119
+ bool "1280x1024 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_11A
+ bool "1280x1024 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_11B
+ bool "1280x1024 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_USER
+ bool "Manually select VESA mode"
+
+endchoice
+
+# Map the config names to an integer (KB).
+config FRAMEBUFFER_VESA_MODE
+ prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
+ hex
+ default 0x100 if FRAMEBUFFER_VESA_MODE_100
+ default 0x101 if FRAMEBUFFER_VESA_MODE_101
+ default 0x102 if FRAMEBUFFER_VESA_MODE_102
+ default 0x103 if FRAMEBUFFER_VESA_MODE_103
+ default 0x104 if FRAMEBUFFER_VESA_MODE_104
+ default 0x105 if FRAMEBUFFER_VESA_MODE_105
+ default 0x106 if FRAMEBUFFER_VESA_MODE_106
+ default 0x107 if FRAMEBUFFER_VESA_MODE_107
+ default 0x108 if FRAMEBUFFER_VESA_MODE_108
+ default 0x109 if FRAMEBUFFER_VESA_MODE_109
+ default 0x10A if FRAMEBUFFER_VESA_MODE_10A
+ default 0x10B if FRAMEBUFFER_VESA_MODE_10B
+ default 0x10C if FRAMEBUFFER_VESA_MODE_10C
+ default 0x10D if FRAMEBUFFER_VESA_MODE_10D
+ default 0x10E if FRAMEBUFFER_VESA_MODE_10E
+ default 0x10F if FRAMEBUFFER_VESA_MODE_10F
+ default 0x110 if FRAMEBUFFER_VESA_MODE_110
+ default 0x111 if FRAMEBUFFER_VESA_MODE_111
+ default 0x112 if FRAMEBUFFER_VESA_MODE_112
+ default 0x113 if FRAMEBUFFER_VESA_MODE_113
+ default 0x114 if FRAMEBUFFER_VESA_MODE_114
+ default 0x115 if FRAMEBUFFER_VESA_MODE_115
+ default 0x116 if FRAMEBUFFER_VESA_MODE_116
+ default 0x117 if FRAMEBUFFER_VESA_MODE_117
+ default 0x118 if FRAMEBUFFER_VESA_MODE_118
+ default 0x119 if FRAMEBUFFER_VESA_MODE_119
+ default 0x11A if FRAMEBUFFER_VESA_MODE_11A
+ default 0x11B if FRAMEBUFFER_VESA_MODE_11B
+ default 0x117 if FRAMEBUFFER_VESA_MODE_USER
+
+endmenu
+
source "arch/x86/cpu/ivybridge/Kconfig"
source "board/coreboot/coreboot/Kconfig"
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
new file mode 100644
index 0000000..36a6018
--- /dev/null
+++ b/arch/x86/Makefile
@@ -0,0 +1,12 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/x86/cpu/start.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+head-y += arch/x86/cpu/start16.o
+head-y += arch/x86/cpu/resetvec.o
+endif
+
+libs-y += arch/x86/cpu/
+libs-y += arch/x86/lib/
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2b9e9b9..7f09db5 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -13,4 +13,8 @@ obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
+obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
+obj-y += lapic.o
obj-$(CONFIG_PCI) += pci.o
+obj-y += turbo.o
diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk
index f7b01d3..84aeaf3 100644
--- a/arch/x86/cpu/config.mk
+++ b/arch/x86/cpu/config.mk
@@ -12,5 +12,6 @@ PLATFORM_CPPFLAGS += -D__I386__ -Werror
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=0xffff0000
LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
-LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
-LDPPFLAGS += -DSTART_16=0xf800
+LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0
+LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
+LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)"
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 2df7288..cfacc05 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,17 +39,6 @@ int board_early_init_f(void)
return 0;
}
-int board_early_init_r(void)
-{
- /* CPU Speed to 100MHz */
- gd->cpu_clk = 100000000;
-
- /* Crystal is 33.000MHz */
- gd->bus_clk = 33000000;
-
- return 0;
-}
-
int print_cpuinfo(void)
{
return default_print_cpuinfo();
diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c
index 5f6c009..3340872 100644
--- a/arch/x86/cpu/coreboot/ipchecksum.c
+++ b/arch/x86/cpu/coreboot/ipchecksum.c
@@ -29,7 +29,8 @@
* SUCH DAMAGE.
*/
-#include <compiler.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
#include <asm/arch/ipchecksum.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index b391b7a..30e5069 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -124,7 +124,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
{
struct gdt_ptr gdt;
- gdt.len = (num_entries * 8) - 1;
+ gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
gdt.ptr = (u32)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
@@ -144,10 +144,13 @@ void setup_gdt(gd_t *id, u64 *gdt_addr)
(ulong)&id->arch.gd_addr, 0xfffff);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
/* 16-bit DS: data, read/write, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
+
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
load_ds(X86_GDT_ENTRY_32BIT_DS);
@@ -320,14 +323,6 @@ int x86_cpu_init_f(void)
return 0;
}
-int x86_cpu_init_r(void)
-{
- /* Initialize core interrupt and exception functionality of CPU */
- cpu_init_interrupts();
- return 0;
-}
-int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
-
void x86_enable_caches(void)
{
unsigned long cr0;
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 51e2c59..a21d2a6 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -20,6 +20,7 @@
#include <linux/compiler.h>
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
+#include <asm/i8259.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -128,9 +129,6 @@ int cpu_init_interrupts(void)
int irq_entry_size = irq_1 - irq_0;
void *irq_entry = (void *)irq_0;
- /* Just in case... */
- disable_interrupts();
-
/* Setup the IDT */
for (i = 0; i < 256; i++) {
idt[i].access = 0x8e;
@@ -146,9 +144,6 @@ int cpu_init_interrupts(void)
load_idt(&idt_ptr);
- /* It is now safe to enable interrupts */
- enable_interrupts();
-
return 0;
}
@@ -172,6 +167,25 @@ int disable_interrupts(void)
return flags & X86_EFLAGS_IF;
}
+int interrupt_init(void)
+{
+ /* Just in case... */
+ disable_interrupts();
+
+#ifdef CONFIG_SYS_PCAT_INTERRUPTS
+ /* Initialize the master/slave i8259 pic */
+ i8259_init();
+#endif
+
+ /* Initialize core interrupt and exception functionality of CPU */
+ cpu_init_interrupts();
+
+ /* It is now safe to enable interrupts */
+ enable_interrupts();
+
+ return 0;
+}
+
/* IRQ Low-Level Service Routine */
void irq_llsr(struct irq_regs *regs)
{
@@ -603,31 +617,3 @@ asm(".globl irq_common_entry\n" \
DECLARE_INTERRUPT(253) \
DECLARE_INTERRUPT(254) \
DECLARE_INTERRUPT(255));
-
-#if defined(CONFIG_INTEL_CORE_ARCH)
-/*
- * Get the number of CPU time counter ticks since it was read first time after
- * restart. This yields a free running counter guaranteed to take almost 6
- * years to wrap around even at 100GHz clock rate.
- */
-u64 get_ticks(void)
-{
- u64 now_tick = rdtsc();
-
- if (!gd->arch.tsc_base)
- gd->arch.tsc_base = now_tick;
-
- return now_tick - gd->arch.tsc_base;
-}
-
-#define PLATFORM_INFO_MSR 0xce
-
-unsigned long get_tbclk(void)
-{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
-
- ratio = (platform_info >> 8) & 0xff;
- return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */
-}
-#endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 721b37e..0c7efae 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -4,13 +4,21 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += bd82x6x.o
obj-y += car.o
obj-y += cpu.o
obj-y += early_init.o
obj-y += early_me.o
+obj-y += gma.o
obj-y += lpc.o
obj-y += me_status.o
+obj-y += model_206ax.o
obj-y += microcode_intel.o
+obj-y += northbridge.o
+obj-y += pch.o
obj-y += pci.o
obj-y += report_platform.o
+obj-y += sata.o
obj-y += sdram.o
+obj-y += usb_ehci.o
+obj-y += usb_xhci.o
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
new file mode 100644
index 0000000..65a17d3
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/lapic.h>
+#include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+void bd82x6x_pci_init(pci_dev_t dev)
+{
+ u16 reg16;
+ u8 reg8;
+
+ debug("bd82x6x PCI init.\n");
+ /* Enable Bus Master */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /* This device has no interrupt */
+ pci_write_config8(dev, INTR, 0xff);
+
+ /* disable parity error response and SERR */
+ reg16 = pci_read_config16(dev, BCTRL);
+ reg16 &= ~(1 << 0);
+ reg16 &= ~(1 << 1);
+ pci_write_config16(dev, BCTRL, reg16);
+
+ /* Master Latency Count must be set to 0x04! */
+ reg8 = pci_read_config8(dev, SMLT);
+ reg8 &= 0x07;
+ reg8 |= (0x04 << 3);
+ pci_write_config8(dev, SMLT, reg8);
+
+ /* Will this improve throughput of bus masters? */
+ pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, PSTS);
+ /* reg16 |= 0xf900; */
+ pci_write_config16(dev, PSTS, reg16);
+
+ reg16 = pci_read_config16(dev, SECSTS);
+ /* reg16 |= 0xf900; */
+ pci_write_config16(dev, SECSTS, reg16);
+}
+
+#define PCI_BRIDGE_UPDATE_COMMAND
+void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
+{
+ uint16_t command;
+
+ command = pci_read_config16(dev, PCI_COMMAND);
+ command |= PCI_COMMAND_IO;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+ /*
+ * If we write to PCI_COMMAND, on some systems this will cause the
+ * ROM and APICs to become invisible.
+ */
+ debug("%x cmd <- %02x\n", dev, command);
+ pci_write_config16(dev, PCI_COMMAND, command);
+#else
+ printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+#endif
+}
+
+void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
+{
+ uint16_t ctrl;
+
+ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ ctrl |= PCI_COMMAND_IO;
+ ctrl |= PCI_BRIDGE_CTL_VGA;
+ debug("%x bridge ctrl <- %04x\n", dev, ctrl);
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+ bd82x6x_pci_dev_enable_resources(dev);
+}
+
+int bd82x6x_init_pci_devices(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct pci_controller *hose;
+ struct x86_cpu_priv *cpu;
+ int sata_node, gma_node;
+ int ret;
+
+ hose = pci_bus_to_hose(0);
+ lpc_enable(PCH_LPC_DEV);
+ lpc_init(hose, PCH_LPC_DEV);
+ sata_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_INTEL_PANTHERPOINT_AHCI);
+ if (sata_node < 0) {
+ debug("%s: Cannot find SATA node\n", __func__);
+ return -EINVAL;
+ }
+ bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
+ bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
+ bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
+
+ cpu = calloc(1, sizeof(*cpu));
+ if (!cpu)
+ return -ENOMEM;
+ model_206ax_init(cpu);
+
+ gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
+ if (gma_node < 0) {
+ debug("%s: Cannot find GMA node\n", __func__);
+ return -EINVAL;
+ }
+ ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
+ gma_node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int bd82x6x_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ int sata_node;
+
+ sata_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_INTEL_PANTHERPOINT_AHCI);
+ if (sata_node < 0) {
+ debug("%s: Cannot find SATA node\n", __func__);
+ return -EINVAL;
+ }
+
+ bd82x6x_pci_init(PCH_DEV);
+ bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
+ northbridge_enable(PCH_DEV);
+ northbridge_init(PCH_DEV);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
new file mode 100644
index 0000000..3d7f740
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -0,0 +1,756 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pci_rom.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+struct gt_powermeter {
+ u16 reg;
+ u32 value;
+};
+
+static const struct gt_powermeter snb_pm_gt1[] = {
+ { 0xa200, 0xcc000000 },
+ { 0xa204, 0x07000040 },
+ { 0xa208, 0x0000fe00 },
+ { 0xa20c, 0x00000000 },
+ { 0xa210, 0x17000000 },
+ { 0xa214, 0x00000021 },
+ { 0xa218, 0x0817fe19 },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0xcc000000 },
+ { 0xa228, 0x07000040 },
+ { 0xa22c, 0x0000fe00 },
+ { 0xa230, 0x00000000 },
+ { 0xa234, 0x17000000 },
+ { 0xa238, 0x00000021 },
+ { 0xa23c, 0x0817fe19 },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter snb_pm_gt2[] = {
+ { 0xa200, 0x330000a6 },
+ { 0xa204, 0x402d0031 },
+ { 0xa208, 0x00165f83 },
+ { 0xa20c, 0xf1000000 },
+ { 0xa210, 0x00000000 },
+ { 0xa214, 0x00160016 },
+ { 0xa218, 0x002a002b },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0x330000a6 },
+ { 0xa228, 0x402d0031 },
+ { 0xa22c, 0x00165f83 },
+ { 0xa230, 0xf1000000 },
+ { 0xa234, 0x00000000 },
+ { 0xa238, 0x00160016 },
+ { 0xa23c, 0x002a002b },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt1[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00021c00 },
+ { 0xa808, 0x00000403 },
+ { 0xa80c, 0x02001700 },
+ { 0xa810, 0x05000200 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00690500 },
+ { 0xa81c, 0x0000007f },
+ { 0xa820, 0x01002501 },
+ { 0xa824, 0x00000300 },
+ { 0xa828, 0x01000331 },
+ { 0xa82c, 0x0000000c },
+ { 0xa830, 0x00010016 },
+ { 0xa834, 0x01100101 },
+ { 0xa838, 0x00010103 },
+ { 0xa83c, 0x00041300 },
+ { 0xa840, 0x00000b30 },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x7f000000 },
+ { 0xa84c, 0x05000008 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000004 },
+ { 0xa858, 0x00000007 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00010000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00001c00 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x06000000 },
+ { 0xa910, 0x09000200 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00590000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x04002501 },
+ { 0xa924, 0x00000100 },
+ { 0xa928, 0x03000410 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00020000 },
+ { 0xa934, 0x02070106 },
+ { 0xa938, 0x00010100 },
+ { 0xa93c, 0x00401c00 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x10000e00 },
+ { 0xa94c, 0x02000004 },
+ { 0xa950, 0x00000001 },
+ { 0xa954, 0x00000004 },
+ { 0xa960, 0x00060000 },
+ { 0xaa3c, 0x00001c00 },
+ { 0xaa54, 0x00000004 },
+ { 0xaa60, 0x00060000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2[] = {
+ { 0xa800, 0x10000000 },
+ { 0xa804, 0x00033800 },
+ { 0xa808, 0x00000902 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x12000400 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20800 },
+ { 0xa81c, 0x00000002 },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00010032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x0000151d },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x20001b00 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000000 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003500 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000500 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000200 },
+ { 0xa928, 0x07000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x050f020d },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_17w[] = {
+ { 0xa800, 0x20000000 },
+ { 0xa804, 0x000e3800 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000800 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000002 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x0000000f },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_35w[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00030400 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000300 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+u32 map_oprom_vendev(u32 vendev)
+{
+ u32 new_vendev = vendev;
+
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ /* Set to GT1 Mobile */
+ new_vendev = 0x80860106;
+ break;
+ }
+
+ return new_vendev;
+}
+
+static inline u32 gtt_read(void *bar, u32 reg)
+{
+ return readl(bar + reg);
+}
+
+static inline void gtt_write(void *bar, u32 reg, u32 data)
+{
+ writel(data, bar + reg);
+}
+
+static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
+{
+ for (; pm && pm->reg; pm++)
+ gtt_write(bar, pm->reg, pm->value);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
+{
+ unsigned try = GTT_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = gtt_read(bar, reg);
+ if ((data & mask) == value)
+ return 1;
+ udelay(10);
+ }
+
+ printf("GT init timeout\n");
+ return 0;
+}
+
+static int gma_pm_init_pre_vbios(void *gtt_bar)
+{
+ u32 reg32;
+
+ debug("GT Power Management Init, silicon = %#x\n",
+ bridge_silicon_revision());
+
+ if (bridge_silicon_revision() < IVB_STEP_C0) {
+ /* 1: Enable force wake */
+ gtt_write(gtt_bar, 0xa18c, 0x00000001);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa180, 1 << 5);
+ gtt_write(gtt_bar, 0xa188, 0xffff0001);
+ gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
+ }
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+ reg32 = gtt_read(gtt_bar, 0x42004);
+ reg32 |= (1 << 14) | (1 << 15);
+ gtt_write(gtt_bar, 0x42004, reg32);
+ }
+
+ if (bridge_silicon_revision() >= IVB_STEP_A0) {
+ /* Display Reset Acknowledge Settings */
+ reg32 = gtt_read(gtt_bar, 0x45010);
+ reg32 |= (1 << 1) | (1 << 0);
+ gtt_write(gtt_bar, 0x45010, reg32);
+ }
+
+ /* 2: Get GT SKU from GTT+0x911c[13] */
+ reg32 = gtt_read(gtt_bar, 0x911c);
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (reg32 & (1 << 13)) {
+ debug("SNB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt1);
+ } else {
+ debug("SNB GT2 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt2);
+ }
+ } else {
+ u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
+
+ if (reg32 & (1 << 13)) {
+ /* GT1 SKU */
+ debug("IVB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
+ } else {
+ /* GT2 SKU */
+ u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
+ tdp /= (1 << unit);
+
+ if (tdp <= 17) {
+ /* <=17W ULV */
+ debug("IVB GT2 17W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
+ } else if ((tdp >= 25) && (tdp <= 35)) {
+ /* 25W-35W */
+ debug("IVB GT2 25W-35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ } else {
+ /* All others */
+ debug("IVB GT2 35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ }
+ }
+ }
+
+ /* 3: Gear ratio map */
+ gtt_write(gtt_bar, 0xa004, 0x00000010);
+
+ /* 4: GFXPAUSE */
+ gtt_write(gtt_bar, 0xa000, 0x00070020);
+
+ /* 5: Dynamic EU trip control */
+ gtt_write(gtt_bar, 0xa080, 0x00000004);
+
+ /* 6: ECO bits */
+ reg32 = gtt_read(gtt_bar, 0xa180);
+ reg32 |= (1 << 26) | (1 << 31);
+ /* (bit 20=1 for SNB step D1+ / IVB A0+) */
+ if (bridge_silicon_revision() >= SNB_STEP_D1)
+ reg32 |= (1 << 20);
+ gtt_write(gtt_bar, 0xa180, reg32);
+
+ /* 6a: for SnB step D2+ only */
+ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
+ (bridge_silicon_revision() >= SNB_STEP_D2)) {
+ reg32 = gtt_read(gtt_bar, 0x9400);
+ reg32 |= (1 << 7);
+ gtt_write(gtt_bar, 0x9400, reg32);
+
+ reg32 = gtt_read(gtt_bar, 0x941c);
+ reg32 &= 0xf;
+ reg32 |= (1 << 1);
+ gtt_write(gtt_bar, 0x941c, reg32);
+ gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
+ }
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ reg32 = gtt_read(gtt_bar, 0x907c);
+ reg32 |= (1 << 16);
+ gtt_write(gtt_bar, 0x907c, reg32);
+
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000001);
+ } else {
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000000);
+ }
+
+ /* 7 */
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
+ gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
+ /* Mailbox Cmd for RC6 VID */
+ gtt_write(gtt_bar, 0x138124, 0x80000004);
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
+ gtt_write(gtt_bar, 0x138124, 0x8000000a);
+ gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
+ }
+
+ /* 8 */
+ gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
+ gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+ gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+ /* 9 */
+ gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
+ gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
+ gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
+
+ /* 10 */
+ gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+ gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
+ gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
+ gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
+ gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+ /* 11 */
+ gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
+ gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
+ gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
+ gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
+ gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
+ gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
+ gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+ /* 11a: Enable Render Standby (RC6) */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /*
+ * IvyBridge should also support DeepRenderStandby.
+ *
+ * Unfortunately it does not work reliably on all SKUs so
+ * disable it here and it can be enabled by the kernel.
+ */
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ } else {
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ }
+
+ /* 12: Normal Frequency Request */
+ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+ reg32 = readl(MCHBAR_REG(0x5998));
+ reg32 >>= 16;
+ reg32 &= 0xef;
+ reg32 <<= 25;
+ gtt_write(gtt_bar, 0xa008, reg32);
+
+ /* 13: RP Control */
+ gtt_write(gtt_bar, 0xa024, 0x00000592);
+
+ /* 14: Enable PM Interrupts */
+ gtt_write(gtt_bar, 0x4402c, 0x03000076);
+
+ /* Clear 0x6c024 [8:6] */
+ reg32 = gtt_read(gtt_bar, 0x6c024);
+ reg32 &= ~0x000001c0;
+ gtt_write(gtt_bar, 0x6c024, reg32);
+
+ return 0;
+}
+
+int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
+{
+ u32 reg32, cycle_delay;
+
+ debug("GT Power Management Init (post VBIOS)\n");
+
+ /* 15: Deassert Force Wake */
+ if (bridge_silicon_revision() < IVB_STEP_C0) {
+ gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa188, 0x1fffe);
+ if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
+ gtt_write(gtt_bar, 0xa188,
+ gtt_read(gtt_bar, 0xa188) | 1);
+ }
+ }
+
+ /* 16: SW RC Control */
+ gtt_write(gtt_bar, 0xa094, 0x00060000);
+
+ /* Setup Digital Port Hotplug */
+ reg32 = gtt_read(gtt_bar, 0xc4030);
+ if (!reg32) {
+ u32 dp_hotplug[3];
+
+ if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
+ dp_hotplug, ARRAY_SIZE(dp_hotplug)))
+ return -EINVAL;
+
+ reg32 = (dp_hotplug[0] & 0x7) << 2;
+ reg32 |= (dp_hotplug[0] & 0x7) << 10;
+ reg32 |= (dp_hotplug[0] & 0x7) << 18;
+ gtt_write(gtt_bar, 0xc4030, reg32);
+ }
+
+ /* Setup Panel Power On Delays */
+ reg32 = gtt_read(gtt_bar, 0xc7208);
+ if (!reg32) {
+ reg32 = (unsigned)fdtdec_get_int(blob, node,
+ "panel-port-select", 0) << 30;
+ reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-on-delay", 0);
+ gtt_write(gtt_bar, 0xc7208, reg32);
+ }
+
+ /* Setup Panel Power Off Delays */
+ reg32 = gtt_read(gtt_bar, 0xc720c);
+ if (!reg32) {
+ reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-off-delay", 0);
+ gtt_write(gtt_bar, 0xc720c, reg32);
+ }
+
+ /* Setup Panel Power Cycle Delay */
+ cycle_delay = fdtdec_get_int(blob, node,
+ "intel,panel-power-cycle-delay", 0);
+ if (cycle_delay) {
+ reg32 = gtt_read(gtt_bar, 0xc7210);
+ reg32 &= ~0xff;
+ reg32 |= cycle_delay;
+ gtt_write(gtt_bar, 0xc7210, reg32);
+ }
+
+ /* Enable Backlight if needed */
+ reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0x48250, (1 << 31));
+ gtt_write(gtt_bar, 0x48254, reg32);
+ }
+ reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0xc8250, (1 << 31));
+ gtt_write(gtt_bar, 0xc8254, reg32);
+ }
+
+ return 0;
+}
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ return 0x80860106; /* GT1 Mobile */
+ }
+
+ return vendev;
+}
+
+static int int15_handler(void)
+{
+ int res = 0;
+
+ debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0003; /* eDP */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ debug("Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ break;
+ }
+ break;
+ case 0x5fac:
+ res = 1;
+ break;
+ default:
+ debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+ break;
+ }
+ return res;
+}
+
+int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
+ const void *blob, int node)
+{
+ void *gtt_bar;
+ u32 reg32;
+ int ret;
+
+ /* IGD needs to be Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
+ debug("GT bar %p\n", gtt_bar);
+ ret = gma_pm_init_pre_vbios(gtt_bar);
+ if (ret)
+ return ret;
+
+ ret = pci_run_vga_bios(dev, int15_handler, false);
+
+ /* Post VBIOS init */
+ ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h
new file mode 100644
index 0000000..e7ec649
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/gma.h
@@ -0,0 +1,156 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/* mailbox 0: header */
+__packed struct opregion_header {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+};
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+__packed struct opregion_mailbox1 {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+};
+
+/* mailbox 2: software sci interface */
+__packed struct opregion_mailbox2 {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+};
+
+/* mailbox 3: power conservation */
+__packed struct opregion_mailbox3 {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+};
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+__packed struct {
+ u8 gvd1[7168];
+} opregion_vbt_t;
+
+/* IGD OpRegion */
+__packed struct igd_opregion {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+};
+
+/* Intel Video BIOS (Option ROM) */
+__packed struct optionrom_header {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+};
+
+#define OPROM_SIGNATURE 0xaa55
+
+__packed struct optionrom_pcir {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+};
+
+__packed struct optionrom_vbt {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+};
+
+#define VBT_SIGNATURE 0x54425624
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 621ef2c..43fdd31 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -9,10 +9,460 @@
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
+#include <rtc.h>
#include <pci.h>
+#include <asm/acpi.h>
+#include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
+#define NMI_OFF 0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT 0
+#define TEST_SMM_FLASH_LOCKDOWN 0
+
+static int pch_enable_apic(pci_dev_t dev)
+{
+ u32 reg32;
+ int i;
+
+ /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
+ pci_write_config8(dev, ACPI_CNTL, 0x80);
+
+ writel(0, IO_APIC_INDEX);
+ writel(1 << 25, IO_APIC_DATA);
+
+ /* affirm full set of redirection table entries ("write once") */
+ writel(1, IO_APIC_INDEX);
+ reg32 = readl(IO_APIC_DATA);
+ writel(1, IO_APIC_INDEX);
+ writel(reg32, IO_APIC_DATA);
+
+ writel(0, IO_APIC_INDEX);
+ reg32 = readl(IO_APIC_DATA);
+ debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+ if (reg32 != (1 << 25)) {
+ printf("APIC Error - cannot write to registers\n");
+ return -EPERM;
+ }
+
+ debug("Dumping IOAPIC registers\n");
+ for (i = 0; i < 3; i++) {
+ writel(i, IO_APIC_INDEX);
+ debug(" reg 0x%04x:", i);
+ reg32 = readl(IO_APIC_DATA);
+ debug(" 0x%08x\n", reg32);
+ }
+
+ /* Select Boot Configuration register. */
+ writel(3, IO_APIC_INDEX);
+
+ /* Use Processor System Bus to deliver interrupts. */
+ writel(1, IO_APIC_DATA);
+
+ return 0;
+}
+
+static void pch_enable_serial_irqs(pci_dev_t dev)
+{
+ u32 value;
+
+ /* Set packet length and toggle silent mode bit for one frame. */
+ value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
+#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
+ pci_write_config8(dev, SERIRQ_CNTL, value);
+#else
+ pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
+#endif
+}
+
+static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
+{
+ uint8_t route[8], *ptr;
+
+ if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
+ sizeof(route)))
+ return -EINVAL;
+ ptr = route;
+ pci_write_config8(dev, PIRQA_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQB_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQC_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQD_ROUT, *ptr++);
+
+ pci_write_config8(dev, PIRQE_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQF_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQG_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQH_ROUT, *ptr++);
+
+ /*
+ * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
+ * here. It's unclear if it is needed
+ */
+ return 0;
+}
+
+static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
+{
+ u8 route[16];
+ u32 reg;
+ int gpi;
+
+ if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
+ sizeof(route)))
+ return -EINVAL;
+
+ for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
+ reg |= route[gpi] << (gpi * 2);
+
+ pci_write_config32(dev, 0xb8, reg);
+
+ return 0;
+}
+
+static int pch_power_options(const void *blob, int node, pci_dev_t dev)
+{
+ u8 reg8;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+ int pwr_on;
+ int nmi_option;
+ int ret;
+
+ /*
+ * Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use Kconfig setting.
+ * TODO(sjg@chromium.org): Make this configurable
+ */
+ pwr_on = MAINBOARD_POWER_ON;
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_3);
+ reg16 &= 0xfffe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg16 |= 1;
+ state = "off";
+ break;
+ case MAINBOARD_POWER_ON:
+ reg16 &= ~1;
+ state = "on";
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg16 &= ~1;
+ state = "state keep";
+ break;
+ default:
+ state = "undefined";
+ }
+
+ reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
+ reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
+
+ reg16 &= ~(1 << 10);
+ reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
+
+ reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
+
+ pci_write_config16(dev, GEN_PMCON_3, reg16);
+ debug("Set power %s after power failure.\n", state);
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ reg8 &= 0x0f; /* Higher Nibble must be 0 */
+ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
+ reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ /* TODO(sjg@chromium.org): Make this configurable */
+ nmi_option = NMI_OFF;
+ if (nmi_option) {
+ debug("NMI sources enabled.\n");
+ reg8 &= ~(1 << 7); /* Set NMI. */
+ } else {
+ debug("NMI sources disabled.\n");
+ /* Can't mask NMI from PCI-E and NMI_NOW */
+ reg8 |= (1 << 7);
+ }
+ outb(reg8, 0x70);
+
+ /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
+ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
+ reg16 |= (3 << 0); /* Periodic SMI every 8s */
+#endif
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ /* Set the board's GPI routing. */
+ ret = pch_gpi_routing(blob, node, dev);
+ if (ret)
+ return ret;
+
+ pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
+ "intel,gpe0-enable", 0));
+ writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
+ "intel,alt-gp-smi-enable", 0));
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); /* PM1_CNT */
+ reg32 &= ~(7 << 10); /* SLP_TYP */
+ reg32 |= (1 << 0); /* SCI_EN */
+ outl(reg32, pmbase + 0x04);
+
+ /* Clear magic status bits to prevent unexpected wake */
+ setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
+ clrbits_le32(RCB_REG(0x3f02), 0xf);
+
+ return 0;
+}
+
+static void pch_rtc_init(pci_dev_t dev)
+{
+ int rtc_failed;
+ u8 reg8;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ rtc_failed = reg8 & RTC_BATTERY_DEAD;
+ if (rtc_failed) {
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ }
+ debug("rtc_failed = 0x%x\n", rtc_failed);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Avoid clearing pending interrupts and resetting the RTC control
+ * register in the resume path because the Linux kernel relies on
+ * this to know if it should restart the RTC timerqueue if the wake
+ * was due to the RTC alarm.
+ */
+ if (acpi_get_slp_type() == 3)
+ return;
+#endif
+ /* TODO: Handle power failure */
+ if (rtc_failed)
+ printf("RTC power failed\n");
+ rtc_init();
+}
+
+/* CougarPoint PCH Power Management init */
+static void cpt_pm_init(pci_dev_t dev)
+{
+ debug("CougarPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
+
+ setbits_le32(RCB_REG(0x228c), 1 << 0);
+ setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
+ setbits_le32(RCB_REG(0x0900), 1 << 14);
+ writel(0xc0388400, RCB_REG(0x2304));
+ setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
+ setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
+ clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
+ writel(0x050f0000, RCB_REG(0x3318));
+ writel(0x04000000, RCB_REG(0x3324));
+ setbits_le32(RCB_REG(0x3340), 0xfffff);
+ setbits_le32(RCB_REG(0x3344), 1 << 1);
+
+ writel(0x0001c000, RCB_REG(0x3360));
+ writel(0x00061100, RCB_REG(0x3368));
+ writel(0x7f8fdfff, RCB_REG(0x3378));
+ writel(0x000003fc, RCB_REG(0x337c));
+ writel(0x00001000, RCB_REG(0x3388));
+ writel(0x0001c000, RCB_REG(0x3390));
+ writel(0x00000800, RCB_REG(0x33a0));
+ writel(0x00001000, RCB_REG(0x33b0));
+ writel(0x00093900, RCB_REG(0x33c0));
+ writel(0x24653002, RCB_REG(0x33cc));
+ writel(0x062108fe, RCB_REG(0x33d0));
+ clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
+ writel(0x01010000, RCB_REG(0x3a28));
+ writel(0x01010404, RCB_REG(0x3a2c));
+ writel(0x01041041, RCB_REG(0x3a80));
+ clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
+ setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
+ setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
+ writel(0x00000001, RCB_REG(0x3a6c));
+ clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
+ clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
+ writel(0, RCB_REG(0x33c8));
+ setbits_le32(RCB_REG(0x21b0), 0xf);
+}
+
+/* PantherPoint PCH Power Management init */
+static void ppt_pm_init(pci_dev_t dev)
+{
+ debug("PantherPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ setbits_le32(RCB_REG(0x2238), 1 << 0);
+ setbits_le32(RCB_REG(0x228c), 1 << 0);
+ setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
+ setbits_le16(RCB_REG(0x0900), 1 << 14);
+ writel(0xc03b8400, RCB_REG(0x2304));
+ setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
+ setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
+ clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
+ writel(0x054f0000, RCB_REG(0x3318));
+ writel(0x04000000, RCB_REG(0x3324));
+ setbits_le32(RCB_REG(0x3340), 0xfffff);
+ setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
+ writel(0x0001c000, RCB_REG(0x3360));
+ writel(0x00061100, RCB_REG(0x3368));
+ writel(0x7f8fdfff, RCB_REG(0x3378));
+ writel(0x000003fd, RCB_REG(0x337c));
+ writel(0x00001000, RCB_REG(0x3388));
+ writel(0x0001c000, RCB_REG(0x3390));
+ writel(0x00000800, RCB_REG(0x33a0));
+ writel(0x00001000, RCB_REG(0x33b0));
+ writel(0x00093900, RCB_REG(0x33c0));
+ writel(0x24653002, RCB_REG(0x33cc));
+ writel(0x067388fe, RCB_REG(0x33d0));
+ clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
+ writel(0x01010000, RCB_REG(0x3a28));
+ writel(0x01010404, RCB_REG(0x3a2c));
+ writel(0x01040000, RCB_REG(0x3a80));
+ clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
+ /* SATA 2/3 disabled */
+ setbits_le32(RCB_REG(0x3a84), 1 << 24);
+ /* SATA 4/5 disabled */
+ setbits_le32(RCB_REG(0x3a88), 1 << 0);
+ writel(0x00000001, RCB_REG(0x3a6c));
+ clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
+ clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
+ setbits_le32(RCB_REG(0x33a4), (1 << 0));
+ writel(0, RCB_REG(0x33c8));
+ setbits_le32(RCB_REG(0x21b0), 0xf);
+}
+
+static void enable_hpet(void)
+{
+ /* Move HPET to default address 0xfed00000 and enable it */
+ clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
+}
+
+static void enable_clock_gating(pci_dev_t dev)
+{
+ u32 reg32;
+ u16 reg16;
+
+ setbits_le32(RCB_REG(0x2234), 0xf);
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 |= (1 << 2) | (1 << 11);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
+ pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+
+ reg32 = readl(RCB_REG(CG));
+ reg32 |= (1 << 31);
+ reg32 |= (1 << 29) | (1 << 28);
+ reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+ reg32 |= (1 << 16);
+ reg32 |= (1 << 17);
+ reg32 |= (1 << 18);
+ reg32 |= (1 << 22);
+ reg32 |= (1 << 23);
+ reg32 &= ~(1 << 20);
+ reg32 |= (1 << 19);
+ reg32 |= (1 << 0);
+ reg32 |= (0xf << 1);
+ writel(reg32, RCB_REG(CG));
+
+ setbits_le32(RCB_REG(0x38c0), 0x7);
+ setbits_le32(RCB_REG(0x36d4), 0x6680c004);
+ setbits_le32(RCB_REG(0x3564), 0x3);
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void pch_lock_smm(pci_dev_t dev)
+{
+#if TEST_SMM_FLASH_LOCKDOWN
+ u8 reg8;
+#endif
+
+ if (acpi_slp_type != 3) {
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+ debug("Enabling ACPI via APMC:\n");
+ outb(0xe1, 0xb2); /* Enable ACPI mode */
+ debug("done.\n");
+#else
+ debug("Disabling ACPI via APMC:\n");
+ outb(0x1e, 0xb2); /* Disable ACPI mode */
+ debug("done.\n");
+#endif
+ }
+
+ /* Don't allow evil boot loaders, kernels, or
+ * userspace applications to deceive us:
+ */
+ smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+ /* Now try this: */
+ debug("Locking BIOS to RO... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+ reg8 &= ~(1 << 0); /* clear BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+ reg8 |= (1 << 1); /* set BLE */
+ pci_write_config8(dev, 0xdc, reg8);
+ debug("ok.\n");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+
+ debug("Writing:\n");
+ writeb(0, 0xfff00000);
+ debug("Testing:\n");
+ reg8 |= (1 << 0); /* set BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+ debug("Done.\n");
+#endif
+}
+#endif
+
+static void pch_disable_smm_only_flashing(pci_dev_t dev)
+{
+ u8 reg8;
+
+ debug("Enabling BIOS updates outside of SMM... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 &= ~(1 << 5);
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void pch_fixups(pci_dev_t dev)
+{
+ u8 gen_pmcon_2;
+
+ /* Indicate DRAM init done for MRC S3 to know it can resume */
+ gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
+ gen_pmcon_2 |= (1 << 7);
+ pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+
+ /* Enable DMI ASPM in the PCH */
+ clrbits_le32(RCB_REG(0x2304), 1 << 10);
+ setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
+ setbits_le32(RCB_REG(0x21a8), 0x3);
+}
+
int lpc_early_init(const void *blob, int node, pci_dev_t dev)
{
struct reg_info {
@@ -22,7 +472,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
int count;
int i;
- count = fdtdec_get_int_array_count(blob, node, "gen-dec",
+ count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
(u32 *)values, sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
@@ -46,3 +496,74 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
return 0;
}
+
+int lpc_init(struct pci_controller *hose, pci_dev_t dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ debug("pch: lpc_init\n");
+ pci_write_bar32(hose, dev, 0, 0);
+ pci_write_bar32(hose, dev, 1, 0xff800000);
+ pci_write_bar32(hose, dev, 2, 0xfec00000);
+ pci_write_bar32(hose, dev, 3, 0x800);
+ pci_write_bar32(hose, dev, 4, 0x900);
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+ if (node < 0)
+ return -ENOENT;
+
+ /* Set the value for PCI command register. */
+ pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+ /* IO APIC initialization. */
+ pch_enable_apic(dev);
+
+ pch_enable_serial_irqs(dev);
+
+ /* Setup the PIRQ. */
+ pch_pirq_init(blob, node, dev);
+
+ /* Setup power options. */
+ pch_power_options(blob, node, dev);
+
+ /* Initialize power management */
+ switch (pch_silicon_type()) {
+ case PCH_TYPE_CPT: /* CougarPoint */
+ cpt_pm_init(dev);
+ break;
+ case PCH_TYPE_PPT: /* PantherPoint */
+ ppt_pm_init(dev);
+ break;
+ default:
+ printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
+ PCI_FUNC(dev));
+ return -ENOSYS;
+ }
+
+ /* Initialize the real time clock. */
+ pch_rtc_init(dev);
+
+ /* Initialize the High Precision Event Timers, if present. */
+ enable_hpet();
+
+ /* Initialize Clock Gating */
+ enable_clock_gating(dev);
+
+ pch_disable_smm_only_flashing(dev);
+
+#if CONFIG_HAVE_SMI_HANDLER
+ pch_lock_smm(dev);
+#endif
+
+ pch_fixups(dev);
+
+ return 0;
+}
+
+void lpc_enable(pci_dev_t dev)
+{
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+}
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
new file mode 100644
index 0000000..11dc625
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -0,0 +1,514 @@
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/acpi.h>
+#include <asm/cpu.h>
+#include <asm/lapic.h>
+#include <asm/lapic_def.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm/speedstep.h>
+#include <asm/turbo.h>
+#include <asm/arch/model_206ax.h>
+
+static void enable_vmx(void)
+{
+ struct cpuid_result regs;
+#ifdef CONFIG_ENABLE_VMX
+ int enable = true;
+#else
+ int enable = false;
+#endif
+ msr_t msr;
+
+ regs = cpuid(1);
+ /* Check that the VMX is supported before reading or writing the MSR. */
+ if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
+ return;
+
+ msr = msr_read(MSR_IA32_FEATURE_CONTROL);
+
+ if (msr.lo & (1 << 0)) {
+ debug("VMX is locked, so %s will do nothing\n", __func__);
+ /* VMX locked. If we set it again we get an illegal
+ * instruction
+ */
+ return;
+ }
+
+ /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
+ * It must be cleared regardless of VMX config setting.
+ */
+ msr.hi = 0;
+ msr.lo = 0;
+
+ debug("%s VMX\n", enable ? "Enabling" : "Disabling");
+
+ /*
+ * Even though the Intel manual says you must set the lock bit in
+ * addition to the VMX bit in order for VMX to work, it is incorrect.
+ * Thus we leave it unlocked for the OS to manage things itself.
+ * This is good for a few reasons:
+ * - No need to reflash the bios just to toggle the lock bit.
+ * - The VMX bits really really should match each other across cores,
+ * so hard locking it on one while another has the opposite setting
+ * can easily lead to crashes as code using VMX migrates between
+ * them.
+ * - Vendors that want to "upsell" from a bios that disables+locks to
+ * one that doesn't is sleazy.
+ * By leaving this to the OS (e.g. Linux), people can do exactly what
+ * they want on the fly, and do it correctly (e.g. across multiple
+ * cores).
+ */
+ if (enable) {
+ msr.lo |= (1 << 2);
+ if (regs.ecx & CPUID_SMX)
+ msr.lo |= (1 << 1);
+ }
+
+ msr_write(MSR_IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+ [0] = 0x00,
+ [1] = 0x0a,
+ [2] = 0x0b,
+ [3] = 0x4b,
+ [4] = 0x0c,
+ [5] = 0x2c,
+ [6] = 0x4c,
+ [7] = 0x6c,
+ [8] = 0x0d,
+ [10] = 0x2d,
+ [12] = 0x4d,
+ [14] = 0x6d,
+ [16] = 0x0e,
+ [20] = 0x2e,
+ [24] = 0x4e,
+ [28] = 0x6e,
+ [32] = 0x0f,
+ [40] = 0x2f,
+ [48] = 0x4f,
+ [56] = 0x6f,
+ [64] = 0x10,
+ [80] = 0x30,
+ [96] = 0x50,
+ [112] = 0x70,
+ [128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+ [0x00] = 0,
+ [0x0a] = 1,
+ [0x0b] = 2,
+ [0x4b] = 3,
+ [0x0c] = 4,
+ [0x2c] = 5,
+ [0x4c] = 6,
+ [0x6c] = 7,
+ [0x0d] = 8,
+ [0x2d] = 10,
+ [0x4d] = 12,
+ [0x6d] = 14,
+ [0x0e] = 16,
+ [0x2e] = 20,
+ [0x4e] = 24,
+ [0x6e] = 28,
+ [0x0f] = 32,
+ [0x2f] = 40,
+ [0x4f] = 48,
+ [0x6f] = 56,
+ [0x10] = 64,
+ [0x30] = 80,
+ [0x50] = 96,
+ [0x70] = 112,
+ [0x11] = 128,
+};
+
+int cpu_config_tdp_levels(void)
+{
+ struct cpuid_result result;
+ msr_t platform_info;
+
+ /* Minimum CPU revision */
+ result = cpuid(1);
+ if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
+ return 0;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+ msr_t msr = msr_read(MSR_PLATFORM_INFO);
+ msr_t limit;
+ unsigned power_unit;
+ unsigned tdp, min_power, max_power, max_time;
+ u8 power_limit_1_val;
+
+ if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+ return;
+
+ if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+ return;
+
+ /* Get units */
+ msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+ /* Get power defaults for this SKU */
+ msr = msr_read(MSR_PKG_POWER_SKU);
+ tdp = msr.lo & 0x7fff;
+ min_power = (msr.lo >> 16) & 0x7fff;
+ max_power = msr.hi & 0x7fff;
+ max_time = (msr.hi >> 16) & 0x7f;
+
+ debug("CPU TDP: %u Watts\n", tdp / power_unit);
+
+ if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+ power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+ if (min_power > 0 && tdp < min_power)
+ tdp = min_power;
+
+ if (max_power > 0 && tdp > max_power)
+ tdp = max_power;
+
+ power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+ /* Set long term power limit to TDP */
+ limit.lo = 0;
+ limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+ limit.lo |= PKG_POWER_LIMIT_EN;
+ limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+ PKG_POWER_LIMIT_TIME_SHIFT;
+
+ /* Set short term power limit to 1.25 * TDP */
+ limit.hi = 0;
+ limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+ limit.hi |= PKG_POWER_LIMIT_EN;
+ /* Power limit 2 time is only programmable on SNB EP/EX */
+
+ msr_write(MSR_PKG_POWER_LIMIT, limit);
+
+ /* Use nominal TDP values for CPUs with configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ limit.hi = 0;
+ limit.lo = msr.lo & 0xff;
+ msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
+ }
+}
+
+static void configure_c_states(void)
+{
+ struct cpuid_result result;
+ msr_t msr;
+
+ msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
+ msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
+ msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
+ msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
+ msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
+ msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
+ msr.lo |= 7; /* No package C-state limit */
+ msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
+
+ msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
+ msr.lo &= ~0x7ffff;
+ msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
+ msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
+ msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
+
+ msr = msr_read(MSR_MISC_PWR_MGMT);
+ msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
+ msr_write(MSR_MISC_PWR_MGMT, msr);
+
+ msr = msr_read(MSR_POWER_CTL);
+ msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
+ msr.lo |= (1 << 1); /* C1E Enable */
+ msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
+ msr_write(MSR_POWER_CTL, msr);
+
+ /* C3 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+ msr_write(MSR_PKGC3_IRTL, msr);
+
+ /* C6 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+ msr_write(MSR_PKGC6_IRTL, msr);
+
+ /* C7 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+ msr_write(MSR_PKGC7_IRTL, msr);
+
+ /* Primary Plane Current Limit */
+ msr = msr_read(MSR_PP0_CURRENT_CONFIG);
+ msr.lo &= ~0x1fff;
+ msr.lo |= PP0_CURRENT_LIMIT;
+ msr_write(MSR_PP0_CURRENT_CONFIG, msr);
+
+ /* Secondary Plane Current Limit */
+ msr = msr_read(MSR_PP1_CURRENT_CONFIG);
+ msr.lo &= ~0x1fff;
+ result = cpuid(1);
+ if (result.eax >= 0x30600)
+ msr.lo |= PP1_CURRENT_LIMIT_IVB;
+ else
+ msr.lo |= PP1_CURRENT_LIMIT_SNB;
+ msr_write(MSR_PP1_CURRENT_CONFIG, msr);
+}
+
+static int configure_thermal_target(void)
+{
+ int tcc_offset;
+ msr_t msr;
+ int node;
+
+ /* Find pointer to CPU configuration */
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_INTEL_MODEL_206AX);
+ if (node < 0)
+ return -ENOENT;
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
+
+ /* Set TCC activaiton offset if supported */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && tcc_offset) {
+ msr = msr_read(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (tcc_offset & 0xf) << 24;
+ msr_write(MSR_TEMPERATURE_TARGET, msr);
+ }
+
+ return 0;
+}
+
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = msr_read(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr_write(IA32_MISC_ENABLE, msr);
+
+ /* Disable Thermal interrupts */
+ msr.lo = 0;
+ msr.hi = 0;
+ msr_write(IA32_THERM_INTERRUPT, msr);
+
+ /* Enable package critical interrupt only */
+ msr.lo = 1 << 4;
+ msr.hi = 0;
+ msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ msr_write(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+ struct cpuid_result cpuid_regs;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ cpuid_regs = cpuid(1);
+ if (cpuid_regs.ecx & (1 << 18)) {
+ msr = msr_read(IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ msr_write(IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+static void set_max_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ perf_ctl.hi = 0;
+
+ /* Check for configurable TDP option */
+ if (cpu_config_tdp_levels()) {
+ /* Set to nominal TDP ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info bits 15:8 give max ratio */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+ msr_write(IA32_PERF_CTL, perf_ctl);
+
+ debug("model_x06ax: frequency set to %d\n",
+ ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+ msr_t msr;
+
+ /* Energy Policy is bits 3:0 */
+ msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
+ msr.lo &= ~0xf;
+ msr.lo |= policy & 0xf;
+ msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+ debug("model_x06ax: energy policy set to %u\n", policy);
+}
+
+static void configure_mca(void)
+{
+ msr_t msr;
+ int i;
+
+ msr.lo = 0;
+ msr.hi = 0;
+ /* This should only be done on a cold boot */
+ for (i = 0; i < 7; i++)
+ msr_write(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static int intel_cores_init(struct x86_cpu_priv *cpu)
+{
+ struct cpuid_result result;
+ unsigned threads_per_package, threads_per_core, i;
+
+ /* Logical processors (threads) per core */
+ result = cpuid_ext(0xb, 0);
+ threads_per_core = result.ebx & 0xffff;
+
+ /* Logical processors (threads) per package */
+ result = cpuid_ext(0xb, 1);
+ threads_per_package = result.ebx & 0xffff;
+
+ debug("CPU: %u has %u cores, %u threads per core\n",
+ cpu->apic_id, threads_per_package / threads_per_core,
+ threads_per_core);
+
+ for (i = 1; i < threads_per_package; ++i) {
+ struct x86_cpu_priv *new_cpu;
+
+ new_cpu = calloc(1, sizeof(*new_cpu));
+ if (!new_cpu)
+ return -ENOMEM;
+
+ new_cpu->apic_id = cpu->apic_id + i;
+
+ /* Update APIC ID if no hyperthreading */
+ if (threads_per_core == 1)
+ new_cpu->apic_id <<= 1;
+
+ debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
+
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+ /* Start the new cpu */
+ if (!start_cpu(new_cpu)) {
+ /* Record the error in cpu? */
+ printk(BIOS_ERR, "CPU %u would not start!\n",
+ new_cpu->apic_id);
+ new_cpu->start_err = 1;
+ }
+#endif
+ }
+
+ return 0;
+}
+
+int model_206ax_init(struct x86_cpu_priv *cpu)
+{
+ int ret;
+
+ /* Clear out pending MCEs */
+ configure_mca();
+
+#if CONFIG_USBDEBUG
+ /* Is this caution really needed? */
+ if (!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
+#endif
+
+ /* Setup MTRRs based on physical address size */
+#if 0 /* TODO: Implement this */
+ struct cpuid_result cpuid_regs;
+
+ cpuid_regs = cpuid(0x80000008);
+ x86_setup_fixed_mtrrs();
+ x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+ x86_mtrr_check();
+#endif
+
+#if CONFIG_USBDEBUG
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Enable the local cpu apics */
+ enable_lapic_tpr();
+ lapic_setup();
+
+ /* Enable virtualization if enabled in CMOS */
+ enable_vmx();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* Thermal throttle activation offset */
+ ret = configure_thermal_target();
+ if (ret)
+ return ret;
+
+ /* Enable Direct Cache Access */
+ configure_dca_cap();
+
+ /* Set energy policy */
+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+ /* Set Max Ratio */
+ set_max_ratio();
+
+ /* Enable Turbo */
+ turbo_enable();
+
+ /* Start up extra cores */
+ intel_cores_init(cpu);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
new file mode 100644
index 0000000..c50b5de
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -0,0 +1,188 @@
+/*
+ * From Coreboot northbridge/intel/sandybridge/northbridge.c
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/acpi.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/sandybridge.h>
+
+static int bridge_revision_id = -1;
+
+int bridge_silicon_revision(void)
+{
+ if (bridge_revision_id < 0) {
+ struct cpuid_result result;
+ uint8_t stepping, bridge_id;
+ pci_dev_t dev;
+
+ result = cpuid(1);
+ stepping = result.eax & 0xf;
+ dev = PCI_BDF(0, 0, 0);
+ bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
+ bridge_revision_id = bridge_id | stepping;
+ }
+
+ return bridge_revision_id;
+}
+
+/*
+ * Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+ pci_dev_t dev = PCI_BDF(0, 0, 0);
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: /* 256MB */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static void add_fixed_resources(pci_dev_t dev, int index)
+{
+ u32 pcie_config_base, pcie_config_size;
+
+ if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
+ pcie_config_base, pcie_config_size);
+ }
+}
+
+static void northbridge_dmi_init(pci_dev_t dev)
+{
+ /* Clear error status bits */
+ writel(0xffffffff, DMIBAR_REG(0x1c4));
+ writel(0xffffffff, DMIBAR_REG(0x1d0));
+
+ /* Steps prior to DMI ASPM */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
+ 1 << 21);
+ }
+
+ setbits_le32(DMIBAR_REG(0x238), 1 << 29);
+
+ if (bridge_silicon_revision() >= SNB_STEP_D0) {
+ setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
+ } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
+ clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
+ setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
+ }
+
+ /* Enable ASPM on SNB link, should happen before PCH link */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
+ setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
+
+ setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
+}
+
+void northbridge_init(pci_dev_t dev)
+{
+ u32 bridge_type;
+
+ add_fixed_resources(dev, 6);
+ northbridge_dmi_init(dev);
+
+ bridge_type = readl(MCHBAR_REG(0x5f10));
+ bridge_type &= ~0xff;
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /* Enable Power Aware Interrupt Routing - fixed priority */
+ clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
+
+ /* 30h for IvyBridge */
+ bridge_type |= 0x30;
+ } else {
+ /* 20h for Sandybridge */
+ bridge_type |= 0x20;
+ }
+ writel(bridge_type, MCHBAR_REG(0x5f10));
+
+ /*
+ * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+ * that BIOS has initialized memory and power management
+ */
+ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
+ debug("Set BIOS_RESET_CPL\n");
+
+ /* Configure turbo power limits 1ms after reset complete bit */
+ mdelay(1);
+ set_power_limits(28);
+
+ /*
+ * CPUs with configurable TDP also need power limits set
+ * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
+ */
+ if (cpu_config_tdp_levels()) {
+ msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
+
+ writel(msr.lo, MCHBAR_REG(0x59A0));
+ writel(msr.hi, MCHBAR_REG(0x59A4));
+ }
+
+ /* Set here before graphics PM init */
+ writel(0x00100001, MCHBAR_REG(0x5500));
+}
+
+void northbridge_enable(pci_dev_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ debug("Normal boot.\n");
+ apci_set_slp_type(0);
+ break;
+ case 0xcafed00d:
+ debug("S3 Resume.\n");
+ apci_set_slp_type(3);
+ break;
+ default:
+ debug("Unknown boot method, assuming normal.\n");
+ apci_set_slp_type(0);
+ break;
+ }
+#endif
+}
diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c
new file mode 100644
index 0000000..fa04d48
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/pch.c
@@ -0,0 +1,123 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+static int pch_revision_id = -1;
+static int pch_type = -1;
+
+int pch_silicon_revision(void)
+{
+ pci_dev_t dev;
+
+ dev = PCH_LPC_DEV;
+
+ if (pch_revision_id < 0)
+ pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
+ return pch_revision_id;
+}
+
+int pch_silicon_type(void)
+{
+ pci_dev_t dev;
+
+ dev = PCH_LPC_DEV;
+
+ if (pch_type < 0)
+ pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
+ return pch_type;
+}
+
+int pch_silicon_supported(int type, int rev)
+{
+ int cur_type = pch_silicon_type();
+ int cur_rev = pch_silicon_revision();
+
+ switch (type) {
+ case PCH_TYPE_CPT:
+ /* CougarPoint minimum revision */
+ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+ return 1;
+ /* PantherPoint any revision */
+ if (cur_type == PCH_TYPE_PPT)
+ return 1;
+ break;
+
+ case PCH_TYPE_PPT:
+ /* PantherPoint minimum revision */
+ if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+ unsigned try = IOBP_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = readl(RCB_REG(IOBPS));
+ if ((data & 1) == 0)
+ return 1;
+ udelay(10);
+ }
+
+ printf("IOBP timeout\n");
+ return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+ u32 data;
+
+ /* Set the address */
+ writel(address, RCB_REG(IOBPIRI));
+
+ /* READ OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_READ_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Read IOBP data */
+ data = readl(RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+
+ /* Check for successful transaction */
+ if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
+ printf("IOBP read 0x%08x failed\n", address);
+ return;
+ }
+
+ /* Update the data */
+ data &= andvalue;
+ data |= orvalue;
+
+ /* WRITE OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Write IOBP data */
+ writel(data, RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+}
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index c1ae658..452d1c3 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -12,6 +12,8 @@
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/pch.h>
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
@@ -58,3 +60,41 @@ void board_pci_setup_hose(struct pci_controller *hose)
hose->region_count = 3;
}
+
+int board_pci_pre_scan(struct pci_controller *hose)
+{
+ pci_dev_t dev;
+ u16 reg16;
+
+ bd82x6x_init();
+
+ reg16 = 0xff;
+ dev = PCH_DEV;
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+ pci_write_bar32(hose, dev, 0, 0xf0000000);
+
+ return 0;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ int ret;
+
+ ret = bd82x6x_init_pci_devices();
+ if (ret) {
+ printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
new file mode 100644
index 0000000..bbcd47d
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -0,0 +1,225 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/bd82x6x.h>
+
+static inline u32 sir_read(pci_dev_t dev, int idx)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ pci_write_config32(dev, SATA_SIRD, value);
+}
+
+static void common_sata_init(pci_dev_t dev, unsigned int port_map)
+{
+ u32 reg32;
+ u16 reg16;
+
+ /* Set IDE I/O Configuration */
+ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ pci_write_config32(dev, IDE_CONFIG, reg32);
+
+ /* Port enable */
+ reg16 = pci_read_config16(dev, 0x92);
+ reg16 &= ~0x3f;
+ reg16 |= port_map;
+ pci_write_config16(dev, 0x92, reg16);
+
+ /* SATA Initialization register */
+ port_map &= 0xff;
+ pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
+}
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+{
+ unsigned int port_map, speed_support, port_tx;
+ struct pci_controller *hose = pci_bus_to_hose(0);
+ const char *mode;
+ u32 reg32;
+ u16 reg16;
+
+ debug("SATA: Initializing...\n");
+
+ /* SATA configuration */
+ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+ speed_support = fdtdec_get_int(blob, node,
+ "sata_interface_speed_support", 0);
+
+ /* Enable BARs */
+ pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+ mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+ if (!mode || !strcmp(mode, "ahci")) {
+ u32 abar;
+
+ debug("SATA: Controller in AHCI mode\n");
+
+ /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0x0a);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+ common_sata_init(dev, 0x8000 | port_map);
+
+ /* Initialize AHCI memory-mapped space */
+ abar = pci_read_bar32(hose, dev, 5);
+ debug("ABAR: %08X\n", abar);
+ /* CAP (HBA Capabilities) : enable power management */
+ reg32 = readl(abar + 0x00);
+ reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
+ reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
+ /* Set ISS, if available */
+ if (speed_support) {
+ reg32 &= ~0x00f00000;
+ reg32 |= (speed_support & 0x03) << 20;
+ }
+ writel(reg32, abar + 0x00);
+ /* PI (Ports implemented) */
+ writel(port_map, abar + 0x0c);
+ (void) readl(abar + 0x0c); /* Read back 1 */
+ (void) readl(abar + 0x0c); /* Read back 2 */
+ /* CAP2 (HBA Capabilities Extended)*/
+ reg32 = readl(abar + 0x24);
+ reg32 &= ~0x00000002;
+ writel(reg32, abar + 0x24);
+ /* VSP (Vendor Specific Register */
+ reg32 = readl(abar + 0xa0);
+ reg32 &= ~0x00000005;
+ writel(reg32, abar + 0xa0);
+ } else if (!strcmp(mode, "combined")) {
+ debug("SATA: Controller in combined mode\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_bar32(hose, dev, 5, 0x00000000);
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ pci_write_config8(dev, 0x09, 0x80);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+ common_sata_init(dev, port_map);
+ } else {
+ debug("SATA: Controller in plain-ide mode\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_bar32(hose, dev, 5, 0x00000000);
+
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /*
+ * Native mode capable on both primary and secondary (0xa)
+ * OR'ed with enabled (0x50) = 0xf
+ */
+ pci_write_config8(dev, 0x09, 0x8f);
+
+ /* Set Interrupt Line */
+ /* Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0xff);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_SITRE | IDE_ISP_3_CLOCKS |
+ IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+ common_sata_init(dev, port_map);
+ }
+
+ /* Set Gen3 Transmitter settings if needed */
+ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
+ if (port_tx)
+ pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
+
+ port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
+ if (port_tx)
+ pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
+
+ /* Additional Programming Requirements */
+ sir_write(dev, 0x04, 0x00001600);
+ sir_write(dev, 0x28, 0xa0000033);
+ reg32 = sir_read(dev, 0x54);
+ reg32 &= 0xff000000;
+ reg32 |= 0x5555aa;
+ sir_write(dev, 0x54, reg32);
+ sir_write(dev, 0x64, 0xcccc8484);
+ reg32 = sir_read(dev, 0x68);
+ reg32 &= 0xffff0000;
+ reg32 |= 0xcccc;
+ sir_write(dev, 0x68, reg32);
+ reg32 = sir_read(dev, 0x78);
+ reg32 &= 0x0000ffff;
+ reg32 |= 0x88880000;
+ sir_write(dev, 0x78, reg32);
+ sir_write(dev, 0x84, 0x001c7000);
+ sir_write(dev, 0x88, 0x88338822);
+ sir_write(dev, 0xa0, 0x001c7000);
+ sir_write(dev, 0xc4, 0x0c0c0c0c);
+ sir_write(dev, 0xc8, 0x0c0c0c0c);
+ sir_write(dev, 0xd4, 0x10000000);
+
+ pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+ pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
+}
+
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+{
+ unsigned port_map;
+ const char *mode;
+ u16 map = 0;
+
+ /*
+ * Set SATA controller mode early so the resource allocator can
+ * properly assign IO/Memory resources for the controller.
+ */
+ mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+ if (mode && !strcmp(mode, "ahci"))
+ map = 0x0060;
+ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+
+ map |= (port_map ^ 0x3f) << 8;
+ pci_write_config16(dev, 0x90, map);
+}
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c
new file mode 100644
index 0000000..291c971
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/usb_ehci.c
@@ -0,0 +1,29 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_ehci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ /* Disable Wake on Disconnect in RMH */
+ reg32 = readl(RCB_REG(0x35b0));
+ reg32 |= 0x22;
+ writel(reg32, RCB_REG(0x35b0));
+
+ debug("EHCI: Setting up controller.. ");
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ /* reg32 |= PCI_COMMAND_SERR; */
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ debug("done.\n");
+}
diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c
new file mode 100644
index 0000000..4a32a7e
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/usb_xhci.c
@@ -0,0 +1,32 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_xhci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ debug("XHCI: Setting up controller.. ");
+
+ /* lock overcurrent map */
+ reg32 = pci_read_config32(dev, 0x44);
+ reg32 |= 1;
+ pci_write_config32(dev, 0x44, reg32);
+
+ /* Enable clock gating */
+ reg32 = pci_read_config32(dev, 0x40);
+ reg32 &= ~((1 << 20) | (1 << 21));
+ reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
+ reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
+ reg32 |= (1 << 31); /* lock */
+ pci_write_config32(dev, 0x40, reg32);
+
+ debug("done.\n");
+}
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
new file mode 100644
index 0000000..4690603
--- /dev/null
+++ b/arch/x86/cpu/lapic.c
@@ -0,0 +1,57 @@
+/*
+ * From coreboot file of same name
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/post.h>
+
+void lapic_setup(void)
+{
+#if NEED_LAPIC == 1
+ /* Only Pentium Pro and later have those MSR stuff */
+ debug("Setting up local apic: ");
+
+ /* Enable the local apic */
+ enable_lapic();
+
+ /*
+ * Set Task Priority to 'accept all'.
+ */
+ lapic_write_around(LAPIC_TASKPRI,
+ lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
+
+ /* Put the local apic in virtual wire mode */
+ lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
+ ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+ lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_EXTINT));
+ lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_NMI));
+
+ debug("apic_id: 0x%02lx, ", lapicid());
+#else /* !NEED_LLAPIC */
+ /* Only Pentium Pro and later have those MSR stuff */
+ debug("Disabling local apic: ");
+ disable_lapic();
+#endif /* !NEED_LAPIC */
+ debug("done.\n");
+ post_code(POST_LAPIC);
+}
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index e399388..f3492c3 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -33,6 +33,16 @@ int pci_early_init_hose(struct pci_controller **hosep)
return 0;
}
+__weak int board_pci_pre_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
+__weak int board_pci_post_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
void pci_init_board(void)
{
struct pci_controller *hose = &x86_hose;
@@ -44,7 +54,9 @@ void pci_init_board(void)
pci_setup_type1(hose);
pci_register_hose(hose);
+ board_pci_pre_scan(hose);
hose->last_busno = pci_hose_scan(hose);
+ board_pci_post_scan(hose);
}
static struct pci_controller *get_hose(void)
diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c
new file mode 100644
index 0000000..254d0de
--- /dev/null
+++ b/arch/x86/cpu/turbo.c
@@ -0,0 +1,98 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 The Chromium Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+#include <asm/turbo.h>
+
+#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+static inline int get_global_turbo_state(void)
+{
+ return TURBO_UNKNOWN;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+}
+#else
+static int g_turbo_state = TURBO_UNKNOWN;
+
+static inline int get_global_turbo_state(void)
+{
+ return g_turbo_state;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+ g_turbo_state = state;
+}
+#endif
+
+static const char *const turbo_state_desc[] = {
+ [TURBO_UNKNOWN] = "unknown",
+ [TURBO_UNAVAILABLE] = "unavailable",
+ [TURBO_DISABLED] = "available but hidden",
+ [TURBO_ENABLED] = "available and visible"
+};
+
+/*
+ * Determine the current state of Turbo and cache it for later.
+ * Turbo is a package level config so it does not need to be
+ * enabled on every core.
+ */
+int turbo_get_state(void)
+{
+ struct cpuid_result cpuid_regs;
+ int turbo_en, turbo_cap;
+ msr_t msr;
+ int turbo_state = get_global_turbo_state();
+
+ /* Return cached state if available */
+ if (turbo_state != TURBO_UNKNOWN)
+ return turbo_state;
+
+ cpuid_regs = cpuid(CPUID_LEAF_PM);
+ turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
+
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+
+ if (!turbo_cap && turbo_en) {
+ /* Unavailable */
+ turbo_state = TURBO_UNAVAILABLE;
+ } else if (!turbo_cap && !turbo_en) {
+ /* Available but disabled */
+ turbo_state = TURBO_DISABLED;
+ } else if (turbo_cap && turbo_en) {
+ /* Available */
+ turbo_state = TURBO_ENABLED;
+ }
+
+ set_global_turbo_state(turbo_state);
+ debug("Turbo is %s\n", turbo_state_desc[turbo_state]);
+ return turbo_state;
+}
+
+void turbo_enable(void)
+{
+ msr_t msr;
+
+ /* Only possible if turbo is available but hidden */
+ if (turbo_get_state() == TURBO_DISABLED) {
+ /* Clear Turbo Disable bit in Misc Enables */
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ msr.hi &= ~H_MISC_DISABLE_TURBO;
+ msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+ /* Update cached turbo state */
+ set_global_turbo_state(TURBO_ENABLED);
+ debug("Turbo has been enabled\n");
+ }
+}
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index f48bff5..b0d8531 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -44,7 +44,9 @@ SECTIONS
. = ALIGN(4);
__rel_dyn_start = .;
- .rel.dyn : { *(.rel.dyn) }
+ .rel.dyn : {
+ *(.rel*)
+ }
__rel_dyn_end = .;
. = ALIGN(4);
_end = .;
@@ -64,15 +66,19 @@ SECTIONS
/DISCARD/ : { *(.gnu*) }
#ifdef CONFIG_X86_RESET_VECTOR
-
/*
* The following expressions place the 16-bit Real-Mode code and
* Reset Vector at the end of the Flash ROM
*/
- . = START_16;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
+ . = START_16 - RESET_SEG_START;
+ .start16 : AT (START_16) {
+ KEEP(*(.start16));
+ }
- . = RESET_VEC_LOC;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
+ . = RESET_VEC_LOC - RESET_SEG_START;
+ .resetvec : AT (RESET_VEC_LOC) {
+ KEEP(*(.resetvec));
+ }
#endif
+
}
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 9329916..592af16 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -163,21 +163,51 @@
};
};
- lpc {
- compatible = "intel,lpc";
- #address-cells = <1>;
- #size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- cros-ec@200 {
- compatible = "google,cros-ec";
- reg = <0x204 1 0x200 1 0x880 0x80>;
+ pci {
+ sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+ };
+
+ gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+ };
- /* This describes the flash memory within the EC */
+ lpc {
+ compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- flash@8000000 {
- reg = <0x08000000 0x20000>;
- erase-value = <0xff>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
+
+ cros-ec@200 {
+ compatible = "google,cros-ec";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /* Describes the flash memory within the EC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
};
};
};
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
new file mode 100644
index 0000000..4872b92
--- /dev/null
+++ b/arch/x86/include/asm/acpi.h
@@ -0,0 +1,24 @@
+/*
+ * From coreboot
+ *
+ * Copyright (C) 2004 SUSE LINUX AG
+ * Copyright (C) 2004 Nick Barker
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan@coresystems.de>)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ACPI_H
+#define __ASM_ACPI_H
+
+#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
+#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */
+#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */
+#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */
+
+/* 0 = S0, 1 = S1 ...*/
+int acpi_get_slp_type(void);
+void apci_set_slp_type(int type);
+
+#endif
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h
index 8e4a61d..832c50a 100644
--- a/arch/x86/include/asm/arch-coreboot/sysinfo.h
+++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h
@@ -10,7 +10,7 @@
#define _COREBOOT_SYSINFO_H
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <libfdt.h>
#include <asm/arch/tables.h>
diff --git a/arch/x86/include/asm/arch-coreboot/tables.h b/arch/x86/include/asm/arch-coreboot/tables.h
index 0d02fe0..e254484 100644
--- a/arch/x86/include/asm/arch-coreboot/tables.h
+++ b/arch/x86/include/asm/arch-coreboot/tables.h
@@ -9,7 +9,7 @@
#ifndef _COREBOOT_TABLES_H
#define _COREBOOT_TABLES_H
-#include <compiler.h>
+#include <linux/compiler.h>
struct cbuint64 {
u32 lo;
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
new file mode 100644
index 0000000..e1d9a9b
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_BD82X6X_H
+#define _ASM_ARCH_BD82X6X_H
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_pci_init(pci_dev_t dev);
+void bd82x6x_usb_ehci_init(pci_dev_t dev);
+void bd82x6x_usb_xhci_init(pci_dev_t dev);
+int bd82x6x_init_pci_devices(void);
+int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
+ const void *blob, int node);
+int bd82x6x_init(void);
+
+struct x86_cpu_priv;
+int model_206ax_init(struct x86_cpu_priv *cpu);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
index 8281d7a..7b4f2e7 100644
--- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -79,4 +79,8 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+
#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index c6efdb8..21df083 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -14,11 +14,41 @@
#include <pci.h>
+/* PCH types */
+#define PCH_TYPE_CPT 0x1c /* CougarPoint */
+#define PCH_TYPE_PPT 0x1e /* IvyBridge */
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0 0
+#define PCH_STEP_A1 1
+#define PCH_STEP_B0 2
+#define PCH_STEP_B1 3
+#define PCH_STEP_B2 4
+#define PCH_STEP_B3 5
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#define SMBUS_IO_BASE 0x0400
+int pch_silicon_revision(void);
+int pch_silicon_type(void);
+int pch_silicon_supported(int type, int rev);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
@@ -30,6 +60,35 @@
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
@@ -63,6 +122,64 @@
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
+
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
+#define IDE_DECODE_ENABLE (1 << 15)
+#define IDE_SITRE (1 << 14)
+#define IDE_ISP_5_CLOCKS (0 << 12)
+#define IDE_ISP_4_CLOCKS (1 << 12)
+#define IDE_ISP_3_CLOCKS (2 << 12)
+#define IDE_RCT_4_CLOCKS (0 << 8)
+#define IDE_RCT_3_CLOCKS (1 << 8)
+#define IDE_RCT_2_CLOCKS (2 << 8)
+#define IDE_RCT_1_CLOCKS (3 << 8)
+#define IDE_DTE1 (1 << 7)
+#define IDE_PPE1 (1 << 6)
+#define IDE_IE1 (1 << 5)
+#define IDE_TIME1 (1 << 4)
+#define IDE_DTE0 (1 << 3)
+#define IDE_PPE0 (1 << 2)
+#define IDE_IE0 (1 << 1)
+#define IDE_TIME0 (1 << 0)
+#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
+
+#define IDE_SDMA_TIM 0x4a
+
+#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
+
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
+#define SATA_SP 0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+
/* PCI Configuration Space (D31:F3): SMBus */
#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
#define SMB_BASE 0x20
@@ -343,6 +460,9 @@
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
+int lpc_init(struct pci_controller *hose, pci_dev_t dev);
+void lpc_enable(pci_dev_t dev);
+
/**
* lpc_early_init() - set up LPC serial ports and other early things
*
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index 114ee19..cf7457f 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -97,11 +97,22 @@
/*
* MCHBAR
*/
-#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg))
+#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
+
+int bridge_silicon_revision(void);
+
+void northbridge_enable(pci_dev_t dev);
+void northbridge_init(pci_dev_t dev);
+
void report_platform_info(void);
void sandybridge_early_init(int chipset_type);
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h
index 73113f9..bc4033b 100644
--- a/arch/x86/include/asm/i8259.h
+++ b/arch/x86/include/asm/i8259.h
@@ -69,4 +69,6 @@
#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
#define ICW4_PM 0x01 /* Microprocessor Mode */
+int i8259_init(void);
+
#endif
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index 3f46e09..25abde7 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -27,4 +27,15 @@ void specific_eoi(int irq);
extern char exception_stack[];
+/**
+ * configure_irq_trigger() - Configure IRQ triggering
+ *
+ * Switch the given interrupt to be level / edge triggered
+ *
+ * @param int_num legacy interrupt number (3-7, 9-15)
+ * @param is_level_triggered true for level triggered interrupt, false for
+ * edge triggered interrupt
+ */
+void configure_irq_trigger(int int_num, bool is_level_triggered);
+
#endif
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index fcd9aa9..e0b2561 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -1,7 +1,7 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#include <compiler.h>
+#include <linux/compiler.h>
/*
* This file contains the definitions for the x86 IO instructions
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
new file mode 100644
index 0000000..699160f
--- /dev/null
+++ b/arch/x86/include/asm/ioapic.h
@@ -0,0 +1,38 @@
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_IOAPIC_H
+#define __ASM_IOAPIC_H
+
+#define IO_APIC_ADDR 0xfec00000
+#define IO_APIC_INDEX IO_APIC_ADDR
+#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
+#define IO_APIC_INTERRUPTS 24
+
+#define ALL (0xff << 24)
+#define NONE 0
+#define DISABLED (1 << 16)
+#define ENABLED (0 << 16)
+#define TRIGGER_EDGE (0 << 15)
+#define TRIGGER_LEVEL (1 << 15)
+#define POLARITY_HIGH (0 << 13)
+#define POLARITY_LOW (1 << 13)
+#define PHYSICAL_DEST (0 << 11)
+#define LOGICAL_DEST (1 << 11)
+#define ExtINT (7 << 8)
+#define NMI (4 << 8)
+#define SMI (2 << 8)
+#define INT (1 << 8)
+
+u32 io_apic_read(u32 ioapic_base, u32 reg);
+void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
+void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
+void clear_ioapic(u32 ioapic_base);
+
+#endif
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
index 948e643..0a7f443 100644
--- a/arch/x86/include/asm/lapic.h
+++ b/arch/x86/include/asm/lapic.h
@@ -14,6 +14,13 @@
#include <asm/msr.h>
#include <asm/processor.h>
+/* See if I need to initialize the local apic */
+#if CONFIG_SMP || CONFIG_IOAPIC
+# define NEED_LAPIC 1
+#else
+# define NEED_LAPIC 0
+#endif
+
static inline __attribute__((always_inline))
unsigned long lapic_read(unsigned long reg)
{
@@ -37,8 +44,9 @@ static inline void enable_lapic(void)
msr = msr_read(LAPIC_BASE_MSR);
msr.hi &= 0xffffff00;
- msr.lo &= 0x000007ff;
- msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
+ msr.lo |= LAPIC_BASE_MSR_ENABLE;
+ msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+ msr.lo |= LAPIC_DEFAULT_BASE;
msr_write(LAPIC_BASE_MSR, msr);
}
@@ -56,4 +64,116 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
return lapic_read(LAPIC_ID) >> 24;
}
+#if !CONFIG_AP_IN_SIPI_WAIT
+/* If we need to go back to sipi wait, we use the long non-inlined version of
+ * this function in lapic_cpu_init.c
+ */
+static inline __attribute__((always_inline)) void stop_this_cpu(void)
+{
+ /* Called by an AP when it is ready to halt and wait for a new task */
+ for (;;)
+ cpu_hlt();
+}
+#else
+void stop_this_cpu(void);
+#endif
+
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr))))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ * but generally the primitive is invalid, *ptr is output argument. --ANK
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+ int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__("xchgb %b0,%1"
+ : "=q" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__("xchgw %w0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__("xchgl %0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ }
+
+ return x;
+}
+
+static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
+{
+ (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
+}
+
+
+#ifdef X86_GOOD_APIC
+# define FORCE_READ_AROUND_WRITE 0
+# define lapic_read_around(x) lapic_read(x)
+# define lapic_write_around(x, y) lapic_write((x), (y))
+#else
+# define FORCE_READ_AROUND_WRITE 1
+# define lapic_read_around(x) lapic_read(x)
+# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
+#endif
+
+static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
+{
+ int timeout;
+ unsigned long status;
+ int result;
+ lapic_wait_icr_idle();
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+ lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+ timeout = 0;
+ do {
+ status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+ } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+
+ result = -1;
+ if (status == LAPIC_ICR_RR_VALID) {
+ *pvalue = lapic_read(LAPIC_RRR);
+ result = 0;
+ }
+ return result;
+}
+
+
+void lapic_setup(void);
+
+#if CONFIG_SMP
+struct device;
+int start_cpu(struct device *cpu);
+#endif /* CONFIG_SMP */
+
+int boot_cpu(void);
+
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+ int apic_id;
+ int start_err;
+};
+
#endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6027d59..2cbb270 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -326,6 +326,8 @@
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PERF_CTL 0xc0010062
+#define MSR_PMG_CST_CONFIG_CTL 0x000000e2
+#define MSR_PMG_IO_CAPTURE_ADR 0x000000e4
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index df43983..1955a75 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -229,17 +229,6 @@ do { \
struct msr *msrs_alloc(void);
void msrs_free(struct msr *msrs);
-#ifdef CONFIG_SMP
-int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
-void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
-int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
-int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
-
-#endif /* CONFIG_SMP */
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_X86_MSR_H */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 98817aa..ac1a808 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -34,6 +34,9 @@ void board_pci_setup_hose(struct pci_controller *hose);
*/
int pci_early_init_hose(struct pci_controller **hosep);
+int board_pci_pre_scan(struct pci_controller *hose);
+int board_pci_post_scan(struct pci_controller *hose);
+
/*
* Simple PCI access routines - these work from either the early PCI hose
* or the 'real' one, created after U-Boot has memory available
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index ce68839..6d2ae5d 100644
--- a/arch/x86/include/asm/post.h
+++ b/arch/x86/include/asm/post.h
@@ -30,6 +30,7 @@
#define POST_PRE_MRC 0x2e
#define POST_MRC 0x2f
#define POST_DRAM 0x2f
+#define POST_LAPIC 0x30
#define POST_RAM_FAILURE 0xea
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index b9317cb..3e26202 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -8,25 +8,18 @@
#ifndef __ASM_PROCESSOR_H_
#define __ASM_PROCESSOR_H_ 1
-#define X86_GDT_ENTRY_SIZE 8
-
-#ifndef __ASSEMBLY__
-
-enum {
- X86_GDT_ENTRY_NULL = 0,
- X86_GDT_ENTRY_UNUSED,
- X86_GDT_ENTRY_32BIT_CS,
- X86_GDT_ENTRY_32BIT_DS,
- X86_GDT_ENTRY_32BIT_FS,
- X86_GDT_ENTRY_16BIT_CS,
- X86_GDT_ENTRY_16BIT_DS,
- X86_GDT_NUM_ENTRIES
-};
-#else
-/* NOTE: If the above enum is modified, this define must be checked */
-#define X86_GDT_ENTRY_32BIT_DS 3
-#define X86_GDT_NUM_ENTRIES 7
-#endif
+#define X86_GDT_ENTRY_SIZE 8
+
+#define X86_GDT_ENTRY_NULL 0
+#define X86_GDT_ENTRY_UNUSED 1
+#define X86_GDT_ENTRY_32BIT_CS 2
+#define X86_GDT_ENTRY_32BIT_DS 3
+#define X86_GDT_ENTRY_32BIT_FS 4
+#define X86_GDT_ENTRY_16BIT_CS 5
+#define X86_GDT_ENTRY_16BIT_DS 6
+#define X86_GDT_ENTRY_16BIT_FLAT_CS 7
+#define X86_GDT_ENTRY_16BIT_FLAT_DS 8
+#define X86_GDT_NUM_ENTRIES 9
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
diff --git a/arch/x86/include/asm/speedstep.h b/arch/x86/include/asm/speedstep.h
new file mode 100644
index 0000000..b938b86
--- /dev/null
+++ b/arch/x86/include/asm/speedstep.h
@@ -0,0 +1,89 @@
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_SPEEDSTEP_H
+#define _ASM_SPEEDSTEP_H
+
+/* Magic value used to locate speedstep configuration in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
+#define PMB1_BASE 0x800
+
+struct sst_state {
+ uint8_t dynfsb:1; /* whether this is SLFM */
+ uint8_t nonint:1; /* add .5 to ratio */
+ uint8_t ratio:6;
+ uint8_t vid;
+ uint8_t is_turbo;
+ uint8_t is_slfm;
+ uint32_t power;
+};
+#define SPEEDSTEP_RATIO_SHIFT 8
+#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
+#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_VID_MASK 0x3f
+#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \
+ 0, /* dynfsb won't be read. */ \
+ ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
+ (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
+ >> SPEEDSTEP_RATIO_SHIFT), \
+ (val & mask) & SPEEDSTEP_VID_MASK, \
+ 0, /* not turbo by default */ \
+ 0, /* not slfm by default */ \
+ 0 /* power is hardcoded in software. */ \
+ })
+#define SPEEDSTEP_ENCODE_STATE(state) ( \
+ ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
+ ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
+ ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
+ ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
+#define SPEEDSTEP_DOUBLE_RATIO(state) ( \
+ ((uint8_t)(state).ratio * 2) + (state).nonint)
+
+struct sst_params {
+ struct sst_state slfm;
+ struct sst_state min;
+ struct sst_state max;
+ struct sst_state turbo;
+};
+
+/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
+ processor is 14, the lowest is always 6. This makes 5 states with the
+ minimal step width of 2. With turbo mode and super LFM we have at most 7. */
+#define SPEEDSTEP_MAX_NORMAL_STATES 5
+#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
+struct sst_table {
+ /* Table of p-states for EMTTM and ACPI by decreasing performance. */
+ struct sst_state states[SPEEDSTEP_MAX_STATES];
+ int num_states;
+};
+
+void speedstep_gen_pstates(struct sst_table *);
+
+#define SPEEDSTEP_MAX_POWER_YONAH 31000
+#define SPEEDSTEP_MIN_POWER_YONAH 13100
+#define SPEEDSTEP_MAX_POWER_MEROM 35000
+#define SPEEDSTEP_MIN_POWER_MEROM 25000
+#define SPEEDSTEP_SLFM_POWER_MEROM 12000
+#define SPEEDSTEP_MAX_POWER_PENRYN 35000
+#define SPEEDSTEP_MIN_POWER_PENRYN 15000
+#define SPEEDSTEP_SLFM_POWER_PENRYN 12000
+
+#endif
diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h
new file mode 100644
index 0000000..bb0d4b4
--- /dev/null
+++ b/arch/x86/include/asm/turbo.h
@@ -0,0 +1,31 @@
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_TURBO_H
+#define _ASM_TURBO_H
+
+#define CPUID_LEAF_PM 6
+#define PM_CAP_TURBO_MODE (1 << 1)
+
+#define MSR_IA32_MISC_ENABLES 0x1a0
+#define H_MISC_DISABLE_TURBO (1 << 6)
+
+enum {
+ TURBO_UNKNOWN,
+ TURBO_UNAVAILABLE,
+ TURBO_DISABLED,
+ TURBO_ENABLED,
+};
+
+/* Return current turbo state */
+int turbo_get_state(void);
+
+/* Enable turbo */
+void turbo_enable(void);
+
+#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 98217dd..36145cb 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -10,8 +10,6 @@
/* cpu/.../cpu.c */
int arch_cpu_init(void);
-int x86_cpu_init_r(void);
-int cpu_init_r(void);
int x86_cpu_init_f(void);
int cpu_init_f(void);
void init_gd(gd_t *id, u64 *gdt_addr);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index e146e64..55de788 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -5,6 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += bios.o
+obj-y += bios_asm.o
+obj-y += bios_interrupts.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cmd_boot.o
obj-y += gcc.o
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
new file mode 100644
index 0000000..298fca6
--- /dev/null
+++ b/arch/x86/lib/bios.c
@@ -0,0 +1,347 @@
+/*
+ * From Coreboot file device/oprom/realmode/x86.c
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <bios_emul.h>
+#include <vbe.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/i8259.h>
+#include <asm/io.h>
+#include <asm/post.h>
+#include "bios.h"
+
+/* Interrupt handlers for each interrupt the ROM can call */
+static int (*int_handler[256])(void);
+
+/* to have a common register file for interrupt handlers */
+X86EMU_sysEnv _X86EMU_env;
+
+asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+ u32 esi, u32 edi);
+
+asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx,
+ u32 edx, u32 esi, u32 edi);
+
+static void setup_realmode_code(void)
+{
+ memcpy((void *)REALMODE_BASE, &asm_realmode_code,
+ asm_realmode_code_size);
+
+ /* Ensure the global pointers are relocated properly. */
+ realmode_call = PTR_TO_REAL_MODE(asm_realmode_call);
+ realmode_interrupt = PTR_TO_REAL_MODE(__realmode_interrupt);
+
+ debug("Real mode stub @%x: %d bytes\n", REALMODE_BASE,
+ asm_realmode_code_size);
+}
+
+static void setup_rombios(void)
+{
+ const char date[] = "06/11/99";
+ memcpy((void *)0xffff5, &date, 8);
+
+ const char ident[] = "PCI_ISA";
+ memcpy((void *)0xfffd9, &ident, 7);
+
+ /* system model: IBM-AT */
+ writeb(0xfc, 0xffffe);
+}
+
+static int int_exception_handler(void)
+{
+ /* compatibility shim */
+ struct eregs reg_info = {
+ .eax = M.x86.R_EAX,
+ .ecx = M.x86.R_ECX,
+ .edx = M.x86.R_EDX,
+ .ebx = M.x86.R_EBX,
+ .esp = M.x86.R_ESP,
+ .ebp = M.x86.R_EBP,
+ .esi = M.x86.R_ESI,
+ .edi = M.x86.R_EDI,
+ .vector = M.x86.intno,
+ .error_code = 0,
+ .eip = M.x86.R_EIP,
+ .cs = M.x86.R_CS,
+ .eflags = M.x86.R_EFLG
+ };
+ struct eregs *regs = &reg_info;
+
+ debug("Oops, exception %d while executing option rom\n", regs->vector);
+ cpu_hlt();
+
+ return 0;
+}
+
+static int int_unknown_handler(void)
+{
+ debug("Unsupported software interrupt #0x%x eax 0x%x\n",
+ M.x86.intno, M.x86.R_EAX);
+
+ return -1;
+}
+
+/* setup interrupt handlers for mainboard */
+void bios_set_interrupt_handler(int intnum, int (*int_func)(void))
+{
+ int_handler[intnum] = int_func;
+}
+
+static void setup_interrupt_handlers(void)
+{
+ int i;
+
+ /*
+ * The first 16 int_handler functions are not BIOS services,
+ * but the CPU-generated exceptions ("hardware interrupts")
+ */
+ for (i = 0; i < 0x10; i++)
+ int_handler[i] = &int_exception_handler;
+
+ /* Mark all other int_handler calls as unknown first */
+ for (i = 0x10; i < 0x100; i++) {
+ /* Skip if bios_set_interrupt_handler() isn't called first */
+ if (int_handler[i])
+ continue;
+
+ /*
+ * Now set the default functions that are actually needed
+ * to initialize the option roms. The board may override
+ * these with bios_set_interrupt_handler()
+ */
+ switch (i) {
+ case 0x10:
+ int_handler[0x10] = &int10_handler;
+ break;
+ case 0x12:
+ int_handler[0x12] = &int12_handler;
+ break;
+ case 0x16:
+ int_handler[0x16] = &int16_handler;
+ break;
+ case 0x1a:
+ int_handler[0x1a] = &int1a_handler;
+ break;
+ default:
+ int_handler[i] = &int_unknown_handler;
+ break;
+ }
+ }
+}
+
+static void write_idt_stub(void *target, u8 intnum)
+{
+ unsigned char *codeptr;
+
+ codeptr = (unsigned char *)target;
+ memcpy(codeptr, &__idt_handler, __idt_handler_size);
+ codeptr[3] = intnum; /* modify int# in the code stub. */
+}
+
+static void setup_realmode_idt(void)
+{
+ struct realmode_idt *idts = NULL;
+ int i;
+
+ /*
+ * Copy IDT stub code for each interrupt. This might seem wasteful
+ * but it is really simple
+ */
+ for (i = 0; i < 256; i++) {
+ idts[i].cs = 0;
+ idts[i].offset = 0x1000 + (i * __idt_handler_size);
+ write_idt_stub((void *)((u32)idts[i].offset), i);
+ }
+
+ /*
+ * Many option ROMs use the hard coded interrupt entry points in the
+ * system bios. So install them at the known locations.
+ */
+
+ /* int42 is the relocated int10 */
+ write_idt_stub((void *)0xff065, 0x42);
+ /* BIOS Int 11 Handler F000:F84D */
+ write_idt_stub((void *)0xff84d, 0x11);
+ /* BIOS Int 12 Handler F000:F841 */
+ write_idt_stub((void *)0xff841, 0x12);
+ /* BIOS Int 13 Handler F000:EC59 */
+ write_idt_stub((void *)0xfec59, 0x13);
+ /* BIOS Int 14 Handler F000:E739 */
+ write_idt_stub((void *)0xfe739, 0x14);
+ /* BIOS Int 15 Handler F000:F859 */
+ write_idt_stub((void *)0xff859, 0x15);
+ /* BIOS Int 16 Handler F000:E82E */
+ write_idt_stub((void *)0xfe82e, 0x16);
+ /* BIOS Int 17 Handler F000:EFD2 */
+ write_idt_stub((void *)0xfefd2, 0x17);
+ /* ROM BIOS Int 1A Handler F000:FE6E */
+ write_idt_stub((void *)0xffe6e, 0x1a);
+}
+
+static u8 vbe_get_mode_info(struct vbe_mode_info *mi)
+{
+ u16 buffer_seg;
+ u16 buffer_adr;
+ char *buffer;
+
+ debug("VBE: Getting information about VESA mode %04x\n",
+ mi->video_mode);
+ buffer = PTR_TO_REAL_MODE(asm_realmode_buffer);
+ buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
+ buffer_adr = ((unsigned long)buffer) & 0xffff;
+
+ realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode,
+ 0x0000, buffer_seg, buffer_adr);
+ memcpy(mi->mode_info_block, buffer, sizeof(struct vbe_mode_info));
+ mi->valid = true;
+
+ return 0;
+}
+
+static u8 vbe_set_mode(struct vbe_mode_info *mi)
+{
+ debug("VBE: Setting VESA mode %#04x\n", mi->video_mode);
+ /* request linear framebuffer mode */
+ mi->video_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ mi->video_mode &= ~(1 << 15);
+ realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode,
+ 0x0000, 0x0000, 0x0000, 0x0000);
+
+ return 0;
+}
+
+static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info)
+{
+ unsigned char *framebuffer;
+
+ mode_info->video_mode = (1 << 14) | vesa_mode;
+ vbe_get_mode_info(mode_info);
+
+ framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr;
+ debug("VBE: resolution: %dx%d@%d\n",
+ le16_to_cpu(mode_info->vesa.x_resolution),
+ le16_to_cpu(mode_info->vesa.y_resolution),
+ mode_info->vesa.bits_per_pixel);
+ debug("VBE: framebuffer: %p\n", framebuffer);
+ if (!framebuffer) {
+ debug("VBE: Mode does not support linear framebuffer\n");
+ return;
+ }
+
+ vbe_set_mode(mode_info);
+}
+
+void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ u32 num_dev;
+
+ num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 |
+ PCI_FUNC(pcidev);
+
+ /* Needed to avoid exceptions in some ROMs */
+ interrupt_init();
+
+ /* Set up some legacy information in the F segment */
+ setup_rombios();
+
+ /* Set up C interrupt handlers */
+ setup_interrupt_handlers();
+
+ /* Set up real-mode IDT */
+ setup_realmode_idt();
+
+ /* Make sure the code is placed. */
+ setup_realmode_code();
+
+ disable_caches();
+ debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev);
+
+ /* Option ROM entry point is at OPROM start + 3 */
+ realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0,
+ 0x0);
+ debug("done\n");
+
+ if (vesa_mode != -1)
+ vbe_set_graphics(vesa_mode, mode_info);
+}
+
+asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses,
+ u32 edi, u32 esi, u32 ebp, u32 esp,
+ u32 ebx, u32 edx, u32 ecx, u32 eax,
+ u32 cs_ip, u16 stackflags)
+{
+ u32 ip;
+ u32 cs;
+ u32 flags;
+ int ret = 0;
+
+ ip = cs_ip & 0xffff;
+ cs = cs_ip >> 16;
+ flags = stackflags;
+
+#ifdef CONFIG_REALMODE_DEBUG
+ debug("oprom: INT# 0x%x\n", intnumber);
+ debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
+ eax, ebx, ecx, edx);
+ debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
+ ebp, esp, edi, esi);
+ debug("oprom: ip: %04x cs: %04x flags: %08x\n",
+ ip, cs, flags);
+ debug("oprom: stackflags = %04x\n", stackflags);
+#endif
+
+ /*
+ * Fetch arguments from the stack and put them to a place
+ * suitable for the interrupt handlers
+ */
+ M.x86.R_EAX = eax;
+ M.x86.R_ECX = ecx;
+ M.x86.R_EDX = edx;
+ M.x86.R_EBX = ebx;
+ M.x86.R_ESP = esp;
+ M.x86.R_EBP = ebp;
+ M.x86.R_ESI = esi;
+ M.x86.R_EDI = edi;
+ M.x86.intno = intnumber;
+ M.x86.R_EIP = ip;
+ M.x86.R_CS = cs;
+ M.x86.R_EFLG = flags;
+
+ /* Call the interrupt handler for this interrupt number */
+ ret = int_handler[intnumber]();
+
+ /*
+ * This code is quite strange...
+ *
+ * Put registers back on the stack. The assembler code will pop them
+ * later. We force (volatile!) changing the values of the parameters
+ * of this function. We know that they stay alive on the stack after
+ * we leave this function.
+ */
+ *(volatile u32 *)&eax = M.x86.R_EAX;
+ *(volatile u32 *)&ecx = M.x86.R_ECX;
+ *(volatile u32 *)&edx = M.x86.R_EDX;
+ *(volatile u32 *)&ebx = M.x86.R_EBX;
+ *(volatile u32 *)&esi = M.x86.R_ESI;
+ *(volatile u32 *)&edi = M.x86.R_EDI;
+ flags = M.x86.R_EFLG;
+
+ /* Pass success or error back to our caller via the CARRY flag */
+ if (ret) {
+ flags &= ~1; /* no error: clear carry */
+ } else {
+ debug("int%02x call returned error\n", intnumber);
+ flags |= 1; /* error: set carry */
+ }
+ *(volatile u16 *)&stackflags = flags;
+
+ return ret;
+}
diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h
new file mode 100644
index 0000000..8491b4a
--- /dev/null
+++ b/arch/x86/lib/bios.h
@@ -0,0 +1,98 @@
+/*
+ * From Coreboot file device/oprom/realmode/x86.h
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _X86_LIB_BIOS_H
+#define _X86_LIB_BIOS_H
+
+#define REALMODE_BASE 0x600
+
+#ifdef __ASSEMBLY__
+
+#define PTR_TO_REAL_MODE(x) (x - asm_realmode_code + REALMODE_BASE)
+
+#else
+
+/* Convert a symbol address to our real mode area */
+#define PTR_TO_REAL_MODE(sym)\
+ (void *)(REALMODE_BASE + ((char *)&(sym) - (char *)&asm_realmode_code))
+
+/*
+ * The following symbols cannot be used directly. They need to be fixed up
+ * to point to the correct address location after the code has been copied
+ * to REALMODE_BASE. Absolute symbols are not used because those symbols are
+ * relocated by U-Boot.
+ */
+extern unsigned char asm_realmode_call, __realmode_interrupt;
+extern unsigned char asm_realmode_buffer;
+
+#define DOWNTO8(A) \
+ union { \
+ struct { \
+ union { \
+ struct { \
+ uint8_t A##l; \
+ uint8_t A##h; \
+ } __packed; \
+ uint16_t A##x; \
+ } __packed; \
+ uint16_t h##A##x; \
+ } __packed; \
+ uint32_t e##A##x; \
+ } __packed;
+
+#define DOWNTO16(A) \
+ union { \
+ struct { \
+ uint16_t A; \
+ uint16_t h##A; \
+ } __packed; \
+ uint32_t e##A; \
+ } __packed;
+
+struct eregs {
+ DOWNTO8(a);
+ DOWNTO8(c);
+ DOWNTO8(d);
+ DOWNTO8(b);
+ DOWNTO16(sp);
+ DOWNTO16(bp);
+ DOWNTO16(si);
+ DOWNTO16(di);
+ uint32_t vector;
+ uint32_t error_code;
+ uint32_t eip;
+ uint32_t cs;
+ uint32_t eflags;
+};
+
+struct realmode_idt {
+ u16 offset, cs;
+};
+
+void x86_exception(struct eregs *info);
+
+/* From x86_asm.S */
+extern unsigned char __idt_handler;
+extern unsigned int __idt_handler_size;
+extern unsigned char asm_realmode_code;
+extern unsigned int asm_realmode_code_size;
+
+asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+ u32 esi, u32 edi);
+
+asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx,
+ u32 edx, u32 esi, u32 edi);
+
+int int10_handler(void);
+int int12_handler(void);
+int int16_handler(void);
+int int1a_handler(void);
+#endif /*__ASSEMBLY__ */
+
+#endif
diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S
new file mode 100644
index 0000000..4faa70e
--- /dev/null
+++ b/arch/x86/lib/bios_asm.S
@@ -0,0 +1,281 @@
+/*
+ * From coreboot x86_asm.S, cleaned up substantially
+ *
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
+#include "bios.h"
+
+#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE
+
+/*
+ * This is the interrupt handler stub code. It gets copied to the IDT and
+ * to some fixed addresses in the F segment. Before the code can used,
+ * it gets patched up by the C function copying it: byte 3 (the $0 in
+ * movb $0, %al) is overwritten with the interrupt numbers.
+ */
+
+ .code16
+ .globl __idt_handler
+__idt_handler:
+ pushal
+ movb $0, %al /* This instruction gets modified */
+ ljmp $0, $__interrupt_handler_16bit
+ .globl __idt_handler_size
+__idt_handler_size:
+ .long . - __idt_handler
+
+.macro setup_registers
+ /* initial register values */
+ movl 44(%ebp), %eax
+ movl %eax, __registers + 0 /* eax */
+ movl 48(%ebp), %eax
+ movl %eax, __registers + 4 /* ebx */
+ movl 52(%ebp), %eax
+ movl %eax, __registers + 8 /* ecx */
+ movl 56(%ebp), %eax
+ movl %eax, __registers + 12 /* edx */
+ movl 60(%ebp), %eax
+ movl %eax, __registers + 16 /* esi */
+ movl 64(%ebp), %eax
+ movl %eax, __registers + 20 /* edi */
+.endm
+
+.macro enter_real_mode
+ /* Activate the right segment descriptor real mode. */
+ ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f)
+1:
+.code16
+ /*
+ * Load the segment registers with properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off.
+ */
+ mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov %ax, %ss
+
+ /* Turn off protection */
+ movl %cr0, %eax
+ andl $~X86_CR0_PE, %eax
+ movl %eax, %cr0
+
+ /* Now really going into real mode */
+ ljmp $0, $PTR_TO_REAL_MODE(1f)
+1:
+ /*
+ * Set up a stack: Put the stack at the end of page zero. That way
+ * we can easily share it between real and protected, since the
+ * 16-bit ESP at segment 0 will work for any case.
+ */
+ mov $0x0, %ax
+ mov %ax, %ss
+
+ /* Load 16 bit IDT */
+ xor %ax, %ax
+ mov %ax, %ds
+ lidt __realmode_idt
+
+.endm
+
+.macro prepare_for_irom
+ movl $0x1000, %eax
+ movl %eax, %esp
+
+ /* Initialise registers for option rom lcall */
+ movl __registers + 0, %eax
+ movl __registers + 4, %ebx
+ movl __registers + 8, %ecx
+ movl __registers + 12, %edx
+ movl __registers + 16, %esi
+ movl __registers + 20, %edi
+
+ /* Set all segments to 0x0000, ds to 0x0040 */
+ push %ax
+ xor %ax, %ax
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax
+ mov %ax, %ds
+ pop %ax
+
+.endm
+
+.macro enter_protected_mode
+ /* Go back to protected mode */
+ movl %cr0, %eax
+ orl $X86_CR0_PE, %eax
+ movl %eax, %cr0
+
+ /* Now that we are in protected mode jump to a 32 bit code segment */
+ data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f)
+1:
+ .code32
+ mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %gs
+ mov %ax, %ss
+ mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax
+ mov %ax, %fs
+
+ /* restore proper idt */
+ lidt idt_ptr
+.endm
+
+/*
+ * In order to be independent of U-Boot's position in RAM we relocate a part
+ * of the code to the first megabyte of RAM, so the CPU can use it in
+ * real-mode. This code lives at asm_realmode_code.
+ */
+ .globl asm_realmode_code
+asm_realmode_code:
+
+/* Realmode IDT pointer structure. */
+__realmode_idt = PTR_TO_REAL_MODE(.)
+ .word 1023 /* 16 bit limit */
+ .long 0 /* 24 bit base */
+ .word 0
+
+/* Preserve old stack */
+__stack = PTR_TO_REAL_MODE(.)
+ .long 0
+
+/* Register store for realmode_call and realmode_interrupt */
+__registers = PTR_TO_REAL_MODE(.)
+ .long 0 /* 0 - EAX */
+ .long 0 /* 4 - EBX */
+ .long 0 /* 8 - ECX */
+ .long 0 /* 12 - EDX */
+ .long 0 /* 16 - ESI */
+ .long 0 /* 20 - EDI */
+
+/* 256 byte buffer, used by int10 */
+ .globl asm_realmode_buffer
+asm_realmode_buffer:
+ .skip 256
+
+ .code32
+ .globl asm_realmode_call
+asm_realmode_call:
+ /* save all registers to the stack */
+ pusha
+ pushf
+ movl %esp, __stack
+ movl %esp, %ebp
+
+ /*
+ * This function is called with regparm=0 and we have to skip the
+ * 36 bytes from pushf+pusha. Hence start at 40.
+ * Set up our call instruction.
+ */
+ movl 40(%ebp), %eax
+ mov %ax, __lcall_instr + 1
+ andl $0xffff0000, %eax
+ shrl $4, %eax
+ mov %ax, __lcall_instr + 3
+
+ wbinvd
+
+ setup_registers
+ enter_real_mode
+ prepare_for_irom
+
+__lcall_instr = PTR_TO_REAL_MODE(.)
+ .byte 0x9a
+ .word 0x0000, 0x0000
+
+ enter_protected_mode
+
+ /* restore stack pointer, eflags and register values and exit */
+ movl __stack, %esp
+ popf
+ popa
+ ret
+
+ .globl __realmode_interrupt
+__realmode_interrupt:
+ /* save all registers to the stack and store the stack pointer */
+ pusha
+ pushf
+ movl %esp, __stack
+ movl %esp, %ebp
+
+ /*
+ * This function is called with regparm=0 and we have to skip the
+ * 36 bytes from pushf+pusha. Hence start at 40.
+ * Prepare interrupt calling code.
+ */
+ movl 40(%ebp), %eax
+ movb %al, __intXX_instr + 1 /* intno */
+
+ setup_registers
+ enter_real_mode
+ prepare_for_irom
+
+__intXX_instr = PTR_TO_REAL_MODE(.)
+ .byte 0xcd, 0x00 /* This becomes intXX */
+
+ enter_protected_mode
+
+ /* restore stack pointer, eflags and register values and exit */
+ movl __stack, %esp
+ popf
+ popa
+ ret
+
+/*
+ * This is the 16-bit interrupt entry point called by the IDT stub code.
+ *
+ * Before this code code is called, %eax is pushed to the stack, and the
+ * interrupt number is loaded into %al. On return this function cleans up
+ * for its caller.
+ */
+ .code16
+__interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
+ push %ds
+ push %es
+ push %fs
+ push %gs
+
+ /* Clear DF to not break ABI assumptions */
+ cld
+
+ /*
+ * Clean up the interrupt number. We could do this in the stub, but
+ * it would cost two more bytes per stub entry.
+ */
+ andl $0xff, %eax
+ pushl %eax /* ... and make it the first parameter */
+
+ enter_protected_mode
+
+ /* Call the C interrupt handler */
+ movl $interrupt_handler, %eax
+ call *%eax
+
+ enter_real_mode
+
+ /*
+ * Restore all registers, including those manipulated by the C
+ * handler
+ */
+ popl %eax
+ pop %gs
+ pop %fs
+ pop %es
+ pop %ds
+ popal
+ iret
+
+ .globl asm_realmode_code_size
+asm_realmode_code_size:
+ .long . - asm_realmode_code
diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
new file mode 100644
index 0000000..b0e2ecb
--- /dev/null
+++ b/arch/x86/lib/bios_interrupts.c
@@ -0,0 +1,217 @@
+/*
+ * From Coreboot
+ *
+ * Copyright (C) 2001 Ronald G. Minnich
+ * Copyright (C) 2005 Nick.Barker9@btinternet.com
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include "bios_emul.h"
+
+/* errors go in AH. Just set these up so that word assigns will work */
+enum {
+ PCIBIOS_SUCCESSFUL = 0x0000,
+ PCIBIOS_UNSUPPORTED = 0x8100,
+ PCIBIOS_BADVENDOR = 0x8300,
+ PCIBIOS_NODEV = 0x8600,
+ PCIBIOS_BADREG = 0x8700
+};
+
+int int10_handler(void)
+{
+ static u8 cursor_row, cursor_col;
+ int res = 0;
+
+ switch ((M.x86.R_EAX & 0xff00) >> 8) {
+ case 0x01: /* Set cursor shape */
+ res = 1;
+ break;
+ case 0x02: /* Set cursor position */
+ if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) ||
+ cursor_col >= (M.x86.R_EDX & 0xff)) {
+ debug("\n");
+ }
+ cursor_row = (M.x86.R_EDX >> 8) & 0xff;
+ cursor_col = M.x86.R_EDX & 0xff;
+ res = 1;
+ break;
+ case 0x03: /* Get cursor position */
+ M.x86.R_EAX &= 0x00ff;
+ M.x86.R_ECX = 0x0607;
+ M.x86.R_EDX = (cursor_row << 8) | cursor_col;
+ res = 1;
+ break;
+ case 0x06: /* Scroll up */
+ debug("\n");
+ res = 1;
+ break;
+ case 0x08: /* Get Character and Mode at Cursor Position */
+ M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */
+ res = 1;
+ break;
+ case 0x09: /* Write Character and attribute */
+ case 0x0e: /* Write Character */
+ debug("%c", M.x86.R_EAX & 0xff);
+ res = 1;
+ break;
+ case 0x0f: /* Get video mode */
+ M.x86.R_EAX = 0x5002; /*80 x 25 */
+ M.x86.R_EBX &= 0x00ff;
+ res = 1;
+ break;
+ default:
+ printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff);
+ break;
+ }
+ return res;
+}
+
+int int12_handler(void)
+{
+ M.x86.R_EAX = 64 * 1024;
+ return 1;
+}
+
+int int16_handler(void)
+{
+ int res = 0;
+
+ switch ((M.x86.R_EAX & 0xff00) >> 8) {
+ case 0x00: /* Check for Keystroke */
+ M.x86.R_EAX = 0x6120; /* Space Bar, Space */
+ res = 1;
+ break;
+ case 0x01: /* Check for Keystroke */
+ M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */
+ res = 1;
+ break;
+ default:
+ printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff);
+
+break;
+ }
+ return res;
+}
+
+#define PCI_CONFIG_SPACE_TYPE1 (1 << 0)
+#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4)
+
+int int1a_handler(void)
+{
+ unsigned short func = (unsigned short)M.x86.R_EAX;
+ int retval = 1;
+ unsigned short devid, vendorid, devfn;
+ /* Use short to get rid of gabage in upper half of 32-bit register */
+ short devindex;
+ unsigned char bus;
+ pci_dev_t dev;
+ u32 dword;
+ u16 word;
+ u8 byte, reg;
+
+ switch (func) {
+ case 0xb101: /* PCIBIOS Check */
+ M.x86.R_EDX = 0x20494350; /* ' ICP' */
+ M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */
+ M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 |
+ PCI_SPECIAL_CYCLE_TYPE1;
+ /*
+ * last bus in the system. Hard code to 255 for now.
+ * dev_enumerate() does not seem to tell us (publically)
+ */
+ M.x86.R_ECX = 0xff;
+ M.x86.R_EDI = 0x00000000; /* protected mode entry */
+ retval = 1;
+ break;
+ case 0xb102: /* Find Device */
+ devid = M.x86.R_ECX;
+ vendorid = M.x86.R_EDX;
+ devindex = M.x86.R_ESI;
+ dev = pci_find_device(vendorid, devid, devindex);
+ if (dev != -1) {
+ unsigned short busdevfn;
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
+ /*
+ * busnum is an unsigned char;
+ * devfn is an int, so we mask it off.
+ */
+ busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 |
+ PCI_FUNC(dev);
+ debug("0x%x: return 0x%x\n", func, busdevfn);
+ M.x86.R_EBX = busdevfn;
+ retval = 1;
+ } else {
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_NODEV;
+ retval = 0;
+ }
+ break;
+ case 0xb10a: /* Read Config Dword */
+ case 0xb109: /* Read Config Word */
+ case 0xb108: /* Read Config Byte */
+ case 0xb10d: /* Write Config Dword */
+ case 0xb10c: /* Write Config Word */
+ case 0xb10b: /* Write Config Byte */
+ devfn = M.x86.R_EBX & 0xff;
+ bus = M.x86.R_EBX >> 8;
+ reg = M.x86.R_EDI;
+ dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
+ if (!dev) {
+ debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func,
+ bus, devfn);
+ /* Or are we supposed to return PCIBIOS_NODEV? */
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_BADREG;
+ retval = 0;
+ return retval;
+ }
+ switch (func) {
+ case 0xb108: /* Read Config Byte */
+ byte = pci_read_config8(dev, reg);
+ M.x86.R_ECX = byte;
+ break;
+ case 0xb109: /* Read Config Word */
+ word = pci_read_config16(dev, reg);
+ M.x86.R_ECX = word;
+ break;
+ case 0xb10a: /* Read Config Dword */
+ dword = pci_read_config32(dev, reg);
+ M.x86.R_ECX = dword;
+ break;
+ case 0xb10b: /* Write Config Byte */
+ byte = M.x86.R_ECX;
+ pci_write_config8(dev, reg, byte);
+ break;
+ case 0xb10c: /* Write Config Word */
+ word = M.x86.R_ECX;
+ pci_write_config16(dev, reg, word);
+ break;
+ case 0xb10d: /* Write Config Dword */
+ dword = M.x86.R_ECX;
+ pci_write_config32(dev, reg, dword);
+ break;
+ }
+
+#ifdef CONFIG_REALMODE_DEBUG
+ debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
+ bus, devfn, reg, M.x86.R_ECX);
+#endif
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
+ retval = 1;
+ break;
+ default:
+ printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_UNSUPPORTED;
+ retval = 0;
+ break;
+ }
+
+ return retval;
+}
diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c
index 4c86f7f..a9af87e 100644
--- a/arch/x86/lib/pcat_interrupts.c
+++ b/arch/x86/lib/pcat_interrupts.c
@@ -24,12 +24,10 @@
#error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
#endif
-int interrupt_init(void)
+int i8259_init(void)
{
u8 i;
- disable_interrupts();
-
/* Mask all interrupts */
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
@@ -62,7 +60,8 @@ int interrupt_init(void)
*/
unmask_irq(2);
- enable_interrupts();
+ /* Interrupt 9 should be level triggered (SCI). The OS might do this */
+ configure_irq_trigger(9, true);
return 0;
}
@@ -114,3 +113,38 @@ void specific_eoi(int irq)
outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
}
+
+#define ELCR1 0x4d0
+#define ELCR2 0x4d1
+
+void configure_irq_trigger(int int_num, bool is_level_triggered)
+{
+ u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
+
+ debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
+ if (is_level_triggered)
+ int_bits |= (1 << int_num);
+ else
+ int_bits &= ~(1 << int_num);
+
+ /* Write new values */
+ debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
+ outb((u8)(int_bits & 0xff), ELCR1);
+ outb((u8)(int_bits >> 8), ELCR2);
+
+#ifdef PARANOID_IRQ_TRIGGERS
+ /*
+ * Try reading back the new values. This seems like an error but is
+ * not
+ */
+ if (inb(ELCR1) != (int_bits & 0xff)) {
+ printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+ __func__, (int_bits & 0xff), inb(ELCR1));
+ }
+
+ if (inb(ELCR2) != (int_bits >> 8)) {
+ printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
+ __func__, (int_bits>>8), inb(ELCR2));
+ }
+#endif
+}
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index faca38f..b33586b 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -76,6 +76,9 @@ int do_elf_reloc_fixups(void)
/* The size of the region of u-boot that runs out of RAM. */
uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+ if (re_src == re_end)
+ panic("No relocation data");
+
do {
/* Get the location from the relocation entry */
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c
index a1656cc..6c66431 100644
--- a/arch/x86/lib/string.c
+++ b/arch/x86/lib/string.c
@@ -8,9 +8,9 @@
/* From glibc-2.14, sysdeps/i386/memset.c */
-#include <compiler.h>
-#include <asm/string.h>
#include <linux/types.h>
+#include <linux/compiler.h>
+#include <asm/string.h>
typedef uint32_t op_t;
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index b96ba81..ee1681b 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -392,9 +392,11 @@ int misc_init_r(void)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index d3d4c18..c5d161b 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -171,10 +171,11 @@ void pci_init_board(void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 79d4bab..c5cc4ff 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -490,9 +490,9 @@ int misc_init_r(void)
#endif /* !defined(CONFIG_ARCHES) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-extern void __ft_board_setup(void *blob, bd_t *bd);
+extern int __ft_board_setup(void *blob, bd_t *bd);
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
__ft_board_setup(blob, bd);
@@ -515,5 +515,7 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
"disabled", sizeof("disabled"), 1);
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 53f9b34..91c6cbf 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <errno.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/ppc4xx.h>
@@ -363,7 +364,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
*/
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int len;
@@ -381,15 +382,14 @@ void ft_board_setup(void *blob, bd_t *bd)
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
if (prop == NULL) {
printf("Unable to update NOR chip select for NAND booting\n");
- return;
+ return -FDT_ERR_NOTFOUND;
}
reg = (u32 *)&prop->data[0];
reg[0] = 3;
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
if (rc) {
- printf("Unable to update property NOR mappings, err=%s\n",
- fdt_strerror(rc));
- return;
+ printf("Unable to update property NOR mappings\n");
+ return rc;
}
/* And now configure NAND chip select to 0 instead of 3 */
@@ -398,15 +398,16 @@ void ft_board_setup(void *blob, bd_t *bd)
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
if (prop == NULL) {
printf("Unable to update NDFC chip select for NAND booting\n");
- return;
+ return len;
}
reg = (u32 *)&prop->data[0];
reg[0] = 0;
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
if (rc) {
- printf("Unable to update property NDFC mappings, err=%s\n",
- fdt_strerror(rc));
- return;
+ printf("Unable to update property NDFC mapping\n");
+ return rc;
}
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 048aa6c..5276907 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -359,9 +359,11 @@ int last_stage_init(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_blob_update(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
index 2b826df..9d4c41b 100644
--- a/board/comelit/dig297/dig297.c
+++ b/board/comelit/dig297/dig297.c
@@ -133,6 +133,11 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
#ifdef CONFIG_CMD_NET
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 09e285b..84e3643 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -458,7 +458,7 @@ int cm_fx6_setup_ecspi(void) { return 0; }
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
uint8_t enetaddr[6];
@@ -467,6 +467,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_find_and_setprop(blob, "/fec", "local-mac-address",
enetaddr, 6, 1);
}
+
+ return 0;
}
#endif
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 886c723..43463d5 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -382,6 +382,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index b1a067d..2c2530a 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -121,7 +121,7 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_USB_HOST_ETHER
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
uint8_t enetaddr[6];
@@ -130,6 +130,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address",
enetaddr, 6, 1);
}
+
+ return 0;
}
static void generate_mac_addr(uint8_t *enetaddr)
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index 9e81bf3..0fddf45 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -147,6 +147,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index c740669..a15a9ed 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -107,8 +107,10 @@ int checkboard (void)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 63cd862..e23ec55 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -508,7 +508,7 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -526,6 +526,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_strerror(rc));
}
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 9700611..cda1d7b 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -199,8 +199,10 @@ int checkboard(void)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 4409ea6..3e17132 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -300,7 +300,7 @@ int pci_pre_init(struct pci_controller *hose)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -318,6 +318,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_strerror(rc));
}
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 062ae67..15c3151 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -882,7 +882,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -899,5 +899,7 @@ void ft_board_setup(void *blob, bd_t *bd)
printf("err=%s\n", fdt_strerror(rc));
}
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index 01365dc..f8f1834 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -74,13 +74,15 @@ int board_eth_init(bd_t *bis)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 34d66d5..6a8fca6 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -19,6 +19,7 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
@@ -333,6 +334,8 @@ int configure_vsc3316_3308(void)
unsigned int num_vsc16_con, num_vsc08_con;
u32 serdes1_prtcl, serdes2_prtcl;
int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -385,15 +388,18 @@ int configure_vsc3316_3308(void)
}
break;
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -487,6 +493,9 @@ int configure_vsc3316_3308(void)
return -1;
}
+ num_vsc08_con = NUM_CON_VSC3308;
+ /* Configure VSC3308 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3308);
switch (serdes2_prtcl) {
#ifdef CONFIG_PPC_B4420
case 0x9d:
@@ -494,14 +503,11 @@ int configure_vsc3316_3308(void)
case 0x9E:
case 0x9A:
case 0x98:
- case 0xb2:
+ case 0x48:
case 0x49:
case 0x4E:
- case 0x8D:
+ case 0x79:
case 0x7A:
- num_vsc08_con = NUM_CON_VSC3308;
- /* Configure VSC3308 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3308);
if (!ret) {
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_amc, num_vsc08_con);
@@ -515,6 +521,71 @@ int configure_vsc3316_3308(void)
return ret;
}
break;
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ if (!ret) {
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup properly yet
+ */
+ getenv_f("hwconfig", buffer, sizeof(buffer));
+ buf = buffer;
+
+ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
+ "sfp_amc", "sfp", buf)) {
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+ /* change default VSC3308 for XFI erratum */
+ ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
+ vsc08_tx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
+ vsc08_rx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+#else
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+#endif
+ } else {
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ }
+
+ } else {
+ return ret;
+ }
+ break;
default:
printf("WARNING:VSC crossbars programming not supported for: %x"
" SerDes2 Protocol.\n", serdes2_prtcl);
@@ -730,19 +801,23 @@ int config_serdes1_refclks(void)
* to 122.88MHz
*/
switch (serdes1_prtcl) {
+ case 0x29:
case 0x2A:
case 0x2C:
case 0x2D:
case 0x2E:
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -860,6 +935,8 @@ int config_serdes2_refclks(void)
#endif
case 0x9E:
case 0x9A:
+ /* fallthrough */
+ case 0xb1:
case 0xb2:
debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
serdes2_prtcl);
@@ -915,6 +992,14 @@ int board_early_init_r(void)
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
int ret;
+ u32 svr = SVR_SOC_VER(get_svr());
+
+ /* Create law for MAPLE only for personalities having MAPLE */
+ if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
+ (svr == SVR_B4420) || (svr == SVR_B4220)) {
+ set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
+ LAW_TRGT_IF_MAPLE);
+ }
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@@ -1110,7 +1195,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -1136,6 +1221,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 12df9a8..501d4b3 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
+ case 0xb1:
case 0xb2:
+ case 0x8c:
+ case 0x8d:
/*
* Configuration:
* SERDES: 2
@@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Setting phy addresses for FM1_DTSEC5: %x and"
- "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_PPC_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Setting phy addresses for FM1_DTSEC3: %x and"
- "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
@@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
break;
case 0x48:
case 0x49:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -255,29 +258,37 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
- case 0x8d:
+ case 0xb1:
case 0xb2:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ case 0x8c:
+ case 0x8d:
+ debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ /*
+ * XFI does not need a PHY to work, but to make U-boot
+ * happy, assign a fake PHY address for a XFI port.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 0);
+ fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
@@ -329,17 +340,20 @@ int board_eth_init(bd_t *bis)
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+ miiphy_get_dev_by_name
+ (DEFAULT_FM_TGEC_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
break;
default:
- printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+ printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
-
cpu_eth_init(bis);
#endif
@@ -351,21 +365,82 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
{
int phy;
char alias[32];
+ struct fixed_link f_link;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
sprintf(alias, "phy_sgmii_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, alias);
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ /* check if it's XFI interface for 10g */
+ switch (prtcl2) {
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ break;
+ case 0x98: /* XAUI interface */
+ sprintf(alias, "phy_xaui_slot1");
+ fdt_status_okay_by_alias(fdt, alias);
+
+ sprintf(alias, "phy_xaui_slot2");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ case 0x9e: /* XAUI interface */
+ case 0x9a:
+ case 0x93:
+ case 0x91:
+ sprintf(alias, "phy_xaui_slot1");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ case 0x97: /* XAUI interface */
+ case 0xc3:
+ sprintf(alias, "phy_xaui_slot2");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ default:
+ break;
+ }
}
}
+/*
+ * Set status to disabled for unused ethernet node
+ */
void fdt_fixup_board_enet(void *fdt)
{
int i;
char alias[32];
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_NONE:
sprintf(alias, "ethernet%u", i);
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index 5b327cc..047c3cb 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -17,9 +17,6 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
- SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
-#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 9146f49..75e1142 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -58,7 +58,7 @@ struct node_info nodes[] = {
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -74,5 +74,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index c88838b..36a68db 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -363,7 +363,7 @@ struct node_info nodes[] = {
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -423,5 +423,7 @@ void ft_board_setup(void *blob, bd_t *bd)
printf("\nRemove sim from hwconfig and reset\n");
}
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 534c6d1..d7577096 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -128,7 +128,7 @@ void fdt_del_sec(void *blob, int offset)
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -150,5 +150,7 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_del_sec(blob, 1);
else if (cpu->soc_ver == SVR_C292)
fdt_del_sec(blob, 2);
+
+ return 0;
}
#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 25a1bc1..59ddeef 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_FMAN_ENET) += fman.o
obj-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
+obj-$(CONFIG_VID) += vid.o
endif
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index 2e5dcdf..571dfbb 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -63,13 +63,14 @@ static void cds_pci_fixup(void *blob)
}
}
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
cds_pci_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index c9c8eaa..5cb7570 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -90,7 +90,7 @@ static void show_eeprom(void)
/* EEPROM tag ID, either CCID or NXID */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
- be32_to_cpu(e.version));
+ e.version);
#else
printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
#endif
@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
- be32_to_cpu(e.version));
+ e.version);
#else
printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
#endif
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
new file mode 100644
index 0000000..6b8af14
--- /dev/null
+++ b/board/freescale/common/vid.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/immap_85xx.h>
+#include "vid.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int __weak i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return 0;
+}
+
+/*
+ * Compensate for a board specific voltage drop between regulator and SoC
+ * return a value in mV
+ */
+int __weak board_vdd_drop_compensation(void)
+{
+ return 0;
+}
+
+/*
+ * Get the i2c address configuration for the IR regulator chip
+ *
+ * There are some variance in the RDB HW regarding the I2C address configuration
+ * for the IR regulator chip, which is likely a problem of external resistor
+ * accuracy. So we just check each address in a hopefully non-intrusive mode
+ * and use the first one that seems to work
+ *
+ * The IR chip can show up under the following addresses:
+ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
+ * 0x09 (Verified on T1040RDB-PA)
+ * 0x38 (Verified on T2080QDS, T2081QDS)
+ */
+static int find_ir_chip_on_i2c(void)
+{
+ int i2caddress;
+ int ret;
+ u8 byte;
+ int i;
+ const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+
+ /* Check all the address */
+ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
+ i2caddress = ir_i2c_addr[i];
+ ret = i2c_read(i2caddress,
+ IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
+ sizeof(byte));
+ if ((ret >= 0) && (byte == IR36021_MFR_ID))
+ return i2caddress;
+ }
+ return -1;
+}
+
+/* Maximum loop count waiting for new voltage to take effect */
+#define MAX_LOOP_WAIT_NEW_VOL 100
+/* Maximum loop count waiting for the voltage to be stable */
+#define MAX_LOOP_WAIT_VOL_STABLE 100
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for WAIT_FOR_ADC before
+ * another reading
+ */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+/* If an INA220 chip is available, we can use it to read back the voltage
+ * as it may have a higher accuracy than the IR chip for the same purpose
+ */
+#ifdef CONFIG_VOL_MONITOR_INA220
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#else
+#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_INA220
+static int read_voltage_from_INA220(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf[2];
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
+ (void *)&buf, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ vol_mon = (buf[0] << 8) | buf[1];
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+#endif
+
+/* read voltage from IR */
+#ifdef CONFIG_VOL_MONITOR_IR36021_READ
+static int read_voltage_from_IR(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(i2caddress,
+ IR36021_LOOP1_VOUT_OFFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read vcpu\n");
+ return ret;
+ }
+ vol_mon = buf;
+ if (!vol_mon) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%02x\n", vol_mon);
+ /* Resolution is 1/128V. We scale up here to get 1/128mV
+ * and divide at the end
+ */
+ voltage_read += vol_mon * 1000;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* Scale down to the real mV as IR resolution is 1/128V, rounding up */
+ voltage_read = DIV_ROUND_UP(voltage_read, 128);
+
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ /* Compensate for a board specific voltage drop between regulator and
+ * SoC before converting into an IR VID value
+ */
+ voltage_read -= board_vdd_drop_compensation();
+
+ return voltage_read;
+}
+#endif
+
+static int read_voltage(int i2caddress)
+{
+ int voltage_read;
+#ifdef CONFIG_VOL_MONITOR_INA220
+ voltage_read = read_voltage_from_INA220(i2caddress);
+#elif defined CONFIG_VOL_MONITOR_IR36021_READ
+ voltage_read = read_voltage_from_IR(i2caddress);
+#else
+ return -1;
+#endif
+ return voltage_read;
+}
+
+/*
+ * We need to calculate how long before the voltage stops to drop
+ * or increase. It returns with the loop count. Each loop takes
+ * several readings (WAIT_FOR_ADC)
+ */
+static int wait_for_new_voltage(int vdd, int i2caddress)
+{
+ int timeout, vdd_current;
+
+ vdd_current = read_voltage(i2caddress);
+ /* wait until voltage starts to reach the target. Voltage slew
+ * rates by typical regulators will always lead to stable readings
+ * within each fairly long ADC interval in comparison to the
+ * intended voltage delta change until the target voltage is
+ * reached. The fairly small voltage delta change to any target
+ * VID voltage also means that this function will always complete
+ * within few iterations. If the timeout was ever reached, it would
+ * point to a serious failure in the regulator system.
+ */
+ for (timeout = 0;
+ abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
+ timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
+ vdd_current = read_voltage(i2caddress);
+ }
+ if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+ return timeout;
+}
+
+/*
+ * this function keeps reading the voltage until it is stable or until the
+ * timeout expires
+ */
+static int wait_for_voltage_stable(int i2caddress)
+{
+ int timeout, vdd_current, vdd;
+
+ vdd = read_voltage(i2caddress);
+ udelay(NUM_READINGS * WAIT_FOR_ADC);
+
+ /* wait until voltage is stable */
+ vdd_current = read_voltage(i2caddress);
+ /* The maximum timeout is
+ * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
+ */
+ for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
+ abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
+ timeout > 0; timeout--) {
+ vdd = vdd_current;
+ udelay(NUM_READINGS * WAIT_FOR_ADC);
+ vdd_current = read_voltage(i2caddress);
+ }
+ if (timeout == 0)
+ return -1;
+ return vdd_current;
+}
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+/* Set the voltage to the IR chip */
+static int set_voltage_to_IR(int i2caddress, int vdd)
+{
+ int wait, vdd_last;
+ int ret;
+ u8 vid;
+
+ /* Compensate for a board specific voltage drop between regulator and
+ * SoC before converting into an IR VID value
+ */
+ vdd += board_vdd_drop_compensation();
+ vid = DIV_ROUND_UP(vdd - 245, 5);
+
+ ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
+ 1, (void *)&vid, sizeof(vid));
+ if (ret) {
+ printf("VID: failed to write VID\n");
+ return -1;
+ }
+ wait = wait_for_new_voltage(vdd, i2caddress);
+ if (wait < 0)
+ return -1;
+ debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+
+ vdd_last = wait_for_voltage_stable(i2caddress);
+ if (vdd_last < 0)
+ return -1;
+ debug("VID: Current voltage is %d mV\n", vdd_last);
+ return vdd_last;
+}
+#endif
+
+static int set_voltage(int i2caddress, int vdd)
+{
+ int vdd_last = -1;
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+ vdd_last = set_voltage_to_IR(i2caddress, vdd);
+#else
+ #error Specific voltage monitor must be defined
+#endif
+ return vdd_last;
+}
+
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ /*
+ * VID is used according to the table below
+ * ---------------------------------------
+ * | DA_V |
+ * |-------------------------------------|
+ * | 5b00000 | 5b00001-5b11110 | 5b11111 |
+ * ---------------+---------+-----------------+---------|
+ * | D | 5b00000 | NO VID | VID = DA_V | NO VID |
+ * | A |----------+---------+-----------------+---------|
+ * | _ | 5b00001 |VID = | VID = |VID = |
+ * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
+ * | _ | 5b11110 | | | |
+ * | A |----------+---------+-----------------+---------|
+ * | L | 5b11111 | No VID | VID = DA_V | NO VID |
+ * | T | | | | |
+ * ------------------------------------------------------
+ */
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else {
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
+static int print_vdd(void)
+{
+ int vdd_last, ret, i2caddress;
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID : I2c failed to switch channel\n");
+ return -1;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ return -1;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ return -1;
+ }
+ printf("VID: Core voltage is at %d mV\n", vdd_last);
+
+ return 0;
+}
+
+static int do_vdd_override(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ ulong override;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!strict_strtoul(argv[1], 10, &override))
+ adjust_vdd(override); /* the value is checked by callee */
+ else
+ return CMD_RET_USAGE;
+ return 0;
+}
+
+static int do_vdd_read(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ print_vdd();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vdd_override, 2, 0, do_vdd_override,
+ "override VDD",
+ " - override with the voltage specified in mV, eg. 1050"
+);
+
+U_BOOT_CMD(
+ vdd_read, 1, 0, do_vdd_read,
+ "read VDD",
+ " - Read the voltage specified in mV"
+)
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
new file mode 100644
index 0000000..a9c7bb4
--- /dev/null
+++ b/board/freescale/common/vid.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __VID_H_
+#define __VID_H_
+
+#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
+#define IR36021_LOOP1_VOUT_OFFSET 0x9A
+#define IR36021_MFR_ID_OFFSET 0x92
+#define IR36021_MFR_ID 0x43
+
+/* step the IR regulator in 5mV increments */
+#define IR_VDD_STEP_DOWN 5
+#define IR_VDD_STEP_UP 5
+int adjust_vdd(ulong vdd_override);
+
+#endif /* __VID_H_ */
diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c
index 97a25e8..dd9c37e 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -13,7 +13,12 @@
#define INPUT_STATE_REG 0x13
#define GLOBAL_INPUT_ISE1 0x51
#define GLOBAL_INPUT_ISE2 0x52
+#define GLOBAL_INPUT_GAIN 0x53
#define GLOBAL_INPUT_LOS 0x55
+#define GLOBAL_OUTPUT_PE1 0x56
+#define GLOBAL_OUTPUT_PE2 0x57
+#define GLOBAL_OUTPUT_LEVEL 0x58
+#define GLOBAL_OUTPUT_TERMINATION 0x5A
#define GLOBAL_CORE_CNTRL 0x5D
#define OUTPUT_MODE_PAGE 0x23
#define CORE_CONTROL_PAGE 0x25
@@ -92,6 +97,109 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
return 0;
}
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con)
+{
+ unsigned int i;
+ u8 rev_id = 0;
+ int ret;
+
+ debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
+ vsc_addr);
+
+ ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+ if (ret < 0) {
+ printf("VSC:0x%x could not read REV_ID from device.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ if (rev_id != 0xab) {
+ printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+ vsc_addr);
+ return -ENODEV;
+ }
+
+ ret = vsc_if_enable(vsc_addr);
+ if (ret) {
+ printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ /* config connections - page 0x00 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+ /* Configure Global Input ISE */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0);
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0);
+
+ /* Configure Tx/Rx Global Output PE1 */
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0);
+
+ /* Configure Tx/Rx Global Output PE2 */
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0);
+
+ /* Configure Tx/Rx Global Input GAIN */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F);
+
+ /* Setting Global Input LOS threshold value */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0);
+
+ /* Setting Global output termination */
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0);
+
+ /* Configure Tx/Rx Global Output level */
+ if (vsc_addr == VSC3308_TX_ADDRESS)
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4);
+ else
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2);
+
+ /* Making crosspoint connections, by connecting required
+ * input to output */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+ /* input state - page 0x13 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+ /* Turning off all the required input of the switch */
+ for (i = 0; i < num_con; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][0], 1);
+
+ /* only turn on specific Tx/Rx requested by the XFI erratum */
+ if (vsc_addr == VSC3308_TX_ADDRESS) {
+ i2c_reg_write(vsc_addr, 2, 0);
+ i2c_reg_write(vsc_addr, 3, 0);
+ } else {
+ i2c_reg_write(vsc_addr, 0, 0);
+ i2c_reg_write(vsc_addr, 1, 0);
+ }
+
+ /* config output mode - page 0x23 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+ /* Turn off the Output driver correspond to required output*/
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], 1);
+
+ /* only turn on specific Tx/Rx requested by the XFI erratum */
+ if (vsc_addr == VSC3308_TX_ADDRESS) {
+ i2c_reg_write(vsc_addr, 0, 0);
+ i2c_reg_write(vsc_addr, 1, 0);
+ } else {
+ i2c_reg_write(vsc_addr, 3, 0);
+ i2c_reg_write(vsc_addr, 4, 0);
+ }
+
+ /* configure global core control register, Turn on Global core power */
+ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+ vsc_wp_config(vsc_addr);
+
+ return 0;
+}
+#endif
+
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con)
{
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
index 2a49187..d722ea3 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -14,6 +14,10 @@
int vsc_if_enable(unsigned int vsc_addr);
int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con);
+#endif
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
void vsc_wp_config(unsigned int vsc_addr);
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 65b3867..6f0fea1 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -190,7 +190,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -213,4 +213,6 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index 35825c4..396103f 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -62,7 +62,7 @@
#ifdef CONFIG_FMAN_ENET
-#define BRDCFG1_EMI1_SEL_MASK 0x70
+#define BRDCFG1_EMI1_SEL_MASK 0x78
#define BRDCFG1_EMI1_SEL_SLOT1 0x10
#define BRDCFG1_EMI1_SEL_SLOT2 0x20
#define BRDCFG1_EMI1_SEL_SLOT5 0x30
@@ -202,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
if (!path)
path = alias;
+ do_fixup_by_path(fdt, path, "reg",
+ &mux, sizeof(mux), 1);
do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
&mux, sizeof(mux), 1);
}
@@ -250,11 +252,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
return;
}
- if (mux == BRDCFG1_EMI1_SEL_RGMII) {
+ if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
/* RGMII */
/* The RGMII PHY is identified by the MAC connected to it */
sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
fdt_set_phy_handle(fdt, compat, addr, phy);
+ return;
}
/* If it's not RGMII or XGMII, it must be SGMII */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 5fafc85..0a7720a 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -17,6 +17,9 @@
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -137,9 +140,8 @@ int board_early_init_f(void)
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifdef CONFIG_TSEC_ENET
- out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
@@ -230,6 +232,13 @@ int board_init(void)
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ /*
+ * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -237,12 +246,19 @@ int board_init(void)
fsl_serdes_init();
config_serdes_mux();
#endif
+
+#ifdef CONFIG_U_QE
+ u_qe_init();
+#endif
+
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
u8 flash_read8(void *addr)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 50d5640..3e8c37b 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -17,6 +17,10 @@
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
@@ -251,11 +255,8 @@ int board_early_init_f(void)
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
- out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
- udelay(10);
- out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
#endif
#ifdef CONFIG_FSL_IFC
@@ -263,9 +264,7 @@ int board_early_init_f(void)
#endif
#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
- out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
#endif
return 0;
@@ -273,11 +272,25 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+ /*
+ * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
config_serdes_mux();
#endif
+#ifdef CONFIG_U_QE
+ u_qe_init();
+#endif
+
return 0;
}
@@ -290,9 +303,11 @@ int misc_init_r(void)
}
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
u8 flash_read8(void *addr)
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index 2c79a71..163a4c4 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -100,7 +100,7 @@ void fdt_fixup_board_enet(void *fdt)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -115,5 +115,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 940978e..40bd55d 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -275,8 +275,10 @@ int checkboard (void)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
index 71b760c..11747ca 100644
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -70,11 +70,12 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index fba41fe..93e1c50 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -161,11 +161,13 @@ int misc_init_r(void)
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 69e98a5..eac193e 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -116,12 +116,14 @@ int misc_init_r(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
#else /* CONFIG_SPL_BUILD */
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index e6f091f..ed611c5 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -188,7 +188,7 @@ void fdt_tsec1_fixup(void *fdt, bd_t *bd)
do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
@@ -196,6 +196,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_dr_usb(blob, bd);
fdt_tsec1_fixup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 3dce362..0a0152a 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -172,12 +172,14 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index b7ea0e4..adf4254 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -154,11 +154,13 @@ int checkboard(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index d909220..02b5040 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -273,11 +273,13 @@ void spi_cs_deactivate(struct spi_slave *slave)
#endif /* CONFIG_HARD_SPI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 803d722..22a1d99 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -378,11 +378,13 @@ int misc_init_r(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 5ff9dff..f0a55f8 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -402,7 +402,7 @@ static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
"peripheral", sizeof("peripheral"), 1);
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
@@ -447,5 +447,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
}
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
index fef230b..478f820 100644
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ b/board/freescale/mpc8360erdk/mpc8360erdk.c
@@ -340,9 +340,11 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_pci_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index c749e55..572913c 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -328,7 +328,7 @@ static void ft_pci_fixup(void *blob, bd_t *bd)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_tsec_fixup(blob, bd);
@@ -340,5 +340,7 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_pci_fixup(blob, bd);
ft_pcie_fixup(blob, bd);
#endif
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 9afdcaf..e0a1031 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -199,7 +199,7 @@ int misc_init_r(void)
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
@@ -207,5 +207,7 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 93eed59..7b0f461 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -271,7 +271,7 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
@@ -285,5 +285,6 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_dr_usb(blob, bd);
#endif
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 93288c7..1069e2c 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -218,8 +218,7 @@ pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
@@ -237,5 +236,7 @@ ft_board_setup(void *blob, bd_t *bd)
}
#endif
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 1b33db6..66fb228 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -305,7 +305,7 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
@@ -314,5 +314,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 7104e33..f99d639 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -438,8 +438,7 @@ pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
@@ -457,5 +456,7 @@ ft_board_setup(void *blob, bd_t *bd)
}
#endif
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index a8fdcb5..a5c5d9d 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -345,10 +345,12 @@ void pci_init_board(void)
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index cb55e1c..836578f 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -514,7 +514,7 @@ void pci_init_board(void)
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_SYS_UCC_RMII_MODE)
int nodeoff, off, err;
@@ -579,5 +579,7 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 1bbf832..3f68cf4 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -232,7 +232,7 @@ int board_eth_init(bd_t *bis)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -249,5 +249,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index d8740dd..95e398c 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -258,12 +258,13 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index a58b5f9..94633b5 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -119,12 +119,11 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int off;
u64 *tmp;
- u32 *addrcells;
+ int addrcells;
ft_cpu_setup(blob, bd);
@@ -136,12 +135,13 @@ ft_board_setup(void *blob, bd_t *bd)
* which is defined by the "reg" property in the soc node.
*/
off = fdt_path_offset(blob, "/soc8641");
- addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+ addrcells = fdt_address_cells(blob, 0);
tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
if (tmp) {
u64 addr;
- if (addrcells && (*addrcells == 1))
+
+ if (addrcells == 1)
addr = *(u32 *)tmp;
else
addr = *tmp;
@@ -152,6 +152,8 @@ ft_board_setup(void *blob, bd_t *bd)
"in u-boot. This means your .dts might "
"be old.\n");
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 491b576..1cf0ab7 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -444,7 +444,7 @@ void fdt_disable_uart1(void *blob)
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -496,6 +496,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_del_flexcan(blob);
fdt_disable_uart1(blob);
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index f5e1851..d7dd478 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -332,7 +332,7 @@ static void ft_codec_setup(void *blob, const char *compatible)
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -356,5 +356,7 @@ void ft_board_setup(void *blob, bd_t *bd)
/* Update the WM8776 node's clock frequency property */
ft_codec_setup(blob, "wlf,wm8776");
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index d4d277b..56f561a 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -130,7 +130,7 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -147,5 +147,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_fman_ethernet(blob);
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index aba4f53..61ed466 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -234,7 +234,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_pci_board_setup(void *blob);
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
const char *soc_usb_compat = "fsl-usb2-dr";
int err, usb1_off, usb2_off;
@@ -263,39 +263,41 @@ void ft_board_setup(void *blob, bd_t *bd)
int off = fdt_node_offset_by_compatible(blob, -1,
soc_elbc_compat);
if (off < 0) {
- printf("WARNING: could not find compatible node"
- " %s: %s.\n", soc_elbc_compat,
- fdt_strerror(off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_elbc_compat);
+ return off;
}
err = fdt_del_node(blob, off);
if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_elbc_compat, fdt_strerror(err));
+ printf("WARNING: could not remove %s\n",
+ soc_elbc_compat);
+ return err;
}
- return;
+ return 0;
}
#endif
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
if (usb1_off < 0) {
- printf("WARNING: could not find compatible node"
- " %s: %s.\n", soc_usb_compat,
- fdt_strerror(usb1_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb1_off;
}
usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
soc_usb_compat);
if (usb2_off < 0) {
- printf("WARNING: could not find compatible node"
- " %s: %s.\n", soc_usb_compat,
- fdt_strerror(usb2_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb2_off;
}
err = fdt_del_node(blob, usb2_off);
- if (err < 0)
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
+ if (err < 0) {
+ printf("WARNING: could not remove %s\n", soc_usb_compat);
+ return err;
+ }
+
+ return 0;
}
+
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a6756c6..3f47cfb 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -424,7 +424,7 @@ static void fdt_board_fixup_qe_pins(void *blob)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -459,17 +459,17 @@ void ft_board_setup(void *blob, bd_t *bd)
int off = fdt_node_offset_by_compatible(blob, -1,
soc_elbc_compat);
if (off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_elbc_compat,
- fdt_strerror(off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_elbc_compat);
+ return off;
}
err = fdt_del_node(blob, off);
if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_elbc_compat, fdt_strerror(err));
+ printf("WARNING: could not remove %s\n",
+ soc_elbc_compat);
+ return err;
}
- return;
+ return 0;
}
#endif
@@ -477,24 +477,23 @@ void ft_board_setup(void *blob, bd_t *bd)
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat,
- fdt_strerror(usb1_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb1_off;
}
usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
soc_usb_compat);
if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat,
- fdt_strerror(usb2_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb2_off;
}
err = fdt_del_node(blob, usb2_off);
if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
+ printf("WARNING: could not remove %s\n", soc_usb_compat);
+ return err;
}
+ return 0;
}
#endif
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index a0a416b..a40bea3 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -261,7 +261,7 @@ static void fdt_board_fixup_qe_pins(void *blob)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -283,5 +283,7 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_board_fixup_qe_pins(blob);
#endif
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
index f777bb9..1db37e3 100644
--- a/board/freescale/p2020come/p2020come.c
+++ b/board/freescale/p2020come/p2020come.c
@@ -250,7 +250,7 @@ int board_eth_init(bd_t *bis)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -269,5 +269,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index b72fcff..5d18e8d 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -236,7 +236,7 @@ int board_eth_init(bd_t *bis)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -257,5 +257,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index a14b43b..e600bdb 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -215,7 +215,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -239,4 +239,6 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
index 230870d..a0fca0d 100644
--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -235,9 +235,11 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
new file mode 100644
index 0000000..4d17798
--- /dev/null
+++ b/board/freescale/t102xqds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T102XQDS
+
+config SYS_BOARD
+ default "t102xqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T102xQDS"
+
+endif
diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS
new file mode 100644
index 0000000..1ffccc4
--- /dev/null
+++ b/board/freescale/t102xqds/MAINTAINERS
@@ -0,0 +1,12 @@
+T102XQDS BOARD
+M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+S: Maintained
+F: board/freescale/t102xqds/
+F: include/configs/T102xQDS.h
+F: configs/T1024QDS_defconfig
+F: configs/T1024QDS_NAND_defconfig
+F: configs/T1024QDS_SDCARD_defconfig
+F: configs/T1024QDS_SPIFLASH_defconfig
+F: configs/T1024QDS_D4_defconfig
+F: configs/T1024QDS_SECURE_BOOT_defconfig
+F: configs/T1024QDS_D4_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
new file mode 100644
index 0000000..d94f230
--- /dev/null
+++ b/board/freescale/t102xqds/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += t102xqds.o
+obj-y += eth_t102xqds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README
new file mode 100644
index 0000000..bb0f280
--- /dev/null
+++ b/board/freescale/t102xqds/README
@@ -0,0 +1,328 @@
+T1024 SoC Overview
+------------------
+The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
+combines two or one 64-bit Power Architecture e5500 core respectively with high
+performance datapath acceleration logic, and network peripheral bus interfaces
+required for networking and telecommunications. This processor can be used in
+applications such as enterprise WLAN access points, routers, switches, firewall
+and other packet processing intensive small enterprise and branch office appliances,
+and general-purpose embedded computing. Its high level of integration offers
+significant performance benefits and greatly helps to simplify board design.
+
+
+The T1024 SoC includes the following function and features:
+- two e5500 cores, each with a private 256 KB L2 cache
+ - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
+ - Three levels of instructions: User, supervisor, and hypervisor
+ - Independent boot and reset
+ - Secure boot capability
+- 256 KB shared L3 CoreNet platform cache (CPC)
+- Interconnect CoreNet platform
+ - CoreNet coherency manager supporting coherent and noncoherent transactions
+ with prioritization and bandwidth allocation amongst CoreNet endpoints
+ - 150 Gbps coherent read bandwidth
+- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
+- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion management
+ - Cryptography Acceleration (SEC 5.x)
+ - IEEE 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - MACSEC on DPAA-based Ethernet ports
+- Ethernet interfaces
+ - Four 1 Gbps Ethernet controllers
+- Parallel Ethernet interfaces
+ - Two RGMII interfaces
+- High speed peripheral interfaces
+ - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
+ - One SATA controller supporting 1.5 and 3.0 Gb/s operation
+ - One QSGMII interface
+ - Four SGMII interface supporting 1000 Mbps
+ - Three SGMII interfaces supporting up to 2500 Mbps
+ - 10GbE XFI or 10Base-KR interface
+- Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD interface (DIU) with 12 bit dual data rate
+- Multicore programmable interrupt controller (PIC)
+- Two 8-channel DMA engines
+- Single source clocking implementation
+- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+- QUICC Engine block
+ - 32-bit RISC controller for flexible support of the communications peripherals
+ - Serial DMA channel for receive and transmit on all serial channels
+ - Two universal communication controllers, supporting TDM, HDLC, and UART
+
+T1023 Personality
+------------------
+T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
+unavailable deep sleep. Rest of the blocks are almost same as T1024.
+Differences between T1024 and T1023
+Feature T1024 T1023
+QUICC Engine: yes no
+DIU: yes no
+Deep Sleep: yes no
+I2C controller: 4 3
+DDR: 64-bit 32-bit
+IFC: 32-bit 28-bit
+
+
+T1024QDS board Overview
+-----------------------
+- SERDES Connections
+ 4 lanes supporting the following:
+ - PCI Express: supports Gen 1 and Gen 2
+ - SGMII 1G and SGMII 2.5G
+ - QSGMII
+ - XFI
+ - SATA 2.0
+ - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
+ - Aurora debug with dedicated connectors.
+- DDR Controller
+ - Supports up to 1600 MTPS data-rate.
+ - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
+ - Supports Single-, dual- or quad-rank DIMMs
+ - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
+- IFC/Local Bus
+ - NAND Flash: 8-bit, async, up to 2GB
+ - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+ - NOR devices support 8 virtual banks
+ - Socketed to allow alternate devices
+ - GASIC: Simple (minimal) target within QIXIS FPGA
+ - PromJET rapid memory download support
+ - IFC Debug/Development card
+- Ethernet
+ - Two on-board RGMII 10M/100M/1G ethernet ports.
+ - One QSGMII interface
+ - Four SGMII interface supporting 1Gbps
+ - Three SGMII interfaces supporting 2.5Gbps
+ - one 10Gbps XFI or 10Base-KR interface
+- QIXIS System Logic FPGA
+ - Manages system power and reset sequencing.
+ - Manages the configurations of DUT, board, and clock for dynamic shmoo.
+ - Collects V-I-T data in background for code/power profiling.
+ - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
+ - General fault monitoring and logging.
+ - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
+- Clocks
+ - System and DDR clock (SYSCLK, DDRCLK).
+ - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
+ - Software programmable in 1 MHz increments from 1-200 MHz.
+ - SERDES clocks
+ - Provides clocks to SerDes blocks and slots.
+ - 100 MHz, 125 MHz and 156.25 MHz options.
+ - Spread-spectrum option for 100 MHz.
+- Power Supplies
+ - Dedicated PMBus regulator for VDD and VDDC.
+ - Adjustable from 0.7V to 1.3V at 35A
+ - VDD can be disabled independanty from VDDC for “deep sleep”.
+ - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
+ - VTT/MVREF automatically track operating voltage.
+ - Dedicated 2.5V VPP supply.
+ - Dedicated regulators/filters for AVDD supplies.
+ - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
+- Video
+ - DIU supports video up to 1280x1024x32 bpp.
+ - Chrontel CH7201 for HDMI connection.
+ - TI DS90C387R for direct LCD connection.
+ - Raw (not encoded) video connector for testing or other encoders.
+- USB
+ - Supports two USB 2.0 ports with integrated PHYs.
+ - Two type A ports with 5V@1.5A per port.
+ - Second port can be converted to OTG mini-AB.
+- SDHC
+ For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
+ - upport for optional clock feedback paths.
+ - Support for optional high-speed voltage translation direction controls.
+ - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
+ - Support for eMMC memory devices.
+- SPI
+ -On-board support of 3 different devices and sizes.
+- Other IO
+ - Two Serial ports
+ - ProfiBus port
+ - Four I2C ports
+
+
+Memory map on T1024QDS
+----------------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128MB NOR Flash memory Map
+--------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+SerDes clock vs DIP-switch settings
+-----------------------------------
+SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
+0x6F 100MHz 125MHz 1101
+0xD6 100MHz 100MHz 1111
+0x99 156.25MHz 100MHz 1011
+
+
+T1024 Clock frequency
+----------------------
+BIN Core DDR Platform FMan
+Bin1: 1400MHz 1600MT/s 400MHz 700MHz
+Bin2: 1200MHz 1600MT/s 400MHz 600MHz
+Bin3: 1000MHz 1600MT/s 400MHz 500MHz
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T1024QDS_defconfig (For DDR3L, by default)
+ or make T1024QDS_D4_defconfig (For DDR4)
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'qixis_reset altbank' in u-boot.
+ via DIP-switch: set SW6[1:4] = '0100'
+
+ To change boot source to vbank0:
+ via software: run command 'qixis_reset' in u-boot.
+ via DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T1024QDS_NAND_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T1024QDS_SPIFLASH_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T1024QDS_SDCARD_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+DIU/QE-TDM/SDXC settings
+-------------------
+a) For TDM Riser: set pin_mux=tdm in hwconfig
+b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
+c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
+d) For LCD(DFP): set pin_mux=lcd in hwconfig
+e) For SDXC: set adaptor=sdxc in hwconfig
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (30KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T1024QDS
+-------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x15FFFF u-boot env 8KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+0x180000 0x19FFFF QE Firmware 128KB
+
+
+SD Card memory Map on T1024QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+
+SPI Flash memory Map on T1024QDS
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+
+For more details, please refer to T1024QDS Reference Manual and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
new file mode 100644
index 0000000..46fc64e
--- /dev/null
+++ b/board/freescale/t102xqds/ddr.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * datarate_mhz_high values need to be in ascending order
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+#if defined(CONFIG_SYS_FSL_DDR4)
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+#else
+#error DDR type not defined
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust according to the board ddr freqency and n_banks
+ * specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+ debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
+ debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+
+ /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
+ * set DDR bus width to 32bit for T1023
+ */
+ if (cpu->soc_ver == SVR_T1023)
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+
+#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+ /* for DDR bus 32bit test on T1024 */
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
new file mode 100644
index 0000000..7723f58
--- /dev/null
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t102xqds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT4 5
+#define EMI1_SLOT5 6
+#define EMI2 7
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "T1024QDS_MDIO_RGMII1",
+ "T1024QDS_MDIO_RGMII2",
+ "T1024QDS_MDIO_SLOT1",
+ "T1024QDS_MDIO_SLOT2",
+ "T1024QDS_MDIO_SLOT3",
+ "T1024QDS_MDIO_SLOT4",
+ "T1024QDS_MDIO_SLOT5",
+ "T1024QDS_MDIO_10GC",
+ "NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {2, 3, 4, 5};
+
+static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name;
+
+ if (muxval > EMI2)
+ return NULL;
+
+ name = t1024qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct t1024qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void t1024qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t1024qds_mdio *priv = bus->priv;
+
+ t1024qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t1024qds_mdio *priv = bus->priv;
+
+ t1024qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1024qds_mdio_reset(struct mii_dev *bus)
+{
+ struct t1024qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t1024qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t1024qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate t1024qds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate t1024qds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t1024qds_mdio_read;
+ bus->write = t1024qds_mdio_write;
+ bus->reset = t1024qds_mdio_reset;
+ sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ struct fixed_link f_link;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
+ if (port == FM1_DTSEC3) {
+ fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
+ fdt_setprop(fdt, offset, "phy-connection-type",
+ "rgmii", 5);
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ if (port == FM1_DTSEC1) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_vsc8234_phy_s5");
+ } else if (port == FM1_DTSEC2) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_vsc8234_phy_s4");
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+ if (port == FM1_DTSEC3) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_aqr105_phy_s3");
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
+ break;
+ case FM1_DTSEC3:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
+ break;
+ case FM1_DTSEC4:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
+ break;
+ default:
+ break;
+ }
+ fdt_delprop(fdt, offset, "phy-connection-type");
+ fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ /* XFI interface */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:D} is configured
+ * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ switch (srds_s1) {
+ case 0x46:
+ case 0x47:
+ lane_to_slot[1] = 2;
+ break;
+ default:
+ break;
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
+
+ switch (srds_s1) {
+ case 0xd5:
+ case 0xd6:
+ /* QSGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC1, 0x8);
+ fm_info_set_phy_address(FM1_DTSEC2, 0x9);
+ fm_info_set_phy_address(FM1_DTSEC3, 0xa);
+ fm_info_set_phy_address(FM1_DTSEC4, 0xb);
+ break;
+ case 0x95:
+ case 0x99:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC, and should not use a real XAUI PHY address, since
+ * MDIO can access it successfully, and then MDIO thinks the
+ * XAUI card is used for the XFI MAC, which will cause error.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x6f:
+ /* SGMII in Slot3, Slot4, Slot5 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x7f:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
+ break;
+ case 0x47:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x77:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
+ break;
+ case 0x5a:
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x6a:
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x5b:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x6b:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ default:
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_2500_FM1_DTSEC1 + idx);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ }
+
+ if (lane < 0)
+ break;
+
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII2;
+ else if (i == FM1_DTSEC4)
+ mdio_mux[i] = EMI1_RGMII1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC1 + idx);
+ if (lane < 0)
+ break;
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c
new file mode 100644
index 0000000..b1c9d01
--- /dev/null
+++ b/board/freescale/t102xqds/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c
new file mode 100644
index 0000000..7369289
--- /dev/null
+++ b/board/freescale/t102xqds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
new file mode 100644
index 0000000..08aef6e
--- /dev/null
+++ b/board/freescale/t102xqds/spl.c
@@ -0,0 +1,151 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/qixis.h"
+#include "t102xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
+ /*
+ * There is T1040 SoC issue where NOR, FPGA are inaccessible during
+ * NAND boot because IFC signals > IFC_AD7 are not enabled.
+ * This workaround changes RCW source to make all signals enabled.
+ */
+ u32 porsr1, pinctl;
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
new file mode 100644
index 0000000..7b9e9b0
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_pbi.cfg
@@ -0,0 +1,26 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_rcw.cfg
new file mode 100644
index 0000000..4b8f719
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_rcw.cfg
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 e8104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
new file mode 100644
index 0000000..f3141b5
--- /dev/null
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <asm/mpc85xx_gpio.h>
+#include "../common/qixis.h"
+#include "t102xqds.h"
+#include "t102xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *const freq[] = {"100", "125", "156.25", "100.0"};
+ int clock;
+ u8 sw = QIXIS_READ(arch);
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+ printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFC Card\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ puts("SERDES Reference: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 6) & 3;
+ printf("Clock1=%sMHz ", freq[clock]);
+ clock = (sw >> 4) & 3;
+ printf("Clock2=%sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int board_mux_lane_to_slot(void)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1;
+ u8 brdcfg9;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
+
+ switch (srds_prtcl_s1) {
+ case 0:
+ /* SerDes1 is not enabled */
+ break;
+ case 0xd5:
+ case 0x5b:
+ case 0x6b:
+ case 0x77:
+ case 0x6f:
+ case 0x7f:
+ QIXIS_WRITE(brdcfg[12], 0x8c);
+ break;
+ case 0x40:
+ QIXIS_WRITE(brdcfg[12], 0xfc);
+ break;
+ case 0xd6:
+ case 0x5a:
+ case 0x6a:
+ case 0x56:
+ QIXIS_WRITE(brdcfg[12], 0x88);
+ break;
+ case 0x47:
+ QIXIS_WRITE(brdcfg[12], 0xcc);
+ break;
+ case 0x46:
+ QIXIS_WRITE(brdcfg[12], 0xc8);
+ break;
+ case 0x95:
+ case 0x99:
+ brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+ QIXIS_WRITE(brdcfg[12], 0x8c);
+ break;
+ case 0x116:
+ QIXIS_WRITE(brdcfg[12], 0x00);
+ break;
+ case 0x115:
+ case 0x119:
+ case 0x129:
+ case 0x12b:
+ /* Aurora, PCIe, SGMII, SATA */
+ QIXIS_WRITE(brdcfg[12], 0x04);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes Protocol %d\n",
+ srds_prtcl_s1);
+ return -1;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PPC_T1024
+static void board_mux_setup(void)
+{
+ u8 brdcfg15;
+
+ brdcfg15 = QIXIS_READ(brdcfg[15]);
+ brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
+
+ if (hwconfig_arg_cmp("pin_mux", "tdm")) {
+ /* Route QE_TDM multiplexed signals to TDM Riser slot */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
+ QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
+ QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
+ ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
+ } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
+ /* to UCC (ProfiBus) interface */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
+ } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
+ /* to DVI (HDMI) encoder */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
+ } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
+ /* to DFP (LCD) encoder */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
+ BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
+ }
+
+ if (hwconfig_arg_cmp("adaptor", "sdxc"))
+ /* Route SPI_CS multiplexed signals to SD slot */
+ QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
+ ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
+}
+#endif
+
+void board_retimer_ds125df111_init(void)
+{
+ u8 reg;
+
+ /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
+ reg = I2C_MUX_CH7;
+ i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
+ reg = I2C_MUX_CH5;
+ i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+
+ /* Read device revision and ID */
+ i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast */
+ reg = 0x0c;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+
+ /* Reset Channel Registers */
+ i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+ reg |= 0x4;
+ i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+
+ /* Enable override divider select and Enable Override Output Mux */
+ i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
+ reg |= 0x24;
+ i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
+ reg &= 0x8f;
+ i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
+
+ /* Select active PFD MUX input as re-timed data (001) */
+ i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
+ reg &= 0x3f;
+ reg |= 0x20;
+ i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
+ reg = 0xb2;
+ i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
+ reg = 0xcd;
+ i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ board_mux_lane_to_slot();
+ board_retimer_ds125df111_init();
+
+ /* Increase IO drive strength to address FCS error on RGMII */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+#define NUM_SRDS_PLL 2
+int misc_init_r(void)
+{
+#ifdef CONFIG_PPC_T1024
+ board_mux_setup();
+#endif
+ return 0;
+}
+
+void fdt_fixup_spi_mux(void *blob)
+{
+ int nodeoff = 0;
+
+ if (hwconfig_arg_cmp("pin_mux", "tdm")) {
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "eon,en25s64")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+ } else {
+ /* remove tdm node */
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "maxim,ds26522")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+ fdt_fixup_spi_mux(blob);
+
+ return 0;
+}
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h
new file mode 100644
index 0000000..64ff623
--- /dev/null
+++ b/board/freescale/t102xqds/t102xqds.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T102x_QDS_H__
+#define __T102x_QDS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
+
+#endif
diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h
new file mode 100644
index 0000000..a429fb7
--- /dev/null
+++ b/board/freescale/t102xqds/t102xqds_qixis.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T1024QDS_QIXIS_H__
+#define __T1024QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T1024/T1023 QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK 0xC0
+#define BRDCFG5_IMX_DIU 0x80
+
+#define BRDCFG5_SPIRTE_MASK 0x07
+#define BRDCFG5_SPIRTE_TDM 0x01
+#define BRDCFG5_SPIRTE_SDHC 0x02
+#define BRDCFG9_XFI_TX_DISABLE 0x10
+
+/* BRDCFG13[0:5] TDM configuration and setup */
+#define BRDCFG13_TDM_MASK 0xfc
+#define BRDCFG13_TDM_INTERFACE 0x37
+#define BRDCFG13_HDLC_LOOPBACK 0x29
+#define BRDCFG13_TDM_LOOPBACK 0x31
+
+/* BRDCFG15[3] controls LCD Panel Powerdown */
+#define BRDCFG15_LCDFM 0x20
+#define BRDCFG15_LCDPD 0x10
+#define BRDCFG15_LCDPD_MASK 0x10
+#define BRDCFG15_LCDPD_ENABLED 0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK 0x03
+#define BRDCFG15_DIUSEL_HDMI 0x00
+#define BRDCFG15_DIUSEL_LCD 0x01
+#define BRDCFG15_DIUSEL_UCC 0x02
+#define BRDCFG15_DIUSEL_TDM 0x03
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+#endif
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
new file mode 100644
index 0000000..409e173
--- /dev/null
+++ b/board/freescale/t102xqds/tlb.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+ /* entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so if needed more, will use entry 16 later.
+ */
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
new file mode 100644
index 0000000..10d49f5
--- /dev/null
+++ b/board/freescale/t102xrdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T102XRDB
+
+config SYS_BOARD
+ default "t102xrdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T102xRDB"
+
+endif
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
new file mode 100644
index 0000000..dc554d4
--- /dev/null
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -0,0 +1,10 @@
+T102XRDB BOARD
+M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+S: Maintained
+F: board/freescale/t102xrdb/
+F: include/configs/T102xRDB.h
+F: configs/T1024RDB_defconfig
+F: configs/T1024RDB_NAND_defconfig
+F: configs/T1024RDB_SDCARD_defconfig
+F: configs/T1024RDB_SPIFLASH_defconfig
+F: configs/T1024RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
new file mode 100644
index 0000000..a0cf8f6
--- /dev/null
+++ b/board/freescale/t102xrdb/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += t102xrdb.o
+obj-y += cpld.o
+obj-y += eth_t102xrdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
new file mode 100644
index 0000000..2b17f50
--- /dev/null
+++ b/board/freescale/t102xrdb/README
@@ -0,0 +1,258 @@
+T1024 SoC Overview
+------------------
+The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
+combines two or one 64-bit Power Architecture e5500 core respectively with high
+performance datapath acceleration logic, and network peripheral bus interfaces
+required for networking and telecommunications. This processor can be used in
+applications such as enterprise WLAN access points, routers, switches, firewall
+and other packet processing intensive small enterprise and branch office appliances,
+and general-purpose embedded computing. Its high level of integration offers
+significant performance benefits and greatly helps to simplify board design.
+
+
+The T1024 SoC includes the following function and features:
+- two e5500 cores, each with a private 256 KB L2 cache
+ - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
+ - Three levels of instructions: User, supervisor, and hypervisor
+ - Independent boot and reset
+ - Secure boot capability
+- 256 KB shared L3 CoreNet platform cache (CPC)
+- Interconnect CoreNet platform
+ - CoreNet coherency manager supporting coherent and noncoherent transactions
+ with prioritization and bandwidth allocation amongst CoreNet endpoints
+ - 150 Gbps coherent read bandwidth
+- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
+- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion management
+ - Cryptography Acceleration (SEC 5.x)
+ - IEEE 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - MACSEC on DPAA-based Ethernet ports
+- Ethernet interfaces
+ - Four 1 Gbps Ethernet controllers
+- Parallel Ethernet interfaces
+ - Two RGMII interfaces
+- High speed peripheral interfaces
+ - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
+ - One SATA controller supporting 1.5 and 3.0 Gb/s operation
+ - One QSGMII interface
+ - Four SGMII interface supporting 1000 Mbps
+ - Three SGMII interfaces supporting up to 2500 Mbps
+ - 10GbE XFI or 10Base-KR interface
+- Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD interface (DIU) with 12 bit dual data rate
+- Multicore programmable interrupt controller (PIC)
+- Two 8-channel DMA engines
+- Single source clocking implementation
+- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+- QUICC Engine block
+ - 32-bit RISC controller for flexible support of the communications peripherals
+ - Serial DMA channel for receive and transmit on all serial channels
+ - Two universal communication controllers, supporting TDM, HDLC, and UART
+
+T1023 Personality
+------------------
+T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
+unavailable deep sleep. Rest of the blocks are almost same as T1024.
+Differences between T1024 and T1023
+Feature T1024 T1023
+QUICC Engine: yes no
+DIU: yes no
+Deep Sleep: yes no
+I2C controller: 4 3
+DDR: 64-bit 32-bit
+IFC: 32-bit 28-bit
+
+
+T1024RDB board Overview
+-----------------------
+ - Ethernet
+ - Two on-board 10M/100M/1G bps RGMII ethernet ports
+ - One on-board 10G bps Base-T port.
+ - DDR Memory
+ - Supports 64-bit 4GB DDR3L DIMM
+ - PCIe
+ - One on-board PCIe slot.
+ - Two on-board PCIe Mini-PCIe connectors.
+ - IFC/Local Bus
+ - NOR: 128MB 16-bit NOR Flash
+ - NAND: 1GB 8-bit NAND flash
+ - CPLD: for system controlling with programable header on-board
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - one SD connector supporting 1.8V/3.3V via J53.
+ - SPI
+ - On-board 64MB SPI flash
+ - Other
+ - Two Serial ports
+ - Four I2C ports
+
+
+Memory map on T1024RDB
+----------------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128MB NOR Flash memory Map
+--------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+T1024 Clock frequency
+---------------------
+BIN Core DDR Platform FMan
+Bin1: 1400MHz 1600MT/s 400MHz 700MHz
+Bin2: 1200MHz 1600MT/s 400MHz 600MHz
+Bin3: 1000MHz 1600MT/s 400MHz 500MHz
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T1024RDB_defconfig
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'cpld reset altbank' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
+
+ To change boot source to vbank0:
+ via software: run command 'cpld reset' in u-boot.
+ via DIP-Switch: set SW3[5:7] = '000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T1024RDB_NAND_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T1024RDB_SPIFLASH_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T1024RDB_SDCARD_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (30KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T1024RDB
+-------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB(2 block)
+0x100000 0x17FFFF u-boot env 512KB(1 block)
+0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
+0x200000 0x27FFFF QE Firmware 512KB(1 block)
+
+
+SD Card memory Map on T1024RDB
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+
+SPI Flash memory Map on T1024RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+
+For more details, please refer to T1024RDB Reference Manual and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c
new file mode 100644
index 0000000..c03894a
--- /dev/null
+++ b/board/freescale/t102xrdb/cpld.c
@@ -0,0 +1,103 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale T1024RDB board-specific CPLD controlling supports.
+ *
+ * The following macros need to be defined:
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+ printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
+ printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
+ printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
+ printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
+ printf("int_status = 0x%02x\n", CPLD_READ(int_status));
+ printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
+ printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
+ printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
+ printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+ printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
+ printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
+ printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
+ printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
+ putc('\n');
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset - hard reset to default bank\n"
+ "cpld reset altbank - reset to alternate bank\n"
+ "cpld dump - display the CPLD registers\n"
+ );
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
new file mode 100644
index 0000000..5a3100f
--- /dev/null
+++ b/board/freescale/t102xrdb/cpld.h
@@ -0,0 +1,45 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+struct cpld_data {
+ u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl1; /* 0x10 - Reset control Register1 */
+ u8 reset_ctl2; /* 0x11 - Reset control Register2 */
+ u8 int_status; /* 0x12 - Interrupt status Register */
+ u8 flash_csr; /* 0x13 - Flash control and status register */
+ u8 fan_ctl_status; /* 0x14 - Fan control and status register */
+ u8 led_ctl_status; /* 0x15 - LED control and status register */
+ u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
+ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
+ u8 boot_override; /* 0x18 - Boot override register */
+ u8 boot_config1; /* 0x19 - Boot config override register*/
+ u8 boot_config2; /* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK 0x3F
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_OVERRIDE 0x40
+#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET 0xFF
+#define CPLD_LBMAP_SHIFT 0x03
+#define CPLD_BOOT_SEL 0x80
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
new file mode 100644
index 0000000..a20330b
--- /dev/null
+++ b/board/freescale/t102xrdb/ddr.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * datarate_mhz_high values need to be in ascending order
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust according to the board ddr freqency and n_banks
+ * specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+ debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
+ debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+
+ /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
+ * force DDR bus width to 32bit for T1023
+ */
+ if (cpu->soc_ver == SVR_T1023)
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+
+#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+ /* for DDR bus 32bit test on T1024 */
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
new file mode 100644
index 0000000..2e400c4
--- /dev/null
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
+
+ switch (srds_s1) {
+ case 0x95:
+ /* 10G XFI with Aquantia PHY */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ break;
+ default:
+ printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+}
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
new file mode 100644
index 0000000..1c9235f
--- /dev/null
+++ b/board/freescale/t102xrdb/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
new file mode 100644
index 0000000..ba7041a
--- /dev/null
+++ b/board/freescale/t102xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
new file mode 100644
index 0000000..dd2dec4
--- /dev/null
+++ b/board/freescale/t102xrdb/spl.c
@@ -0,0 +1,107 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg
new file mode 100644
index 0000000..7b9e9b0
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_pbi.cfg
@@ -0,0 +1,26 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/freescale/t102xrdb/t1024_rcw.cfg b/board/freescale/t102xrdb/t1024_rcw.cfg
new file mode 100644
index 0000000..cd6f906
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 ec027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
new file mode 100644
index 0000000..f5c438d
--- /dev/null
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <asm/mpc85xx_gpio.h>
+#include <fm_eth.h>
+#include "t102xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ u8 reg;
+
+ reg = CPLD_READ(flash_csr);
+
+ if (reg & CPLD_BOOT_SEL) {
+ puts("NAND\n");
+ } else {
+ reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+ printf("NOR vBank%d\n", reg);
+ }
+#endif
+
+ puts("SERDES Reference Clocks:\n");
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
new file mode 100644
index 0000000..2f23579
--- /dev/null
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T1024_RDB_H__
+#define __T1024_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
new file mode 100644
index 0000000..8269b3d
--- /dev/null
+++ b/board/freescale/t102xrdb/tlb.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+ /* entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so if needed more, will use entry 16 later.
+ */
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 19af46e..13285be 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -233,7 +233,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -259,6 +259,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
void qixis_dump_switch(void)
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 3822a37..e394b12 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -34,20 +34,26 @@ unsigned long get_board_ddr_clk(void)
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, uart_clk;
-#ifdef CONFIG_SPL_NAND_BOOT
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
u32 porsr1, pinctl;
+ u32 svr = get_svr();
#endif
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifdef CONFIG_SPL_NAND_BOOT
- /*
- * There is T1040 SoC issue where NOR, FPGA are inaccessible during
- * NAND boot because IFC signals > IFC_AD7 are not enabled.
- * This workaround changes RCW source to make all signals enabled.
- */
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
+ if (IS_SVR_REV(svr, 1, 0)) {
+ /*
+ * There is T1040 SoC issue where NOR, FPGA are inaccessible
+ * during NAND boot because IFC signals > IFC_AD7 are not
+ * enabled. This workaround changes RCW source to make all
+ * signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
+ | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+ pinctl);
+ }
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index ddb669f..4734f9d 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -85,7 +85,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -110,6 +110,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
#endif
+
+ return 0;
}
#ifdef CONFIG_DEEP_SLEEP
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
new file mode 100755
index 0000000..83060c1
--- /dev/null
+++ b/board/freescale/t208xqds/README
@@ -0,0 +1,274 @@
+The T2080QDS is a high-performance computing evaluation, development and
+test platform supporting the T2080 QorIQ Power Architecture processor.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+ - Up to four 10 Gbps Ethernet MACs
+ - Up to eight 1 Gbps Ethernet MACs
+ - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+ - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 2.0) controllers
+ - Two high-speed USB 2.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+ - Enhanced serial peripheral interface (eSPI)
+ - Four I2C controllers
+ - Four 2-pin UARTs or two 4-pin UARTs
+ - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+ Feature T2080 T2081
+ 1G Ethernet numbers: 8 6
+ 10G Ethernet numbers: 4 2
+ SerDes lanes: 16 8
+ Serial RapidIO,RMan: 2 no
+ SATA Controller: 2 no
+ Aurora: yes no
+ SoC Package: 896-pins 780-pins
+
+
+T2080QDS feature overview
+-------------------------
+Processor:
+ - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
+Memory:
+ - Single memory controller capable of supporting DDR3 and DDR3-LV devices
+ - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
+Ethernet interfaces:
+ - Two 1Gbps RGMII on-board ports
+ - Four 10Gbps XFI on-board cages
+ - 1Gbps/2.5Gbps SGMII Riser card
+ - 10Gbps XAUI Riser card
+Accelerator:
+ - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
+SerDes:
+ - 16 lanes up to 10.3125GHz
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+IFC:
+ - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
+eSPI:
+ - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
+USB:
+ - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
+PCIE:
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+SATA:
+ - Two SATA 2.0 ports on-board
+SRIO:
+ - Two Serial RapidIO 2.0 ports up to 5 GHz
+eSDHC:
+ - Supports SD/SDHC/SDXC/eMMC Card
+I2C:
+ - Four I2C controllers.
+UART:
+ - Dual 4-pins UART serial ports
+System Logic:
+ - QIXIS-II FPGA system controll
+Debug Features:
+ - Support Legacy, COP/JTAG, Aurora, Event and EVT
+XFI:
+ - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+ a on-board SFP+ cages, which to house optical module (fiber cable) or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+ introduced to indicate a XFI port will use copper cable, and U-boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:<10g_mac_name>
+ The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
+ hwconfig, then both four XFI ports will use copper cable.
+ set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
+1000BASE-KX(1G-KX):
+ - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
+ runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
+ in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
+ Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
+ initialization.
+ Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
+ 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
+ MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
+ stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
+ For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
+ hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
+
+System Memory map
+----------------
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T2080QDS_config
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ by software: run command 'qixis_reset altbank' in u-boot.
+ by DIP-switch: set SW6[1:4] = '0100'
+
+ To change boot source to vbank0:
+ by software: run command 'qixis_reset' in u-boot.
+ by DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T2080QDS_NAND_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T2080QDS_SPIFLASH_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T2080QDS_SDCARD_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_T2080_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
+0x100000 0x17FFFF u-boot env 512KB (1 block)
+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
+
+
+Micro SD Card memory Map on T2080QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+
+SPI Flash memory Map on T2080QDS
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x11FFFF FMAN ucode 64KB
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080QDS User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index ed52fef6..9c26fdf 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -28,17 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
- {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
- {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
+ {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
+ {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
+ {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
+ {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 5879198..b82e9e7 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -23,6 +23,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "t208xqds_qixis.h"
@@ -46,6 +47,15 @@
#define EMI2 8
#endif
+#define PCCR1_SGMIIA_KX_MASK 0x00008000
+#define PCCR1_SGMIIB_KX_MASK 0x00004000
+#define PCCR1_SGMIIC_KX_MASK 0x00002000
+#define PCCR1_SGMIID_KX_MASK 0x00001000
+#define PCCR1_SGMIIE_KX_MASK 0x00000800
+#define PCCR1_SGMIIF_KX_MASK 0x00000400
+#define PCCR1_SGMIIG_KX_MASK 0x00000200
+#define PCCR1_SGMIIH_KX_MASK 0x00000100
+
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
@@ -187,8 +197,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
{
int phy;
char alias[20];
+ char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
+ char buf[32] = "serdes-1,";
struct fixed_link f_link;
+ int media_type = 0;
+ int off;
+
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_T2080QDS
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
+#endif
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -199,9 +219,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
switch (port) {
#if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx1");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIH_KX_MASK);
+ break;
+ }
case FM1_DTSEC2:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx2");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIG_KX_MASK);
+ break;
+ }
case FM1_DTSEC9:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx9");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIE_KX_MASK);
+ break;
+ }
case FM1_DTSEC10:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx10");
+ fdt_status_okay_by_alias(fdt,
+ "1gkx_pcs_mdio10");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIF_KX_MASK);
+ break;
+ }
if (mdio_mux[port] == EMI1_SLOT2) {
sprintf(alias, "phy_sgmii_s2_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
@@ -213,7 +278,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
}
break;
case FM1_DTSEC5:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx5");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
+ sprintf(buf, "%s%s%s", buf, "lane-g,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIC_KX_MASK);
+ break;
+ }
case FM1_DTSEC6:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx6");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
+ sprintf(buf, "%s%s%s", buf, "lane-h,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIID_KX_MASK);
+ break;
+ }
if (mdio_mux[port] == EMI1_SLOT1) {
sprintf(alias, "phy_sgmii_s1_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
@@ -257,6 +344,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
default:
break;
}
+ if (media_type) {
+ /* set property for 1000BASE-KX in dtb */
+ off = fdt_node_offset_by_compat_reg(fdt,
+ "fsl,fman-memac-mdio", addr + 0x1000);
+ fdt_setprop_string(fdt, off, "lane-instance", buf);
+ }
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
switch (srds_s1) {
@@ -265,15 +358,77 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
case 0x6c:
case 0x6d:
case 0x71:
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for XFI */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
+ /*
+ * if the 10G is XFI, check hwconfig to see what is the
+ * media type, there are two types, fiber or copper,
+ * fix the dtb accordingly.
+ */
+ switch (port) {
+ case FM1_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+ /* it's MAC9 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi9");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+ /* it's MAC10 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi10");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC3:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
+ /* it's MAC1 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi1");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC4:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
+ /* it's MAC2 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi2");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ default:
+ return;
+ }
+
+ if (!media_type) {
+ /* fixed-link is used for XFI fiber cable */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ } else {
+ /* set property for copper cable */
+ off = fdt_node_offset_by_compat_reg(fdt,
+ "fsl,fman-memac-mdio", addr + 0x1000);
+ fdt_setprop_string(fdt, off,
+ "lane-instance", buf);
+ }
break;
default:
break;
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
index 972dedc..52a1652 100644
--- a/board/freescale/t208xqds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -1,8 +1,16 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#SerDes Protocol: 0x66_0x16
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-66150002 00008400 e8104000 c1000000
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index fc6d256..7c89cd5 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -20,6 +20,7 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
+#include "../common/vid.h"
#include "t208xqds.h"
#include "t208xqds_qixis.h"
@@ -86,6 +87,11 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
}
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
int brd_mux_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -358,6 +364,13 @@ int board_early_init_r(void)
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -437,7 +450,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -460,4 +473,6 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
index 15e1bf4..59025ea 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -1,8 +1,16 @@
-#PBL preamble and RCW header for T2080RDB
+#PBL preamble and RCW header
aa55aa55 010e0100
-#SerDes Protocol: 0x66_0x16
-#Core/DDR: 1533Mhz/1600MT/s
-120c0017 15000000 00000000 00000000
-66150002 00008400 ec104000 c1000000
-00000000 00000000 00000000 000307fc
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+1206001b 15000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00800000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index be99fb8..341453b 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -103,7 +103,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -126,4 +126,6 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index 479e124..5441094 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -69,7 +69,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -83,4 +83,6 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 6205fea..4f2cccd 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -683,7 +683,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -706,6 +706,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 2ff77b8..fac442b 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -88,7 +88,7 @@ int misc_init_r(void)
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -111,6 +111,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*
diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c
index 29e40eb..5d957b7 100644
--- a/board/galaxy5200/galaxy5200.c
+++ b/board/galaxy5200/galaxy5200.c
@@ -146,9 +146,11 @@ int checkboard(void)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index df491a8..bb08cd2 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1483,7 +1483,7 @@ int misc_init_r(void)
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
struct ventana_board_info *info = &ventana_info;
struct ventana_eeprom_config *cfg;
@@ -1495,7 +1495,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (getenv("fdt_noauto")) {
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
- return;
+ return 0;
}
/* Update partition nodes using info from mtdparts env var */
@@ -1504,7 +1504,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (!model) {
puts("invalid board info: Leaving FDT fully enabled\n");
- return;
+ return 0;
}
printf(" Adjusting FDT per EEPROM for %s...\n", model);
@@ -1523,7 +1523,7 @@ void ft_board_setup(void *blob, bd_t *bd)
*/
if (getenv("fdt_noconfig")) {
puts(" Skiping periperhal config (fdt_noconfig defined)\n");
- return;
+ return 0;
}
cfg = econfig;
while (cfg->name) {
@@ -1533,6 +1533,8 @@ void ft_board_setup(void *blob, bd_t *bd)
}
cfg++;
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index ee6f9e0..8d01d8b 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -206,7 +206,7 @@ int misc_init_r(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
extern void __ft_board_setup(void *blob, bd_t *bd);
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
__ft_board_setup(blob, bd);
@@ -215,5 +215,7 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
"disabled", sizeof("disabled"), 1);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index a051682..e4434b3 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -531,11 +531,13 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index f76d968..64d90dd 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -326,7 +326,7 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -343,6 +343,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 88cee05..1822237 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -5,15 +5,14 @@
*/
#include <common.h>
+#include <cros_ec.h>
#include <asm/gpio.h>
int arch_early_init_r(void)
{
- return 0;
-}
+ if (cros_ec_board_init())
+ return -1;
-int board_early_init_r(void)
-{
return 0;
}
diff --git a/board/hermes/Kconfig b/board/hermes/Kconfig
deleted file mode 100644
index deb37fd..0000000
--- a/board/hermes/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_HERMES
-
-config SYS_BOARD
- default "hermes"
-
-config SYS_CONFIG_NAME
- default "hermes"
-
-endif
diff --git a/board/hermes/MAINTAINERS b/board/hermes/MAINTAINERS
deleted file mode 100644
index a596dad..0000000
--- a/board/hermes/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HERMES BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/hermes/
-F: include/configs/hermes.h
-F: configs/hermes_defconfig
diff --git a/board/hermes/Makefile b/board/hermes/Makefile
deleted file mode 100644
index ccca520..0000000
--- a/board/hermes/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hermes.o flash.o
diff --git a/board/hermes/flash.c b/board/hermes/flash.c
deleted file mode 100644
index 38d3cd3..0000000
--- a/board/hermes/flash.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- uchar value;
- vu_char *caddr = (vu_char *)addr;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0AAA] = 0xAA;
- caddr[0x0555] = 0x55;
- caddr[0x0AAA] = 0x90;
-
- value = caddr[0];
- switch (value) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = caddr[2]; /* device ID */
-
- switch (value) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[4] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *)info->start[0];
-
- *caddr = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
- addr[0x0AAA] = 0x80;
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char*)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_char*)(info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
- addr[0x0AAA] = 0xA0;
-
- *((vu_char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
deleted file mode 100644
index 6126b73..0000000
--- a/board/hermes/hermes.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static ulong board_init (void);
-static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
- uchar * msg);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
- 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ID string (HERMES...)
- *
- * Return code for board revision and network speed
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: ");
-
- if (l < 0 || strncmp(buf, "HERMES", 6)) {
- puts ("### No HW ID - assuming HERMES-PRO");
- } else {
- for (i = 0; i < l; i++) {
- if (buf[i] == ' ')
- break;
- putc (buf[i]);
- }
- }
-
- gd->board_type = board_init ();
-
- printf (" Rev. %ld.x\n", (gd->board_type >> 16));
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size, size8, size9;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = 0x0400;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 1 to the SDRAM banks at preliminary address
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- /* HERMES-PRO boards have only one bank SDRAM */
-
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mamr = 0xD0802114;
- memctl->memc_mcr = 0x80002105;
- udelay (1);
- memctl->memc_mamr = 0xD0802118;
- memctl->memc_mcr = 0x80002130;
- udelay (1);
- memctl->memc_mamr = 0xD0802114;
- memctl->memc_mcr = 0x80002106;
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- udelay (10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define PB_LED_3 0x00020000 /* Status LED's */
-#define PB_LED_2 0x00010000
-#define PB_LED_1 0x00008000
-#define PB_LED_0 0x00004000
-
-#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
-
-#define PC_REP_SPD1 0x00000800
-#define PC_REP_SPD0 0x00000400
-
-#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
-
-#define PB_MAI_4 0x00000010 /* Configuration */
-#define PB_MAI_3 0x00000008
-#define PB_MAI_2 0x00000004
-#define PB_MAI_1 0x00000002
-#define PB_MAI_0 0x00000001
-
-#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
-
-
-#define PC_REP_MGRPRS 0x0200
-#define PC_REP_SPD 0x0040 /* Select 100 Mbps */
-#define PC_REP_RES 0x0004
-#define PC_BIT14 0x0002 /* ??? */
-#define PC_BIT15 0x0001 /* ??? ENDSL ?? */
-
-/* ------------------------------------------------------------------------- */
-
-static ulong board_init (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ulong reg, revision, speed = 100;
- int ethspeed;
- char *s;
-
- if ((s = getenv ("ethspeed")) != NULL) {
- if (strcmp (s, "100") == 0) {
- ethspeed = 100;
- } else if (strcmp (s, "10") == 0) {
- ethspeed = 10;
- } else {
- ethspeed = 0;
- }
- } else {
- ethspeed = 0;
- }
-
- /* Configure Port B Output Pins => 0x0003cc3F */
- reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
- PB_MAI_ALL;
- immr->im_cpm.cp_pbpar &= ~reg;
- immr->im_cpm.cp_pbodr &= ~reg;
- immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
- immr->im_cpm.cp_pbdir |= reg;
-
- /* Check hardware revision */
- if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
- /*
- * Revision 3.x hardware
- */
- revision = 3;
-
- immr->im_ioport.iop_pcdat = 0x0240;
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */
- immr->im_ioport.iop_pcdat |= PC_REP_RES;
- } else {
- immr->im_ioport.iop_pcdat = 0x0002;
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */
-
- if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
- /*
- * Revision 2.x hardware: PC9 connected to PB21
- */
- revision = 2;
-
- if (ethspeed == 0) {
- /* both 10 and 100 Mbps allowed:
- * select 10 Mbps and autonegotiation
- */
- puts (" [10+100]");
- immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
- speed = 10;
- } else if (ethspeed == 10) {
- /* we are asked for 10 Mbps,
- * so select 10 Mbps
- */
- puts (" [10]");
- immr->im_cpm.cp_pbdat = 0; /* ??? */
- speed = 10;
- } else {
- /* anything else:
- * select 100 Mbps
- */
- puts (" [100]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
- /* SPD1:SPD0 = 1:1 - 100 Mbps */
- speed = 100;
- }
- immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
-
- /* must be run from RAM */
- /* start_lxt980 (speed); */
- /*************************/
- } else {
- /*
- * Revision 1.x hardware
- */
- revision = 1;
-
- immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */
-
- if (ethspeed == 0) {
- /* both 10 and 100 Mbps allowed:
- * select 100 Mbps and autonegotiation
- */
- puts (" [10+100]");
- immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
- immr->im_ioport.iop_pcdat |= PC_REP_SPD;
- } else if (ethspeed == 10) {
- /* we are asked for 10 Mbps,
- * so select 10 Mbps
- */
- puts (" [10]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
- } else {
- /* anything else:
- * select 100 Mbps
- */
- puts (" [100]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
- /* SPD1:SPD0 = 1:1 - 100 Mbps */
- immr->im_ioport.iop_pcdat |= PC_REP_SPD;
- }
-
- immr->im_ioport.iop_pcdat |= PC_REP_RES;
- }
- }
- SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC);
-
- return ((revision << 16) | (speed & 0xFFFF));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define SCC_SM 1 /* Index => SCC2 */
-#define PROFF PROFF_SCC2
-
-#define SMI_MSGLEN 8 /* Length of SMI Messages */
-
-#define PHYGPCR_ADDR 0x109 /* Port Enable */
-#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
-#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
-#define RPRESET_ADDR 0x144 /* Repeater Reset */
-
-#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
-#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
-#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
-#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
-#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Must run from RAM:
- * uses parameter RAM area which is used for stack while running from ROM
- */
-void hermes_start_lxt980 (int speed)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
- volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
- volatile cbd_t *bd;
- volatile hdlc_pram_t *hp;
- uchar smimsg[SMI_MSGLEN];
- ushort phypcrval;
- uint bd_off;
- int pnr;
-
- printf ("LXT9880: %3d Mbps\n", speed);
-
- immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
- immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
- immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
- immr->im_ioport.iop_padir |= 0x4000;
-
- /* get temporary BD; no need for permanent alloc */
- bd_off = dpram_base_align (8);
-
- bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
-
- bd->cbd_bufaddr = 0;
- bd->cbd_datlen = 0;
- bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
-
- /* init. baudrate generator BRG4 */
- cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */
-
- cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
- cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
-
- /* init SCC_SM register */
- sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
- sp->scc_todr = 0x0000;
- sp->scc_dsr = 0x7e7e;
-
- /* init. SCC_SM parameter area */
- hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
-
- hp->tbase = bd_off; /* offset from beginning of DPRAM */
-
- hp->rfcr = 0x18;
- hp->tfcr = 0x18;
- hp->mrblr = 10;
-
- hp->c_mask = 0x0000f0b8;
- hp->c_pres = 0x0000ffff;
-
- hp->disfc = 0;
- hp->crcec = 0;
- hp->abtsc = 0;
- hp->nmarc = 0;
- hp->retrc = 0;
-
- hp->mflr = 10;
-
- hp->rfthr = 1;
-
- hp->hmask = 0;
- hp->haddr1 = 0;
- hp->haddr2 = 0;
- hp->haddr3 = 0;
- hp->haddr4 = 0;
-
- cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */
- while (cp->cp_cpcr & CPM_CR_FLG);
-
- /* clear all outstanding SCC events */
- sp->scc_scce = ~0;
-
- /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
- sp->scc_gsmrh = 0;
- sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
- SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
-
-#if 0
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
- smimsg[3] = RPRESET_ADDR >> 4;
- smimsg[4] = 0x01;
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-#endif
-
- smimsg[0] = 0x7f; /* BROADCAST */
- smimsg[1] = 0x34; /* ASSIGN HUB ID */
- smimsg[2] = 0x00;
- smimsg[3] = 0x00;
- smimsg[4] = 0x00; /* HUB ID = 0 */
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- smimsg[0] = 0x7f; /* BROADCAST */
- smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
- smimsg[2] = 0x00; /* ADDRESS = 0 */
- smimsg[3] = 0x00;
- smimsg[4] = 0x00; /* DATA = 0 */
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- if (speed == 100) {
- phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
- } else {
- phypcrval = 0; /* 10 MBIT, disable autoneg. */
- }
-
- /* send MSGs */
- for (pnr = 0; pnr < 8; pnr++) {
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
- smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
- smimsg[4] = (unsigned char) (phypcrval & 0xff);
- smimsg[5] = (unsigned char) (phypcrval >> 8);
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
- }
-
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
- smimsg[3] = PHYGPCR_ADDR >> 4;
- smimsg[4] = 0xff; /* enable port 1-8 */
- smimsg[5] = 0x01; /* enable MII1 (0x01) */
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
- smimsg[3] = LEDPCR_ADDR >> 4;
- smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
- smimsg[5] = 0xaa;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- /*
- * Disable Transmitter (so that we can free the BD, too)
- */
- sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
- uchar * msg)
-{
-#ifdef DEBUG
- unsigned hub, chip, cmd, length, addr;
-
- hub = msg[0] & 0x1F;
- chip = msg[0] >> 5;
- cmd = msg[1] & 0x1F;
- length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
- addr = (msg[2] >> 4) | (msg[3] << 4);
-
- printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
- "%02x %02x %02x %02x\n",
- hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
-#endif /* DEBUG */
-
- bd->cbd_bufaddr = (uint) msg;
- bd->cbd_datlen = SMI_MSGLEN;
- bd->cbd_sc |= BD_SC_READY;
-
- /* wait for msg transmitted */
- while ((sp->scc_scce & 0x0002) == 0);
- /* clear all events */
- sp->scc_scce = ~0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void show_boot_progress (int status)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* let things compatible */
- if (status < -BOOTSTAGE_ID_POST_FAIL_R)
- status = -1;
- status ^= 0x0F;
- status = (status & 0x0F) << 14;
- immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
deleted file mode 100644
index 0309860..0000000
--- a/board/hermes/u-boot.lds
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- board/hermes/built-in.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug
deleted file mode 100644
index f34c07b..0000000
--- a/board/hermes/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index a1b6749..fc2385c 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -94,7 +94,7 @@ void dram_init_banksize(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *fdt, bd_t *bd)
+int ft_board_setup(void *fdt, bd_t *bd)
{
static const char disabled[] = "disabled";
u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
@@ -106,6 +106,8 @@ void ft_board_setup(void *fdt, bd_t *bd)
if (!(reg & PWRDOM_STAT_EMMC))
do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
disabled, sizeof(disabled), 1);
+
+ return 0;
}
#endif
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index a99416b..f0af24a 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -311,10 +311,11 @@ void ide_set_reset (int idereset)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index f742143..e7838dc 100644
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -138,9 +138,11 @@ phys_size_t initdram(int board_type)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
index 0fbdfdb..5d2ab2f 100644
--- a/board/ifm/ac14xx/ac14xx.c
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -608,8 +608,10 @@ int checkboard(void)
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
index 6716ffc..ca09767 100644
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -364,7 +364,7 @@ int update_flash_size(int flash_size)
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
@@ -380,5 +380,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 5843725..4ab7160 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -454,7 +454,7 @@ int update_flash_size (int flash_size)
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
@@ -478,5 +478,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
index d44c4bf..2078f53 100644
--- a/board/ipek01/ipek01.c
+++ b/board/ipek01/ipek01.c
@@ -196,10 +196,12 @@ void pci_init_board (void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 7b87cc2..47522f8 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -150,6 +150,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
void set_fdt(void)
{
switch (gd->bd->bi_arch_number) {
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 78e4b5d..8856393 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -283,9 +283,10 @@ void ide_set_reset (int idereset)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
index dfbfab8..bf84676 100644
--- a/board/keymile/km82xx/km82xx.c
+++ b/board/keymile/km82xx/km82xx.c
@@ -300,11 +300,9 @@ phys_size_t initdram(int board_type)
out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
-#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
psize = probe_sdram(memctl);
-#endif /* CONFIG_SYS_RAMBOOT */
icache_enable();
@@ -460,8 +458,10 @@ static void setports(int gpio)
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 0543483..1da0dcb 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -359,9 +359,11 @@ int checkboard(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 4a73613..a74f75b 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -261,7 +261,7 @@ void fdt_fixup_fman_mac_addresses(void *blob)
}
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -286,6 +286,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_fman_mac_addresses(blob);
#endif
+
+ return 0;
}
#if defined(CONFIG_POST)
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 8b83000..d9ab2fd 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -610,7 +610,7 @@ void pci_target_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
@@ -627,5 +627,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c
index a4c1998..71c6a79 100644
--- a/board/kup/kup4k/kup4k.c
+++ b/board/kup/kup4k/kup4k.c
@@ -280,8 +280,10 @@ static unsigned char swapbyte(unsigned char c)
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 1fd9f2c..609edf1 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -128,6 +128,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#ifdef CONFIG_SMC911X
/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
static const u32 gpmc_lan92xx_config[] = {
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 9ef0026..d39203a 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -109,6 +109,11 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
#ifdef CONFIG_CMD_NET
diff --git a/board/manroland/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c
index c3ce66d..c8ed5b7 100644
--- a/board/manroland/mucmc52/mucmc52.c
+++ b/board/manroland/mucmc52/mucmc52.c
@@ -385,8 +385,10 @@ void pci_init_board (void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/manroland/uc101/uc101.c b/board/manroland/uc101/uc101.c
index 5c5afa2..e794c46 100644
--- a/board/manroland/uc101/uc101.c
+++ b/board/manroland/uc101/uc101.c
@@ -358,8 +358,10 @@ void hw_watchdog_reset(void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
index a69359f..c9d615b 100644
--- a/board/matrix_vision/mvblx/mvblx.c
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -94,6 +94,12 @@ int board_mmc_init(bd_t *bis)
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
#endif
#if defined(CONFIG_CMD_NET)
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index a6235e5..4d0ebaa 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -185,9 +185,11 @@ int checkboard(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
index 2009e62..688cc12 100644
--- a/board/mpc8308_p1m/mpc8308_p1m.c
+++ b/board/mpc8308_p1m/mpc8308_p1m.c
@@ -62,10 +62,12 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c
index 08eb5e8..e0c4dba 100644
--- a/board/muas3001/muas3001.c
+++ b/board/muas3001/muas3001.c
@@ -243,14 +243,11 @@ phys_size_t initdram (int board_type)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
long psize;
-#ifndef CONFIG_SYS_RAMBOOT
long sizelittle, sizebig;
-#endif
memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
@@ -263,7 +260,6 @@ phys_size_t initdram (int board_type)
psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
(uchar *) CONFIG_SYS_SDRAM_BASE);
}
-#endif /* CONFIG_SYS_RAMBOOT */
icache_enable ();
@@ -329,9 +325,11 @@ void ft_blob_update (void *blob, bd_t *bd)
}
}
-void ft_board_setup (void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
ft_blob_update (blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 319fa8c..23d0f56 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -146,9 +146,10 @@ void pci_init_board(void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index c2e07db..b6b8ad6 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -659,3 +659,9 @@ int board_mmc_init(bd_t *bis)
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
diff --git a/board/overo/overo.c b/board/overo/overo.c
index dfb8602..b7f85e7 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -493,6 +493,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 146dcea..59b5a7e 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -126,4 +126,9 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 15f8f31..81f3024 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -477,7 +477,7 @@ static unsigned char edid_buf[128] = {
};
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[8];
int rc, i = 0;
@@ -526,6 +526,8 @@ void ft_board_setup(void *blob, bd_t *bd)
if (rc)
printf("Unable to update flash reg property, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
index ce515d8..ed41de1 100644
--- a/board/phytec/pcm030/pcm030.c
+++ b/board/phytec/pcm030/pcm030.c
@@ -164,9 +164,11 @@ void pci_init_board(void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/raspberrypi/rpi_b/Kconfig b/board/raspberrypi/rpi/Kconfig
index 501d511..6a538cf 100644
--- a/board/raspberrypi/rpi_b/Kconfig
+++ b/board/raspberrypi/rpi/Kconfig
@@ -1,7 +1,7 @@
-if TARGET_RPI_B
+if TARGET_RPI
config SYS_BOARD
- default "rpi_b"
+ default "rpi"
config SYS_VENDOR
default "raspberrypi"
@@ -10,6 +10,6 @@ config SYS_SOC
default "bcm2835"
config SYS_CONFIG_NAME
- default "rpi_b"
+ default "rpi"
endif
diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS
new file mode 100644
index 0000000..6dcb7bd
--- /dev/null
+++ b/board/raspberrypi/rpi/MAINTAINERS
@@ -0,0 +1,6 @@
+RPI BOARD
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: board/raspberrypi/rpi/
+F: include/configs/rpi.h
+F: configs/rpi_defconfig
diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi/Makefile
index 7e9bfbf..c53c92b 100644
--- a/board/raspberrypi/rpi_b/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -12,4 +12,4 @@
# GNU General Public License for more details.
#
-obj-y := rpi_b.o
+obj-y := rpi.o
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi/rpi.c
index 7445f53..51a4fa1 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -42,6 +42,12 @@ struct msg_get_arm_mem {
u32 end_tag;
};
+struct msg_get_board_rev {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+ u32 end_tag;
+};
+
struct msg_get_mac_address {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_get_mac_address get_mac_address;
@@ -60,6 +66,67 @@ struct msg_get_clock_rate {
u32 end_tag;
};
+/* See comments in mbox.h for data source */
+static const struct {
+ const char *name;
+ const char *fdtfile;
+} models[] = {
+ [BCM2835_BOARD_REV_B_I2C0_2] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C0_3] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_4] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_5] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_6] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_A_7] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_A_8] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_A_9] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_d] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_e] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_f] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_PLUS] = {
+ "Model B+",
+ "bcm2835-rpi-b-plus.dtb",
+ },
+ [BCM2835_BOARD_REV_CM] = {
+ "Compute Module",
+ "bcm2835-rpi-cm.dtb",
+ },
+};
+
+u32 rpi_board_rev = 0;
+
int dram_init(void)
{
ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
@@ -79,13 +146,27 @@ int dram_init(void)
return 0;
}
-int misc_init_r(void)
+static void set_fdtfile(void)
+{
+ const char *fdtfile;
+
+ if (getenv("fdtfile"))
+ return;
+
+ fdtfile = models[rpi_board_rev].fdtfile;
+ if (!fdtfile)
+ fdtfile = "bcm2835-rpi-other.dtb";
+
+ setenv("fdtfile", fdtfile);
+}
+
+static void set_usbethaddr(void)
{
ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
int ret;
if (getenv("usbethaddr"))
- return 0;
+ return;
BCM2835_MBOX_INIT_HDR(msg);
BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
@@ -94,11 +175,18 @@ int misc_init_r(void)
if (ret) {
printf("bcm2835: Could not query MAC address\n");
/* Ignore error; not critical */
- return 0;
+ return;
}
eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+ return;
+}
+
+int misc_init_r(void)
+{
+ set_fdtfile();
+ set_usbethaddr();
return 0;
}
@@ -126,8 +214,36 @@ static int power_on_module(u32 module)
return 0;
}
+static void get_board_rev(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+ int ret;
+ const char *name;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query board revision\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ rpi_board_rev = msg->get_board_rev.body.resp.rev;
+ if (rpi_board_rev >= ARRAY_SIZE(models))
+ rpi_board_rev = 0;
+
+ name = models[rpi_board_rev].name;
+ if (!name)
+ name = "Unknown model";
+ printf("RPI model: %s\n", name);
+}
+
int board_init(void)
{
+ get_board_rev();
+
gd->bd->bi_boot_params = 0x100;
return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
@@ -154,7 +270,7 @@ int board_mmc_init(bd_t *bis)
msg_clk->get_clock_rate.body.resp.rate_hz);
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
/*
* For now, we simply always add the simplefb DT node. Later, we
@@ -162,4 +278,6 @@ void ft_board_setup(void *blob, bd_t *bd)
* node exists for the "real" graphics driver.
*/
lcd_dt_simplefb_add_node(blob);
+
+ return 0;
}
diff --git a/board/raspberrypi/rpi_b/MAINTAINERS b/board/raspberrypi/rpi_b/MAINTAINERS
deleted file mode 100644
index 14f3948..0000000
--- a/board/raspberrypi/rpi_b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RPI_B BOARD
-M: Stephen Warren <swarren@wwwdotorg.org>
-S: Maintained
-F: board/raspberrypi/rpi_b/
-F: include/configs/rpi_b.h
-F: configs/rpi_b_defconfig
diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
index 9ed12bd..6904e39 100644
--- a/board/renesas/alt/Makefile
+++ b/board/renesas/alt/Makefile
@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := alt.o qos.o
+obj-y := alt.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 523c5f1..8cc17e9 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -15,6 +15,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@@ -37,30 +39,11 @@ void s_init(void)
qos_init();
}
-#define MSTPSR1 0xE6150038
-#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
-
-#define MSTPSR7 0xE61501C4
-#define SMSTPCR7 0xE615014C
#define SCIF2_MSTP719 (1 << 19)
-
-#define MSTPSR8 0xE61509A0
-#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-
-#define MSTPSR3 0xE6150048
-#define SMSTPCR3 0xE615013C
#define IIC1_MSTP323 (1 << 23)
-
-#define mstp_setbits(type, addr, saddr, set) \
- out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
- out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
- mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear) \
- mstp_clrbits(le32, addr, saddr, clear)
+#define MMC0_MSTP315 (1 << 15)
int board_early_init_f(void)
{
@@ -76,15 +59,13 @@ int board_early_init_f(void)
/* IIC1 / sh-i2c ch1 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
+#ifdef CONFIG_SH_MMCIF
+ /* MMC */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
+#endif
return 0;
}
-void arch_preboot_os(void)
-{
- /* Disable TMU0 */
- mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
int board_init(void)
{
/* adress of boot parameters */
@@ -145,6 +126,19 @@ int board_eth_init(bd_t *bis)
#endif
}
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+ gpio_request(GPIO_GP_4_31, NULL);
+ gpio_set_value(GPIO_GP_4_31, 1);
+
+ ret = mmcif_mmc_init();
+#endif
+ return ret;
+}
+
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile
index a4fb6cc..2dac748 100644
--- a/board/renesas/gose/Makefile
+++ b/board/renesas/gose/Makefile
@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := gose.o qos.o
+obj-y := gose.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 715fba0..677b976 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -15,6 +15,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@@ -41,27 +42,10 @@ void s_init(void)
qos_init();
}
-#define MSTPSR1 0xE6150038
-#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
-
-#define MSTPSR7 0xE61501C4
-#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
-
-#define MSTPSR8 0xE61509A0
-#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-#define mstp_setbits(type, addr, saddr, set) \
- out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
- out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
- mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear) \
- mstp_clrbits(le32, addr, saddr, clear)
-
int board_early_init_f(void)
{
/* TMU0 */
@@ -76,16 +60,6 @@ int board_early_init_f(void)
return 0;
}
-#define TSTR0 0x04
-#define TSTR0_STR0 0x01
-void arch_preboot_os(void)
-{
- /* stop TMU0 */
- mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
- /* Disable TMU0 */
- mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
#define PUPR5 0xE6060114
#define PUPR5_ETH 0x3FFC0000
#define PUPR5_ETH_MAGIC (1 << 27)
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
index b4d0183..c10bba5 100644
--- a/board/renesas/koelsch/Makefile
+++ b/board/renesas/koelsch/Makefile
@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := koelsch.o qos.o
+obj-y := koelsch.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 244bc58..10fa571 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -16,6 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@@ -43,27 +44,10 @@ void s_init(void)
qos_init();
}
-#define MSTPSR1 0xE6150038
-#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
-
-#define MSTPSR7 0xE61501C4
-#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
-
-#define MSTPSR8 0xE61509A0
-#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-#define mstp_setbits(type, addr, saddr, set) \
- out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
- out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
- mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear) \
- mstp_clrbits(le32, addr, saddr, clear)
-
int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
@@ -77,12 +61,6 @@ int board_early_init_f(void)
return 0;
}
-void arch_preboot_os(void)
-{
- /* Disable TMU0 */
- mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
/* LSI pin pull-up control */
#define PUPR5 0xe6060114
#define PUPR5_ETH 0x3FFC0000
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
index 034c6f8..8d03461 100644
--- a/board/renesas/lager/Makefile
+++ b/board/renesas/lager/Makefile
@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := lager.o qos.o
+obj-y := lager.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 93273b2..d1e29d2 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -18,8 +18,11 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
#include <miiphy.h>
#include <i2c.h>
+#include <mmc.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -50,26 +53,10 @@ void s_init(void)
qos_init();
}
-#define MSTPSR1 0xE6150038
-#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
-
-#define MSTPSR7 0xE61501C4
-#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
-
-#define MSTPSR8 0xE61509A0
-#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-
-#define mstp_setbits(type, addr, saddr, set) \
- out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
- out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
- mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear) \
- mstp_clrbits(le32, addr, saddr, clear)
+#define MMC1_MSTP305 (1 << 5)
int board_early_init_f(void)
{
@@ -79,16 +66,12 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+ /* eMMC */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
return 0;
}
-void arch_preboot_os(void)
-{
- /* Disable TMU0 */
- mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
@@ -163,6 +146,28 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+ gpio_request(GPIO_FN_MMC1_D0, NULL);
+ gpio_request(GPIO_FN_MMC1_D1, NULL);
+ gpio_request(GPIO_FN_MMC1_D2, NULL);
+ gpio_request(GPIO_FN_MMC1_D3, NULL);
+ gpio_request(GPIO_FN_MMC1_D4, NULL);
+ gpio_request(GPIO_FN_MMC1_D5, NULL);
+ gpio_request(GPIO_FN_MMC1_D6, NULL);
+ gpio_request(GPIO_FN_MMC1_D7, NULL);
+ gpio_request(GPIO_FN_MMC1_CLK, NULL);
+ gpio_request(GPIO_FN_MMC1_CMD, NULL);
+
+ ret = mmcif_mmc_init();
+#endif
+ return ret;
+}
+
+
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
diff --git a/board/renesas/rcar-gen2-common/common.c b/board/renesas/rcar-gen2-common/common.c
new file mode 100644
index 0000000..0103f42
--- /dev/null
+++ b/board/renesas/rcar-gen2-common/common.c
@@ -0,0 +1,59 @@
+/*
+ * board/renesas/rcar-gen2-common/common.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#define TSTR0 0x04
+#define TSTR0_STR0 0x01
+
+static struct mstp_ctl mstptbl[] = {
+ { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
+ RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
+ { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
+ RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
+ { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
+ RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
+ { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
+ RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
+ { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
+ RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
+ { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
+ RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
+ /* No MSTP6 */
+ { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
+ RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
+ { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
+ RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
+ { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
+ RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
+ { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
+ RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
+ { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
+ RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
+};
+
+void arch_preboot_os(void)
+{
+ int i;
+
+ /* stop TMU0 */
+ mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
+
+ /* Stop module clock */
+ for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
+ mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
+ mstptbl[i].s_ena);
+ mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
+ mstptbl[i].r_ena);
+ }
+}
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 33003ee..b7d2381 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -382,6 +382,22 @@ static void board_gpio_init(void)
gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
gpio_direction_input(EXYNOS4X12_GPIO_X31);
+
+ /* Blue LED (Odroid X2/U2/U3) */
+ gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
+
+ gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
+
+#ifdef CONFIG_CMD_USB
+ /* USB3503A Reference frequency */
+ gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
+
+ /* USB3503A Connect */
+ gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
+
+ /* USB3503A Reset */
+ gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
+#endif
}
static int pmic_init_max77686(void)
@@ -462,9 +478,39 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
.usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
+#endif
+
+#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
int board_usb_init(int index, enum usb_init_type init)
{
+#ifdef CONFIG_CMD_USB
+ struct pmic *p_pmic;
+
+ /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
+ /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
+ if (gd->board_type == ODROID_TYPE_U3)
+ gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
+ else
+ gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+
+ /* Disconnect, Reset, Connect */
+ gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
+
+ /* Power off and on BUCK8 for LAN9730 */
+ debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
+
+ p_pmic = pmic_get("MAX77686_PMIC");
+ if (p_pmic && !pmic_probe(p_pmic)) {
+ max77686_set_buck_voltage(p_pmic, 8, 750000);
+ max77686_set_buck_voltage(p_pmic, 8, 3300000);
+ }
+
+#endif
+
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
}
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
index d3a5b7f..e7aafe5 100644
--- a/board/samsung/smdk5420/Kconfig
+++ b/board/samsung/smdk5420/Kconfig
@@ -1,3 +1,19 @@
+if TARGET_PEACH_PI
+
+config SYS_BOARD
+ string
+ default "smdk5420"
+
+config SYS_VENDOR
+ string
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ string
+ default "peach-pi"
+
+endif
+
if TARGET_PEACH_PIT
config SYS_BOARD
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
index e0f5c7a..1423f83 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -6,3 +6,5 @@ F: include/configs/peach-pit.h
F: configs/peach-pit_defconfig
F: include/configs/smdk5420.h
F: configs/smdk5420_defconfig
+F: include/configs/peach-pi.h
+F: configs/peach-pi_defconfig
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 89da47e..72786d2 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -214,11 +214,13 @@ void sdram_init(void)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index d584276..25329e4 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -301,12 +301,14 @@ int last_stage_init(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_FSL_PCI_INIT
FT_FSL_PCI_SETUP;
#endif
+
+ return 0;
}
#endif
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 4906be4..6bdf1a2 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -173,11 +173,13 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 2782bcc..cc0ac6b 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -96,15 +96,6 @@ const struct dpll_params *get_dpll_ddr_params(void)
return &dpll_ddr;
}
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- omap_nand_switch_ecc(1, 8);
-
- return 0;
-}
-#endif
-
#ifndef CONFIG_SPL_BUILD
#if defined(BOARD_DFU_BUTTON_GPIO)
/*
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index 266dbbb..7baac3d 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -86,6 +86,7 @@ int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record,
int i, nxt = 0;
int c;
unsigned char end = 0xff;
+ unsigned char tmp;
for (i = 0; fact_get_char(i) != end; i = nxt) {
nxt = i + 1;
@@ -93,6 +94,7 @@ int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record,
int pos;
int endpos;
int z;
+ int level = 0;
c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
strlen((char *)record));
@@ -103,22 +105,30 @@ int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record,
/* search for "<" */
c = -1;
for (z = pos; fact_get_char(z) != end; z++) {
- if ((fact_get_char(z) == '<') ||
- (fact_get_char(z) == '>')) {
- endpos = z;
- nxt = endpos;
- c = 0;
- break;
+ if (fact_get_char(z) == '<') {
+ if (level == 0) {
+ endpos = z;
+ nxt = endpos;
+ c = 0;
+ break;
+ } else {
+ level--;
+ }
}
+ if (fact_get_char(z) == '>')
+ level++;
}
+ } else {
+ continue;
}
if (c == 0) {
/* end found -> call get_factory_val */
+ tmp = eeprom_buf[endpos];
eeprom_buf[endpos] = end;
ret = get_factory_val(&eeprom_buf[pos],
- size - pos, name, buf, len);
+ endpos - pos, name, buf, len);
/* fix buffer */
- eeprom_buf[endpos] = '<';
+ eeprom_buf[endpos] = tmp;
debug("%s: %s.%s = %s\n",
__func__, record, name, buf);
return ret;
@@ -210,15 +220,6 @@ int factoryset_read_eeprom(int i2c_addr)
printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
factory_dat.usb_product_id);
#endif
- if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
- (uchar *)"id", buf,
- MAX_STRING_LENGTH)) {
- if (strncmp((const char *)buf, "PXM50", 5) == 0)
- factory_dat.pxm50 = 1;
- else
- factory_dat.pxm50 = 0;
- }
- debug("PXM50: %d\n", factory_dat.pxm50);
#if defined(CONFIG_VIDEO)
if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
(uchar *)"name", factory_dat.disp_name,
@@ -238,6 +239,23 @@ int factoryset_read_eeprom(int i2c_addr)
NULL, 16);
debug("version number: %d\n", factory_dat.version);
}
+ /* Get ASN from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"id", factory_dat.asn,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset asn: %s\n", factory_dat.asn);
+ } else {
+ factory_dat.asn[0] = 0;
+ }
+ /* Get COMP/ver from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP",
+ (uchar *)"ver",
+ factory_dat.comp_version,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset COMP/ver: %s\n", factory_dat.comp_version);
+ } else {
+ strcpy((char *)factory_dat.comp_version, "1.0");
+ }
return 0;
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index 4d6de10..3f23d5e 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -20,6 +20,8 @@ struct factorysetcontainer {
#endif
unsigned char serial[MAX_STRING_LENGTH];
int version;
+ uchar asn[MAX_STRING_LENGTH];
+ uchar comp_version[MAX_STRING_LENGTH];
};
int factoryset_read_eeprom(int i2c_addr);
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 9be2e34..ede73ba 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -280,4 +280,13 @@ U_BOOT_CMD(
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ omap_nand_switch_ecc(1, 8);
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 559af0e..264ba02 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -428,4 +428,38 @@ static int board_video_init(void)
return 0;
}
#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+
+ omap_nand_switch_ecc(1, 8);
+
+#ifdef CONFIG_FACTORYSET
+ if (factory_dat.asn[0] != 0) {
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
+ factory_dat.pxm50 = 1;
+ else
+ factory_dat.pxm50 = 0;
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+ } else {
+ factory_dat.pxm50 = 1;
+ ret = setenv("boardid", "PXM50_1.0");
+ if (ret)
+ printf("error setting board id\n");
+ }
+ debug("PXM50: %d\n", factory_dat.pxm50);
+#endif
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 1752df2..fb840f7 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -467,4 +467,27 @@ static int board_video_init(void)
return 0;
}
#endif /* ifdef CONFIG_VIDEO */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ omap_nand_switch_ecc(1, 8);
+
+ if (factory_dat.asn[0] != 0)
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ else
+ sprintf(tmp, "QMX7.E38_4.0");
+
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 2caefbb..953a43f 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -218,8 +218,7 @@ int board_early_init_r (void)
#endif /* CONFIG_BOARD_EARLY_INIT_R */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[12];
int rc, i = 0;
@@ -251,6 +250,8 @@ ft_board_setup(void *blob, bd_t *bd)
if (rc)
printf("Unable to update localbus ranges, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig
new file mode 100644
index 0000000..8bda349
--- /dev/null
+++ b/board/st/stv0991/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_STV0991
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_BOARD
+ string
+ default "stv0991"
+
+config SYS_VENDOR
+ string
+ default "st"
+
+config SYS_SOC
+ string
+ default "stv0991"
+
+config SYS_CONFIG_NAME
+ string
+ default "stv0991"
+
+endif
diff --git a/board/st/stv0991/MAINTAINERS b/board/st/stv0991/MAINTAINERS
new file mode 100644
index 0000000..87221e9
--- /dev/null
+++ b/board/st/stv0991/MAINTAINERS
@@ -0,0 +1,5 @@
+STV0991 APPLICATION BOARD
+M: Vikas Manocha <vikas.manocha@st.com>
+S: Maintained
+F: board/st/stv0991/
+F: include/configs/stv0991.h
diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile
new file mode 100644
index 0000000..fb5169a
--- /dev/null
+++ b/board/st/stv0991/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := stv0991.o
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
new file mode 100644
index 0000000..f465699
--- /dev/null
+++ b/board/st/stv0991/stv0991.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/stv0991_periph.h>
+#include <asm/arch/stv0991_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gpio_regs *const gpioa_regs =
+ (struct gpio_regs *) GPIOA_BASE_ADDR;
+
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = 0x80406000,
+ .type = TYPE_PL011,
+ .clock = 2700 * 1000,
+};
+
+U_BOOT_DEVICE(stv09911_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+ printf("%i\n", progress);
+}
+#endif
+
+void enable_eth_phy(void)
+{
+ /* Set GPIOA_06 pad HIGH (Appli board)*/
+ writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
+ writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
+}
+int board_eth_enable(void)
+{
+ stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
+ clock_setup(ETH_CLOCK_CFG);
+ enable_eth_phy();
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ board_eth_enable();
+ return 0;
+}
+
+int board_uart_init(void)
+{
+ stv0991_pinmux_config(UART_GPIOC_30_31);
+ clock_setup(UART_CLOCK_CFG);
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ board_uart_init();
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index f5c3d75..6e4eed8 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -233,9 +233,11 @@ reset_phy(void)
}
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 7555896..246cd9a 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -24,6 +24,7 @@ config MACH_SUN7I
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I
bool "sun8i (Allwinner A23)"
@@ -215,4 +216,18 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
+config VIDEO
+ boolean "Enable graphical uboot console on HDMI"
+ default y
+ ---help---
+ Say Y here to add support for using a cfb console on the HDMI output
+ found on most sunxi devices.
+
+config USB_KEYBOARD
+ boolean "Enable USB keyboard support"
+ default y
+ ---help---
+ Say Y here to add support for using a USB keyboard (typically used
+ in combination with a graphical console on HDMI).
+
endif
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
index 5e12328..b7f0dda 100644
--- a/board/sunxi/ahci.c
+++ b/board/sunxi/ahci.c
@@ -76,6 +76,8 @@ void scsi_init(void)
#ifdef CONFIG_SATAPWR
gpio_request(CONFIG_SATAPWR, "satapwr");
gpio_direction_output(CONFIG_SATAPWR, 1);
+ /* Give attached sata device time to power-up to avoid link timeouts */
+ mdelay(500);
#endif
if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index e6ec5b8..4c1c69a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -24,6 +24,7 @@
#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/display.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
@@ -237,3 +238,12 @@ int misc_init_r(void)
return 0;
}
#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_VIDEO_DT_SIMPLEFB
+ return sunxi_simplefb_setup(blob);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 051aca0..571bc9e 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
+#ifndef CONFIG_MACH_SUN6I
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+ setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#endif
/* Set MII clock */
#ifdef CONFIG_RGMII
@@ -33,6 +38,7 @@ int sunxi_gmac_initialize(bd_t *bis)
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
#endif
+#ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
@@ -43,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis)
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
+#elif defined CONFIG_RGMII
+ /* Configure sun6i RGMII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+#elif defined CONFIG_GMII
+ /* Configure sun6i GMII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#else
+ /* Configure sun6i MII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+#endif
#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#elif defined CONFIG_GMII
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
#else
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
#endif
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
index 44a8240..744ff44 100644
--- a/board/technexion/tao3530/tao3530.c
+++ b/board/technexion/tao3530/tao3530.c
@@ -188,6 +188,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 4c5e381..7b37fbe 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -534,6 +534,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig
new file mode 100644
index 0000000..a305ff1
--- /dev/null
+++ b/board/ti/beagle_x15/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BEAGLE_X15
+
+config SYS_BOARD
+ default "beagle_x15"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "beagle_x15"
+
+endif
diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile
new file mode 100644
index 0000000..5cd6873
--- /dev/null
+++ b/board/ti/beagle_x15/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Texas Instruments, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
new file mode 100644
index 0000000..db96e34
--- /dev/null
+++ b/board/ti/beagle_x15/board.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <palmas.h>
+#include <sata.h>
+#include <usb.h>
+#include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <asm/arch/gpio.h>
+#include <environment.h>
+
+#include "mux_data.h"
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: BeagleBoard x15\n"
+};
+
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80740300,
+ .is_ma_present = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &beagle_x15_lisa_regs;
+}
+
+static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+ .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00360036,
+ 0x00340034,
+ 0x00360036,
+ 0x00350035,
+ 0x00350035,
+
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+
+ 0x00430043,
+ 0x003e003e,
+ 0x004a004a,
+ 0x00470047,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
+ .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00370037,
+ 0x00390039,
+ 0x00360036,
+ 0x00370037,
+ 0x00350035,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x00540054,
+ 0x00540054,
+ 0x004e004e,
+ 0x004c004c,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+ break;
+ case 2:
+ *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ break;
+ }
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ case 2:
+ *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ }
+}
+
+struct vcores_data beagle_x15_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS45,
+ .gpu.pmic = &tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS6,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS45,
+ .iva.pmic = &tps659038,
+};
+
+void hw_data_init(void)
+{
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &beagle_x15_volts;
+ *ctrl = &dra7xx_ctrl;
+}
+
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ init_sata(0);
+ /*
+ * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
+ * This is the POWERHOLD-in-Low behavior.
+ */
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+ return 0;
+}
+
+static void do_set_mux32(u32 base,
+ struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 1,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 2,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ uint32_t ctrl_val;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+ ret = cpsw_register(&cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+int board_usb_init(int index, enum usb_init_type init)
+{
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
+
+ return 0;
+}
+#endif
diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h
new file mode 100644
index 0000000..2294abe
--- /dev/null
+++ b/board/ti/beagle_x15/mux_data.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MUX_DATA_BEAGLE_X15_H_
+#define _MUX_DATA_BEAGLE_X15_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+ {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
+ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
+ {RGMII0_TXC, (M0) },
+ {RGMII0_TXCTL, (M0) },
+ {RGMII0_TXD3, (M0) },
+ {RGMII0_TXD2, (M0) },
+ {RGMII0_TXD1, (M0) },
+ {RGMII0_TXD0, (M0) },
+ {RGMII0_RXC, (IEN | M0) },
+ {RGMII0_RXCTL, (IEN | M0) },
+ {RGMII0_RXD3, (IEN | M0) },
+ {RGMII0_RXD2, (IEN | M0) },
+ {RGMII0_RXD1, (IEN | M0) },
+ {RGMII0_RXD0, (IEN | M0) },
+ {USB1_DRVVBUS, (M0 | FSC) },
+ {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+};
+#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 37df7b2..6522241 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -96,18 +96,6 @@ int board_late_init(void)
return 0;
}
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- return 0;
-}
-
static void do_set_mux32(u32 base,
struct pad_conf_entry const *array, int size)
{
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 7276014..4824077 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -130,8 +130,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
- {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
- {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
{GPMC_A18, (M1)}, /* QSPI1_SCLK */
{GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 81dd081..3f93d9c 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -20,6 +20,7 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/gpio.h>
#include <i2c.h>
+#include <twl4030.h>
#include <asm/mach-types.h>
#include <linux/mtd/nand.h>
#include "evm.h"
@@ -264,3 +265,10 @@ int board_mmc_init(bd_t *bis)
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index ff7bc4b..04ec675 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -114,7 +114,7 @@ u32 spl_boot_device(void)
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int lpae;
char *env;
@@ -217,6 +217,8 @@ void ft_board_setup(void *blob, bd_t *bd)
}
}
}
+
+ return 0;
}
void ft_board_setup_ex(void *blob, bd_t *bd)
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
index 957940d..7171363 100644
--- a/board/ti/sdp3430/sdp.c
+++ b/board/ti/sdp3430/sdp.c
@@ -195,4 +195,9 @@ int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index bcbee73..b978044 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -124,6 +124,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
/*
* Routine: board_eth_init
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index a1f56cd..e9363ea 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -863,12 +863,14 @@ int board_get_height (void)
#endif /* CONFIG_VIDEO_SM501 */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#if defined(CONFIG_VIDEO)
fdt_add_edid(blob, "smi,sm501", edid_buf);
#endif
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index 814fcb2..d891a38 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -414,12 +414,14 @@ static void set_ddr_config(void) {
}
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif /* CONFIG_PCI */
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
index 9ce2a57..3b5230a 100644
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -674,10 +674,12 @@ void ft_blob_update (void *blob, bd_t *bd)
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_blob_update(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index e480d57..c9e163e 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -266,12 +266,14 @@ int checkboard(void)
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
/* bring in eMMC dsr settings */
do_fixup_by_path_u32(blob,
"/soc/aips-bus@02100000/usdhc@02198000",
"dsr", tqma6_emmc_dsr, 2);
tqma6_bb_ft_board_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index c4feef8..7f24a30 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -192,11 +192,13 @@ void pci_init_board(void)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index b7ad349..0028870 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -69,11 +69,13 @@ phys_size_t initdram(int board_type)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c
index aa9e99d..6a3df52 100644
--- a/board/xes/xpedite520x/xpedite520x.c
+++ b/board/xes/xpedite520x/xpedite520x.c
@@ -70,11 +70,13 @@ int board_early_init_r(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c
index efd563b..41419fe 100644
--- a/board/xes/xpedite537x/xpedite537x.c
+++ b/board/xes/xpedite537x/xpedite537x.c
@@ -72,11 +72,13 @@ int board_early_init_r(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
index e64d682..1f05150 100644
--- a/board/xes/xpedite550x/xpedite550x.c
+++ b/board/xes/xpedite550x/xpedite550x.c
@@ -72,11 +72,13 @@ int board_early_init_r(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/common/Makefile b/common/Makefile
index 9c47e20..c668a2f 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -8,22 +8,12 @@
# core
ifndef CONFIG_SPL_BUILD
obj-y += main.o
-obj-y += command.o
obj-y += exports.o
obj-y += hash.o
ifdef CONFIG_SYS_HUSH_PARSER
obj-y += cli_hush.o
endif
-# We always have this since drivers/ddr/fs/interactive.c needs it
-obj-y += cli_simple.o
-
-obj-y += cli.o
-obj-y += cli_readline.o
-obj-y += s_record.o
-obj-y += xyzModem.o
-obj-y += cmd_disk.o
-
# This option is not just y/n - it can have a numeric value
ifdef CONFIG_BOOTDELAY
obj-y += autoboot.o
@@ -272,4 +262,14 @@ endif
obj-$(CONFIG_CMD_BLOB) += cmd_blob.o
+# We always have this since drivers/ddr/fs/interactive.c needs it
+obj-y += cli_simple.o
+
+obj-y += cli.o
+obj-y += cli_readline.o
+obj-y += command.o
+obj-y += s_record.o
+obj-y += xyzModem.o
+obj-y += cmd_disk.o
+
CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
diff --git a/common/board_f.c b/common/board_f.c
index f8fd324..98c9c72 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -581,7 +581,7 @@ static int reserve_stacks(void)
gd->irq_sp = gd->start_addr_sp;
# endif
#else
-# if defined(CONFIG_PPC) || defined(CONFIG_MIPS)
+# ifdef CONFIG_PPC
ulong *s;
# endif
@@ -611,12 +611,6 @@ static int reserve_stacks(void)
s = (ulong *) gd->start_addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
-# elif defined(CONFIG_MIPS)
- /* Clear initial stack frame */
- s = (ulong *) gd->start_addr_sp;
- *s-- = 0;
- *s-- = 0;
- gd->start_addr_sp = (ulong) s;
# endif /* Architecture specific code */
return 0;
diff --git a/common/board_r.c b/common/board_r.c
index 19c6427..4eb7a02 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -291,26 +291,14 @@ static int initr_flash(void)
{
ulong flash_size = 0;
bd_t *bd = gd->bd;
- int ok;
puts("Flash: ");
- if (board_flash_wp_on()) {
+ if (board_flash_wp_on())
printf("Uninitialized - Write Protect On\n");
- /* Since WP is on, we can't find real size. Set to 0 */
- ok = 1;
- } else {
+ else
flash_size = flash_init();
- ok = flash_size > 0;
- }
- if (!ok) {
- puts("*** failed ***\n");
-#ifdef CONFIG_PPC
- /* Why does PPC do this? */
- hang();
-#endif
- return -1;
- }
+
print_size(flash_size, "");
#ifdef CONFIG_SYS_FLASH_CHECKSUM
/*
@@ -454,24 +442,6 @@ static int initr_env(void)
return 0;
}
-#ifdef CONFIG_HERMES
-static int initr_hermes(void)
-{
- if ((gd->board_type >> 16) == 2)
- gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;
- else
- gd->bd->bi_ethspeed = 0xFFFF;
- return 0;
-}
-
-static int initr_hermes_start(void)
-{
- if (gd->bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980((int) gd->bd->bi_ethspeed);
- return 0;
-}
-#endif
-
#ifdef CONFIG_SC3
/* TODO: with new initcalls, move this into the driver */
extern void sc3_read_eeprom(void);
@@ -775,7 +745,7 @@ init_fnc_t init_sequence_r[] = {
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_X86)
+#if defined(CONFIG_PPC)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
@@ -803,9 +773,6 @@ init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_SC3
initr_sc3_read_eeprom,
#endif
-#ifdef CONFIG_HERMES
- initr_hermes,
-#endif
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom,
#endif
@@ -831,18 +798,12 @@ init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_MISC_INIT_R
misc_init_r, /* miscellaneous platform-dependent init */
#endif
-#ifdef CONFIG_HERMES
- initr_hermes_start,
-#endif
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_CMD_KGDB
initr_kgdb,
#endif
-#ifdef CONFIG_X86
- board_early_init_r,
-#endif
interrupt_init,
-#if defined(CONFIG_ARM) || defined(CONFIG_x86)
+#if defined(CONFIG_ARM)
initr_enable_interrupts,
#endif
#ifdef CONFIG_X86
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 3d37a86..f0b713c 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -144,9 +144,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
print_eth(5);
#endif
-#ifdef CONFIG_HERMES
- print_mhz("ethspeed", bd->bi_ethspeed);
-#endif
printf("IP addr = %s\n", getenv("ipaddr"));
printf("baudrate = %6u bps\n", gd->baudrate);
print_num("relocaddr", gd->relocaddr);
diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 5640ded..25b4675 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -566,8 +566,27 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
#ifdef CONFIG_OF_BOARD_SETUP
/* Call the board-specific fixup routine */
- else if (strncmp(argv[1], "boa", 3) == 0)
- ft_board_setup(working_fdt, gd->bd);
+ else if (strncmp(argv[1], "boa", 3) == 0) {
+ int err = ft_board_setup(working_fdt, gd->bd);
+
+ if (err) {
+ printf("Failed to update board information in FDT: %s\n",
+ fdt_strerror(err));
+ return CMD_RET_FAILURE;
+ }
+ }
+#endif
+#ifdef CONFIG_OF_SYSTEM_SETUP
+ /* Call the board-specific fixup routine */
+ else if (strncmp(argv[1], "sys", 3) == 0) {
+ int err = ft_system_setup(working_fdt, gd->bd);
+
+ if (err) {
+ printf("Failed to add system information to FDT: %s\n",
+ fdt_strerror(err));
+ return CMD_RET_FAILURE;
+ }
+ }
#endif
/* Create a chosen node */
else if (strncmp(argv[1], "cho", 3) == 0) {
@@ -1008,6 +1027,9 @@ static char fdt_help_text[] =
#ifdef CONFIG_OF_BOARD_SETUP
"fdt boardsetup - Do board-specific set up\n"
#endif
+#ifdef CONFIG_OF_SYSTEM_SETUP
+ "fdt systemsetup - Do system-specific set up\n"
+#endif
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n"
"fdt resize - Resize fdt to size + padding to 4k addr\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
diff --git a/common/cmd_fuse.c b/common/cmd_fuse.c
index abab978..d4bc0f6 100644
--- a/common/cmd_fuse.c
+++ b/common/cmd_fuse.c
@@ -128,7 +128,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
err:
puts("ERROR\n");
- return ret;
+ return CMD_RET_FAILURE;
}
U_BOOT_CMD(
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 0d50dcf..bcb3ee3 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -19,6 +19,7 @@
#include <dataflash.h>
#endif
#include <hash.h>
+#include <inttypes.h>
#include <watchdog.h>
#include <asm/io.h>
#include <linux/compiler.h>
@@ -338,7 +339,8 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (word1 != word2) {
ulong offset = buf1 - base;
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
- printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
+ printf("%s at 0x%p (%#0*"PRIx64") != %s at 0x%p (%#0*"
+ PRIx64 ")\n",
type, (void *)(addr1 + offset), size, word1,
type, (void *)(addr2 + offset), size, word2);
#else
@@ -1146,7 +1148,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
printf(" %08x", *((u32 *)ptr));
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
else if (size == 8)
- printf(" %016llx", *((u64 *)ptr));
+ printf(" %016" PRIx64, *((u64 *)ptr));
#endif
else if (size == 2)
printf(" %04x", *((u16 *)ptr));
diff --git a/common/console.c b/common/console.c
index 4695386..29560c3 100644
--- a/common/console.c
+++ b/common/console.c
@@ -125,12 +125,12 @@ static int console_setfile(int file, struct stdio_dev * dev)
*/
switch (file) {
case stdin:
- gd->jt[XF_getc] = dev->getc;
- gd->jt[XF_tstc] = dev->tstc;
+ gd->jt[XF_getc] = getc;
+ gd->jt[XF_tstc] = tstc;
break;
case stdout:
- gd->jt[XF_putc] = dev->putc;
- gd->jt[XF_puts] = dev->puts;
+ gd->jt[XF_putc] = putc;
+ gd->jt[XF_puts] = puts;
gd->jt[XF_printf] = printf;
break;
}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 2d3c387..8266bca 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <inttypes.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
@@ -16,22 +17,6 @@
#include <fdt_support.h>
#include <exports.h>
-/*
- * Get cells len in bytes
- * if #NNNN-cells property is 2 then len is 8
- * otherwise len is 4
- */
-static int get_cells_len(const void *fdt, const char *nr_cells_name)
-{
- const fdt32_t *cell;
-
- cell = fdt_getprop(fdt, 0, nr_cells_name, NULL);
- if (cell && fdt32_to_cpu(*cell) == 2)
- return 8;
-
- return 4;
-}
-
/**
* fdt_getprop_u32_default_node - Return a node's property or a default
*
@@ -113,7 +98,8 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
}
/**
- * fdt_find_or_add_subnode - find or possibly add a subnode of a given node
+ * fdt_find_or_add_subnode() - find or possibly add a subnode of a given node
+ *
* @fdt: pointer to the device tree blob
* @parentoffset: structure block offset of a node
* @name: name of the subnode to locate
@@ -121,8 +107,7 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
* fdt_subnode_offset() finds a subnode of the node with a given name.
* If the subnode does not exist, it will be created.
*/
-static int fdt_find_or_add_subnode(void *fdt, int parentoffset,
- const char *name)
+int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name)
{
int offset;
@@ -246,7 +231,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
return err;
}
- is_u64 = (get_cells_len(fdt, "#address-cells") == 8);
+ is_u64 = (fdt_address_cells(fdt, 0) == 2);
err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-start",
(uint64_t)initrd_start, is_u64);
@@ -382,26 +367,26 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
/*
* fdt_pack_reg - pack address and size array into the "reg"-suitable stream
*/
-static int fdt_pack_reg(const void *fdt, void *buf, uint64_t *address,
- uint64_t *size, int n)
+static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size,
+ int n)
{
int i;
- int address_len = get_cells_len(fdt, "#address-cells");
- int size_len = get_cells_len(fdt, "#size-cells");
+ int address_cells = fdt_address_cells(fdt, 0);
+ int size_cells = fdt_size_cells(fdt, 0);
char *p = buf;
for (i = 0; i < n; i++) {
- if (address_len == 8)
+ if (address_cells == 2)
*(fdt64_t *)p = cpu_to_fdt64(address[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(address[i]);
- p += address_len;
+ p += 4 * address_cells;
- if (size_len == 8)
+ if (size_cells == 2)
*(fdt64_t *)p = cpu_to_fdt64(size[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(size[i]);
- p += size_len;
+ p += 4 * size_cells;
}
return p - (char *)buf;
@@ -930,8 +915,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
fdt_delprop(blob, off, alias);
}
-#define PRu64 "%llx"
-
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR ((u64)-1)
@@ -968,13 +951,8 @@ void of_bus_default_count_cells(void *blob, int parentoffset,
{
const fdt32_t *prop;
- if (addrc) {
- prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL);
- if (prop)
- *addrc = be32_to_cpup(prop);
- else
- *addrc = 2;
- }
+ if (addrc)
+ *addrc = fdt_address_cells(blob, parentoffset);
if (sizec) {
prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL);
@@ -994,8 +972,8 @@ static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range,
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr, na);
- debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n",
- cp, s, da);
+ debug("OF: default map, cp=%" PRIu64 ", s=%" PRIu64
+ ", da=%" PRIu64 "\n", cp, s, da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
@@ -1073,7 +1051,7 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus,
finish:
of_dump_addr("OF: parent translation for:", addr, pna);
- debug("OF: with offset: "PRu64"\n", offset);
+ debug("OF: with offset: %" PRIu64 "\n", offset);
/* Translate it into parent bus space */
return pbus->translate(addr, offset, pna);
@@ -1402,9 +1380,9 @@ int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr)
dt_addr = fdt_translate_address(fdt, node, reg);
if (addr != dt_addr) {
- printf("Warning: U-Boot configured device %s at address %llx,\n"
- " but the device tree has it address %llx.\n",
- alias, addr, dt_addr);
+ printf("Warning: U-Boot configured device %s at address %"
+ PRIx64 ",\n but the device tree has it address %"
+ PRIx64 ".\n", alias, addr, dt_addr);
return 0;
}
@@ -1420,11 +1398,7 @@ u64 fdt_get_base_address(void *fdt, int node)
u32 naddr;
const fdt32_t *prop;
- prop = fdt_getprop(fdt, node, "#address-cells", &size);
- if (prop && size == 4)
- naddr = be32_to_cpup(prop);
- else
- naddr = 2;
+ naddr = fdt_address_cells(fdt, node);
prop = fdt_getprop(fdt, node, "ranges", &size);
@@ -1524,3 +1498,65 @@ int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
return 0;
}
+
+/**
+ * fdt_setup_simplefb_node - Fill and enable a simplefb node
+ *
+ * @fdt: ptr to device tree
+ * @node: offset of the simplefb node
+ * @base_address: framebuffer base address
+ * @width: width in pixels
+ * @height: height in pixels
+ * @stride: bytes per line
+ * @format: pixel format string
+ *
+ * Convenience function to fill and enable a simplefb node.
+ */
+int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
+ u32 height, u32 stride, const char *format)
+{
+ char name[32];
+ fdt32_t cells[4];
+ int i, addrc, sizec, ret;
+
+ of_bus_default_count_cells(fdt, fdt_parent_offset(fdt, node),
+ &addrc, &sizec);
+ i = 0;
+ if (addrc == 2)
+ cells[i++] = cpu_to_fdt32(base_address >> 32);
+ cells[i++] = cpu_to_fdt32(base_address);
+ if (sizec == 2)
+ cells[i++] = 0;
+ cells[i++] = cpu_to_fdt32(height * stride);
+
+ ret = fdt_setprop(fdt, node, "reg", cells, sizeof(cells[0]) * i);
+ if (ret < 0)
+ return ret;
+
+ snprintf(name, sizeof(name), "framebuffer@%llx", base_address);
+ ret = fdt_set_name(fdt, node, name);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u32(fdt, node, "width", width);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u32(fdt, node, "height", height);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u32(fdt, node, "stride", stride);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_string(fdt, node, "format", format);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_string(fdt, node, "status", "okay");
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
diff --git a/common/image-fdt.c b/common/image-fdt.c
index a39ae1b..e3f06cd 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -237,6 +237,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
int fdt_noffset;
#endif
const char *select = NULL;
+ int ok_no_fdt = 0;
*of_flat_tree = NULL;
*of_size = 0;
@@ -309,7 +310,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
fdt_addr);
fdt_hdr = image_get_fdt(fdt_addr);
if (!fdt_hdr)
- goto error;
+ goto no_fdt;
/*
* move image data to the load address,
@@ -379,7 +380,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
break;
default:
puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
@@ -413,11 +414,11 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
}
} else {
debug("## No Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
} else {
debug("## No Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
*of_flat_tree = fdt_blob;
@@ -427,9 +428,15 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
return 0;
+no_fdt:
+ ok_no_fdt = 1;
error:
*of_flat_tree = NULL;
*of_size = 0;
+ if (!select && ok_no_fdt) {
+ debug("Continuing to boot without FDT\n");
+ return 0;
+ }
return 1;
}
@@ -460,19 +467,32 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
{
ulong *initrd_start = &images->initrd_start;
ulong *initrd_end = &images->initrd_end;
- int ret;
+ int ret = -EPERM;
+ int fdt_ret;
if (fdt_chosen(blob) < 0) {
- puts("ERROR: /chosen node create failed");
- puts(" - must RESET the board to recover.\n");
- return -1;
+ printf("ERROR: /chosen node create failed\n");
+ goto err;
}
if (arch_fixup_fdt(blob) < 0) {
- puts("ERROR: arch specific fdt fixup failed");
- return -1;
+ printf("ERROR: arch-specific fdt fixup failed\n");
+ goto err;
+ }
+ if (IMAGE_OF_BOARD_SETUP) {
+ fdt_ret = ft_board_setup(blob, gd->bd);
+ if (fdt_ret) {
+ printf("ERROR: board-specific fdt fixup failed: %s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
+ }
+ if (IMAGE_OF_SYSTEM_SETUP) {
+ if (ft_system_setup(blob, gd->bd)) {
+ printf("ERROR: system-specific fdt fixup failed: %s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
}
- if (IMAGE_OF_BOARD_SETUP)
- ft_board_setup(blob, gd->bd);
fdt_fixup_ethernet(blob);
/* Delete the old LMB reservation */
@@ -481,7 +501,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
ret = fdt_shrink_to_minimum(blob);
if (ret < 0)
- return ret;
+ goto err;
of_size = ret;
if (*initrd_start && *initrd_end) {
@@ -493,7 +513,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
fdt_initrd(blob, *initrd_start, *initrd_end);
if (!ft_verify_fdt(blob))
- return -1;
+ goto err;
#if defined(CONFIG_SOC_KEYSTONE)
if (IMAGE_OF_BOARD_SETUP)
@@ -501,4 +521,8 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
#endif
return 0;
+err:
+ printf(" - must RESET the board to recover.\n\n");
+
+ return ret;
}
diff --git a/common/lcd.c b/common/lcd.c
index d8e1371..3ed504d 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -30,6 +30,7 @@
#include <splash.h>
#include <asm/io.h>
#include <asm/unaligned.h>
+#include <fdt_support.h>
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
@@ -529,7 +530,7 @@ static int lcd_init(void *lcdbase)
lcd_ctrl_init(lcdbase);
/*
- * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores
+ * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi) ignores
* the 'lcdbase' argument and uses custom lcd base address
* by setting up gd->fb_base. Check for this condition and fixup
* 'lcd_base' address.
@@ -1172,51 +1173,13 @@ int lcd_get_screen_columns(void)
#if defined(CONFIG_LCD_DT_SIMPLEFB)
static int lcd_dt_simplefb_configure_node(void *blob, int off)
{
- u32 stride;
- fdt32_t cells[2];
- int ret;
- static const char format[] =
#if LCD_BPP == LCD_COLOR16
- "r5g6b5";
+ return fdt_setup_simplefb_node(blob, off, gd->fb_base,
+ panel_info.vl_col, panel_info.vl_row,
+ panel_info.vl_col * 2, "r5g6b5");
#else
- "";
+ return -1;
#endif
-
- if (!format[0])
- return -1;
-
- stride = panel_info.vl_col * 2;
-
- cells[0] = cpu_to_fdt32(gd->fb_base);
- cells[1] = cpu_to_fdt32(stride * panel_info.vl_row);
- ret = fdt_setprop(blob, off, "reg", cells, sizeof(cells[0]) * 2);
- if (ret < 0)
- return -1;
-
- cells[0] = cpu_to_fdt32(panel_info.vl_col);
- ret = fdt_setprop(blob, off, "width", cells, sizeof(cells[0]));
- if (ret < 0)
- return -1;
-
- cells[0] = cpu_to_fdt32(panel_info.vl_row);
- ret = fdt_setprop(blob, off, "height", cells, sizeof(cells[0]));
- if (ret < 0)
- return -1;
-
- cells[0] = cpu_to_fdt32(stride);
- ret = fdt_setprop(blob, off, "stride", cells, sizeof(cells[0]));
- if (ret < 0)
- return -1;
-
- ret = fdt_setprop(blob, off, "format", format, strlen(format) + 1);
- if (ret < 0)
- return -1;
-
- ret = fdt_delprop(blob, off, "status");
- if (ret < 0)
- return -1;
-
- return 0;
}
int lcd_dt_simplefb_add_node(void *blob)
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 5ff9bc5..9d37fd3 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -43,7 +43,7 @@ int spl_load_image_ext(block_dev_desc_t *block_dev,
goto end;
}
err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen);
- if (err <= 0) {
+ if (err < 0) {
puts("spl: ext4fs_read failed\n");
goto end;
}
@@ -54,12 +54,12 @@ int spl_load_image_ext(block_dev_desc_t *block_dev,
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (err <= 0)
+ if (err < 0)
printf("%s: error reading image %s, err - %d\n",
__func__, filename, err);
#endif
- return err <= 0;
+ return err < 0;
}
#ifdef CONFIG_SPL_OS_BOOT
@@ -95,7 +95,7 @@ int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
goto defaults;
}
err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
- if (err <= 0) {
+ if (err < 0) {
printf("spl: error reading image %s, err - %d, falling back to default\n",
file, err);
goto defaults;
@@ -124,7 +124,7 @@ defaults:
puts("spl: ext4fs_open failed\n");
err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
- if (err <= 0) {
+ if (err < 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
__func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ee71f79..7bae16b 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -15,7 +15,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector)
+static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
{
unsigned long err;
u32 image_size_sectors;
@@ -51,6 +51,22 @@ end:
return (err == 0);
}
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
+{
+ disk_partition_t info;
+
+ if (get_partition_info(&mmc->block_dev, partition, &info)) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("spl: partition error\n");
+#endif
+ return -1;
+ }
+
+ return mmc_load_image_raw_sector(mmc, info.start);
+}
+#endif
+
#ifdef CONFIG_SPL_OS_BOOT
static int mmc_load_image_raw_os(struct mmc *mmc)
{
@@ -64,7 +80,8 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
return -1;
}
- return mmc_load_image_raw(mmc, CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
+ return mmc_load_image_raw_sector(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
}
#endif
@@ -98,18 +115,24 @@ void spl_mmc_load_image(void)
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
- err = mmc_load_image_raw(mmc,
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ err = mmc_load_image_raw_partition(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
+#else
+ err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#endif
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
- } else if (boot_mode == MMCSD_MODE_FS) {
+ }
+ if (err || boot_mode == MMCSD_MODE_FS) {
debug("boot mode - FS\n");
#ifdef CONFIG_SPL_FAT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_fat(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if(err)
#endif /* CONFIG_SPL_FAT_SUPPORT */
@@ -117,10 +140,10 @@ void spl_mmc_load_image(void)
#ifdef CONFIG_SPL_EXT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_ext(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
#endif /* CONFIG_SPL_EXT_SUPPORT */
}
@@ -146,7 +169,7 @@ void spl_mmc_load_image(void)
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
- err = mmc_load_image_raw(mmc,
+ err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#endif
} else {
diff --git a/common/usb.c b/common/usb.c
index 7d33a0f..736cd9f 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -33,7 +33,6 @@
#include <linux/ctype.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
-#include <compiler.h>
#include <errno.h>
#include <usb.h>
#ifdef CONFIG_4xx
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 8517203..be8652b 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -2,6 +2,8 @@ CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
CONFIG_USB1_VBUS_PIN="PG11"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN5I=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 61f5466..654e12a 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -2,6 +2,8 @@ CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
CONFIG_USB1_VBUS_PIN="PG11"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN5I=y
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index bef568d..de78a01 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -1,5 +1,6 @@
CONFIG_SPL=y
CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
+CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN6I=y
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index fc67bd9..50c2f93 100644
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -4,3 +4,5 @@ CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I=y
CONFIG_TARGET_IPPO_Q8H_V5=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index f46439f..ac3cd36 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -1,5 +1,5 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-m9.dtb"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
@@ -14,5 +14,7 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb"
# HDMI power ?
+S:CONFIG_AXP221_ALDO2_VOLT=1800
+S:CONFIG_AXP221_ALDO3_VOLT=3000
-# No Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN=""
+# Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN="PC27"
+# No Vbus gpio for usb2
++S:CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_D4_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..d86ae05
--- /dev/null
+++ b/configs/T1024QDS_D4_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
new file mode 100644
index 0000000..acbbe43
--- /dev/null
+++ b/configs/T1024QDS_NAND_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
new file mode 100644
index 0000000..82c6e19
--- /dev/null
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..b932619
--- /dev/null
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
new file mode 100644
index 0000000..52aeac7
--- /dev/null
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
new file mode 100644
index 0000000..73d14ab
--- /dev/null
+++ b/configs/T1024RDB_NAND_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
new file mode 100644
index 0000000..3599f1d
--- /dev/null
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..8377260
--- /dev/null
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
new file mode 100644
index 0000000..c8ea985
--- /dev/null
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
new file mode 100644
index 0000000..e19e404
--- /dev/null
+++ b/configs/T1024RDB_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig
new file mode 100644
index 0000000..872ab63
--- /dev/null
+++ b/configs/beagle_x15_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
++S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
++S:CONFIG_TARGET_BEAGLE_X15=y
diff --git a/configs/hermes_defconfig b/configs/hermes_defconfig
deleted file mode 100644
index a923a61..0000000
--- a/configs/hermes_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_HERMES=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
new file mode 100644
index 0000000..8ada0db
--- /dev/null
+++ b/configs/peach-pi_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
++S:CONFIG_TARGET_PEACH_PI=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index f54b15f..3155340 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -1,7 +1,34 @@
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_LD4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index e795752..7ea4e6e 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -1,7 +1,34 @@
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_PRO4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index 6510937..ddf210c 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -1,7 +1,34 @@
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_SLD8=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/rpi_b_defconfig b/configs/rpi_b_defconfig
deleted file mode 100644
index 9a4705e..0000000
--- a/configs/rpi_b_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_RPI_B=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
new file mode 100644
index 0000000..9379cf0
--- /dev/null
+++ b/configs/rpi_defconfig
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_RPI=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
new file mode 100644
index 0000000..a05e991
--- /dev/null
+++ b/configs/stv0991_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="stv0991"
+CONFIG_ARM=y
+CONFIG_TARGET_STV0991=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 612f092..efed58f 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <ide.h>
+#include <inttypes.h>
#include <malloc.h>
#include <part_efi.h>
#include <linux/ctype.h>
@@ -553,28 +554,28 @@ static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
/* Check that the my_lba entry points to the LBA that contains the GPT */
if (le64_to_cpu(pgpt_head->my_lba) != lba) {
- printf("GPT: my_lba incorrect: %llX != %llX\n",
- le64_to_cpu(pgpt_head->my_lba),
- lba);
+ printf("GPT: my_lba incorrect: %llX != %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->my_lba),
+ lba);
return 0;
}
/* Check the first_usable_lba and last_usable_lba are within the disk. */
lastlba = (u64)dev_desc->lba;
if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
- printf("GPT: first_usable_lba incorrect: %llX > %llX\n",
- le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
+ printf("GPT: first_usable_lba incorrect: %llX > %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
return 0;
}
if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
- printf("GPT: last_usable_lba incorrect: %llX > %llX\n",
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ printf("GPT: last_usable_lba incorrect: %llX > %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
return 0;
}
- debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %llX\n",
- le64_to_cpu(pgpt_head->first_usable_lba),
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %"
+ PRIX64 "\n", le64_to_cpu(pgpt_head->first_usable_lba),
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
/* Read and allocate Partition Table Entries */
*pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
diff --git a/doc/README.clang b/doc/README.clang
index 52495d3..fe36909 100644
--- a/doc/README.clang
+++ b/doc/README.clang
@@ -28,7 +28,7 @@ sudo apt-get install clang
To compile U-Boot with clang on linux without IAS use e.g.:
export TRIPLET=arm-linux-gnueabi && export CROSS_COMPILE="$TRIPLET-"
-make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_b_defconfig
+make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_defconfig
make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" all V=1 -j8
FreeBSD 11 (Current):
@@ -42,7 +42,7 @@ ln -s /usr/local/bin/arm-gnueabi-freebsd-as /usr/bin/arm-freebsd-eabi-as
# The following commands compile U-Boot using the clang xdev toolchain.
# NOTE: CROSS_COMPILE and target differ on purpose!
export CROSS_COMPILE=arm-gnueabi-freebsd-
-gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_b_defconfig
+gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig
gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8
Given that u-boot will default to gcc, above commands can be
diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa
new file mode 100644
index 0000000..0d8d4f6
--- /dev/null
+++ b/doc/README.fsl-dpaa
@@ -0,0 +1,10 @@
+This file documents Freescale DPAA-specific options.
+
+FMan (Frame Manager)
+ - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+ on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
+ 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
+ on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
+ 10GEC1->MAC1, 10GEC2->MAC2
+ so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on
+ which 10GEC enumeration is consistent with MAC enumeration.
diff --git a/doc/README.odroid b/doc/README.odroid
index 528bb95..25b962b 100644
--- a/doc/README.odroid
+++ b/doc/README.odroid
@@ -141,3 +141,172 @@ And the boot sequence is:
- boot_fit - if "Image.itb" exists
- boot_zimg - if "zImage" exists
- boot_uimg - if "uImage" exists
+
+11. USB host support
+====================
+
+The ethernet can be accessed after starting the USB subsystem in U-Boot.
+The adapter does not come with a preconfigured MAC address, and hence it needs
+to be set before starting USB.
+setenv usbethaddr 02:DE:AD:BE:EF:FF
+
+Note that in this example a locally managed MAC address is chosen. Care should
+be taken to make these MAC addresses unique within the same subnet.
+
+Start the USB subsystem:
+Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF
+Odroid # usb start
+(Re)start USB...
+USB0: USB EHCI 1.00
+scanning bus 0 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+Odroid #
+
+Automatic IP assignment:
+------------------------
+If the ethernet is connected to a DHCP server (router maybe with DHCP enabled),
+then the below will automatically assign an ip address through DHCP.
+setenv autoload no
+dhcp
+
+Odroid # setenv autoload no
+Odroid # dhcp
+Waiting for Ethernet connection... done.
+BOOTP broadcast 1
+DHCP client bound to address 192.168.1.10 (524 ms)
+Odroid #
+
+Note that this automatically sets the many IP address related variables in
+U-Boot that is obtained from the DHCP server.
+
+Odroid # printenv ipaddr netmask gatewayip dnsip
+ipaddr=192.168.1.10
+netmask=255.255.255.0
+gatewayip=192.168.1.1
+dnsip=192.168.1.1
+
+Ping example:
+The ping command can be used a test to check connectivity. In this example,
+192.168.1.27 is a pingable server in the network.
+Odroid # ping 192.168.1.27
+Waiting for Ethernet connection... done.
+Using sms0 device
+host 192.168.1.27 is alive
+Odroid #
+
+Static IP assignment:
+---------------------
+In the case where there are no DHCP servers in the network, or you want to
+set the IP address statically, it can be done by:
+Odroid # setenv ipaddr 192.168.1.10
+Odroid # ping 192.168.1.27
+Waiting for Ethernet connection... done.
+Using sms0 device
+host 192.168.1.27 is alive
+
+TFTP booting:
+-------------
+Say there exists a tftp server in the network with address 192.168.1.27 and
+it serves a kernel image (zImage.3.17) and a DTB blob (exynos4412-odroidu3.dtb)
+that needs to be loaded and booted. It can be accomplished as below:
+(Assumes that you have setenv usbethaddr, and have not set autoload to no)
+
+Odroid # setenv serverip 192.168.1.27
+Odroid # tftpboot 0x40080000 zImage.3.17
+Waiting for Ethernet connection... done.
+Using sms0 device
+TFTP from server 192.168.1.27; our IP address is 192.168.1.10
+Filename 'zImage.3.17'.
+Load address: 0x40080000
+Loading: #################################################################
+ #################################################################
+ #################################################################
+ #######################
+ 52.7 KiB/s
+done
+Bytes transferred = 3194200 (30bd58 hex)
+Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb
+Waiting for Ethernet connection... done.
+Using sms0 device
+TFTP from server 192.168.1.27; our IP address is 192.168.1.10
+Filename 'exynos4412-odroidu3.dtb'.
+Load address: 0x42000000
+Loading: ####
+ 40 KiB/s
+done
+Bytes transferred = 46935 (b757 hex)
+Odroid # printenv bootargs
+bootargs=Please use defined boot
+Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/mmcblk0p2 rootwait
+Odroid # bootz 40080000 - 42000000
+Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
+## Flattened Device Tree blob at 42000000
+ Booting using the fdt blob at 0x42000000
+ Loading Device Tree to 4fff1000, end 4ffff756 ... OK
+
+Starting kernel ...
+
+[ 0.000000] Booting Linux on physical CPU 0xa00
+... etc ...
+
+In the above example you can substitute 'dhcp' for 'tftpboot' as well.
+
+USB Storage booting:
+--------------------
+Similarly we can use the USB storage to load the kernel image/initrd/fdt etc
+and boot. For this example, there is a USB drive plugged in. It has a FAT
+1st partition and an EXT 2nd partition. Using the generic FS (ls/load) makes
+it even easier to work with FAT/EXT file systems.
+For this example the second EXT partition is used for booting and as rootfs.
+The boot files - kernel and the dtb are present in the /boot directory of the
+second partition.
+
+Odroid # usb start
+(Re)start USB...
+USB0: USB EHCI 1.00
+scanning bus 0 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices...
+Error: sms0 address not set. <----- Note the error as usbethaddr
+Warning: failed to set MAC address <----- is not set.
+1 Ethernet Device(s) found
+Odroid # usb part 0
+
+Partition Map for USB device 0 -- Partition Type: DOS
+
+Part Start Sector Num Sectors UUID Type
+ 1 3072 263168 000c4046-01 06
+ 2 266240 13457408 000c4046-02 83
+
+Odroid # ls usb 0:2 /boot
+<DIR> 4096 .
+<DIR> 4096 ..
+ 353 boot.scr
+ 281 boot.txt
+ 101420 config-3.8.13.23
+ 2127254 initrd.img-3.8.13.23
+ 2194825 uInitrd
+ 2194825 uInitrd-3.8.13.23
+ 2453112 zImage
+ 101448 config-3.8.13.26
+ 2127670 uInitrd-3.8.13.26
+ 2127606 initrd.img-3.8.13.26
+ 3194200 zImage.3.17 <--- Kernel
+ 46935 exynos4412-odroidu3.dtb <--- DTB
+Odroid # load usb 0:2 40080000 /boot/zImage.3.17
+3194200 bytes read in 471 ms (6.5 MiB/s)
+Odroid # load usb 0:2 42000000 /boot/exynos4412-odroidu3.dtb
+46935 bytes read in 233 ms (196.3 KiB/s)
+Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/sda2 rootwait
+Odroid # bootz 40080000 - 42000000
+Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
+## Flattened Device Tree blob at 42000000
+ Booting using the fdt blob at 0x42000000
+ Loading Device Tree to 4fff1000, end 4ffff756 ... OK
+
+Starting kernel ...
+
+[ 0.000000] Booting Linux on physical CPU 0xa00
+
+Please refer to README.usb for additional information.
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 8ba6e0a..deb4af4 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,8 +12,9 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-PRS200 powerpc mpc5200 - -
-MCC200 powerpc mpc5200 - -
+hermes powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+PRS200 powerpc mpc5200 ecfdcee 2014-11-12
+MCC200 powerpc mpc5200 ecfdcee 2014-11-12
TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
diff --git a/doc/device-tree-bindings/ata/intel-sata.txt b/doc/device-tree-bindings/ata/intel-sata.txt
new file mode 100644
index 0000000..5e4da83
--- /dev/null
+++ b/doc/device-tree-bindings/ata/intel-sata.txt
@@ -0,0 +1,26 @@
+Intel Pantherpoint SATA Device Binding
+======================================
+
+The device tree node which describes the operation of the Intel Pantherpoint
+SATA device is as follows:
+
+Required properties :
+- compatible = "intel,pantherpoint-ahci"
+- intel,sata-mode : string, one of:
+ "ahci" : Use AHCI mode (default)
+ "combined" : Use combined IDE + legacy mode
+ "plain-ide" : Use plain IDE mode
+- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
+ bit 1=enable second port, etc.
+- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
+- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
+
+Example
+-------
+
+sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+};
diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt
index 7e1b389..ba6ca9d 100644
--- a/doc/device-tree-bindings/misc/intel-lpc.txt
+++ b/doc/device-tree-bindings/misc/intel-lpc.txt
@@ -6,10 +6,37 @@ Count device is as follows:
Required properties :
- compatible = "intel,lpc"
-- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
- pairs can be provided - the first of each pair is the base address and
+- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
+ ALT_GP_SMI_EN register
+- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
+ cell pairs can be provided - the first of each pair is the base address and
the second is the size. These are written into the GENx_DEC registers of
the LPC device
+- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
+ values are:
+ 0 No effect (default)
+ 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ 2 SCI (if corresponding GPIO_EN bit is also set)
+- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
+ one cell for each.
+ 0x00 - 0000 = Reserved
+ 0x01 - 0001 = Reserved
+ 0x02 - 0010 = Reserved
+ 0x03 - 0011 = IRQ3
+ 0x04 - 0100 = IRQ4
+ 0x05 - 0101 = IRQ5
+ 0x06 - 0110 = IRQ6
+ 0x07 - 0111 = IRQ7
+ 0x08 - 1000 = Reserved
+ 0x09 - 1001 = IRQ9
+ 0x0A - 1010 = IRQ10
+ 0x0B - 1011 = IRQ11
+ 0x0C - 1100 = IRQ12
+ 0x0D - 1101 = Reserved
+ 0x0E - 1110 = IRQ14
+ 0x0F - 1111 = IRQ15
+ PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ 0x80 - The PIRQ is not routed.
Example
@@ -19,5 +46,19 @@ lpc {
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ /*
+ * GPI routing
+ * 0 No effect (default)
+ * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is
+ * also set)
+ * 2 SCI (if corresponding GPIO_EN bit is also set)
+ */
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
};
diff --git a/doc/device-tree-bindings/video/intel-gma.txt b/doc/device-tree-bindings/video/intel-gma.txt
new file mode 100644
index 0000000..914be4f
--- /dev/null
+++ b/doc/device-tree-bindings/video/intel-gma.txt
@@ -0,0 +1,40 @@
+Intel GMA Bindings
+==================
+
+This is the Intel Graphics Media Accelerator. This binding supports selection
+of display parameters only.
+
+
+Required properties:
+ - compatible : "intel,gma";
+
+Optional properties:
+ - intel,dp-hotplug : values for digital port hotplug, one cell per value for
+ ports B, C and D
+ - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D
+ - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
+
+ The following delays are in units of 0.1ms:
+ - intel,panel-power-up-delay : T1+T2 time sequence
+ - intel,panel-power-down-delay : T3 time sequence
+ - intel,panel-power-backlight-on-delay : T5 time sequence
+ - intel,panel-power-backlight-off-delay : Tx time sequence
+
+ - intel,cpu-backlight : Value for CPU Backlight PWM
+ - intel,pch-backlight : Value for PCH Backlight PWM
+
+Example
+-------
+
+gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+};
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ad22763..6c79a6d 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -14,6 +14,9 @@ alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net>
alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com>
alias afleming Andy Fleming <afleming@gmail.com>
alias ag Anatolij Gustschin <agust@denx.de>
+alias alisonwang Alison Wang <alison.wang@freescale.com>
+alias angelo_ts Angelo Dureghello <angelo@sysam.it>
+alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias galak Kumar Gala <galak@kernel.crashing.org>
alias gruss Graeme Russ <graeme.russ@gmail.com>
alias hs Heiko Schocher <hs@denx.de>
@@ -72,13 +75,13 @@ alias avr32 uboot, abiessmann
alias bfin uboot, vapier, sonic
alias blackfin bfin
-alias m68k uboot, jasonjin
+alias m68k uboot, alisonwang, angelo_ts
alias coldfire m68k
alias microblaze uboot, monstr
alias mb microblaze
-alias mips uboot, Shinya Kuribayashi <skuribay@pobox.com>
+alias mips uboot, danielschwierzeck
alias nds32 uboot, macpaul
@@ -119,6 +122,7 @@ alias mmc uboot, panto
alias nand uboot, scottwood
alias net uboot, jhersh
alias spi uboot, jagan
+alias ubi uboot, hs
alias usb uboot, marex
alias video uboot, ag
alias patman uboot, sjg
diff --git a/drivers/Makefile b/drivers/Makefile
index 7683c61..5ef58c0 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,6 +16,7 @@ obj-y += twserial/
obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
+obj-$(CONFIG_U_QE) += qe/
obj-y += memory/
obj-y += pwm/
obj-y += input/
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index e56356e..2ba43ac 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -9,4 +9,4 @@ obj-y = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/debug.o
ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \
- -D__PPC__ -D__BIG_ENDIAN__
+ $(if $(CONFIG_PPC),-D__PPC__ -D__BIG_ENDIAN__)
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 3b2ed6e..93b815c 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -46,8 +46,11 @@
* BIOS in u-boot.
****************************************************************************/
#include <common.h>
-#include "biosemui.h"
+#include <bios_emul.h>
+#include <errno.h>
#include <malloc.h>
+#include <vbe.h>
+#include "biosemui.h"
/* Length of the BIOS image */
#define MAX_BIOSLEN (128 * 1024L)
@@ -59,17 +62,54 @@ static u32 saveBaseAddress14;
static u32 saveBaseAddress18;
static u32 saveBaseAddress20;
+static void atibios_set_vesa_mode(RMREGS *regs, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ debug("VBE: Setting VESA mode %#04x\n", vesa_mode);
+ /* request linear framebuffer mode */
+ vesa_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ vesa_mode &= ~(1 << 15);
+ regs->e.eax = VESA_SET_MODE;
+ regs->e.ebx = vesa_mode;
+ BE_int86(0x10, regs, regs);
+
+ int offset = 0x2000;
+ void *buffer = (void *)(M.mem_base + offset);
+
+ u16 buffer_seg = (((unsigned long)offset) >> 4) & 0xff00;
+ u16 buffer_adr = ((unsigned long)offset) & 0xffff;
+ regs->e.eax = VESA_GET_MODE_INFO;
+ regs->e.ebx = 0;
+ regs->e.ecx = vesa_mode;
+ regs->e.edx = 0;
+ regs->e.esi = buffer_seg;
+ regs->e.edi = buffer_adr;
+ BE_int86(0x10, regs, regs);
+ memcpy(mode_info->mode_info_block, buffer,
+ sizeof(struct vbe_mode_info));
+ mode_info->valid = true;
+
+ vesa_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ vesa_mode &= ~(1 << 15);
+ regs->e.eax = VESA_SET_MODE;
+ regs->e.ebx = vesa_mode;
+ BE_int86(0x10, regs, regs);
+}
+
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
-VGAInfo - BIOS emulator VGA info structure
+vga_info - BIOS emulator VGA info structure
REMARKS:
This function executes the BIOS POST code on the controller. We assume that
at this stage the controller has its I/O and memory space enabled and
that all other controllers are in a disabled state.
****************************************************************************/
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
+static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
+ int vesa_mode, struct vbe_mode_info *mode_info)
{
RMREGS regs;
RMSREGS sregs;
@@ -84,13 +124,16 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
/*Setup the X86 emulator for the VGA BIOS*/
- BE_setVGA(VGAInfo);
+ BE_setVGA(vga_info);
/*Execute the BIOS POST code*/
BE_callRealMode(0xC000, 0x0003, &regs, &sregs);
/*Cleanup and exit*/
- BE_getVGA(VGAInfo);
+ BE_getVGA(vga_info);
+
+ if (vesa_mode != -1)
+ atibios_set_vesa_mode(&regs, vesa_mode, mode_info);
}
/****************************************************************************
@@ -244,60 +287,61 @@ REMARKS:
Loads and POST's the display controllers BIOS, directly from the BIOS
image we can extract over the PCI bus.
****************************************************************************/
-static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
+static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int vesa_mode,
+ struct vbe_mode_info *mode_info)
{
- u32 BIOSImageLen;
- uchar *mappedBIOS;
- uchar *copyOfBIOS;
-
- /*Allocate memory to store copy of BIOS from display controller*/
- if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) {
- printf("videoboot: Video ROM failed to map!\n");
- return false;
- }
+ u32 bios_image_len;
+ uchar *mapped_bios;
+ uchar *copy_of_bios;
+
+ if (bios_rom) {
+ copy_of_bios = bios_rom;
+ bios_image_len = bios_len;
+ } else {
+ /*
+ * Allocate memory to store copy of BIOS from display
+ * controller
+ */
+ mapped_bios = PCI_mapBIOSImage(pcidev);
+ if (mapped_bios == NULL) {
+ printf("videoboot: Video ROM failed to map!\n");
+ return false;
+ }
- BIOSImageLen = mappedBIOS[2] * 512;
+ bios_image_len = mapped_bios[2] * 512;
- if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) {
- printf("videoboot: Out of memory!\n");
- return false;
+ copy_of_bios = malloc(bios_image_len);
+ if (copy_of_bios == NULL) {
+ printf("videoboot: Out of memory!\n");
+ return false;
+ }
+ memcpy(copy_of_bios, mapped_bios, bios_image_len);
+ PCI_unmapBIOSImage(pcidev, mapped_bios);
}
- memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen);
- PCI_unmapBIOSImage(pcidev, mappedBIOS);
-
- /*Save information in VGAInfo structure*/
- VGAInfo->function = PCI_FUNC(pcidev);
- VGAInfo->device = PCI_DEV(pcidev);
- VGAInfo->bus = PCI_BUS(pcidev);
- VGAInfo->pcidev = pcidev;
- VGAInfo->BIOSImage = copyOfBIOS;
- VGAInfo->BIOSImageLen = BIOSImageLen;
+ /*Save information in vga_info structure*/
+ vga_info->function = PCI_FUNC(pcidev);
+ vga_info->device = PCI_DEV(pcidev);
+ vga_info->bus = PCI_BUS(pcidev);
+ vga_info->pcidev = pcidev;
+ vga_info->BIOSImage = copy_of_bios;
+ vga_info->BIOSImageLen = bios_image_len;
/*Now execute the BIOS POST for the device*/
- if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) {
+ if (copy_of_bios[0] != 0x55 || copy_of_bios[1] != 0xAA) {
printf("videoboot: Video ROM image is invalid!\n");
return false;
}
- PCI_doBIOSPOST(pcidev, VGAInfo);
+ PCI_doBIOSPOST(pcidev, vga_info, vesa_mode, mode_info);
/*Reset the size of the BIOS image to the final size*/
- VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512;
+ vga_info->BIOSImageLen = copy_of_bios[2] * 512;
return true;
}
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus to boot
-pVGAInfo - Place to return VGA info structure is requested
-cleanUp - true to clean up on exit, false to leave emulator active
-
-REMARKS:
-Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
-and the X86 BIOS emulator module.
-****************************************************************************/
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp)
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
{
BE_VGAInfo *VGAInfo;
@@ -307,28 +351,70 @@ int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp)
/*Initialise the x86 BIOS emulator*/
if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
printf("videoboot: Out of memory!\n");
- return false;
+ return -ENOMEM;
}
memset(VGAInfo, 0, sizeof(*VGAInfo));
BE_init(0, 65536, VGAInfo, 0);
+ *vga_infop = VGAInfo;
- /*Post all the display controller BIOS'es*/
- if (!PCI_postController(pcidev, VGAInfo))
- return false;
+ return 0;
+}
- /*Cleanup and exit the emulator if requested. If the BIOS emulator
- is needed after booting the card, we will not call BE_exit and
- leave it enabled for further use (ie: VESA driver etc).
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void))
+{
+ X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
+}
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ /*Post all the display controller BIOS'es*/
+ if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
+ vesa_mode, mode_info))
+ return -EINVAL;
+
+ /*
+ * Cleanup and exit the emulator if requested. If the BIOS emulator
+ * is needed after booting the card, we will not call BE_exit and
+ * leave it enabled for further use (ie: VESA driver etc).
*/
- if (cleanUp) {
+ if (clean_up) {
BE_exit();
- if (VGAInfo->BIOSImage)
- free(VGAInfo->BIOSImage);
- free(VGAInfo);
- VGAInfo = NULL;
+ if (vga_info->BIOSImage)
+ free(vga_info->BIOSImage);
+ free(vga_info);
+ vga_info = NULL;
}
- /*Return VGA info pointer if the caller requested it*/
+
+ return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+pcidev - PCI device info for the video card on the bus to boot
+pVGAInfo - Place to return VGA info structure is requested
+cleanUp - true to clean up on exit, false to leave emulator active
+
+REMARKS:
+Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
+and the X86 BIOS emulator module.
+****************************************************************************/
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
+{
+ BE_VGAInfo *VGAInfo;
+ int ret;
+
+ ret = biosemu_setup(pcidev, &VGAInfo);
+ if (ret)
+ return false;
+ ret = biosemu_run(pcidev, NULL, 0, VGAInfo, clean_up, -1, NULL);
+ if (ret)
+ return false;
+
+ /* Return VGA info pointer if the caller requested it*/
if (pVGAInfo)
*pVGAInfo = VGAInfo;
+
return true;
}
diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c
index ad88a53..752a928 100644
--- a/drivers/bios_emulator/besys.c
+++ b/drivers/bios_emulator/besys.c
@@ -54,12 +54,20 @@
/*------------------------- Global Variables ------------------------------*/
-#ifndef __i386__
+#ifndef CONFIG_X86EMU_RAW_IO
static char *BE_biosDate = "08/14/99";
static u8 BE_model = 0xFC;
static u8 BE_submodel = 0x00;
#endif
+#undef DEBUG_IO_ACCESS
+
+#ifdef DEBUG_IO_ACCESS
+#define debug_io(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define debug_io(x, b...)
+#endif
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
@@ -80,38 +88,40 @@ static u8 *BE_memaddr(u32 addr)
if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
return (u8*)(_BE_env.biosmem_base + addr - 0xC0000);
} else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) {
- DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);)
- return M.mem_base;
+ DB(printf("BE_memaddr: address %#lx may be invalid!\n",
+ (ulong)addr);)
+ return (u8 *)M.mem_base;
} else if (addr >= 0xA0000 && addr <= 0xBFFFF) {
return (u8*)(_BE_env.busmem_base + addr - 0xA0000);
}
-#ifdef __i386__
+#ifdef CONFIG_X86EMU_RAW_IO
else if (addr >= 0xD0000 && addr <= 0xFFFFF) {
/* We map the real System BIOS directly on real PC's */
- DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);)
- return _BE_env.busmem_base + addr - 0xA0000;
+ DB(printf("BE_memaddr: System BIOS address %#lx\n",
+ (ulong)addr);)
+ return (u8 *)_BE_env.busmem_base + addr - 0xA0000;
}
#else
else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
/* Return a faked BIOS date string for non-x86 machines */
- DB(printf("BE_memaddr - Returning BIOS date\n");)
+ debug_io("BE_memaddr - Returning BIOS date\n");
return (u8 *)(BE_biosDate + addr - 0xFFFF5);
} else if (addr == 0xFFFFE) {
/* Return system model identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning model\n");)
+ debug_io("BE_memaddr - Returning model\n");
return &BE_model;
} else if (addr == 0xFFFFF) {
/* Return system submodel identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning submodel\n");)
+ debug_io("BE_memaddr - Returning submodel\n");
return &BE_submodel;
}
#endif
else if (addr > M.mem_size - 1) {
HALT_SYS();
- return M.mem_base;
+ return (u8 *)M.mem_base;
}
- return M.mem_base + addr;
+ return (u8 *)(M.mem_base + addr);
}
/****************************************************************************
@@ -230,7 +240,7 @@ void X86API BE_wrl(u32 addr, u32 val)
}
}
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
/* For Non-Intel machines we may need to emulate some I/O port accesses that
* the BIOS may try to access, such as the PCI config registers.
@@ -258,6 +268,7 @@ static u8 VGA_inpb (const int port)
{
u8 val = 0xff;
+ debug_io("vga_inb.%04X -> ", (u16) port);
switch (port) {
case 0x3C0:
/* 3C0 has funky characteristics because it can act as either
@@ -560,7 +571,7 @@ u8 X86API BE_inb(X86EMU_pioAddr port)
{
u8 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_VGA_PORT(port)){
/*seems reading port 0x3c3 return the high 16 bit of io port*/
if(port == 0x3c3)
@@ -581,7 +592,12 @@ u8 X86API BE_inb(X86EMU_pioAddr port)
val = LOG_inpb(port);
} else
#endif
+ {
+ debug_io("inb.%04X -> ", (u16) port);
val = LOG_inpb(port);
+ debug_io("%02X\n", val);
+ }
+
return val;
}
@@ -601,7 +617,7 @@ u16 X86API BE_inw(X86EMU_pioAddr port)
{
u16 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_WORD);
else if (port < 0x100) {
@@ -609,7 +625,12 @@ u16 X86API BE_inw(X86EMU_pioAddr port)
val = LOG_inpw(port);
} else
#endif
+ {
+ debug_io("inw.%04X -> ", (u16) port);
val = LOG_inpw(port);
+ debug_io("%04X\n", val);
+ }
+
return val;
}
@@ -629,14 +650,19 @@ u32 X86API BE_inl(X86EMU_pioAddr port)
{
u32 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_DWORD);
else if (port < 0x100) {
val = LOG_inpd(port);
} else
#endif
+ {
+ debug_io("inl.%04X -> ", (u16) port);
val = LOG_inpd(port);
+ debug_io("%08X\n", val);
+ }
+
return val;
}
@@ -652,7 +678,7 @@ through to the real hardware if we don't need to special case it.
****************************************************************************/
void X86API BE_outb(X86EMU_pioAddr port, u8 val)
{
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_VGA_PORT(port))
VGA_outpb(port, val);
else if (IS_TIMER_PORT(port))
@@ -668,7 +694,11 @@ void X86API BE_outb(X86EMU_pioAddr port, u8 val)
LOG_outpb(port, val);
} else
#endif
+ {
+ debug_io("outb.%04X <- %02X", (u16) port, val);
LOG_outpb(port, val);
+ debug_io("\n");
+ }
}
/****************************************************************************
@@ -683,19 +713,23 @@ through to the real hardware if we don't need to special case it.
****************************************************************************/
void X86API BE_outw(X86EMU_pioAddr port, u16 val)
{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_VGA_PORT(port)) {
- VGA_outpb(port, val);
- VGA_outpb(port + 1, val >> 8);
- } else if (IS_PCI_PORT(port))
- PCI_outp(port, val, REG_WRITE_WORD);
- else if (port < 0x100) {
- DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port,
- val);)
- LOG_outpw(port, val);
- } else
+#if !defined(CONFIG_X86EMU_RAW_IO)
+ if (IS_VGA_PORT(port)) {
+ VGA_outpb(port, val);
+ VGA_outpb(port + 1, val >> 8);
+ } else if (IS_PCI_PORT(port)) {
+ PCI_outp(port, val, REG_WRITE_WORD);
+ } else if (port < 0x100) {
+ DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16)port,
+ val);)
+ LOG_outpw(port, val);
+ } else
#endif
- LOG_outpw(port, val);
+ {
+ debug_io("outw.%04X <- %04X", (u16) port, val);
+ LOG_outpw(port, val);
+ debug_io("\n");
+ }
}
/****************************************************************************
@@ -710,13 +744,17 @@ through to the real hardware if we don't need to special case it.
****************************************************************************/
void X86API BE_outl(X86EMU_pioAddr port, u32 val)
{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_PCI_PORT(port))
+#if !defined(CONFIG_X86EMU_RAW_IO)
+ if (IS_PCI_PORT(port)) {
PCI_outp(port, val, REG_WRITE_DWORD);
- else if (port < 0x100) {
+ } else if (port < 0x100) {
DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);)
LOG_outpd(port, val);
} else
#endif
+ {
+ debug_io("outl.%04X <- %08X", (u16) port, val);
LOG_outpd(port, val);
+ debug_io("\n");
+ }
}
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index bcc192f..152d70a 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -84,14 +84,14 @@ static void X86API int42(int intno)
PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02);
return;
}
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
else {
printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",
M.x86.R_AL);
}
#endif
}
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
else {
printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",
M.x86.R_AH, M.x86.R_AL, M.x86.R_BL);
diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h
index 8c1f111..7853015 100644
--- a/drivers/bios_emulator/biosemui.h
+++ b/drivers/bios_emulator/biosemui.h
@@ -48,7 +48,7 @@
#include <asm/io.h>
/*---------------------- Macros and type definitions ----------------------*/
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define DB(x) x
#else
#define DB(x) do{}while(0);
diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h
index e92e96e..124d79d 100644
--- a/drivers/bios_emulator/include/biosemu.h
+++ b/drivers/bios_emulator/include/biosemu.h
@@ -43,6 +43,8 @@
#ifndef __BIOSEMU_H
#define __BIOSEMU_H
+#include <bios_emul.h>
+
#ifdef __KERNEL__
#include "x86emu.h"
#else
@@ -55,57 +57,6 @@
#pragma pack(1)
-#ifndef __KERNEL__
-/****************************************************************************
-REMARKS:
-Data structure used to describe the details specific to a particular VGA
-controller. This information is used to allow the VGA controller to be
-swapped on the fly within the BIOS emulator.
-
-HEADER:
-biosemu.h
-
-MEMBERS:
-pciInfo - PCI device information block for the controller
-BIOSImage - Pointer to a read/write copy of the BIOS image
-BIOSImageLen - Length of the BIOS image
-LowMem - Copy of key low memory areas
-****************************************************************************/
-typedef struct {
- PCIDeviceInfo *pciInfo;
- void *BIOSImage;
- ulong BIOSImageLen;
- uchar LowMem[1536];
-} BE_VGAInfo;
-#else
-/****************************************************************************
-REMARKS:
-Data structure used to describe the details for the BIOS emulator system
-environment as used by the X86 emulator library.
-
-HEADER:
-biosemu.h
-
-MEMBERS:
-vgaInfo - VGA BIOS information structure
-biosmem_base - Base of the BIOS image
-biosmem_limit - Limit of the BIOS image
-busmem_base - Base of the VGA bus memory
-****************************************************************************/
-typedef struct {
- int function;
- int device;
- int bus;
- u32 VendorID;
- u32 DeviceID;
- pci_dev_t pcidev;
- void *BIOSImage;
- u32 BIOSImageLen;
- u8 LowMem[1536];
-} BE_VGAInfo;
-
-#endif /* __KERNEL__ */
-
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h
index a70a768..b28cdc6 100644
--- a/drivers/bios_emulator/include/x86emu.h
+++ b/drivers/bios_emulator/include/x86emu.h
@@ -53,9 +53,9 @@ typedef u16 X86EMU_pioAddr;
/*---------------------- Macros and type definitions ----------------------*/
-#if defined (CONFIG_ARM)
+#if defined(CONFIG_ARM)
#define GAS_LINE_COMMENT "@"
-#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_X86)
#define GAS_LINE_COMMENT "#"
#elif defined (CONFIG_SH)
#define GAS_LINE_COMMENT "!"
@@ -153,6 +153,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */
void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs);
void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs);
void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
+ void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func);
void X86EMU_prepareForInt(int num);
/* decode.c */
@@ -160,7 +161,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */
void X86EMU_exec(void);
void X86EMU_halt_sys(void);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define HALT_SYS() \
printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \
X86EMU_halt_sys()
diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h
index 268c9d3..304b2bf 100644
--- a/drivers/bios_emulator/include/x86emu/debug.h
+++ b/drivers/bios_emulator/include/x86emu/debug.h
@@ -48,7 +48,7 @@
#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */
#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F)
# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F)
# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F)
@@ -60,7 +60,7 @@
# define CHECK_DATA_ACCESS()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
@@ -99,7 +99,11 @@
# define DEBUG_DECODE_NOPRINT() 0
#endif
-#ifdef DEBUG
+# define ERR_PRINTF(x) printf(x)
+# define ERR_PRINTF2(x, y) printf(x, y)
+
+#ifdef CONFIG_X86EMU_DEBUG103
+
# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \
x86emu_decode_printf(x)
@@ -129,7 +133,7 @@
# define SAVE_IP_CS(x,y)
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define TRACE_REGS() \
if (DEBUG_DISASSEMBLE()) { \
x86emu_just_disassemble(); \
@@ -140,7 +144,7 @@
# define TRACE_REGS()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step()
#else
# define SINGLE_STEP()
@@ -150,7 +154,7 @@
TRACE_REGS(); \
SINGLE_STEP()
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define START_OF_INSTR()
# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr();
# define END_OF_INSTR_NO_TRACE() x86emu_end_instr();
@@ -160,7 +164,7 @@
# define END_OF_INSTR_NO_TRACE()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define CALL_TRACE(u,v,w,x,s) \
if (DEBUG_TRACECALLREGS()) \
x86emu_dump_regs(); \
@@ -176,7 +180,7 @@
# define RETURN_TRACE(n,u,v)
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define DB(x) x
#else
#define DB(x)
diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h
index a7fedd2..2934129 100644
--- a/drivers/bios_emulator/include/x86emu/regs.h
+++ b/drivers/bios_emulator/include/x86emu/regs.h
@@ -282,7 +282,7 @@ typedef struct {
u8 intno;
volatile int intr; /* mask of pending interrupts */
int debug;
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
int check;
u16 saved_ip;
u16 saved_cs;
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index 2fa8050..27e90e4 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -44,7 +44,7 @@
/*----------------------------- Implementation ----------------------------*/
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static void print_encoded_bytes(u16 s, u16 o);
static void print_decoded_instruction(void);
@@ -211,9 +211,7 @@ void X86EMU_dump_memory(u16 seg, u16 off, u32 amt)
u32 start = off & 0xfffffff0;
u32 end = (off + 16) & 0xfffffff0;
u32 i;
- u32 current;
- current = start;
while (end <= off + amt) {
printk("%04x:%04x ", seg, start);
for (i = start; i < off; i++)
@@ -229,7 +227,7 @@ void X86EMU_dump_memory(u16 seg, u16 off, u32 amt)
void x86emu_single_step(void)
{
char s[1024];
- int ps[10];
+ int ps[10];
int ntok;
int cmd;
int done;
@@ -238,8 +236,6 @@ void x86emu_single_step(void)
static int breakpoint;
static int noDecode = 1;
- char *p;
-
if (DEBUG_BREAK()) {
if (M.x86.saved_ip != breakpoint) {
return;
@@ -255,6 +251,8 @@ void x86emu_single_step(void)
offset = M.x86.saved_ip;
while (!done) {
printk("-");
+ ps[1] = 0; /* Avoid dodgy compiler warnings */
+ ps[2] = 0;
cmd = x86emu_parse_line(s, ps, &ntok);
switch (cmd) {
case 'u':
diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c
index a782b81..da44c3d 100644
--- a/drivers/bios_emulator/x86emu/decode.c
+++ b/drivers/bios_emulator/x86emu/decode.c
@@ -303,7 +303,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline!
u8 fetch_data_byte(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -322,7 +322,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline!
u16 fetch_data_word(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -341,7 +341,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline!
u32 fetch_data_long(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -362,7 +362,7 @@ u8 fetch_data_byte_abs(
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -383,7 +383,7 @@ u16 fetch_data_word_abs(
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -404,7 +404,7 @@ u32 fetch_data_long_abs(
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -426,7 +426,7 @@ void store_data_byte(
uint offset,
u8 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -448,7 +448,7 @@ void store_data_word(
uint offset,
u16 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -470,7 +470,7 @@ void store_data_long(
uint offset,
u32 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -493,7 +493,7 @@ void store_data_byte_abs(
uint offset,
u8 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -516,7 +516,7 @@ void store_data_word_abs(
uint offset,
u16 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -539,7 +539,7 @@ void store_data_long_abs(
uint offset,
u32 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index f8e093d..2bb5e2d 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -79,7 +79,7 @@
/* constant arrays to do several instructions in just one function */
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static char *x86emu_GenOpName[8] = {
"ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"};
#endif
@@ -160,7 +160,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) =
sar_long,
};
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static char *opF6_names[8] =
{ "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" };
@@ -179,7 +179,7 @@ void x86emuOp_illegal_op(
{
START_OF_INSTR();
if (M.x86.R_SP != 0) {
- DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL X86 OPCODE\n");
TRACE_REGS();
DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-1,op1));
@@ -1281,7 +1281,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -1359,7 +1359,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -1475,7 +1475,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -1551,7 +1551,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -2148,7 +2148,7 @@ void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1))
DECODE_PRINTF("POP\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
@@ -3083,7 +3083,7 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3158,7 +3158,7 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3347,7 +3347,7 @@ void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
HALT_SYS();
}
if (mod < 3) {
@@ -3381,7 +3381,7 @@ void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1))
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
@@ -3630,7 +3630,7 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3701,7 +3701,7 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3803,7 +3803,7 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3876,7 +3876,7 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3968,7 +3968,7 @@ void x86emuOp_aam(u8 X86EMU_UNUSED(op1))
DECODE_PRINTF("AAM\n");
a = fetch_byte_imm(); /* this is a stupid encoding. */
if (a != 10) {
- DECODE_PRINTF("ERROR DECODING AAM\n");
+ ERR_PRINTF("ERROR DECODING AAM\n");
TRACE_REGS();
HALT_SYS();
}
@@ -4443,7 +4443,7 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
test_byte(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4490,7 +4490,7 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
test_byte(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4559,7 +4559,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
test_long(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
@@ -4611,7 +4611,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
test_word(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
@@ -4666,7 +4666,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
test_long(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4715,7 +4715,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
test_word(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4859,7 +4859,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -4879,7 +4879,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
case 5:
case 6:
case 7:
- DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
+ ERR_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod);
HALT_SYS();
break;
}
@@ -4923,7 +4923,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -4961,7 +4961,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
DECODE_PRINTF("PUSH\t");
break;
case 7:
- DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
+ ERR_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
HALT_SYS();
break;
}
@@ -5092,7 +5092,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
M.x86.R_IP = *destreg;
break;
case 3: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ ERR_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
@@ -5104,7 +5104,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
M.x86.R_IP = (u16) (*destreg);
break;
case 5: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ ERR_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c
index 59dbb42..be4ef36 100644
--- a/drivers/bios_emulator/x86emu/ops2.c
+++ b/drivers/bios_emulator/x86emu/ops2.c
@@ -58,7 +58,7 @@ void x86emuOp2_illegal_op(
u8 op2)
{
START_OF_INSTR();
- DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-2,op2);
@@ -1089,7 +1089,7 @@ void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
DECODE_PRINTF("BTC\t");
break;
default:
- DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index 21f9730..0ba9c0c 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -273,6 +273,11 @@ void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs)
sys_outl = funcs->outl;
}
+void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func)
+{
+ _X86EMU_intrTab[intnum] = func;
+}
+
/****************************************************************************
PARAMETERS:
funcs - New interrupt vector table to make active
diff --git a/drivers/block/pata_bfin.h b/drivers/block/pata_bfin.h
index 2093cf0..b678f60 100644
--- a/drivers/block/pata_bfin.h
+++ b/drivers/block/pata_bfin.h
@@ -43,7 +43,6 @@ struct ata_port {
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
-#define __iomem
#define ATA_REG_CTRL 0x0E
#define ATA_REG_ALTSTATUS ATA_REG_CTRL
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9e2a4d2..fe8aa98 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -253,22 +253,30 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
#if !defined(CONFIG_SYS_FSL_DDR1)
+/*
+ * Check DIMM configuration, return 2 if quad-rank or two dual-rank
+ * Return 1 if other two slots configuration. Return 0 if single slot.
+ */
static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
{
#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
if (dimm_params[0].n_ranks == 4)
- return 1;
+ return 2;
#endif
#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
if ((dimm_params[0].n_ranks == 2) &&
(dimm_params[1].n_ranks == 2))
- return 1;
+ return 2;
#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (dimm_params[0].n_ranks == 4)
- return 1;
+ return 2;
#endif
+
+ if ((dimm_params[0].n_ranks != 0) &&
+ (dimm_params[2].n_ranks != 0))
+ return 1;
#endif
return 0;
}
@@ -316,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
#elif defined(CONFIG_SYS_FSL_DDR3)
unsigned int data_rate = get_ddr_freq(0);
int txp;
+ int odt_overlap;
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@@ -331,13 +340,23 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
/* set the turnaround time */
/*
- * for single quad-rank DIMM and two dual-rank DIMMs
+ * for single quad-rank DIMM and two-slot DIMMs
* to avoid ODT overlap
*/
- if (avoid_odt_overlap(dimm_params)) {
+ odt_overlap = avoid_odt_overlap(dimm_params);
+ switch (odt_overlap) {
+ case 2:
twwt_mclk = 2;
trrt_mclk = 1;
+ break;
+ case 1:
+ twwt_mclk = 1;
+ trrt_mclk = 0;
+ break;
+ default:
+ break;
}
+
/* for faster clock, need more time for data setup */
trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
@@ -383,7 +402,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
);
debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
}
-#endif /* defined(CONFIG_SYS_FSL_DDR2) */
+#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
index 2418dca..aaddc8f 100644
--- a/drivers/ddr/fsl/ddr4_dimm_params.c
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -126,6 +126,12 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
{
unsigned int retval;
int i;
+ const u8 udimm_rc_e_dq[18] = {
+ 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
+ 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
+ };
+ int spd_error = 0;
+ u8 *ptr;
if (spd->mem_type) {
if (spd->mem_type != SPD_MEMTYPE_DDR4) {
@@ -179,6 +185,22 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
/* Unbuffered DIMMs */
if (spd->mod_section.unbuffered.addr_mapping & 0x1)
pdimm->mirrored_dimm = 1;
+ if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
+ (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
+ /* Fix SPD error found on DIMMs with raw card E0 */
+ for (i = 0; i < 18; i++) {
+ if (spd->mapping[i] == udimm_rc_e_dq[i])
+ continue;
+ spd_error = 1;
+ debug("SPD byte %d: 0x%x, should be 0x%x\n",
+ 60 + i, spd->mapping[i],
+ udimm_rc_e_dq[i]);
+ ptr = (u8 *)&spd->mapping[i];
+ *ptr = udimm_rc_e_dq[i];
+ }
+ if (spd_error)
+ puts("SPD DQ mapping error fixed\n");
+ }
break;
default:
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index d34b749..41cc3b8 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -174,11 +174,11 @@ static int i2c_mux_set_all(void)
return 0;
}
-static int i2c_mux_disconnet_all(void)
+static int i2c_mux_disconnect_all(void)
{
struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
int i;
- uint8_t buf;
+ uint8_t buf = 0;
if (I2C_ADAP->init_done == 0)
return 0;
@@ -197,7 +197,7 @@ static int i2c_mux_disconnet_all(void)
ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
if (ret != 0) {
- printf("i2c: mux diconnect error\n");
+ printf("i2c: mux disconnect error\n");
return ret;
}
} while (i > 0);
@@ -293,7 +293,7 @@ int i2c_set_bus_num(unsigned int bus)
}
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
- i2c_mux_disconnet_all();
+ i2c_mux_disconnect_all();
#endif
gd->cur_i2c_bus = bus;
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index cb46b13..c55eb28 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -618,7 +618,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
#endif
cfg->cfg.f_min = 400000;
- cfg->cfg.f_max = min(gd->arch.sdhc_clk, (u32)52000000);
+ cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 44a4feb..8436bc7 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1277,6 +1277,11 @@ block_dev_desc_t *mmc_get_dev(int dev)
}
#endif
+/* board-specific MMC power initializations. */
+__weak void board_mmc_power_init(void)
+{
+}
+
int mmc_start_init(struct mmc *mmc)
{
int err;
@@ -1293,6 +1298,8 @@ int mmc_start_init(struct mmc *mmc)
if (mmc->has_init)
return 0;
+ board_mmc_power_init();
+
/* made sure it's not NULL earlier */
err = mmc->cfg->ops->init(mmc);
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index ffb5284..c880ced 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -135,12 +135,7 @@ static unsigned char mmc_board_init(struct mmc *mmc)
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
writel(pbias_lite, &t2_base->pbias_lite);
-#endif
-#if defined(CONFIG_TWL4030_POWER)
- twl4030_power_mmc_init();
- mdelay(100); /* ramp-up delay from Linux code */
-#endif
-#if defined(CONFIG_OMAP34XX)
+
writel(pbias_lite | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
@@ -663,7 +658,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
+ defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
+ defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
@@ -672,7 +668,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
+#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index ed83a14..76ba93b 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -103,20 +103,18 @@ static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
{
- int i;
-
sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
if (!clk)
return;
- if (clk == CLKDEV_EMMC_DATA) {
+
+ if (clk == CLKDEV_EMMC_DATA)
sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
- } else {
- for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
- ;
- sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
- }
+ else
+ sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
+ clk) - 1) - 1) << 16,
+ &host->regs->ce_clk_ctrl);
sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
}
@@ -581,8 +579,6 @@ static struct mmc_config sh_mmcif_cfg = {
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT | MMC_MODE_HC,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .f_min = CLKDEV_MMC_INIT,
- .f_max = CLKDEV_EMMC_DATA,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
@@ -599,6 +595,9 @@ int mmcif_mmc_init(void)
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
+ sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
+ sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
+
mmc = mmc_create(&sh_mmcif_cfg, host);
if (mmc == NULL) {
free(host);
diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h
index bd6fbf7..4b6752f 100644
--- a/drivers/mmc/sh_mmcif.h
+++ b/drivers/mmc/sh_mmcif.h
@@ -199,7 +199,13 @@ struct sh_mmcif_regs {
#define SOFT_RST_OFF (0 << 31)
#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
-#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */
+#ifdef CONFIG_RMOBILE
+#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
+#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
+#else
+#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8))
+#define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA
+#endif
#define MMC_BUS_WIDTH_1 0
#define MMC_BUS_WIDTH_4 2
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 75c2c06..c242214 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -1,9 +1,16 @@
menu "NAND Device Support"
+config SYS_NAND_SELF_INIT
+ bool
+ help
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process.
+
if !SPL_BUILD
config NAND_DENALI
bool "Support Denali NAND controller"
+ select SYS_NAND_SELF_INIT
help
Enable support for the Denali NAND controller.
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 308b784..9e0429a 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -44,7 +44,7 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
* this macro allows us to convert from an MTD structure to our own
* device context (denali) structure.
*/
-#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)
+#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand)
/* These constants are defined by the driver to enable common driver
* configuration options. */
@@ -1144,70 +1144,128 @@ static void denali_hw_init(struct denali_nand_info *denali)
static struct nand_ecclayout nand_oob;
-static int denali_nand_init(struct nand_chip *nand)
+static int denali_init(struct denali_nand_info *denali)
{
- struct denali_nand_info *denali;
+ int ret;
- denali = malloc(sizeof(*denali));
- if (!denali)
- return -ENOMEM;
+ denali_hw_init(denali);
- nand->priv = denali;
+ denali->mtd->name = "denali-nand";
+ denali->mtd->owner = THIS_MODULE;
+ denali->mtd->priv = &denali->nand;
- denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ /* register the driver with the NAND core subsystem */
+ denali->nand.select_chip = denali_select_chip;
+ denali->nand.cmdfunc = denali_cmdfunc;
+ denali->nand.read_byte = denali_read_byte;
+ denali->nand.read_buf = denali_read_buf;
+ denali->nand.waitfunc = denali_waitfunc;
+
+ /*
+ * scan for NAND devices attached to the controller
+ * this is the first stage in a two step process to register
+ * with the nand subsystem
+ */
+ if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) {
+ ret = -ENXIO;
+ goto fail;
+ }
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
/* check whether flash got BBT table (located at end of flash). As we
* use NAND_BBT_NO_OOB, the BBT page will start with
* bbt_pattern. We will have mirror pattern too */
- nand->bbt_options |= NAND_BBT_USE_FLASH;
+ denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
/*
* We are using main + spare with ECC support. As BBT need ECC support,
* we need to ensure BBT code don't write to OOB for the BBT pattern.
* All BBT info will be stored into data area with ECC support.
*/
- nand->bbt_options |= NAND_BBT_NO_OOB;
+ denali->nand.bbt_options |= NAND_BBT_NO_OOB;
#endif
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
- nand->ecc.read_oob = denali_read_oob;
- nand->ecc.write_oob = denali_write_oob;
- nand->ecc.read_page = denali_read_page;
- nand->ecc.read_page_raw = denali_read_page_raw;
- nand->ecc.write_page = denali_write_page;
- nand->ecc.write_page_raw = denali_write_page_raw;
+ denali->nand.ecc.mode = NAND_ECC_HW;
+ denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+
/*
* Tell driver the ecc strength. This register may be already set
* correctly. So we read this value out.
*/
- nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
- switch (nand->ecc.size) {
+ denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
+ switch (denali->nand.ecc.size) {
case 512:
- nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2;
+ denali->nand.ecc.bytes =
+ (denali->nand.ecc.strength * 13 + 15) / 16 * 2;
break;
case 1024:
- nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2;
+ denali->nand.ecc.bytes =
+ (denali->nand.ecc.strength * 14 + 15) / 16 * 2;
break;
default:
pr_err("Unsupported ECC size\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto fail;
}
- nand_oob.eccbytes = nand->ecc.bytes;
- nand->ecc.layout = &nand_oob;
-
- /* Set address of hardware control function */
- nand->cmdfunc = denali_cmdfunc;
- nand->read_byte = denali_read_byte;
- nand->read_buf = denali_read_buf;
- nand->select_chip = denali_select_chip;
- nand->waitfunc = denali_waitfunc;
- denali_hw_init(denali);
- return 0;
+ nand_oob.eccbytes = denali->nand.ecc.bytes;
+ denali->nand.ecc.layout = &nand_oob;
+
+ writel(denali->mtd->erasesize / denali->mtd->writesize,
+ denali->flash_reg + PAGES_PER_BLOCK);
+ writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
+ denali->flash_reg + DEVICE_WIDTH);
+ writel(denali->mtd->writesize,
+ denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
+ writel(denali->mtd->oobsize,
+ denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
+ writel(1, denali->flash_reg + DEVICES_CONNECTED);
+
+ /* override the default operations */
+ denali->nand.ecc.read_page = denali_read_page;
+ denali->nand.ecc.read_page_raw = denali_read_page_raw;
+ denali->nand.ecc.write_page = denali_write_page;
+ denali->nand.ecc.write_page_raw = denali_write_page_raw;
+ denali->nand.ecc.read_oob = denali_read_oob;
+ denali->nand.ecc.write_oob = denali_write_oob;
+
+ if (nand_scan_tail(denali->mtd)) {
+ ret = -ENXIO;
+ goto fail;
+ }
+
+ ret = nand_register(0);
+
+fail:
+ return ret;
+}
+
+static int __board_nand_init(void)
+{
+ struct denali_nand_info *denali;
+
+ denali = kzalloc(sizeof(*denali), GFP_KERNEL);
+ if (!denali)
+ return -ENOMEM;
+
+ /*
+ * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
+ * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
+ * still provides a "struct mtd_info nand_info" instance.
+ */
+ denali->mtd = &nand_info[0];
+
+ /*
+ * In the future, these base addresses should be taken from
+ * Device Tree or platform data.
+ */
+ denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+ denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+
+ return denali_init(denali);
}
-int board_nand_init(struct nand_chip *chip)
+void board_nand_init(void)
{
- return denali_nand_init(chip);
+ if (__board_nand_init() < 0)
+ pr_warn("Failed to initialize Denali NAND controller.\n");
}
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index 3277da7..a258df0 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -434,9 +434,8 @@ struct nand_buf {
#define DT 3
struct denali_nand_info {
- struct mtd_info mtd;
- struct nand_chip *nand;
-
+ struct mtd_info *mtd;
+ struct nand_chip nand;
int flash_bank; /* currently selected chip */
int status;
int platform;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 0b6e7ee..70e780c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -634,6 +634,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
{
struct nand_chip *chip = mtd->priv;
+ if (!(chip->options & NAND_BBT_SCANNED)) {
+ chip->scan_bbt(mtd);
+ chip->options |= NAND_BBT_SCANNED;
+ }
+
if (!chip->bbt)
return chip->block_bad(mtd, ofs, getchip);
@@ -4322,10 +4327,9 @@ int nand_scan_tail(struct mtd_info *mtd)
/* Check, if we should skip the bad block table scan */
if (chip->options & NAND_SKIP_BBTSCAN)
- return 0;
+ chip->options |= NAND_BBT_SCANNED;
- /* Build bad block table */
- return chip->scan_bbt(mtd);
+ return 0;
}
EXPORT_SYMBOL(nand_scan_tail);
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 40d6705..93829a4 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -73,14 +73,11 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SPL_BUILD
/* Check wait pin as dev ready indicator */
-static int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_dev_ready(struct mtd_info *mtd)
{
return gpmc_cfg->status & (1 << 8);
}
-#endif
-
/*
* gen_true_ecc - This function will generate true ECC value, which
@@ -887,7 +884,9 @@ int board_nand_init(struct nand_chip *nand)
nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
- nand->dev_ready = omap_spl_dev_ready;
#endif
+
+ nand->dev_ready = omap_dev_ready;
+
return 0;
}
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index db87d07..b3a2a60 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -38,10 +38,10 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
}
#endif
-static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
@@ -67,35 +67,35 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
writeb(cmd, chip->IO_ADDR_W);
}
-static int s3c2410_dev_ready(struct mtd_info *mtd)
+static int s3c24x0_dev_ready(struct mtd_info *mtd)
{
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug("dev_ready\n");
return readl(&nand->nfstat) & 0x01;
}
#ifdef CONFIG_S3C2410_NAND_HWECC
-void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
- debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode);
writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
}
-static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
ecc_code[0] = readb(&nand->nfecc);
ecc_code[1] = readb(&nand->nfecc + 1);
ecc_code[2] = readb(&nand->nfecc + 2);
- debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
- mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
+ debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
+ mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
return 0;
}
-static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
if (read_ecc[0] == calc_ecc[0] &&
@@ -103,7 +103,7 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
read_ecc[2] == calc_ecc[2])
return 0;
- printf("s3c2410_nand_correct_data: not implemented\n");
+ printf("s3c24x0_nand_correct_data: not implemented\n");
return -1;
}
#endif
@@ -113,7 +113,7 @@ int board_nand_init(struct nand_chip *nand)
u_int32_t cfg;
u_int8_t tacls, twrph0, twrph1;
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
+ struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
debug("board_nand_init()\n");
@@ -149,14 +149,14 @@ int board_nand_init(struct nand_chip *nand)
#endif
/* hwcontrol always must be implemented */
- nand->cmd_ctrl = s3c2410_hwcontrol;
+ nand->cmd_ctrl = s3c24x0_hwcontrol;
- nand->dev_ready = s3c2410_dev_ready;
+ nand->dev_ready = s3c24x0_dev_ready;
#ifdef CONFIG_S3C2410_NAND_HWECC
- nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
- nand->ecc.calculate = s3c2410_nand_calculate_ecc;
- nand->ecc.correct = s3c2410_nand_correct_data;
+ nand->ecc.hwctl = s3c24x0_nand_enable_hwecc;
+ nand->ecc.calculate = s3c24x0_nand_calculate_ecc;
+ nand->ecc.correct = s3c24x0_nand_correct_data;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 7feb3a7..928d58b 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -611,6 +611,9 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
}
+ /* Disable subpage writes as we do not provide ecc->hwctl */
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+
chip->dev_ready = vf610_nfc_dev_ready;
chip->cmdfunc = vf610_nfc_command;
chip->read_byte = vf610_nfc_read_byte;
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 5ae3b16..d052fcb 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_PPC_T1040) += t1040.o
obj-$(CONFIG_PPC_T1042) += t1040.o
obj-$(CONFIG_PPC_T1020) += t1040.o
obj-$(CONFIG_PPC_T1022) += t1040.o
+obj-$(CONFIG_PPC_T1023) += t1024.o
+obj-$(CONFIG_PPC_T1024) += t1024.o
obj-$(CONFIG_PPC_T2080) += t2080.o
obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 373cc4f..eb058c9 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
@@ -46,15 +47,76 @@ void fman_enable_port(enum fm_port port)
phy_interface_t fman_port_enet_if(enum fm_port port)
{
+#if defined(CONFIG_B4860QDS)
+ u32 serdes2_prtcl;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
- (is_serdes_configured(XAUI_FM1_MAC10))))
+ #if !defined(CONFIG_B4860QDS)
+ (is_serdes_configured(XFI_FM1_MAC9)) ||
+ (is_serdes_configured(XFI_FM1_MAC10)) ||
+ #endif
+ (is_serdes_configured(XAUI_FM1_MAC10))
+ ))
return PHY_INTERFACE_MODE_XGMII;
+#if defined(CONFIG_B4860QDS)
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ if (serdes2_prtcl) {
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ switch (serdes2_prtcl) {
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup yet
+ */
+ getenv_f("hwconfig", buffer, sizeof(buffer));
+ buf = buffer;
+
+ /* check if XFI interface enable in hwconfig for 10g */
+ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
+ "sfp_amc", "sfp", buf)) {
+ if ((port == FM1_10GEC1 ||
+ port == FM1_10GEC2) &&
+ ((is_serdes_configured(XFI_FM1_MAC9)) ||
+ (is_serdes_configured(XFI_FM1_MAC10))))
+ return PHY_INTERFACE_MODE_XGMII;
+ else if ((port == FM1_DTSEC1) ||
+ (port == FM1_DTSEC2) ||
+ (port == FM1_DTSEC3) ||
+ (port == FM1_DTSEC4))
+ return PHY_INTERFACE_MODE_NONE;
+ }
+ }
+ }
+#endif
+
/* Fix me need to handle RGMII here first */
switch (port) {
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 218a5ed..f1e39b9 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -39,9 +39,14 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
u32 value;
struct mii_dev bus;
bus.priv = priv->mac->phyregs;
+ bool sgmii_2500 = (priv->enet_if ==
+ PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+
+ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
+ value = PHY_SGMII_IF_MODE_SGMII;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_IF_MODE_AN;
- /* SGMII IF mode + AN enable */
- value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
@@ -54,7 +59,9 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
/* Restart AN */
- value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
+ value = PHY_SGMII_CR_DEF_VAL;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
#else
struct dtsec *regs = priv->mac->base;
@@ -83,7 +90,8 @@ static void dtsec_init_phy(struct eth_device *dev)
out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
#endif
- if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
+ if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+ fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
@@ -557,9 +565,11 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
num = fm_eth->num;
#ifdef CONFIG_SYS_FMAN_V3
+#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
if (fm_eth->type == FM_ETH_10G_E) {
- /* 10GEC1/10GEC2 use mEMAC9/mEMAC10
- * 10GEC3/10GEC4 use mEMAC1/mEMAC2
+ /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
+ * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
+ * 10GEC1 uses mEMAC1 on T1024.
* so it needs to change the num.
*/
if (fm_eth->num >= 2)
@@ -567,6 +577,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
else
num += 8;
}
+#endif
base = &reg->memac[num].fm_memac;
phyregs = &reg->memac[num].fm_memac_mdio;
#else
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 6cf21c6..5d82f29 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -254,8 +254,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
*/
if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
+ ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
+ ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c
new file mode 100644
index 0000000..9b31173
--- /dev/null
+++ b/drivers/net/fm/t1024.c
@@ -0,0 +1,88 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+ [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_RGMII) &&
+ (!is_serdes_configured(QSGMII_FM1_A)))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_RGMII) &&
+ (!is_serdes_configured(QSGMII_FM1_A)))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ /* handle SGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+ + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII_2500;
+ break;
+ default:
+ break;
+ }
+
+ /* handle QSGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ /* check lane A on SerDes1 */
+ if (is_serdes_configured(QSGMII_FM1_A))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ default:
+ break;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index 4cce46d..d2a097e 100644
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -25,8 +25,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
- else
- return PHY_INTERFACE_MODE_NONE;
}
if ((port == FM1_DTSEC4) &&
@@ -38,8 +36,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
- else
- return PHY_INTERFACE_MODE_NONE;
}
if (port == FM1_DTSEC5) {
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9556536..f46bf00 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHYLIB) += phy.o
obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
obj-$(CONFIG_PHY_ATHEROS) += atheros.o
obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
+obj-$(CONFIG_PHY_CORTINA) += cortina.o
obj-$(CONFIG_PHY_DAVICOM) += davicom.o
obj-$(CONFIG_PHY_ET1011C) += et1011c.o
obj-$(CONFIG_PHY_LXT) += lxt.o
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
new file mode 100644
index 0000000..254f056
--- /dev/null
+++ b/drivers/net/phy/cortina.c
@@ -0,0 +1,333 @@
+/*
+ * Cortina CS4315/CS4340 10G PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/err.h>
+#include <phy.h>
+#include <cortina.h>
+#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
+#include <nand.h>
+#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
+#include <spi_flash.h>
+#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
+#include <mmc.h>
+#endif
+
+#ifndef CONFIG_PHYLIB_10G
+#error The Cortina PHY needs 10G support
+#endif
+
+struct cortina_reg_config cortina_reg_cfg[] = {
+ /* CS4315_enable_sr_mode */
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
+ {VILLA_MSEQ_OPTIONS, 0xf},
+ {VILLA_MSEQ_PC, 0x0},
+ {VILLA_MSEQ_BANKSELECT, 0x4},
+ {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
+ {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
+ {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
+ {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
+ {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
+ {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
+ {VILLA_MSEQ_ENABLE_MSB, 0x0000},
+ {VILLA_MSEQ_SPARE21_LSB, 0x6},
+ {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
+ {VILLA_MSEQ_SPARE12_MSB, 0x0000},
+ /*
+ * to invert the receiver path, uncomment the next line
+ * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
+ *
+ * SPARE2_LSB is used to configure the device while in sr mode to
+ * enable power savings and to use the optical module LOS signal.
+ * in power savings mode, the internal prbs checker can not be used.
+ * if the optical module LOS signal is used as an input to the micro
+ * code, then the micro code will wait until the optical module
+ * LOS = 0 before turning on the adaptive equalizer.
+ * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
+ * while setting bit 0 to 0 disables power savings mode.
+ * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
+ * optical module LOS signal while setting bit 2 to 1 configures the
+ * device so that it will ignore the optical module LOS SPARE2_LSB = 0
+ */
+
+ /* enable power savings, ignore optical module LOS */
+ {VILLA_MSEQ_SPARE2_LSB, 0x5},
+
+ {VILLA_MSEQ_SPARE7_LSB, 0x1e},
+ {VILLA_MSEQ_BANKSELECT, 0x4},
+ {VILLA_MSEQ_SPARE9_LSB, 0x2},
+ {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
+ {VILLA_MSEQ_SPARE3_MSB, 0x2006},
+ {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
+ {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
+ {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
+ {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
+ {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
+ {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
+ {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
+ {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
+ {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
+ {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
+ {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
+ {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
+ {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
+ {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
+ {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
+ {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
+ {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
+ {VILLA_MSEQ_OPTIONS, 0x7},
+
+ /* set up min value for ffe1 */
+ {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
+ {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
+
+ /* CS4315_sr_rx_pre_eq_set_4in */
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
+ {VILLA_MSEQ_OPTIONS, 0xf},
+ {VILLA_MSEQ_BANKSELECT, 0x4},
+ {VILLA_MSEQ_PC, 0x0},
+
+ /* for lengths from 3.5 to 4.5inches */
+ {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
+ {VILLA_MSEQ_SPARE25_LSB, 0x0306},
+ {VILLA_MSEQ_SPARE21_LSB, 0x2},
+ {VILLA_MSEQ_SPARE23_LSB, 0x2},
+ {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
+
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
+ {VILLA_MSEQ_OPTIONS, 0x7},
+
+ /* CS4315_rx_drive_4inch */
+ /* for length 4inches */
+ {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
+ {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
+ {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
+
+ /* CS4315_tx_drive_4inch */
+ /* for length 4inches */
+ {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
+ {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
+ {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
+};
+
+void cs4340_upload_firmware(struct phy_device *phydev)
+{
+ char line_temp[0x50] = {0};
+ char reg_addr[0x50] = {0};
+ char reg_data[0x50] = {0};
+ int i, line_cnt = 0, column_cnt = 0;
+ struct cortina_reg_config fw_temp;
+ char *addr = NULL;
+
+#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
+ defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
+
+ addr = (char *)CONFIG_CORTINA_FW_ADDR;
+#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
+ int ret;
+ size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
+
+ addr = malloc(CONFIG_CORTINA_FW_LENGTH);
+ ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
+ &fw_length, (u_char *)addr);
+ if (ret == -EUCLEAN) {
+ printf("NAND read of Cortina firmware at 0x%x failed %d\n",
+ CONFIG_CORTINA_FW_ADDR, ret);
+ }
+#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
+ int ret;
+ struct spi_flash *ucode_flash;
+
+ addr = malloc(CONFIG_CORTINA_FW_LENGTH);
+ ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (!ucode_flash) {
+ puts("SF: probe for Cortina ucode failed\n");
+ } else {
+ ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
+ CONFIG_CORTINA_FW_LENGTH, addr);
+ if (ret)
+ puts("SF: read for Cortina ucode failed\n");
+ spi_flash_free(ucode_flash);
+ }
+#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
+ u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ puts("Failed to find MMC device for Cortina ucode\n");
+ } else {
+ addr = malloc(CONFIG_CORTINA_FW_LENGTH);
+ printf("MMC read: dev # %u, block # %u, count %u ...\n",
+ dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512);
+ }
+#endif
+
+ while (*addr != 'Q') {
+ i = 0;
+
+ while (*addr != 0x0a) {
+ line_temp[i++] = *addr++;
+ if (0x50 < i) {
+ printf("Not found Cortina PHY ucode at 0x%x\n",
+ CONFIG_CORTINA_FW_ADDR);
+ return;
+ }
+ }
+
+ addr++; /* skip '\n' */
+ line_cnt++;
+ column_cnt = i;
+ line_temp[column_cnt] = '\0';
+
+ if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
+ return;
+
+ for (i = 0; i < column_cnt; i++) {
+ if (isspace(line_temp[i++]))
+ break;
+ }
+
+ memcpy(reg_addr, line_temp, i);
+ memcpy(reg_data, &line_temp[i], column_cnt - i);
+ strim(reg_addr);
+ strim(reg_data);
+ fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
+ fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
+ 0xffff;
+ phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
+ }
+}
+
+int cs4340_phy_init(struct phy_device *phydev)
+{
+ int timeout = 100; /* 100ms */
+ int reg_value;
+
+ /* step1: BIST test */
+ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
+ phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
+ phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
+ while (--timeout) {
+ reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
+ if (reg_value & mseq_edc_bist_done) {
+ if (0 == (reg_value & mseq_edc_bist_fail))
+ break;
+ }
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
+ return -1;
+ }
+
+ /* setp2: upload ucode */
+ cs4340_upload_firmware(phydev);
+ reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
+ if (reg_value) {
+ debug("%s checksum status failed.\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int cs4340_config(struct phy_device *phydev)
+{
+ cs4340_phy_init(phydev);
+ return 0;
+}
+
+int cs4340_startup(struct phy_device *phydev)
+{
+ phydev->link = 1;
+
+ /* For now just lie and say it's 10G all the time */
+ phydev->speed = SPEED_10000;
+ phydev->duplex = DUPLEX_FULL;
+ return 0;
+}
+
+struct phy_driver cs4340_driver = {
+ .name = "Cortina CS4315/CS4340",
+ .uid = PHY_UID_CS4340,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
+ MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
+ MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
+ .config = &cs4340_config,
+ .startup = &cs4340_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
+int phy_cortina_init(void)
+{
+ phy_register(&cs4340_driver);
+ return 0;
+}
+
+int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+{
+ int phy_reg;
+ bool is_cortina_phy = false;
+
+ switch (addr) {
+#ifdef CORTINA_PHY_ADDR1
+ case CORTINA_PHY_ADDR1:
+#endif
+#ifdef CORTINA_PHY_ADDR2
+ case CORTINA_PHY_ADDR2:
+#endif
+#ifdef CORTINA_PHY_ADDR3
+ case CORTINA_PHY_ADDR3:
+#endif
+#ifdef CORTINA_PHY_ADDR4
+ case CORTINA_PHY_ADDR4:
+#endif
+ is_cortina_phy = true;
+ break;
+ default:
+ break;
+ }
+
+ /* Cortina PHY has non-standard offset of PHY ID registers */
+ if (is_cortina_phy)
+ phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
+ else
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+
+ if (phy_reg < 0)
+ return -EIO;
+
+ *phy_id = (phy_reg & 0xffff) << 16;
+ if (is_cortina_phy)
+ phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
+ else
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+
+ if (phy_reg < 0)
+ return -EIO;
+
+ *phy_id |= (phy_reg & 0xffff);
+
+ return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 467c972..5b04c85 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -448,6 +448,9 @@ int phy_init(void)
#ifdef CONFIG_PHY_BROADCOM
phy_broadcom_init();
#endif
+#ifdef CONFIG_PHY_CORTINA
+ phy_cortina_init();
+#endif
#ifdef CONFIG_PHY_DAVICOM
phy_davicom_init();
#endif
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 2b29cd8..20a6746 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -1,8 +1,8 @@
/*
* Vitesse PHY drivers
*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Author: Andy Fleming
+ * Copyright 2010-2014 Freescale Semiconductor, Inc.
+ * Original Author: Andy Fleming
* Add vsc8662 phy support - Priyanka Jain
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -50,6 +50,7 @@
#define MIIM_VSC8574_18G_CMDSTAT 0x8000
/* Vitesse VSC8514 control register */
+#define MIIM_VSC8514_MAC_SERDES_CON 0x10
#define MIIM_VSC8514_GENERAL18 0x12
#define MIIM_VSC8514_GENERAL19 0x13
#define MIIM_VSC8514_GENERAL23 0x17
@@ -246,6 +247,14 @@ static int vsc8514_config(struct phy_device *phydev)
val = (val & 0xf8ff);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
+ /* Enable Serdes Auto-negotiation */
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+ PHY_EXT_PAGE_ACCESS_EXTENDED3);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON);
+ val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
genphy_config_aneg(phydev);
return 0;
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e73a498..55d6a9b 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,7 +6,7 @@
#
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI) += pci.o pci_auto.o
+obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7ee21d1..3daf73c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -366,9 +366,27 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
return phys_addr;
}
-/*
- *
- */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+ u32 addr_and_ctrl)
+{
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
+}
+
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
+{
+ u32 addr;
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ pci_hose_read_config_dword(hose, dev, bar, &addr);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ return addr & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
new file mode 100644
index 0000000..af6a3ae
--- /dev/null
+++ b/drivers/pci/pci_rom.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
+ *
+ * Modifications are:
+ * Copyright (C) 2003-2004 Linux Networx
+ * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
+ * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
+ * Copyright (C) 2005-2006 Tyan
+ * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
+ * Copyright (C) 2005-2009 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+ *
+ * PCI Bus Services, see include/linux/pci.h for further explanation.
+ *
+ * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
+ * David Mosberger-Tang
+ *
+ * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <video_fb.h>
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+#include <asm/acpi.h>
+#endif
+
+__weak bool board_should_run_oprom(pci_dev_t dev)
+{
+ return true;
+}
+
+static bool should_load_oprom(pci_dev_t dev)
+{
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ if (acpi_get_slp_type() == 3)
+ return false;
+#endif
+ if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
+ return 1;
+ if (board_should_run_oprom(dev))
+ return 1;
+
+ return 0;
+}
+
+__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ return vendev;
+}
+
+static int pci_rom_probe(pci_dev_t dev, uint class,
+ struct pci_rom_header **hdrp)
+{
+ struct pci_rom_header *rom_header;
+ struct pci_rom_data *rom_data;
+ u16 vendor, device;
+ u32 vendev;
+ u32 mapped_vendev;
+ u32 rom_address;
+
+ pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(dev, PCI_DEVICE_ID, &device);
+ vendev = vendor << 16 | device;
+ mapped_vendev = board_map_oprom_vendev(vendev);
+ if (vendev != mapped_vendev)
+ debug("Device ID mapped to %#08x\n", mapped_vendev);
+
+#ifdef CONFIG_X86_OPTION_ROM_ADDR
+ rom_address = CONFIG_X86_OPTION_ROM_ADDR;
+#else
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
+ pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+ if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
+ debug("%s: rom_address=%x\n", __func__, rom_address);
+ return -ENOENT;
+ }
+
+ /* Enable expansion ROM address decoding. */
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
+ rom_address | PCI_ROM_ADDRESS_ENABLE);
+#endif
+ debug("Option ROM address %x\n", rom_address);
+ rom_header = (struct pci_rom_header *)rom_address;
+
+ debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
+ le32_to_cpu(rom_header->signature),
+ rom_header->size * 512, le32_to_cpu(rom_header->data));
+
+ if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
+ printf("Incorrect expansion ROM header signature %04x\n",
+ le32_to_cpu(rom_header->signature));
+ return -EINVAL;
+ }
+
+ rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
+
+ debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
+ rom_data->vendor, rom_data->device);
+
+ /* If the device id is mapped, a mismatch is expected */
+ if ((vendor != rom_data->vendor || device != rom_data->device) &&
+ (vendev == mapped_vendev)) {
+ printf("ID mismatch: vendor ID %04x, device ID %04x\n",
+ rom_data->vendor, rom_data->device);
+ return -EPERM;
+ }
+
+ debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n",
+ rom_data->class_hi, rom_data->class_lo, rom_data->type);
+
+ if (class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
+ debug("Class Code mismatch ROM %08x, dev %08x\n",
+ (rom_data->class_hi << 8) | rom_data->class_lo,
+ class);
+ }
+ *hdrp = rom_header;
+
+ return 0;
+}
+
+int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
+ struct pci_rom_header **ram_headerp)
+{
+ struct pci_rom_data *rom_data;
+ unsigned int rom_size;
+ unsigned int image_size = 0;
+ void *target;
+
+ do {
+ /* Get next image, until we see an x86 version */
+ rom_header = (struct pci_rom_header *)((void *)rom_header +
+ image_size);
+
+ rom_data = (struct pci_rom_data *)((void *)rom_header +
+ le32_to_cpu(rom_header->data));
+
+ image_size = le32_to_cpu(rom_data->ilen) * 512;
+ } while ((rom_data->type != 0) && (rom_data->indicator != 0));
+
+ if (rom_data->type != 0)
+ return -EACCES;
+
+ rom_size = rom_header->size * 512;
+
+ target = (void *)PCI_VGA_RAM_IMAGE_START;
+ if (target != rom_header) {
+ debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
+ rom_header, target, rom_size);
+ memcpy(target, rom_header, rom_size);
+ if (memcmp(target, rom_header, rom_size)) {
+ printf("VGA ROM copy failed\n");
+ return -EFAULT;
+ }
+ }
+ *ram_headerp = target;
+
+ return 0;
+}
+
+static struct vbe_mode_info mode_info;
+
+int vbe_get_video_info(struct graphic_device *gdev)
+{
+#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+
+ gdev->winSizeX = vesa->x_resolution;
+ gdev->winSizeY = vesa->y_resolution;
+
+ gdev->plnSizeX = vesa->x_resolution;
+ gdev->plnSizeY = vesa->y_resolution;
+
+ gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
+
+ switch (vesa->bits_per_pixel) {
+ case 24:
+ gdev->gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ gdev->gdfIndex = GDF_16BIT_565RGB;
+ break;
+ default:
+ gdev->gdfIndex = GDF__8BIT_INDEX;
+ break;
+ }
+
+ gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
+ gdev->pciBase = vesa->phys_base_ptr;
+
+ gdev->frameAdrs = vesa->phys_base_ptr;
+ gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution;
+
+ gdev->vprBase = vesa->phys_base_ptr;
+ gdev->cprBase = vesa->phys_base_ptr;
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
+{
+ struct pci_rom_header *rom, *ram;
+ int vesa_mode = -1;
+ uint16_t class;
+ int ret;
+
+ /* Only execute VGA ROMs */
+ pci_read_config_word(dev, PCI_CLASS_DEVICE, &class);
+ if ((class ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ debug("%s: Class %#x, should be %#x\n", __func__, class,
+ PCI_CLASS_DISPLAY_VGA);
+ return -ENODEV;
+ }
+
+ if (!should_load_oprom(dev))
+ return -ENXIO;
+
+ ret = pci_rom_probe(dev, class, &rom);
+ if (ret)
+ return ret;
+
+ ret = pci_rom_load(class, rom, &ram);
+ if (ret)
+ return ret;
+
+ if (!board_should_run_oprom(dev))
+ return -ENXIO;
+
+#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
+ defined(CONFIG_FRAMEBUFFER_VESA_MODE)
+ vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
+#endif
+ debug("Selected vesa mode %d\b", vesa_mode);
+ if (emulate) {
+#ifdef CONFIG_BIOSEMU
+ BE_VGAInfo *info;
+
+ ret = biosemu_setup(dev, &info);
+ if (ret)
+ return ret;
+ biosemu_set_interrupt_handler(0x15, int15_handler);
+ ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
+ vesa_mode, &mode_info);
+ if (ret)
+ return ret;
+#else
+ printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
+ return -ENOSYS;
+#endif
+ } else {
+#ifdef CONFIG_X86
+ bios_set_interrupt_handler(0x15, int15_handler);
+
+ bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
+ &mode_info);
+#else
+ printf("BIOS native execution is only available on x86\n");
+ return -ENOSYS;
+#endif
+ }
+ debug("Final vesa mode %d\n", mode_info.video_mode);
+
+ return 0;
+}
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index cfbc9dc..6430fe0 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -27,7 +27,7 @@ int palmas_mmc1_poweron_ldo(void)
{
u8 val = 0;
-#if defined(CONFIG_DRA7XX)
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/*
* Currently valid for the dra7xx_evm board:
* Set TPS659038 LDO1 to 3.0 V
diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c
index df1fd91..95b1a57 100644
--- a/drivers/power/pmic/pmic_max77686.c
+++ b/drivers/power/pmic/pmic_max77686.c
@@ -42,11 +42,30 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
return 0;
}
+static int max77686_buck_volt2hex(int buck, ulong uV)
+{
+ int hex = 0;
+
+ if (buck < 5 || buck > 9) {
+ debug("%s: buck %d is not supported\n", __func__, buck);
+ return -EINVAL;
+ }
+
+ hex = (uV - 750000) / 50000;
+
+ if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
+ return hex;
+
+ debug("%s: %ld is wrong voltage value for BUCK%d\n",
+ __func__, uV, buck);
+ return -EINVAL;
+}
+
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
{
unsigned int val, ret, hex, adr;
- if (ldo < 1 && ldo > 26) {
+ if (ldo < 1 || ldo > 26) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
@@ -68,11 +87,38 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
return ret;
}
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
+{
+ unsigned int val, adr;
+ int hex, ret;
+
+ if (buck < 5 || buck > 9) {
+ printf("%s: %d is an unsupported bucket number\n",
+ __func__, buck);
+ return -EINVAL;
+ }
+
+ adr = max77686_buck_addr[buck] + 1;
+ hex = max77686_buck_volt2hex(buck, uV);
+
+ if (hex < 0)
+ return hex;
+
+ ret = pmic_reg_read(p, adr, &val);
+ if (ret)
+ return ret;
+
+ val &= ~MAX77686_BUCK_VOLT_MASK;
+ ret |= pmic_reg_write(p, adr, val | hex);
+
+ return ret;
+}
+
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
{
unsigned int val, ret, adr, mode;
- if (ldo < 1 && 26 < ldo) {
+ if (ldo < 1 || 26 < ldo) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
@@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
/* mode */
switch (opmode) {
case OPMODE_OFF:
- mode = MAX77686_BUCK_MODE_OFF;
+ mode = MAX77686_BUCK_MODE_OFF << mode_shift;
break;
case OPMODE_STANDBY:
switch (buck) {
diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
index 594cd11..0dcf9fe 100644
--- a/drivers/power/power_i2c.c
+++ b/drivers/power/power_i2c.c
@@ -14,7 +14,7 @@
#include <linux/types.h>
#include <power/pmic.h>
#include <i2c.h>
-#include <compiler.h>
+#include <linux/compiler.h>
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
{
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index e578ae6..7f1fdd1 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -91,17 +91,23 @@ void twl4030_power_init(void)
TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
-void twl4030_power_mmc_init(void)
+void twl4030_power_mmc_init(int dev_index)
{
- /* Set VMMC1 to 3.15 Volts */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
- TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
- TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ if (dev_index == 0) {
+ /* Set VMMC1 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
- /* Set VMMC2 to 3.15 Volts */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
- TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
- TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ mdelay(100); /* ramp-up delay from Linux code */
+ } else if (dev_index == 1) {
+ /* Set VMMC2 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ mdelay(100); /* ramp-up delay from Linux code */
+ }
}
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 7f1bd06..8fa4866 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_U_QE) += qe.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index d9a7d82..dfae4bf 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -12,6 +12,7 @@
#include <fdt_support.h>
#include "qe.h"
+#ifdef CONFIG_QE
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -72,3 +73,4 @@ void ft_qe_setup(void *blob)
"clock-frequency", gd->arch.qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
}
+#endif
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 4358a91..bc94673 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
return;
}
+#ifdef CONFIG_QE
uint qe_muram_alloc(uint size, uint align)
{
uint retloc;
@@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align)
return retloc;
}
+#endif
void *qe_muram_addr(uint offset)
{
@@ -180,6 +182,17 @@ void qe_init(uint qe_base)
qe_snums_init();
}
+#ifdef CONFIG_U_QE
+void u_qe_init(void)
+{
+ uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
+ qe_immr = (qe_map_t *)qe_base;
+
+ u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
void qe_reset(void)
{
qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -212,6 +225,7 @@ void qe_assign_page(uint snum, uint para_ram_base)
#define BRG_CLK (gd->arch.brg_clk)
+#ifdef CONFIG_QE
int qe_set_brg(uint brg, uint rate)
{
volatile uint *bp;
@@ -239,6 +253,7 @@ int qe_set_brg(uint brg, uint rate)
return 0;
}
+#endif
/* Set ethernet MII clock master
*/
@@ -429,6 +444,131 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
return 0;
}
+#ifdef CONFIG_U_QE
+/*
+ * Upload a microcode to the I-RAM at a specific address.
+ *
+ * See docs/README.qe_firmware for information on QE microcode uploading.
+ *
+ * Currently, only version 1 is supported, so the 'version' field must be
+ * set to 1.
+ *
+ * The SOC model and revision are not validated, they are only displayed for
+ * informational purposes.
+ *
+ * 'calc_size' is the calculated size, in bytes, of the firmware structure and
+ * all of the microcode structures, minus the CRC.
+ *
+ * 'length' is the size that the structure says it is, including the CRC.
+ */
+int u_qe_upload_firmware(const struct qe_firmware *firmware)
+{
+ unsigned int i;
+ unsigned int j;
+ u32 crc;
+ size_t calc_size = sizeof(struct qe_firmware);
+ size_t length;
+ const struct qe_header *hdr;
+#ifdef CONFIG_DEEP_SLEEP
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+ if (!firmware) {
+ printf("Invalid address\n");
+ return -EINVAL;
+ }
+
+ hdr = &firmware->header;
+ length = be32_to_cpu(hdr->length);
+
+ /* Check the magic */
+ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+ (hdr->magic[2] != 'F')) {
+ printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
+ return -EPERM;
+ }
+
+ /* Check the version */
+ if (hdr->version != 1) {
+ printf("Unsupported version\n");
+ return -EPERM;
+ }
+
+ /* Validate some of the fields */
+ if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+ printf("Invalid data\n");
+ return -EINVAL;
+ }
+
+ /* Validate the length and check if there's a CRC */
+ calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
+
+ for (i = 0; i < firmware->count; i++)
+ /*
+ * For situations where the second RISC uses the same microcode
+ * as the first, the 'code_offset' and 'count' fields will be
+ * zero, so it's okay to add those.
+ */
+ calc_size += sizeof(u32) *
+ be32_to_cpu(firmware->microcode[i].count);
+
+ /* Validate the length */
+ if (length != calc_size + sizeof(u32)) {
+ printf("Invalid length\n");
+ return -EPERM;
+ }
+
+ /*
+ * Validate the CRC. We would normally call crc32_no_comp(), but that
+ * function isn't available unless you turn on JFFS support.
+ */
+ crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
+ if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
+ printf("Firmware CRC is invalid\n");
+ return -EIO;
+ }
+
+ /*
+ * If the microcode calls for it, split the I-RAM.
+ */
+ if (!firmware->split) {
+ out_be16(&qe_immr->cp.cercr,
+ in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+ }
+
+ if (firmware->soc.model)
+ printf("Firmware '%s' for %u V%u.%u\n",
+ firmware->id, be16_to_cpu(firmware->soc.model),
+ firmware->soc.major, firmware->soc.minor);
+ else
+ printf("Firmware '%s'\n", firmware->id);
+
+ /* Loop through each microcode. */
+ for (i = 0; i < firmware->count; i++) {
+ const struct qe_microcode *ucode = &firmware->microcode[i];
+
+ /* Upload a microcode if it's present */
+ if (ucode->code_offset)
+ qe_upload_microcode(firmware, ucode);
+
+ /* Program the traps for this processor */
+ for (j = 0; j < 16; j++) {
+ u32 trap = be32_to_cpu(ucode->traps[j]);
+
+ if (trap)
+ out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+ }
+
+ /* Enable traps */
+ out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+ }
+
+ return 0;
+}
+#endif
+
struct qe_firmware_info *qe_get_firmware_info(void)
{
return qe_firmware_uploaded ? &qe_firmware_info : NULL;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index ebb7c5f..33878f8 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -285,4 +285,9 @@ void ft_qe_setup(void *blob);
void qe_init(uint qe_base);
void qe_reset(void);
+#ifdef CONFIG_U_QE
+void u_qe_init(void);
+int u_qe_upload_firmware(const struct qe_firmware *firmware);
+#endif
+
#endif /* __QE_H__ */
diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c
index 21a2189..4cf2d83 100644
--- a/drivers/rtc/bfin_rtc.c
+++ b/drivers/rtc/bfin_rtc.c
@@ -27,7 +27,7 @@
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
/* Enable the RTC prescaler enable register */
-static void rtc_init(void)
+void rtc_init(void)
{
if (!(bfin_read_RTC_PREN() & 0x1))
bfin_write_RTC_PREN(0x1);
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index f7cf106..39e6041 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <rtc.h>
+#include <version.h>
#if defined(__I386__) || defined(CONFIG_MALTA)
#include <asm/io.h>
@@ -23,6 +24,9 @@
#if defined(CONFIG_CMD_DATE)
+/* Set this to 1 to clear the CMOS RAM */
+#define CLEAR_CMOS 0
+
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
@@ -41,7 +45,14 @@ static void rtc_write (uchar reg, uchar val);
#define RTC_CONFIG_B 0x0B
#define RTC_CONFIG_C 0x0C
#define RTC_CONFIG_D 0x0D
+#define RTC_REG_SIZE 0x80
+
+#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5)
+#define RTC_CONFIG_A_RATE_1024HZ 6
+#define RTC_CONFIG_B_24H (1 << 1)
+
+#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80
/* ------------------------------------------------------------------------- */
@@ -128,25 +139,49 @@ void rtc_reset (void)
*/
static uchar rtc_read (uchar reg)
{
- return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg));
+ return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
}
static void rtc_write (uchar reg, uchar val)
{
- out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val);
+ out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
}
#else
static uchar rtc_read (uchar reg)
{
out8(RTC_PORT_MC146818,reg);
- return(in8(RTC_PORT_MC146818+1));
+ return in8(RTC_PORT_MC146818 + 1);
}
static void rtc_write (uchar reg, uchar val)
{
out8(RTC_PORT_MC146818,reg);
- out8(RTC_PORT_MC146818+1,val);
+ out8(RTC_PORT_MC146818+1, val);
}
#endif
+void rtc_init(void)
+{
+#if CLEAR_CMOS
+ int i;
+
+ rtc_write(RTC_SECONDS_ALARM, 0);
+ rtc_write(RTC_MINUTES_ALARM, 0);
+ rtc_write(RTC_HOURS_ALARM, 0);
+ for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++)
+ rtc_write(i, 0);
+ printf("RTC: zeroing CMOS RAM\n");
+#endif
+
+ /* Setup the real time clock */
+ rtc_write(RTC_CONFIG_B, RTC_CONFIG_B_24H);
+ /* Setup the frequency it operates at */
+ rtc_write(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
+ RTC_CONFIG_A_RATE_1024HZ);
+ /* Ensure all reserved bits are 0 in register D */
+ rtc_write(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
+
+ /* Clear any pending interrupts */
+ rtc_read(RTC_CONFIG_C);
+}
#endif
diff --git a/drivers/rtc/mvrtc.h b/drivers/rtc/mvrtc.h
index ebddc12..424743c 100644
--- a/drivers/rtc/mvrtc.h
+++ b/drivers/rtc/mvrtc.h
@@ -13,7 +13,7 @@
#define _MVRTC_H_
#include <asm/arch/soc.h>
-#include <compiler.h>
+#include <linux/compiler.h>
/* RTC registers */
struct mvrtc_registers {
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8f05191..af5beba 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -132,11 +132,12 @@ static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+#if (defined(CONFIG_SPL_BUILD) && \
+ (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
/*
- * On some OMAP3 devices when UART3 is configured for boot mode before
- * SPL starts only THRE bit is set. We have to empty the transmitter
- * before initialization starts.
+ * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
+ * before SPL starts only THRE bit is set. We have to empty the
+ * transmitter before initialization starts.
*/
if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
== UART_LSR_THRE) {
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index b09053f..d1b5777 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -39,7 +39,7 @@ static void serial_find_console_or_panic(void)
/* Check for a chosen console */
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
- node = fdtdec_get_alias_node(gd->fdt_blob, "console");
+ node = fdt_path_offset(gd->fdt_blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
gd->cur_serial_dev = dev;
return;
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 38dda91..e1bf496 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -72,30 +72,39 @@ static int pl01x_tstc(struct pl01x_regs *regs)
static int pl01x_generic_serial_init(struct pl01x_regs *regs,
enum pl01x_type type)
{
- unsigned int lcr;
-
+ switch (type) {
+ case TYPE_PL010:
+ /* disable everything */
+ writel(0, &regs->pl010_cr);
+ break;
+ case TYPE_PL011:
#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- if (type == TYPE_PL011) {
/* Empty RX fifo if necessary */
if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
readl(&regs->dr);
}
- }
#endif
+ /* disable everything */
+ writel(0, &regs->pl011_cr);
+ break;
+ default:
+ return -EINVAL;
+ }
- /* First, disable everything */
- writel(0, &regs->pl010_cr);
+ return 0;
+}
- /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
+static int set_line_control(struct pl01x_regs *regs)
+{
+ unsigned int lcr;
+ /*
+ * Internal update of baud rate register require line
+ * control register write
+ */
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
- writel(lcr, &regs->pl011_lcrh);
-
- switch (type) {
- case TYPE_PL010:
- break;
- case TYPE_PL011: {
#ifdef CONFIG_PL011_SERIAL_RLCR
+ {
int i;
/*
@@ -107,15 +116,9 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs,
writel(lcr, &regs->fr);
writel(lcr, &regs->pl011_rlcr);
- /* lcrh needs to be set again for change to be effective */
- writel(lcr, &regs->pl011_lcrh);
-#endif
- break;
- }
- default:
- return -EINVAL;
}
-
+#endif
+ writel(lcr, &regs->pl011_lcrh);
return 0;
}
@@ -175,6 +178,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
writel(divider, &regs->pl011_ibrd);
writel(fraction, &regs->pl011_fbrd);
+ set_line_control(regs);
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
@@ -201,7 +205,7 @@ static void pl01x_serial_init_baud(int baudrate)
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
pl01x_generic_serial_init(base_regs, pl01x_type);
- pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
+ pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
}
/*
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 6046efb..e8a1608 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -11,6 +11,7 @@
#include <dm/device.h>
#include <dm/platform_data/serial-uniphier.h>
#include <serial.h>
+#include <fdtdec.h>
#define UART_REG(x) \
u8 x; \
@@ -113,19 +114,21 @@ static int uniphier_serial_remove(struct udevice *dev)
}
#ifdef CONFIG_OF_CONTROL
-static const struct udevice_id uniphier_uart_of_match = {
- { .compatible = "panasonic,uniphier-uart"},
+static const struct udevice_id uniphier_uart_of_match[] = {
+ { .compatible = "panasonic,uniphier-uart" },
{},
};
static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
{
- /*
- * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com)
- *
- * Implement conversion code from DTB to platform data
- * when supporting CONFIG_OF_CONTROL on UniPhir platform.
- */
+ struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+ DECLARE_GLOBAL_DATA_PTR;
+
+ plat->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 0);
+
+ return 0;
}
#endif
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index fd7fea8..857b604 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -102,7 +102,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
struct spi_slave *slave = &qslave->slave;
u32 memval = 0;
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
slave->memory_map = (void *)MMAP_START_ADDR_DRA;
#else
slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
@@ -244,7 +244,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
uint status;
int timeout;
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
int val;
#endif
@@ -254,7 +254,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
writel(MM_SWITCH, &qslave->base->memswitch);
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
@@ -262,7 +262,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, &qslave->base->memswitch);
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val &= MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c
index bc0f964..31761ec 100644
--- a/drivers/tpm/tpm.c
+++ b/drivers/tpm/tpm.c
@@ -34,7 +34,7 @@
#include <config.h>
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <fdtdec.h>
#include <i2c.h>
#include <tpm.h>
diff --git a/drivers/tpm/tpm_tis_i2c.c b/drivers/tpm/tpm_tis_i2c.c
index 2dd8501..c1bbed4 100644
--- a/drivers/tpm/tpm_tis_i2c.c
+++ b/drivers/tpm/tpm_tis_i2c.c
@@ -38,7 +38,7 @@
#include <common.h>
#include <fdtdec.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <i2c.h>
#include <tpm.h>
#include <asm-generic/errno.h>
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index edd91a8..6fdbf57 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -85,15 +85,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
}
#endif
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct exynos_usb_phy *usb)
+static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
- set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
-
- set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
-
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
@@ -150,8 +145,34 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
EHCICTRL_ENAINCR16);
}
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct exynos_usb_phy *usb)
+static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
+{
+ writel(CLK_24MHZ, &usb->usbphyclk);
+
+ clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+ PHYPWR_NORMAL_MASK_PHY0));
+
+ setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+ udelay(10);
+ clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+}
+
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+ set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
+ set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+
+ if (cpu_is_exynos5())
+ exynos5_setup_usb_phy(usb);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
+ usb);
+}
+
+static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
@@ -171,6 +192,24 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+}
+
+static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
+{
+ setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+ PHYPWR_NORMAL_MASK_PHY0));
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+ if (cpu_is_exynos5())
+ exynos5_reset_usb_phy(usb);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
+ usb);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
}
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45062e6..8f55464 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,7 +14,7 @@
#include <asm/io.h>
#include <usb/ehci-fsl.h>
#include <hwconfig.h>
-#include <asm/fsl_errata.h>
+#include <fsl_usb.h>
#include "ehci.h"
@@ -130,8 +130,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
in_le32(&ehci->usbmode);
- if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
- IS_SVR_REV(get_svr(), 2, 0))
+ if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
return 0;
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
index 77f6c9d..32a4375 100644
--- a/drivers/usb/host/ehci-uniphier.c
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -6,10 +6,43 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <usb.h>
#include <asm/arch/ehci-uniphier.h>
#include "ehci.h"
+#ifdef CONFIG_OF_CONTROL
+#include <fdtdec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FDT gd->fdt_blob
+#define COMPAT "panasonic,uniphier-ehci"
+
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+ int offset;
+
+ for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
+ offset >= 0;
+ offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
+ if (index == 0) {
+ *base = (struct ehci_hccr *)
+ fdtdec_get_addr(FDT, offset, "reg");
+ return 0;
+ }
+ index--;
+ }
+
+ return -ENODEV; /* not found */
+}
+#else
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+ *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
+ return 0;
+}
+#endif
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
@@ -17,12 +50,15 @@
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
+ int ret;
struct ehci_hccr *cr;
struct ehci_hcor *or;
uniphier_ehci_reset(index, 0);
- cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
+ ret = get_uniphier_ehci_base(index, &cr);
+ if (ret < 0)
+ return ret;
or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
*hccr = cr;
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f78d532..52a3664 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -118,7 +118,6 @@ void usb_phy_power(int on)
void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
{
omap_usb_dpll_lock(phy_regs);
-
usb3_phy_partial_powerup(phy_regs);
/*
* Give enough time for the PHY to partially power-up before
@@ -126,7 +125,6 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
* team.
*/
mdelay(100);
- usb3_phy_power(1);
}
static void omap_enable_usb3_phy(struct omap_xhci *omap)
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 14a6781..00b563f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -39,8 +39,10 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+obj-$(CONFIG_VIDEO_X86) += x86_fb.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c
index 618f5d9..5748951 100644
--- a/drivers/video/ati_radeon_fb.c
+++ b/drivers/video/ati_radeon_fb.c
@@ -19,6 +19,7 @@
#include <common.h>
#include <command.h>
+#include <bios_emul.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
@@ -544,7 +545,6 @@ void radeon_setmode_9200(int vesa_idx, int bpp)
}
#include "../bios_emulator/include/biosemu.h"
-extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
int radeon_probe(struct radeonfb_info *rinfo)
{
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
new file mode 100644
index 0000000..d241397
--- /dev/null
+++ b/drivers/video/sunxi_display.c
@@ -0,0 +1,451 @@
+/*
+ * Display driver for Allwinner SoCs.
+ *
+ * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/display.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <linux/fb.h>
+#include <video_fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sunxi_display {
+ GraphicDevice graphic_device;
+ bool enabled;
+} sunxi_display;
+
+static int sunxi_hdmi_hpd_detect(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+
+ /* Set pll3 to 300MHz */
+ clock_set_pll3(300000000);
+
+ /* Set hdmi parent to pll3 */
+ clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
+ CCM_HDMI_CTRL_PLL3);
+
+ /* Set ahb gating to pass */
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+#endif
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
+
+ /* Clock on */
+ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+
+ writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
+ writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
+
+ udelay(1000);
+
+ if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
+ return 1;
+
+ /* No need to keep these running */
+ clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
+ clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+ clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
+#ifdef CONFIG_MACH_SUN6I
+ clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+#endif
+ clock_set_pll3(0);
+
+ return 0;
+}
+
+/*
+ * This is the entity that mixes and matches the different layers and inputs.
+ * Allwinner calls it the back-end, but i like composer better.
+ */
+static void sunxi_composer_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+ int i;
+
+#ifdef CONFIG_MACH_SUN6I
+ /* Reset off */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
+#endif
+
+ /* Clocks on */
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
+ setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
+ clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
+
+ /* Engine bug, clear registers after reset */
+ for (i = 0x0800; i < 0x1000; i += 4)
+ writel(0, SUNXI_DE_BE0_BASE + i);
+
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
+}
+
+static void sunxi_composer_mode_set(struct fb_videomode *mode,
+ unsigned int address)
+{
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+
+ writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
+ &de_be->disp_size);
+ writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
+ &de_be->layer0_size);
+ writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
+ writel(address << 3, &de_be->layer0_addr_low32b);
+ writel(address >> 29, &de_be->layer0_addr_high4b);
+ writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
+
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
+}
+
+/*
+ * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
+ */
+static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int value, n, m, diff;
+ int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
+ int best_double = 0;
+
+ /*
+ * Find the lowest divider resulting in a matching clock, if there
+ * is no match, pick the closest lower clock, as monitors tend to
+ * not sync to higher frequencies.
+ */
+ for (m = 15; m > 0; m--) {
+ n = (m * dotclock) / 3000;
+
+ if ((n >= 9) && (n <= 127)) {
+ value = (3000 * n) / m;
+ diff = dotclock - value;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_m = m;
+ best_n = n;
+ best_double = 0;
+ }
+ }
+
+ /* These are just duplicates */
+ if (!(m & 1))
+ continue;
+
+ n = (m * dotclock) / 6000;
+ if ((n >= 9) && (n <= 127)) {
+ value = (6000 * n) / m;
+ diff = dotclock - value;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_m = m;
+ best_n = n;
+ best_double = 1;
+ }
+ }
+ }
+
+ debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
+ dotclock, (best_double + 1) * 3000 * best_n / best_m,
+ best_double + 1, best_n, best_m);
+
+ clock_set_pll3(best_n * 3000000);
+
+ writel(CCM_LCD_CH1_CTRL_GATE |
+ (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
+ CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
+
+ *clk_div = best_m;
+ *clk_double = best_double;
+}
+
+static void sunxi_lcdc_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+
+ /* Reset off */
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
+#else
+ setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
+#endif
+
+ /* Clock on */
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
+
+ /* Init lcdc */
+ writel(0, &lcdc->ctrl); /* Disable tcon */
+ writel(0, &lcdc->int0); /* Disable all interrupts */
+
+ /* Disable tcon0 dot clock */
+ clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
+
+ /* Set all io lines to tristate */
+ writel(0xffffffff, &lcdc->tcon0_io_tristate);
+ writel(0xffffffff, &lcdc->tcon1_io_tristate);
+}
+
+static void sunxi_lcdc_mode_set(struct fb_videomode *mode,
+ int *clk_div, int *clk_double)
+{
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+ int bp, total;
+
+ /* Use tcon1 */
+ clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
+ SUNXI_LCDC_CTRL_IO_MAP_TCON1);
+
+ /* Enabled, 0x1e start delay */
+ writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
+ SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
+
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon1_timing_source);
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon1_timing_scale);
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon1_timing_out);
+
+ bp = mode->hsync_len + mode->left_margin;
+ total = mode->xres + mode->right_margin + bp;
+ writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
+ SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
+
+ bp = mode->vsync_len + mode->upper_margin;
+ total = mode->yres + mode->lower_margin + bp;
+ writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
+ SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
+
+ writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
+ &lcdc->tcon1_timing_sync);
+
+ sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
+}
+
+#ifdef CONFIG_MACH_SUN6I
+static void sunxi_drc_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* On sun6i the drc must be clocked even when in pass-through mode */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
+ clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
+}
+#endif
+
+static void sunxi_hdmi_mode_set(struct fb_videomode *mode,
+ int clk_div, int clk_double)
+{
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ int x, y;
+
+ /* Write clear interrupt status bits */
+ writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
+
+ /* Init various registers, select pll3 as clock source */
+ writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
+ writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
+ writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
+ writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
+ writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
+
+ /* Setup clk div and doubler */
+ clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
+ SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
+ if (!clk_double)
+ setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
+
+ /* Setup timing registers */
+ writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
+ &hdmi->video_size);
+
+ x = mode->hsync_len + mode->left_margin;
+ y = mode->vsync_len + mode->upper_margin;
+ writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
+
+ x = mode->right_margin;
+ y = mode->lower_margin;
+ writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
+
+ x = mode->hsync_len;
+ y = mode->vsync_len;
+ writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
+
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
+}
+
+static void sunxi_engines_init(void)
+{
+ sunxi_composer_init();
+ sunxi_lcdc_init();
+#ifdef CONFIG_MACH_SUN6I
+ sunxi_drc_init();
+#endif
+}
+
+static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address)
+{
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ int clk_div, clk_double;
+ int retries = 3;
+
+retry:
+ clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
+ clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
+ clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
+
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
+ sunxi_hdmi_mode_set(mode, clk_div, clk_double);
+
+ setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
+
+ udelay(1000000 / mode->refresh + 500);
+
+ setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
+
+ udelay(1000000 / mode->refresh + 500);
+
+ setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
+
+ udelay(1000000 / mode->refresh + 500);
+
+ /*
+ * Sometimes the display pipeline does not sync up properly, if
+ * this happens the hdmi fifo underrun or overrun bits are set.
+ */
+ if (readl(&hdmi->irq) &
+ (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
+ if (retries--)
+ goto retry;
+ printf("HDMI fifo under or overrun\n");
+ }
+}
+
+void *video_hw_init(void)
+{
+ static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
+ /*
+ * Vesa standard 1024x768@60
+ * 65.0 1024 1048 1184 1344 768 771 777 806 -hsync -vsync
+ */
+ struct fb_videomode mode = {
+ .name = "1024x768",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 65000,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = 0,
+ .vmode = 0,
+ .flag = 0,
+ };
+ int ret;
+
+ memset(&sunxi_display, 0, sizeof(struct sunxi_display));
+
+ printf("Reserved %dkB of RAM for Framebuffer.\n",
+ CONFIG_SUNXI_FB_SIZE >> 10);
+ gd->fb_base = gd->ram_top;
+
+ ret = sunxi_hdmi_hpd_detect();
+ if (!ret)
+ return NULL;
+
+ printf("HDMI connected.\n");
+ sunxi_display.enabled = true;
+
+ printf("Setting up a %s console.\n", mode.name);
+ sunxi_engines_init();
+ sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
+
+ /*
+ * These are the only members of this structure that are used. All the
+ * others are driver specific. There is nothing to decribe pitch or
+ * stride, but we are lucky with our hw.
+ */
+ graphic_device->frameAdrs = gd->fb_base;
+ graphic_device->gdfIndex = GDF_32BIT_X888RGB;
+ graphic_device->gdfBytesPP = 4;
+ graphic_device->winSizeX = mode.xres;
+ graphic_device->winSizeY = mode.yres;
+
+ return graphic_device;
+}
+
+/*
+ * Simplefb support.
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
+int sunxi_simplefb_setup(void *blob)
+{
+ static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
+ int offset, ret;
+
+ if (!sunxi_display.enabled)
+ return 0;
+
+ /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
+ offset = fdt_node_offset_by_compatible(blob, -1,
+ "allwinner,simple-framebuffer");
+ while (offset >= 0) {
+ ret = fdt_find_string(blob, offset, "allwinner,pipeline",
+ "de_be0-lcd0-hdmi");
+ if (ret == 0)
+ break;
+ offset = fdt_node_offset_by_compatible(blob, offset,
+ "allwinner,simple-framebuffer");
+ }
+ if (offset < 0) {
+ eprintf("Cannot setup simplefb: node not found\n");
+ return 0; /* Keep older kernels working */
+ }
+
+ ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
+ graphic_device->winSizeX, graphic_device->winSizeY,
+ graphic_device->winSizeX * graphic_device->gdfBytesPP,
+ "x8r8g8b8");
+ if (ret)
+ eprintf("Cannot setup simplefb: Error setting properties\n");
+
+ return ret;
+}
+#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */
diff --git a/drivers/video/x86_fb.c b/drivers/video/x86_fb.c
new file mode 100644
index 0000000..8743a8c
--- /dev/null
+++ b/drivers/video/x86_fb.c
@@ -0,0 +1,37 @@
+/*
+ *
+ * Vesa frame buffer driver for x86
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <video_fb.h>
+#include <vbe.h>
+#include "videomodes.h"
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+
+void *video_hw_init(void)
+{
+ GraphicDevice *gdev = &ctfb;
+ int bits_per_pixel;
+
+ printf("Video: ");
+ if (vbe_get_video_info(gdev)) {
+ printf("No video mode configured\n");
+ return NULL;
+ }
+
+ bits_per_pixel = gdev->gdfBytesPP * 8;
+ sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+ bits_per_pixel);
+ printf("%s\n", gdev->modeIdent);
+
+ return (void *)gdev;
+}
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 943b5bc..258b937 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -25,6 +25,7 @@
#include <ext_common.h>
#include <ext4fs.h>
#include "ext4_common.h"
+#include <div64.h>
int ext4fs_symlinknest;
struct ext_filesystem ext_fs;
@@ -67,11 +68,11 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
if (len > filesize)
len = filesize;
- blockcnt = ((len + pos) + blocksize - 1) / blocksize;
+ blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
- for (i = pos / blocksize; i < blockcnt; i++) {
+ for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
lbaint_t blknr;
- int blockoff = pos % blocksize;
+ int blockoff = pos - (blocksize * i);
int blockend = blocksize;
int skipfirst = 0;
blknr = read_allocated_block(&(node->inode), i);
@@ -82,7 +83,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
/* Last block. */
if (i == blockcnt - 1) {
- blockend = (len + pos) % blocksize;
+ blockend = (len + pos) - (blocksize * i);
/* The last portion is exactly blocksize. */
if (!blockend)
@@ -90,7 +91,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
}
/* First block. */
- if (i == pos / blocksize) {
+ if (i == lldiv(pos, blocksize)) {
skipfirst = blockoff;
blockend -= skipfirst;
}
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 88dd495..98b88ad 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -13,6 +13,8 @@
#include <asm/byteorder.h>
#include <part.h>
#include <linux/ctype.h>
+#include <div64.h>
+#include <linux/math64.h>
#include "fat.c"
static void uppercase(char *str, int len)
@@ -770,7 +772,7 @@ static void fill_dentry(fsdata *mydata, dir_entry *dentptr,
*/
static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
{
- __u32 startsect, sect_num;
+ __u32 startsect, sect_num, offset;
if (clustnum > 0) {
startsect = mydata->data_begin +
@@ -779,13 +781,13 @@ static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
startsect = mydata->rootdir_sect;
}
- sect_num = size / mydata->sect_size;
- if (size % mydata->sect_size)
+ sect_num = div_u64_rem(size, mydata->sect_size, &offset);
+
+ if (offset != 0)
sect_num++;
if (startsect + sect_num > cur_part_info.start + total_sector)
return -1;
-
return 0;
}
diff --git a/fs/fs.c b/fs/fs.c
index 3da7860..ddd751c 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -23,6 +23,8 @@
#include <fs.h>
#include <sandboxfs.h>
#include <asm/io.h>
+#include <div64.h>
+#include <linux/math64.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -399,7 +401,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
puts(" (");
- print_size(len_read / time * 1000, "/s");
+ print_size(div_u64(len_read, time) * 1000, "/s");
puts(")");
}
puts("\n");
@@ -469,7 +471,7 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
printf("%llu bytes written in %lu ms", len, time);
if (time > 0) {
puts(" (");
- print_size(len / time * 1000, "/s");
+ print_size(div_u64(len, time) * 1000, "/s");
puts(")");
}
puts("\n");
diff --git a/include/bios_emul.h b/include/bios_emul.h
new file mode 100644
index 0000000..3643b82
--- /dev/null
+++ b/include/bios_emul.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 1996-1999 SciTech Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _BIOS_EMUL_H
+#define _BIOS_EMUL_H
+
+/* Include the register header directly here */
+#include "../drivers/bios_emulator/include/x86emu/regs.h"
+#include <pci.h>
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details for the BIOS emulator system
+environment as used by the X86 emulator library.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+vgaInfo - VGA BIOS information structure
+biosmem_base - Base of the BIOS image
+biosmem_limit - Limit of the BIOS image
+busmem_base - Base of the VGA bus memory
+****************************************************************************/
+typedef struct {
+ int function;
+ int device;
+ int bus;
+ u32 VendorID;
+ u32 DeviceID;
+ pci_dev_t pcidev;
+ void *BIOSImage;
+ u32 BIOSImageLen;
+ u8 LowMem[1536];
+} BE_VGAInfo;
+
+struct vbe_mode_info;
+
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
+
+/* Run a BIOS ROM natively (only supported on x86 machines) */
+void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+
+/**
+ * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS
+ *
+ * This installs an interrupt handler that the BIOS will call when needed.
+ *
+ * @intnum: Interrupt number to install a handler for
+ * @int_handler_func: Function to call to handle interrupt
+ */
+void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
+
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+
+#endif
diff --git a/include/common.h b/include/common.h
index f1ab2cf..46f07fe 100644
--- a/include/common.h
+++ b/include/common.h
@@ -73,6 +73,9 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_ARM
#define asmlinkage /* nothing */
#endif
+#ifdef CONFIG_X86
+#define asmlinkage __attribute__((regparm(0)))
+#endif
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
@@ -442,11 +445,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int);
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
-#ifdef CONFIG_HERMES
-/* $(BOARD)/hermes.c */
-void hermes_start_lxt980 (int speed);
-#endif
-
#ifdef CONFIG_EVB64260
void evb64260_init(void);
void debug_led(int, int);
diff --git a/include/commproc.h b/include/commproc.h
index d78ab00..6875c4c 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -535,34 +535,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
-/*** HERMES-PRO ******************************************************/
-
-/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
-
-#ifdef CONFIG_HERMES
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_HERMES */
-
/*** IP860 **********************************************************/
#if defined(CONFIG_IP860)
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index dc1a9bc..9e8e319 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_PCI */
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
-#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
+#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
+#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
@@ -731,6 +731,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
+#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+
/*
* Environment
*/
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 5d11278..ecb3d7b 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -12,6 +12,8 @@
#define __CONFIG_H
#define CONFIG_PHYS_64BIT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_C29XPCIE
#define CONFIG_PPC_C29X
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 695e47b..832c10f 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -387,6 +387,11 @@ extern int board_pci_host_broken(void);
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1d1f4c0..8ed0f7c 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -685,6 +685,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_NETDEV "eth1"
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index d378dbd..cd6a39c 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -14,6 +14,8 @@
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_P1010
#define CONFIG_E500 /* BOOKE e500 family */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index bd08090..4371110 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -11,6 +11,9 @@
#include "../board/freescale/common/ics307_clk.h"
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index ba3da06..2ce186e 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -10,6 +10,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
@@ -374,6 +377,49 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off $ubootaddr +$filesize; " \
+ "erase $ubootaddr +$filesize; " \
+ "cp.b $loadaddr $ubootaddr $filesize; " \
+ "protect on $ubootaddr +$filesize; " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=p1023rdb.dtb\0" \
+ "othbootargs=ramdisk_size=600000\0" \
+ "bdev=sda1\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
#endif /* __CONFIG_H */
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index 371485f..e4a031a 100644
--- a/include/configs/P5040DS.h
+++ b/include/configs/P5040DS.h
@@ -17,6 +17,7 @@
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_PCIE3
+#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
new file mode 100644
index 0000000..78ed243
--- /dev/null
+++ b/include/configs/T102xQDS.h
@@ -0,0 +1,939 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T1024/T1023 QDS board configuration file
+ */
+
+#ifndef __T1024QDS_H
+#define __T1024QDS_H
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+/* PCIe Boot - Master */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#endif
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
+#endif
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/* PCIe Boot - Slave */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+/* Set 1M boot space for PCIe boot */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (256 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3
+#endif
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x51
+
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_BASE 0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH 0x06
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RST_FORCE_MEM 0x01
+
+#define CONFIG_SYS_CSPR3_EXT (0xf)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x8) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Video */
+#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
+#define I2C_MUX_PCA_ADDR 0x77
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_DIU 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH7 0xF
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR 0x38
+#define CONFIG_SYS_I2C_DVI_ADDR 0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCIe
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/*
+ *SATA
+ */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * SDHC
+ */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+
+#define CONFIG_QE
+#define CONFIG_U_QE
+/* Default address of microcode for the Linux FMan driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_QE_FW_ADDR 0x130000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
+#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
+#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC4"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.0"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);"\
+ "fff800000.flash:2m(uboot),9m(kernel),"\
+ "128k(dtb),96m(fs),-(user);spife110000.0:" \
+ "2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
+#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+#define __USB_PHY_TYPE utmi
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
+ "ramdiskfile=t1024qds/ramdisk.uboot\0" \
+ "fdtfile=t1024qds/t1024qds.dtb\0" \
+ "netdev=eth0\0" \
+ "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "fdtaddr=d00000\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __T1024QDS_H */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
new file mode 100644
index 0000000..6f1fcd6
--- /dev/null
+++ b/include/configs/T102xRDB.h
@@ -0,0 +1,896 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T1024/T1023 RDB board configuration file
+ */
+
+#ifndef __T1024RDB_H
+#define __T1024RDB_H
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+/* PCIe Boot - Master */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#endif
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
+#endif
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/* PCIe Boot - Slave */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+/* Set 1M boot space for PCIe boot */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 66660000
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (256 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x51
+
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE 0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT (0xf)
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x8) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Video */
+#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
+#define I2C_MUX_PCA_ADDR 0x77
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT 0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS1337 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCIe
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#ifdef CONFIG_PPC_T1040
+#define CONFIG_PCIE4 /* PCIE controler 4 */
+#endif
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+/* controller 4, Base address 203000, to be removed */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
+#else
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
+#endif
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#else
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
+#endif
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * SDHC
+ */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+
+#define CONFIG_QE
+#define CONFIG_U_QE
+/* Default address of microcode for the Linux FMan driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_QE_FW_ADDR 0x130000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_REALTEK
+#define RGMII_PHY1_ADDR 0x2
+#define RGMII_PHY2_ADDR 0x6
+#define FM1_10GEC1_PHY_ADDR 0x1
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC4"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.1"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
+ "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
+ "1m(uboot),5m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
+#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+#define __USB_PHY_TYPE utmi
+
+#ifdef CONFIG_PPC_T1024
+#define CONFIG_BOARDNAME "t1024rdb"
+#else
+#define CONFIG_BOARDNAME "t1023rdb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+ "bank_intlv=cs0_cs1\0" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
+ "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
+ __stringify(CONFIG_BOARDNAME) ".dtb\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
+ "netdev=eth0\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "fdtaddr=c00000\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __T1024RDB_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 2178f9d..6b396bb 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -28,6 +28,8 @@
*/
#define CONFIG_T1040QDS
#define CONFIG_PHYS_64BIT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
@@ -176,8 +178,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_SPD
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3
-#define CONFIG_FSL_DDR_INTERACTIVE
#endif
+#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
@@ -768,8 +770,7 @@ unsigned long get_board_ddr_clk(void);
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1;" \
+ "hwconfig=fsl_ddr:bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 216f34f..1eb1371 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -12,6 +12,11 @@
*/
#define CONFIG_T104xRDB
#define CONFIG_PHYS_64BIT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_E500 /* BOOKE e500 family */
+#include <asm/config_mpc85xx.h>
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -93,7 +98,6 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -386,6 +390,12 @@
#define CONFIG_SYS_RAMBOOT
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
+#if defined(CONFIG_NAND)
+#define CONFIG_A008044_WORKAROUND
+#endif
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2f381e7..d1fe78e 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -234,7 +234,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
-#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
@@ -494,6 +494,23 @@ unsigned long get_board_ddr_clk(void);
#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T208xQDS */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
/*
* RapidIO
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index e639e1d..db03993 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -533,7 +533,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
@@ -690,6 +690,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* Hash command with SHA acceleration supported in hardware */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 120fdc6..d23d2c4 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -418,8 +418,6 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xfc000000
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 5c8223c..58eac31 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -95,4 +95,23 @@
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+/* MMCIF */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_SH_MMCIF
+#define CONFIG_SH_MMCIF_ADDR 0xee200000
+#define CONFIG_SH_MMCIF_CLK 48000000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA 0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA 0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA 0x00000180
+/* SCIF2 */
+#define CONFIG_SMSTP7_ENA 0x00080000
+
#endif /* __ALT_H */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 0fbfa3f..09ee10c 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -304,7 +304,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 8719f76..190ef0e 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -313,7 +313,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index aa6b631..81e8a7c 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -9,6 +9,9 @@
#ifndef __CONFIG_ARNDALE_H
#define __CONFIG_ARNDALE_H
+#define EXYNOS_FDTFILE_SETTING \
+ "fdtfile=exynos5250-arndale.dtb\0"
+
#include "exynos5250-common.h"
/* SD/MMC configuration */
@@ -17,8 +20,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CMD_EXT2
-
/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h
new file mode 100644
index 0000000..cc36330
--- /dev/null
+++ b/include/configs/beagle_x15.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated.
+ * Felipe Balbi <balbi@ti.com>
+ *
+ * Configuration settings for the TI Beagle x15 board.
+ * See ti_omap5_common.h for omap5 common settings.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BEAGLE_X15_H
+#define __CONFIG_BEAGLE_X15_H
+
+#define CONFIG_AM57XX
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+
+#define CONFIG_CMD_SAVEENV
+
+#define CONSOLEDEV "ttyO2"
+#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
+#define CONFIG_PHY_GIGE /* per-board part of CPSW */
+#define CONFIG_PHYLIB
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB3PHY1_HOST
+
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#endif /* __CONFIG_BEAGLE_X5_H */
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 8caeca6..645b31c 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -21,7 +21,6 @@
#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_X86_RESET_VECTOR
@@ -40,20 +39,9 @@
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-/*
- * These common x86 features are not yet supported, but are added in
- * follow-on patches in this series. Add undefs here to avoid every patch
- * having to put things back into x86-common.h
- */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-#undef CONFIG_ICH_SPI
-#undef CONFIG_SPI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_SF
-#undef CONFIG_USB_EHCI
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_SCSI
+#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
+#define CONFIG_VIDEO_X86
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
@@ -67,6 +55,18 @@
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xefff
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_BIOSEMU
+#define VIDEO_IO_OFFSET 0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_CROS_EC
+#define CONFIG_CROS_EC_LPC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_ARCH_EARLY_INIT_R
+
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 1919cde..ccd9b88 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -321,7 +321,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 641ab48..92ce1e1 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -16,7 +16,6 @@
#include <configs/ti_omap5_common.h>
-#undef CONFIG_MISC_INIT_R
#undef CONFIG_SPL_OS_BOOT
/* Enable Generic board */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index e0bf3dc..8a7447d 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -15,6 +15,9 @@
#define CONFIG_DBAU1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_SOC_AU1000 1
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index ca62461..930b08e 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -299,7 +299,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 2eaabde..174a711 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -50,6 +50,7 @@
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index b258cb9..1f3ee55 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -30,9 +30,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-/* Enable fdt support */
-#define CONFIG_OF_LIBFDT
-
/* Keep L2 Cache Disabled */
#define CONFIG_CMD_CACHE
@@ -42,7 +39,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_ENV_OVERWRITE
/* Size of malloc() pool before and after relocation */
@@ -61,7 +57,6 @@
#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
/* PWM */
@@ -71,22 +66,16 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_PART
#define CONFIG_PARTITION_UUIDS
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
@@ -96,4 +85,6 @@
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
+#include <config_distro_defaults.h>
+
#endif /* __CONFIG_H */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index ba591e7..8f9b780 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -47,17 +47,6 @@
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CONSOLE_MUX
-#define EXYNOS_DEVICE_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- EXYNOS_DEVICE_SETTINGS
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NET
#define CONFIG_CMD_HASH
/* Thermal Management Unit */
@@ -174,12 +163,6 @@
#define CONFIG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
-/* Enable PXE Support */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#endif
-
/* SHA hashing */
#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
@@ -189,8 +172,6 @@
/* Enable Time Command */
#define CONFIG_CMD_TIME
-#define CONFIG_CMD_BOOTZ
-
#define CONFIG_CMD_GPIO
/* USB boot mode */
@@ -203,4 +184,41 @@
#define CONFIG_FIT
#define CONFIG_FIT_BEST_MATCH
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+/* 2GB RAM, bootm size of 256M, load scripts after that */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "ramdisk_addr_r=0x43300000\0" \
+ "scriptaddr=0x50000000\0" \
+ "pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS \
+ EXYNOS_FDTFILE_SETTING \
+ MEM_LAYOUT_ENV_SETTINGS \
+ BOOTENV
+
#endif /* __CONFIG_EXYNOS5_COMMON_H */
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index 66547fa..9cef0b0 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h
@@ -9,6 +9,13 @@
#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
#define __CONFIG_EXYNOS5_DT_COMMON_H
+/* Console configuration */
+#undef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial,cros-ec-keyb\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
#include "exynos5-common.h"
/* PMIC */
@@ -22,14 +29,4 @@
#define CONFIG_CMD_CROS_EC
#define CONFIG_KEYBOARD
-/* Console configuration */
-#undef EXYNOS_DEVICE_SETTINGS
-#define EXYNOS_DEVICE_SETTINGS \
- "stdin=serial,cros-ec-keyb\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- EXYNOS_DEVICE_SETTINGS
-
#endif
diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h
index 713614f..a0107e8 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -29,8 +29,6 @@
#define CONFIG_SPL_TEXT_BASE 0x02023400
-#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
-
#define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index b0f940c..ef6e155 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -10,6 +10,8 @@
#define __CONFIG_EXYNOS5420_H
#define CONFIG_EXYNOS5420
+/* A variant of Exynos5420 (Exynos5 Family) */
+#define CONFIG_EXYNOS5800
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
@@ -38,14 +40,13 @@
#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
-#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
+#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \
+ "exynos5420-peach-pit exynos5420-smdk5420"
#define CONFIG_MAX_I2C_NUM 11
#define CONFIG_BOARD_REV_GPIO_COUNT 2
-#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
-
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
/*
@@ -54,10 +55,6 @@
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
-/* DRAM Memory Banks */
-#define CONFIG_NR_DRAM_BANKS 7
-#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
-
/* Miscellaneous configurable options */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
diff --git a/include/configs/gose.h b/include/configs/gose.h
index c347e45..44c8a30 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -91,4 +91,14 @@
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA 0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA 0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA 0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA 0x00200000
+
#endif /* __GOSE_H */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
deleted file mode 100644
index 736ffb61..0000000
--- a/include/configs/hermes.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
-#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x000000C0
- */
-#define CONFIG_SYS_SIUMCR 0
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => 0x00B0D0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* +0x0282 => 0x03800000 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CONFIG_SYS_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 4 MB of Flash */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
- OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 8 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR1/OR1 - SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
- */
-#define HPRO2_BASE 0xE0000000
-#define HPRO2_OR_AM 0xFFFF8000
-#define HPRO2_TIMING 0x00000934
-
-#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
-#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: not used
- * BR4/OR4: not used
- * BR5/OR5: not used
- * BR6/OR6: not used
- * BR7/OR7: not used
- */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-#endif /* __CONFIG_H */
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 5a5f940..1b9c277 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -28,7 +28,6 @@
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x10000
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
#define CONFIG_SPL_STACK 0x0091FFB8
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -46,7 +45,7 @@
#if defined(CONFIG_SPL_MMC_SUPPORT)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
#endif
diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h
index 69ba66a..14fd290 100644
--- a/include/configs/km82xx.h
+++ b/include/configs/km82xx.h
@@ -207,9 +207,6 @@
""
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
#define CONFIG_SYS_MONITOR_LEN (768 << 10)
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index bb98302..c14889c 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -92,4 +92,15 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA 0x00400000
+/* MSIF*/
+#define CONFIG_SMSTP2_ENA 0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA 0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA 0x00200000
+
#endif /* __KOELSCH_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 37be38f..291267f 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -93,4 +93,23 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SH_MMCIF
+#define CONFIG_SH_MMCIF_ADDR 0xEE220000
+#define CONFIG_SH_MMCIF_CLK 97500000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA 0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA 0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA 0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA 0x00200000
+
#endif /* __LAGER_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index b19a60f..48e10ec 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -70,6 +70,11 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_HAS_SERDES
#define CONFIG_FSL_CAAM /* Enable CAAM */
+
+#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#define CONFIG_U_QE
+#endif
+
/*
* IFC Definitions
*/
@@ -110,6 +115,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
@@ -274,6 +280,23 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_GENERIC_MMC
/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+/*
* eTSEC
*/
#define CONFIG_TSEC_ENET
@@ -332,6 +355,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_BOOTDELAY 3
+#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"fdt_high=0xcfffffff\0" \
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index e98e102..3eac7ee 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -50,6 +50,10 @@
#define CONFIG_FSL_CAAM /* Enable CAAM */
+#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#define CONFIG_U_QE
+#endif
+
/*
* IFC Definitions
*/
@@ -95,6 +99,7 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
/* CPLD */
@@ -156,6 +161,17 @@
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+/* EEPROM */
+#ifndef CONFIG_SD_BOOT
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#endif
+
/*
* MMC
*/
@@ -274,6 +290,8 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+
/*
* Environment
*/
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 58e7295..d43db52 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -671,8 +671,6 @@
#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index b775ebd..26eb220 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -369,7 +369,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* NAND boot config */
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index 7343c94..df2ecc1 100644
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -206,10 +206,6 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
#define CONFIG_ENV_IS_IN_FLASH
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index b928af8..807e96b 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -198,6 +198,19 @@
#define CONFIG_CMD_GPIO
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
/*
* Supported Odroid boards: X3, U3
* TODO: Add Odroid X support
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 27bf89c..8bdc08f 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -75,7 +75,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* Partition tables */
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index 2daf13c..1185f42 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -87,7 +87,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif /* __OMAP3_EVM_QUICK_MMC_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index e8dc462..e07795f 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -23,6 +23,7 @@
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_BAUDRATE 115200
+#define CONFIG_MISC_INIT_R
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index da9d6a1..8f1e256 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -56,6 +56,10 @@
#undef CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
@@ -63,7 +67,36 @@
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SPL_TEXT_BASE 0x02021410
-#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x40007000\0" \
+ "rdaddr=0x48000000\0" \
+ "kerneladdr=0x40007000\0" \
+ "ramdiskaddr=0x48000000\0" \
+ "console=ttySAC2,115200n8\0" \
+ "mmcdev=0\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0"
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "fi; " \
+ "fi;" \
+ "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
#define CONFIG_IDENT_STRING " for ORIGEN"
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 681bc92..9864c15 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -10,6 +10,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_P1025
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 1c04a58..61e6af3 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -15,6 +15,9 @@
#define CONFIG_PB1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_PB1000
#define CONFIG_SOC_AU1000 1
#else
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
new file mode 100644
index 0000000..8a82402
--- /dev/null
+++ b/include/configs/peach-pi.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_PEACH_PI_H
+#define __CONFIG_PEACH_PI_H
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE 0x12D30000
+#define FLASH_SIZE (0x4 << 20)
+#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
+
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-dt-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
+
+#define CONFIG_SYS_PROMPT "Peach-Pi # "
+#define CONFIG_IDENT_STRING " for Peach-Pi"
+
+#define CONFIG_VIDEO_PARADE
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_BPP LCD_COLOR16
+#endif
+
+#define CONFIG_POWER_TPS65090_EC
+#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
+#define CONFIG_DM_CROS_EC
+
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 7
+#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+
+#endif /* __CONFIG_PEACH_PI_H */
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 91bd37d..ad5db57 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -23,8 +23,8 @@
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
-#define CONFIG_SYS_PROMPT "Peach # "
-#define CONFIG_IDENT_STRING " for Peach"
+#define CONFIG_SYS_PROMPT "Peach-Pit # "
+#define CONFIG_IDENT_STRING " for Peach-Pit"
#define CONFIG_VIDEO_PARADE
@@ -43,4 +43,8 @@
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 4
+#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+
#endif /* __CONFIG_PEACH_PIT_H */
diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h
deleted file mode 100644
index 73a95e6..0000000
--- a/include/configs/ph1_ld4.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h
deleted file mode 100644
index fc5132d..0000000
--- a/include/configs/ph1_pro4.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 2
-
-#define CONFIG_UNIPHIER_SMP
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x20000000
-#define CONFIG_SDRAM1_BASE 0xa0000000
-#define CONFIG_SDRAM1_SIZE 0x20000000
-
-#define CONFIG_SPL_TEXT_BASE 0x100000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h
deleted file mode 100644
index e2f1102..0000000
--- a/include/configs/ph1_sld8.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/* #define CONFIG_DDR_STANDARD */
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index d75d562..946b2c8 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -150,4 +150,8 @@
#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FIT
+#endif
+
#endif /* ! __CONFIG_PXM2_H */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 98ed8bc..1548d3e 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -13,6 +13,9 @@
#define __CONFIG_H
#define CONFIG_QEMU_MIPS
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index e8f5a4c..61cafad 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -13,6 +13,9 @@
#define __CONFIG_H
#define CONFIG_QEMU_MIPS
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 46c7526..c33f1cb 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -28,6 +28,9 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
@@ -36,6 +39,7 @@
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/rpi_b.h b/include/configs/rpi.h
index 41e975f..4d5426e 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi.h
@@ -105,15 +105,15 @@
/* Environment */
#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_PREBOOT \
- "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
- "env import -t -r ${loadaddr} ${filesize}; " \
- "fi"
/* Shell */
#define CONFIG_SYS_MAXARGS 8
@@ -138,7 +138,6 @@
/* Some things don't make sense on this HW or yet */
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SAVEENV
/* Environment */
#define ENV_DEVICE_SETTINGS \
@@ -175,7 +174,6 @@
"pxefile_addr_r=0x00100000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
- "fdtfile=bcm2835-rpi-b.dtb\0" \
"ramdisk_addr_r=0x02100000\0" \
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 6bddede..0067ea4 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -154,4 +154,8 @@
#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FIT
+#endif
+
#endif /* ! __CONFIG_RUT_H */
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 5b77db2..d5588b1 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -230,7 +230,7 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index dfbf3cb..f2849d7 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -276,7 +276,7 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 0d5dba1..21e13e5 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -148,7 +148,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index b83c15f..71eb81c 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -23,6 +23,8 @@
#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index fd2d482..5c9a3c0 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -23,4 +23,8 @@
#define CONFIG_IDENT_STRING " for SMDK5420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 7
+#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+
#endif /* __CONFIG_SMDK5420_H */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
new file mode 100644
index 0000000..fd9bd63
--- /dev/null
+++ b/include/configs/stv0991.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_STV0991_H
+#define __CONFIG_STV0991_H
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_CORTEX_R4
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_NO_FLASH
+
+/* ram memory-related information */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x00000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define PHYS_SDRAM_1_SIZE 0x00198000
+
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR \
+ (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
+#define CONFIG_SYS_MALLOC_F_LEN 0x2000
+
+#define CONFIG_DM
+/* serial port (PL011) configuration */
+#define CONFIG_BAUDRATE 115200
+#ifdef CONFIG_DM
+#define CONFIG_DM_SERIAL
+#define CONFIG_PL01X_SERIAL
+#else
+#define CONFIG_SYS_SERIAL0 0x80406000
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
+#define CONFIG_PL011_CLOCK (2700 * 1000)
+#endif
+
+/* user interface */
+#define CONFIG_SYS_PROMPT "STV0991> "
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* MISC */
+#define CONFIG_SYS_LOAD_ADDR 0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* U-boot Load Address */
+#define CONFIG_SYS_TEXT_BASE 0x00010000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* GMAC related configs */
+
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+#define CONFIG_CMD_NET
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_PHY_MICREL
+
+/* Command support defines */
+#define CONFIG_CMD_PING
+#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+
+#include "config_cmd_default.h"
+#undef CONFIG_CMD_SAVEENV
+
+#define CONFIG_SYS_MEMTEST_START 0x0000
+#define CONFIG_SYS_MEMTEST_END 1024*1024
+#define CONFIG_CMD_MEMTEST
+
+/* Misc configuration */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "go 0x40040000"
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 3629587..f6b1b3e 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -23,7 +23,6 @@
#endif
#define CONFIG_ARMV7_PSCI 1
-#define CONFIG_ARMV7_PSCI_NR_CPUS 2
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_SYS_CLK_FREQ 24000000
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ce038ed..3f890b2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -197,6 +197,36 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_CMD_GPIO
+#ifdef CONFIG_VIDEO
+/*
+ * The amount of RAM that is reserved for the FB. This will not show up as
+ * RAM to the kernel, but will be reclaimed by a KMS driver in future.
+ */
+#define CONFIG_SUNXI_FB_SIZE (8 << 20)
+
+/* Do we want to initialize a simple FB? */
+#define CONFIG_VIDEO_DT_SIMPLEFB
+
+#define CONFIG_VIDEO_SUNXI
+
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+
+/* allow both serial and cfb console. */
+#define CONFIG_CONSOLE_MUX
+/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#define CONFIG_SYS_MEM_TOP_HIDE ((CONFIG_SUNXI_FB_SIZE + 0xFFF) & ~0xFFF)
+
+/* To be able to hook simplefb into dt */
+#ifdef CONFIG_VIDEO_DT_SIMPLEFB
+#define CONFIG_OF_BOARD_SETUP
+#endif
+
+#endif /* CONFIG_VIDEO */
+
/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_MII /* MII PHY management */
@@ -217,6 +247,13 @@
#define CONFIG_USB_STORAGE
#endif
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_PREBOOT
+#define CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+#endif
+
#if !defined CONFIG_ENV_IS_IN_MMC && \
!defined CONFIG_ENV_IS_IN_NAND && \
!defined CONFIG_ENV_IS_IN_FAT && \
@@ -225,6 +262,7 @@
#endif
#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
@@ -266,7 +304,31 @@
#include <config_distro_bootcmd.h>
+#ifdef CONFIG_USB_KEYBOARD
+#define CONSOLE_STDIN_SETTINGS \
+ "preboot=usb start\0" \
+ "stdin=serial,usbkbd\0"
+#else
+#define CONSOLE_STDIN_SETTINGS \
+ "stdin=serial\0"
+#endif
+
+#ifdef CONFIG_VIDEO
+#define CONSOLE_STDOUT_SETTINGS \
+ "stdout=serial,vga\0" \
+ "stderr=serial,vga\0"
+#else
+#define CONSOLE_STDOUT_SETTINGS \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#define CONSOLE_ENV_SETTINGS \
+ CONSOLE_STDIN_SETTINGS \
+ CONSOLE_STDOUT_SETTINGS
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0,115200\0" \
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index a160329..7d2c0d2 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -304,7 +304,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 2fddef3..deb6bb2 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -178,7 +178,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index aeabb1b..87a4efc 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -144,7 +144,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index a8790c2..bc75172 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -233,7 +233,7 @@
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
/* FAT sd card locations. */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 3166392..c47651d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -19,7 +19,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_R
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
@@ -79,7 +78,7 @@
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
"mmcdev=0\0" \
- "mmcroot=/dev/mmcblk1p2 rw\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
@@ -118,6 +117,8 @@
"setenv fdtfile dra7-evm.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
+ "if test $board_name = beagle_x15; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 6e7a7fb..36621a5 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -349,7 +349,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier.h
index 7c4dba0..dd022fb 100644
--- a/include/configs/uniphier-common.h
+++ b/include/configs/uniphier.h
@@ -10,10 +10,37 @@
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) && \
- defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
-are defined. Select only one of them."
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x20000000
+#define CONFIG_SDRAM1_BASE 0xa0000000
+#define CONFIG_SDRAM1_SIZE 0x20000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_LD4)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x10000000
+#define CONFIG_SDRAM1_BASE 0x90000000
+#define CONFIG_SDRAM1_SIZE 0x10000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x10000000
+#define CONFIG_SDRAM1_BASE 0x90000000
+#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
/*
@@ -40,6 +67,13 @@ are defined. Select only one of them."
#define CONFIG_SYS_NS16550_REG_SIZE -2
#endif
+/* TODO: move to Kconfig and device tree */
+#if 0
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SMC911X
+
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT
@@ -58,6 +92,7 @@ are defined. Select only one of them."
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
@@ -87,17 +122,7 @@ are defined. Select only one of them."
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_BANKS_LIST {0x00000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES {0x02000000}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_BANKS_LIST {0x04000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES {0x04000000}
-#endif
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
@@ -112,7 +137,6 @@ are defined. Select only one of them."
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -143,15 +167,6 @@ are defined. Select only one of them."
*/
#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_NAND /* NAND flash suppport */
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
@@ -167,7 +182,6 @@ are defined. Select only one of them."
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* USB */
-#define CONFIG_CMD_USB
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
@@ -216,7 +230,6 @@ are defined. Select only one of them."
"image_offset=0x00080000\0" \
"image_size=0x00f00000\0" \
"verify=n\0" \
- "autostart=yes\0" \
"norboot=run add_default_bootargs;" \
"bootm $image_offset\0" \
"nandboot=run add_default_bootargs;" \
@@ -225,10 +238,6 @@ are defined. Select only one of them."
"add_default_bootargs=setenv bootargs $bootargs" \
" console=ttyS0,$baudrate\0" \
-/* FIT support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
@@ -248,6 +257,13 @@ are defined. Select only one of them."
#define CONFIG_SYS_TEXT_BASE 0x84000000
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_SPL_TEXT_BASE 0x00040000
+#endif
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_SPL_TEXT_BASE 0x00100000
+#endif
+
#define CONFIG_BOARD_POSTCLK_INIT
#ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 217ba2f..83e4163 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -25,6 +25,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index c39c568..87b4fff 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -265,7 +265,7 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
diff --git a/include/cortina.h b/include/cortina.h
new file mode 100644
index 0000000..6cadd28
--- /dev/null
+++ b/include/cortina.h
@@ -0,0 +1,75 @@
+/*
+ * Cortina PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _CORTINA_H_
+#define _CORTINA_H_
+
+#define VILLA_GLOBAL_CHIP_ID_LSB 0x000
+#define VILLA_GLOBAL_CHIP_ID_MSB 0x001
+#define VILLA_GLOBAL_BIST_CONTROL 0x002
+#define VILLA_GLOBAL_BIST_STATUS 0x003
+#define VILLA_GLOBAL_LINE_SOFT_RESET 0x007
+#define VILLA_GLOBAL_HOST_SOFT_RESET 0x008
+#define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A
+#define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B
+#define VILLA_GLOBAL_MSEQCLKCTRL 0x00E
+#define VILLA_MSEQ_OPTIONS 0x1D0
+#define VILLA_MSEQ_PC 0x1D3
+#define VILLA_MSEQ_BANKSELECT 0x1DF
+#define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB
+#define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E
+#define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403
+#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404
+#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405
+#define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369
+#define VILLA_MSEQ_ENABLE_MSB 0x194
+#define VILLA_MSEQ_SPARE21_LSB 0x226
+#define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0
+#define VILLA_MSEQ_SPARE12_MSB 0x215
+#define VILLA_MSEQ_SPARE2_LSB 0x200
+#define VILLA_MSEQ_SPARE7_LSB 0x20A
+#define VILLA_MSEQ_SPARE9_LSB 0x20E
+#define VILLA_MSEQ_SPARE3_LSB 0x202
+#define VILLA_MSEQ_SPARE3_MSB 0x203
+#define VILLA_MSEQ_SPARE8_LSB 0x20C
+#define VILLA_MSEQ_SPARE8_MSB 0x20D
+#define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2
+#define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4
+#define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6
+#define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8
+#define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA
+#define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC
+#define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0
+#define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE
+#define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2
+#define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2
+#define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360
+#define VILLA_MSEQ_POWER_DOWN_LSB 0x198
+#define VILLA_MSEQ_POWER_DOWN_MSB 0x199
+#define VILLA_MSEQ_CAL_RX_SLICER 0x1B8
+#define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365
+#define VILLA_MSEQ_COEF_INIT_SEL 0x1AE
+#define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A
+#define VILLA_MSEQ_SERDES_PARAM_LSB 0x195
+#define VILLA_MSEQ_SPARE25_LSB 0x22E
+#define VILLA_MSEQ_SPARE23_LSB 0x22A
+#define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA
+#define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030
+#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812
+#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813
+#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427
+#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428
+
+#define mseq_edc_bist_done (0x1<<0)
+#define mseq_edc_bist_fail (0x1<<8)
+
+struct cortina_reg_config {
+ unsigned short reg_addr;
+ unsigned short reg_value;
+};
+#endif
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 55cef94..1f19fe4 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -64,7 +64,20 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
#endif
-void ft_board_setup(void *blob, bd_t *bd);
+int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * Add board-specific data to the FDT before booting the OS.
+ *
+ * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space.
+ * This function is called if CONFIG_OF_BOARD_SETUP is defined
+ *
+ * @param blob FDT blob to update
+ * @param bd_t Pointer to board data
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int ft_board_setup(void *blob, bd_t *bd);
+
/*
* The keystone2 SOC requires all 32 bit aliased addresses to be converted
* to their 36 physical format. This has to happen after all fdt nodes
@@ -75,6 +88,18 @@ void ft_board_setup_ex(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
+/**
+ * Add system-specific data to the FDT before booting the OS.
+ *
+ * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space.
+ * This function is called if CONFIG_OF_SYSTEM_SETUP is defined
+ *
+ * @param blob FDT blob to update
+ * @param bd_t Pointer to board data
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int ft_system_setup(void *blob, bd_t *bd);
+
void set_working_fdt_addr(void *addr);
int fdt_shrink_to_minimum(void *blob);
int fdt_increase_size(void *fdt, int add_len);
@@ -147,6 +172,9 @@ void of_bus_default_count_cells(void *blob, int parentoffset,
int ft_verify_fdt(void *fdt);
int arch_fixup_memory_node(void *blob);
+int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
+ u32 height, u32 stride, const char *format);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#ifdef USE_HOSTCC
diff --git a/include/fdtdec.h b/include/fdtdec.h
index abfd678..d2b665c 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -120,6 +120,9 @@ enum fdt_compat_id {
COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_MEMORY_SPD, /* Memory SPD information */
+ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
+ COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */
+ COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
COMPAT_COUNT,
};
@@ -390,17 +393,6 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int node,
int *seqp);
/**
- * Get the offset of the given alias node
- *
- * This looks up an alias in /aliases then finds the offset of that node.
- *
- * @param blob Device tree blob (if NULL, then error is returned)
- * @param name Alias name, e.g. "console"
- * @return Node offset referred to by that alias, or -ve FDT_ERR_...
- */
-int fdtdec_get_alias_node(const void *blob, const char *name);
-
-/**
* Get the offset of the given chosen node
*
* This looks up a property in /chosen containing the path to another node,
@@ -613,17 +605,33 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node,
* @param blob FDT blob
* @param node node to examine
* @param prop_name name of property to find
- * @param ptrp returns pointer to region, or NULL if no address
- * @param size returns size of region
- * @return 0 if ok, -1 on error (propery not found)
+ * @param basep Returns base address of region
+ * @param size Returns size of region
+ * @return 0 if ok, -1 on error (property not found)
*/
-int fdtdec_decode_region(const void *blob, int node,
- const char *prop_name, void **ptrp, size_t *size);
+int fdtdec_decode_region(const void *blob, int node, const char *prop_name,
+ fdt_addr_t *basep, fdt_size_t *sizep);
+
+enum fmap_compress_t {
+ FMAP_COMPRESS_NONE,
+ FMAP_COMPRESS_LZO,
+};
+
+enum fmap_hash_t {
+ FMAP_HASH_NONE,
+ FMAP_HASH_SHA1,
+ FMAP_HASH_SHA256,
+};
/* A flash map entry, containing an offset and length */
struct fmap_entry {
uint32_t offset;
uint32_t length;
+ uint32_t used; /* Number of bytes used in region */
+ enum fmap_compress_t compress_algo; /* Compression type */
+ enum fmap_hash_t hash_algo; /* Hash algorithm */
+ const uint8_t *hash; /* Hash value */
+ int hash_size; /* Hash size */
};
/**
@@ -679,4 +687,31 @@ int fdt_get_named_resource(const void *fdt, int node, const char *property,
*/
int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf);
+/**
+ * Decode a named region within a memory bank of a given type.
+ *
+ * This function handles selection of a memory region. The region is
+ * specified as an offset/size within a particular type of memory.
+ *
+ * The properties used are:
+ *
+ * <mem_type>-memory<suffix> for the name of the memory bank
+ * <mem_type>-offset<suffix> for the offset in that bank
+ *
+ * The property value must have an offset and a size. The function checks
+ * that the region is entirely within the memory bank.5
+ *
+ * @param blob FDT blob
+ * @param node Node containing the properties (-1 for /config)
+ * @param mem_type Type of memory to use, which is a name, such as
+ * "u-boot" or "kernel".
+ * @param suffix String to append to the memory/offset
+ * property names
+ * @param basep Returns base of region
+ * @param sizep Returns size of region
+ * @return 0 if OK, -ive on error
+ */
+int fdtdec_decode_memory_region(const void *blob, int node,
+ const char *mem_type, const char *suffix,
+ fdt_addr_t *basep, fdt_size_t *sizep);
#endif
diff --git a/include/fm_eth.h b/include/fm_eth.h
index e46a684..3e1b9f4 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -75,6 +75,20 @@ enum fm_eth_type {
offsetof(struct ccsr_fman, memac[n-1]),\
}
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{ \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ .index = idx, \
+ .num = n - 1, \
+ .type = FM_ETH_10G_E, \
+ .port = FM##idx##_10GEC##n, \
+ .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
+ .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
+ .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ offsetof(struct ccsr_fman, memac[n-1]),\
+}
+#else
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
@@ -87,6 +101,7 @@ enum fm_eth_type {
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
+#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 1a6c9c1..e4902aa 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -85,4 +85,81 @@ struct ccsr_usb_phy {
#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
#endif
+/* USB Erratum Checking code */
+#ifdef CONFIG_PPC
+static inline bool has_erratum_a006261(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P2041:
+ case SVR_P2040:
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+ case SVR_P3041:
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 1, 1) ||
+ IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+ case SVR_P5010:
+ case SVR_P5020:
+ case SVR_P5021:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_T4240:
+ case SVR_T4160:
+ case SVR_T4080:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_T1040:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P5040:
+ return IS_SVR_REV(svr, 1, 0);
+ }
+
+ return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P4080:
+ return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+ }
+ return false;
+}
+
+static inline bool has_erratum_a007798(void)
+{
+ return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+ IS_SVR_REV(get_svr(), 2, 0);
+}
+#else
+static inline bool has_erratum_a006261(void)
+{
+ return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+ return false;
+}
+
+static inline bool has_erratum_a007798(void)
+{
+ return false;
+}
+
+#endif
#endif /*_ASM_FSL_USB_H_ */
diff --git a/include/image.h b/include/image.h
index 07e9aed..af30d60 100644
--- a/include/image.h
+++ b/include/image.h
@@ -119,6 +119,12 @@ struct lmb;
# define IMAGE_OF_BOARD_SETUP 0
#endif
+#ifdef CONFIG_OF_SYSTEM_SETUP
+# define IMAGE_OF_SYSTEM_SETUP 1
+#else
+# define IMAGE_OF_SYSTEM_SETUP 0
+#endif
+
/*
* Operating System Codes
*/
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 47b0889..b40133c 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -215,13 +215,11 @@ typedef int wait_queue_head_t;
#define cond_resched() do { } while (0)
#define yield() do { } while (0)
-#define __user
#define __init
#define __exit
#define __devinit
#define __devinitdata
#define __devinitconst
-#define __iomem
#define kthread_create(...) __builtin_return_address(0)
#define kthread_stop(...) do { } while (0)
@@ -252,8 +250,6 @@ struct cdev {
#define cdev_add(...) 0
#define cdev_del(...) do { } while (0)
-#define MAX_ERRNO 4095
-
#define prandom_u32(...) 0
typedef struct {
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 89fcae0..0b61671 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -16,7 +16,9 @@
#define LLONG_MAX ((long long)(~0ULL>>1))
#define LLONG_MIN (-LLONG_MAX - 1)
#define ULLONG_MAX (~0ULL)
+#ifndef SIZE_MAX
#define SIZE_MAX (~(size_t)0)
+#endif
#define U8_MAX ((u8)~0U)
#define S8_MAX ((s8)(U8_MAX>>1))
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index 82630ad..cb166e6 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -14,6 +14,10 @@
#define OMAP_XHCI_BASE 0x488d0000
#define OMAP_OCP1_SCP_BASE 0x4A081000
#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM57XX
+#define OMAP_XHCI_BASE 0x48890000
+#define OMAP_OCP1_SCP_BASE 0x4A084c00
+#define OMAP_OTG_WRAPPER_BASE 0x48880000
#elif defined CONFIG_AM43XX
#define OMAP_XHCI_BASE 0x483d0000
#define OMAP_OCP1_SCP_BASE 0x483E8000
diff --git a/include/mmc.h b/include/mmc.h
index d74a190..adffc35 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -385,6 +385,7 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
int mmc_legacy_init(int verbose);
#endif
+void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
diff --git a/include/pci.h b/include/pci.h
index d211351..216f448 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -678,5 +678,28 @@ extern void pci_mpc824x_init (struct pci_controller *hose);
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
+/**
+ * pci_write_bar32() - Write the address of a BAR including control bits
+ *
+ * This writes a raw address (with control bits) to a bar
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address with control bits
+ */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+ u32 addr_and_ctrl);
+
+/**
+ * pci_read_bar32() - read the address of a bar
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to inspect
+ * @barnum: BAR number (0-5)
+ * @return address of the bar, masking out any control bits
+ * */
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index f84c13a..ee98bee 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -526,7 +526,19 @@
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
-#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
+#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e
+#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600
+#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
+#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
+#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603
+#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604
+#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605
+#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533
+#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
@@ -569,8 +581,9 @@
#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A
#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081
#define PCI_DEVICE_ID_AMD_LX_AES 0x2082
-#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800
+#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b
+#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_VENDOR_ID_TRIDENT 0x1023
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
@@ -616,6 +629,8 @@
#define PCI_DEVICE_ID_MATROX_G550 0x2527
#define PCI_DEVICE_ID_MATROX_VIA 0x4536
+#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2
+
#define PCI_VENDOR_ID_CT 0x102c
#define PCI_DEVICE_ID_CT_69000 0x00c0
#define PCI_DEVICE_ID_CT_65545 0x00d8
@@ -724,6 +739,7 @@
#define PCI_DEVICE_ID_SI_7018 0x7018
#define PCI_VENDOR_ID_HP 0x103c
+#define PCI_VENDOR_ID_HP_3PAR 0x1590
#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005
#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006
#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008
@@ -755,6 +771,8 @@
#define PCI_DEVICE_ID_HP_CISSD 0x3238
#define PCI_DEVICE_ID_HP_CISSE 0x323a
#define PCI_DEVICE_ID_HP_CISSF 0x323b
+#define PCI_DEVICE_ID_HP_CISSH 0x323c
+#define PCI_DEVICE_ID_HP_CISSI 0x3239
#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031
#define PCI_VENDOR_ID_PCTECH 0x1042
@@ -779,6 +797,29 @@
#define PCI_DEVICE_ID_ELSA_QS3000 0x3000
#define PCI_VENDOR_ID_STMICRO 0x104A
+#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00
+#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01
+#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02
+#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03
+#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04
+#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05
+#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06
+#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07
+#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08
+#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09
+#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A
+#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B
+#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C
+#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10
+#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11
+#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12
+#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13
+#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14
+#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15
+#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16
#define PCI_VENDOR_ID_BUSLOGIC 0x104B
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
@@ -1294,6 +1335,8 @@
#define PCI_VENDOR_ID_TUNDRA 0x10e3
#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000
+#define PCI_VENDOR_ID_AMCC 0x10e8
+
#define PCI_VENDOR_ID_INTERG 0x10ea
#define PCI_DEVICE_ID_INTERG_1682 0x1682
#define PCI_DEVICE_ID_INTERG_2000 0x2000
@@ -1322,6 +1365,7 @@
#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041
#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042
#define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043
+#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062
#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000
#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */
@@ -1411,6 +1455,7 @@
#define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581
#define PCI_DEVICE_ID_VIA_VX800 0x8353
#define PCI_DEVICE_ID_VIA_VX855 0x8409
+#define PCI_DEVICE_ID_VIA_VX900 0x8410
#define PCI_DEVICE_ID_VIA_8371_1 0x8391
#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
#define PCI_DEVICE_ID_VIA_838X_1 0xB188
@@ -1551,6 +1596,8 @@
#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476
#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478
#define PCI_DEVICE_ID_RICOH_R5C822 0x0822
+#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822
+#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823
#define PCI_DEVICE_ID_RICOH_R5C832 0x0832
#define PCI_DEVICE_ID_RICOH_R5C843 0x0843
@@ -1586,6 +1633,7 @@
#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
#define PCI_VENDOR_ID_MARVELL 0x11ab
+#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b
#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
@@ -1798,6 +1846,8 @@
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */
+
#define PCI_VENDOR_ID_SIIG 0x131f
#define PCI_SUBVENDOR_ID_SIIG 0x131f
#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
@@ -1860,8 +1910,23 @@
#define PCI_VENDOR_ID_QUATECH 0x135C
#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040
#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
+#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120
+#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130
+#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140
+#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150
+#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170
+#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180
+#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181
+#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190
+#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0
+#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0
+#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1
+#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0
+#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0
#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
#define PCI_VENDOR_ID_SEALEVEL 0x135e
@@ -1978,6 +2043,9 @@
#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152
#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154
#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158
+#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352
+#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354
+#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358
#define PCI_VENDOR_ID_MICROGATE 0x13c0
#define PCI_DEVICE_ID_MICROGATE_USC 0x0010
@@ -2002,6 +2070,10 @@
#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
+#define PCI_VENDOR_ID_ADVANTECH 0x13fe
+
+#define PCI_VENDOR_ID_MEILHAUS 0x1402
+
#define PCI_VENDOR_ID_LAVA 0x1407
#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */
#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */
@@ -2047,6 +2119,8 @@
#define PCI_VENDOR_ID_CHELSIO 0x1425
+#define PCI_VENDOR_ID_ADLINK 0x144a
+
#define PCI_VENDOR_ID_SAMSUNG 0x144d
#define PCI_VENDOR_ID_GIGABYTE 0x1458
@@ -2080,6 +2154,8 @@
#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
+#define PCI_VENDOR_ID_AMPLICON 0x14dc
+
#define PCI_VENDOR_ID_BCM_GVC 0x14a4
#define PCI_VENDOR_ID_BROADCOM 0x14e4
#define PCI_DEVICE_ID_TIGON3_5752 0x1600
@@ -2100,19 +2176,25 @@
#define PCI_DEVICE_ID_NX2_57711E 0x1650
#define PCI_DEVICE_ID_TIGON3_5705 0x1653
#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
+#define PCI_DEVICE_ID_TIGON3_5719 0x1657
#define PCI_DEVICE_ID_TIGON3_5721 0x1659
#define PCI_DEVICE_ID_TIGON3_5722 0x165a
#define PCI_DEVICE_ID_TIGON3_5723 0x165b
#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
+#define PCI_DEVICE_ID_NX2_57712 0x1662
+#define PCI_DEVICE_ID_NX2_57712E 0x1663
+#define PCI_DEVICE_ID_NX2_57712_MF 0x1663
#define PCI_DEVICE_ID_TIGON3_5714 0x1668
#define PCI_DEVICE_ID_TIGON3_5714S 0x1669
#define PCI_DEVICE_ID_TIGON3_5780 0x166a
#define PCI_DEVICE_ID_TIGON3_5780S 0x166b
#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
+#define PCI_DEVICE_ID_NX2_57712_VF 0x166f
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
+#define PCI_DEVICE_ID_TIGON3_5750 0x1676
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
@@ -2124,6 +2206,9 @@
#define PCI_DEVICE_ID_TIGON3_5761E 0x1680
#define PCI_DEVICE_ID_TIGON3_5761 0x1681
#define PCI_DEVICE_ID_TIGON3_5764 0x1684
+#define PCI_DEVICE_ID_NX2_57800 0x168a
+#define PCI_DEVICE_ID_NX2_57840 0x168d
+#define PCI_DEVICE_ID_NX2_57810 0x168e
#define PCI_DEVICE_ID_TIGON3_5787M 0x1693
#define PCI_DEVICE_ID_TIGON3_5782 0x1696
#define PCI_DEVICE_ID_TIGON3_5784 0x1698
@@ -2131,11 +2216,19 @@
#define PCI_DEVICE_ID_TIGON3_5787 0x169b
#define PCI_DEVICE_ID_TIGON3_5788 0x169c
#define PCI_DEVICE_ID_TIGON3_5789 0x169d
+#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1
+#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2
+#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4
+#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5
#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
+#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9
#define PCI_DEVICE_ID_NX2_5706S 0x16aa
#define PCI_DEVICE_ID_NX2_5708S 0x16ac
+#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad
+#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae
+#define PCI_DEVICE_ID_NX2_57810_VF 0x16af
#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
#define PCI_DEVICE_ID_TIGON3_5781 0x16dd
@@ -2307,6 +2400,8 @@
#define PCI_VENDOR_ID_TOPSPIN 0x1867
+#define PCI_VENDOR_ID_COMMTECH 0x18f7
+
#define PCI_VENDOR_ID_SILAN 0x1904
#define PCI_VENDOR_ID_RENESAS 0x1912
@@ -2316,6 +2411,11 @@
#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
#define PCI_DEVICE_ID_RENESAS_SH7786 0x0010
+#define PCI_VENDOR_ID_SOLARFLARE 0x1924
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710
+
#define PCI_VENDOR_ID_TDI 0x192E
#define PCI_DEVICE_ID_TDI_EHCI 0x0101
@@ -2414,6 +2514,11 @@
#define PCI_VENDOR_ID_AZWAVE 0x1a3b
+#define PCI_VENDOR_ID_ASMEDIA 0x1b21
+
+#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
#define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
@@ -2463,6 +2568,9 @@
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
+#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
+#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
+#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320
#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321
#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329
@@ -2485,6 +2593,7 @@
#define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
+#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
@@ -2564,13 +2673,50 @@
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68 0x1c44
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67 0x1c46
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67 0x1c47
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65 0x1c49
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67 0x1c4a
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67 0x1c4b
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65 0x1c4c
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67 0x1c4d
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67 0x1c4e
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67 0x1c4f
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65 0x1c50
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202 0x1c52
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204 0x1c54
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206 0x1c56
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61 0x1c5c
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75 0x1e49
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216 0x1e53
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77 0x1e4A
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70 0x1e5e
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75 0x1e5d
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76 0x1e59
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77 0x1e57
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70 0x1e5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75 0x1e48
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77 0x1e47
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77 0x1e55
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77 0x1e56
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77 0x1e58
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75 0x1e46
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77 0x1e44
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
@@ -2783,8 +2929,30 @@
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
+#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46
+#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0
+#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1
+#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4
+#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5
+#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41
+#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42
+#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
+#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
+#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6
#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030
@@ -2823,6 +2991,7 @@
#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a
+#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186
#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
@@ -2905,7 +3074,11 @@
#define PCI_DEVICE_ID_NETMOS_9845 0x9845
#define PCI_DEVICE_ID_NETMOS_9855 0x9855
#define PCI_DEVICE_ID_NETMOS_9865 0x9865
+#define PCI_DEVICE_ID_NETMOS_9900 0x9900
#define PCI_DEVICE_ID_NETMOS_9901 0x9901
+#define PCI_DEVICE_ID_NETMOS_9904 0x9904
+#define PCI_DEVICE_ID_NETMOS_9912 0x9912
+#define PCI_DEVICE_ID_NETMOS_9922 0x9922
#define PCI_VENDOR_ID_3COM_2 0xa727
@@ -2927,3 +3100,5 @@
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
+
+#define PCI_VENDOR_ID_OCZ 0x1b85
diff --git a/include/pci_rom.h b/include/pci_rom.h
new file mode 100644
index 0000000..8b2674c
--- /dev/null
+++ b/include/pci_rom.h
@@ -0,0 +1,58 @@
+/*
+ * From coreboot file of same name
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PCI_ROM_H
+#define _PCI_ROM_H
+
+#define PCI_ROM_HDR 0xaa55
+#define PCI_VGA_RAM_IMAGE_START 0xc0000
+
+struct pci_rom_header {
+ uint16_t signature;
+ uint8_t size;
+ uint8_t init[3];
+ uint8_t reserved[0x12];
+ uint16_t data;
+};
+
+struct pci_rom_data {
+ uint32_t signature;
+ uint16_t vendor;
+ uint16_t device;
+ uint16_t reserved_1;
+ uint16_t dlen;
+ uint8_t drevision;
+ uint8_t class_lo;
+ uint16_t class_hi;
+ uint16_t ilen;
+ uint16_t irevision;
+ uint8_t type;
+ uint8_t indicator;
+ uint16_t reserved_2;
+};
+
+ /**
+ * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ *
+ * @dev: Video device containing the BIOS
+ * @int15_handler: Function to call to handle int 0x15
+ * @emulate: true to use the x86 emulator, false to run native
+ */
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate);
+
+/**
+ * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
+ *
+ * Some VGA option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ *
+ * @vendev: Vendor and device for the video device
+ * @return standard vendor and device expected by the ROM
+ */
+uint32_t board_map_oprom_vendev(uint32_t vendev);
+
+#endif
diff --git a/include/phy.h b/include/phy.h
index b495077..1e282e2 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -41,6 +41,7 @@ typedef enum {
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_SGMII_2500,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
@@ -57,6 +58,7 @@ static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
+ [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
[PHY_INTERFACE_MODE_TBI] = "tbi",
[PHY_INTERFACE_MODE_RMII] = "rmii",
@@ -225,6 +227,7 @@ int gen10g_discover_mmds(struct phy_device *phydev);
int phy_atheros_init(void);
int phy_broadcom_init(void);
+int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
@@ -239,6 +242,7 @@ int phy_vitesse_init(void);
int board_phy_config(struct phy_device *phydev);
/* PHY UIDs for various PHYs that are referenced in external code */
+#define PHY_UID_CS4340 0x13e51002
#define PHY_UID_TN2020 0x00a19410
#endif
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index c2a772a..b0e4255 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -150,6 +150,7 @@ enum {
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
@@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
+#define MAX77686_BUCK_VOLT_MAX_HEX 0x3f
+#define MAX77686_BUCK_VOLT_MASK 0x3f
#define MAX77686_BUCK_MODE_MASK 0x03
#define MAX77686_BUCK_MODE_SHIFT_1 0x00
#define MAX77686_BUCK_MODE_SHIFT_2 0x04
diff --git a/include/rtc.h b/include/rtc.h
index c034966..d11aa8b 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -50,4 +50,9 @@ void to_tm (int, struct rtc_time *);
unsigned long mktime (unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int);
+/**
+ * rtc_init() - Set up the real time clock ready for use
+ */
+void rtc_init(void);
+
#endif /* _RTC_H_ */
diff --git a/include/twl4030.h b/include/twl4030.h
index f33cd1e..50f8da8 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -651,7 +651,7 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
/* For initializing power device */
void twl4030_power_init(void);
/* For initializing mmc power */
-void twl4030_power_mmc_init(void);
+void twl4030_power_mmc_init(int dev_index);
/*
* LED
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index dd77ad6..897018b 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -163,6 +163,9 @@
#elif defined(CONFIG_MPC512X)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0
+#elif defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR 0
#endif
/*
diff --git a/include/vbe.h b/include/vbe.h
new file mode 100644
index 0000000..d405691
--- /dev/null
+++ b/include/vbe.h
@@ -0,0 +1,103 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+#ifndef _VBE_H
+#define _VBE_H
+
+/* these structs are for input from and output to OF */
+struct __packed screen_info {
+ u8 display_type; /* 0=NONE, 1= analog, 2=digital */
+ u16 screen_width;
+ u16 screen_height;
+ /* bytes per line in framebuffer, may be more than screen_width */
+ u16 screen_linebytes;
+ u8 color_depth; /* color depth in bits per pixel */
+ u32 framebuffer_address;
+ u8 edid_block_zero[128];
+};
+
+struct __packed screen_info_input {
+ u8 signature[4];
+ u16 size_reserved;
+ u8 monitor_number;
+ u16 max_screen_width;
+ u8 color_depth;
+};
+
+/* these structs only store the required a subset of the VBE-defined fields */
+struct __packed vbe_info {
+ char signature[4];
+ u16 version;
+ u8 *oem_string_ptr;
+ u32 capabilities;
+ u16 video_mode_list[256];
+ u16 total_memory;
+};
+
+struct __packed vesa_mode_info {
+ u16 mode_attributes; /* 00 */
+ u8 win_a_attributes; /* 02 */
+ u8 win_b_attributes; /* 03 */
+ u16 win_granularity; /* 04 */
+ u16 win_size; /* 06 */
+ u16 win_a_segment; /* 08 */
+ u16 win_b_segment; /* 0a */
+ u32 win_func_ptr; /* 0c */
+ u16 bytes_per_scanline; /* 10 */
+ u16 x_resolution; /* 12 */
+ u16 y_resolution; /* 14 */
+ u8 x_charsize; /* 16 */
+ u8 y_charsize; /* 17 */
+ u8 number_of_planes; /* 18 */
+ u8 bits_per_pixel; /* 19 */
+ u8 number_of_banks; /* 20 */
+ u8 memory_model; /* 21 */
+ u8 bank_size; /* 22 */
+ u8 number_of_image_pages; /* 23 */
+ u8 reserved_page;
+ u8 red_mask_size;
+ u8 red_mask_pos;
+ u8 green_mask_size;
+ u8 green_mask_pos;
+ u8 blue_mask_size;
+ u8 blue_mask_pos;
+ u8 reserved_mask_size;
+ u8 reserved_mask_pos;
+ u8 direct_color_mode_info;
+ u32 phys_base_ptr;
+ u32 offscreen_mem_offset;
+ u16 offscreen_mem_size;
+ u8 reserved[206];
+};
+
+struct vbe_mode_info {
+ u16 video_mode;
+ bool valid;
+ union {
+ struct vesa_mode_info vesa;
+ u8 mode_info_block[256];
+ };
+};
+
+struct vbe_ddc_info {
+ u8 port_number; /* i.e. monitor number */
+ u8 edid_transfer_time;
+ u8 ddc_level;
+ u8 edid_block_zero[128];
+};
+
+#define VESA_GET_INFO 0x4f00
+#define VESA_GET_MODE_INFO 0x4f01
+#define VESA_SET_MODE 0x4f02
+
+struct graphic_device;
+int vbe_get_video_info(struct graphic_device *gdev);
+
+#endif
diff --git a/include/video_fb.h b/include/video_fb.h
index 6cd4e37..55ec24d 100644
--- a/include/video_fb.h
+++ b/include/video_fb.h
@@ -40,7 +40,7 @@
/* Export Graphic Driver Control */
/******************************************************************************/
-typedef struct {
+typedef struct graphic_device {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
diff --git a/lib/Makefile b/lib/Makefile
index 320197a..3ceb697 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -11,14 +11,12 @@ obj-$(CONFIG_RSA) += rsa/
obj-$(CONFIG_LZMA) += lzma/
obj-$(CONFIG_LZO) += lzo/
obj-$(CONFIG_ZLIB) += zlib/
+obj-$(CONFIG_BZIP2) += bzip2/
obj-$(CONFIG_TIZEN) += tizen/
+obj-$(CONFIG_OF_LIBFDT) += libfdt/
+obj-$(CONFIG_FIT) += libfdt/
obj-$(CONFIG_AES) += aes.o
-obj-$(CONFIG_BZIP2) += bzlib.o
-obj-$(CONFIG_BZIP2) += bzlib_crctable.o
-obj-$(CONFIG_BZIP2) += bzlib_decompress.o
-obj-$(CONFIG_BZIP2) += bzlib_randtable.o
-obj-$(CONFIG_BZIP2) += bzlib_huffman.o
obj-$(CONFIG_USB_TTY) += circbuf.o
obj-y += crc7.o
obj-y += crc8.o
diff --git a/lib/bzip2/Makefile b/lib/bzip2/Makefile
new file mode 100644
index 0000000..929c24e
--- /dev/null
+++ b/lib/bzip2/Makefile
@@ -0,0 +1,2 @@
+obj-y += bzlib.o bzlib_crctable.o bzlib_decompress.o \
+ bzlib_randtable.o bzlib_huffman.o
diff --git a/lib/bzlib.c b/lib/bzip2/bzlib.c
index 5844e18..5844e18 100644
--- a/lib/bzlib.c
+++ b/lib/bzip2/bzlib.c
diff --git a/lib/bzlib_crctable.c b/lib/bzip2/bzlib_crctable.c
index 325b966..325b966 100644
--- a/lib/bzlib_crctable.c
+++ b/lib/bzip2/bzlib_crctable.c
diff --git a/lib/bzlib_decompress.c b/lib/bzip2/bzlib_decompress.c
index 4412b8a..4412b8a 100644
--- a/lib/bzlib_decompress.c
+++ b/lib/bzip2/bzlib_decompress.c
diff --git a/lib/bzlib_huffman.c b/lib/bzip2/bzlib_huffman.c
index 801b8ec..801b8ec 100644
--- a/lib/bzlib_huffman.c
+++ b/lib/bzip2/bzlib_huffman.c
diff --git a/lib/bzlib_private.h b/lib/bzip2/bzlib_private.h
index 87d8f94..87d8f94 100644
--- a/lib/bzlib_private.h
+++ b/lib/bzip2/bzlib_private.h
diff --git a/lib/bzlib_randtable.c b/lib/bzip2/bzlib_randtable.c
index c3dc7e4..c3dc7e4 100644
--- a/lib/bzlib_randtable.c
+++ b/lib/bzip2/bzlib_randtable.c
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index e8775df..9d86dba 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -75,6 +75,9 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(MEMORY_SPD, "memory-spd"),
+ COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
+ COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
+ COMPAT(INTEL_GMA, "intel,gma"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -370,21 +373,6 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
return -ENOENT;
}
-int fdtdec_get_alias_node(const void *blob, const char *name)
-{
- const char *prop;
- int alias_node;
- int len;
-
- if (!blob)
- return -FDT_ERR_NOTFOUND;
- alias_node = fdt_path_offset(blob, "/aliases");
- prop = fdt_getprop(blob, alias_node, name, &len);
- if (!prop)
- return -FDT_ERR_NOTFOUND;
- return fdt_path_offset(blob, prop);
-}
-
int fdtdec_get_chosen_node(const void *blob, const char *name)
{
const char *prop;
@@ -691,20 +679,25 @@ char *fdtdec_get_config_string(const void *blob, const char *prop_name)
return (char *)nodep;
}
-int fdtdec_decode_region(const void *blob, int node,
- const char *prop_name, void **ptrp, size_t *size)
+int fdtdec_decode_region(const void *blob, int node, const char *prop_name,
+ fdt_addr_t *basep, fdt_size_t *sizep)
{
const fdt_addr_t *cell;
int len;
- debug("%s: %s\n", __func__, prop_name);
+ debug("%s: %s: %s\n", __func__, fdt_get_name(blob, node, NULL),
+ prop_name);
cell = fdt_getprop(blob, node, prop_name, &len);
- if (!cell || (len != sizeof(fdt_addr_t) * 2))
+ if (!cell || (len < sizeof(fdt_addr_t) * 2)) {
+ debug("cell=%p, len=%d\n", cell, len);
return -1;
+ }
+
+ *basep = fdt_addr_to_cpu(*cell);
+ *sizep = fdt_size_to_cpu(cell[1]);
+ debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
+ (ulong)*sizep);
- *ptrp = map_sysmem(fdt_addr_to_cpu(*cell), *size);
- *size = fdt_size_to_cpu(cell[1]);
- debug("%s: size=%zx\n", __func__, *size);
return 0;
}
@@ -720,6 +713,7 @@ int fdtdec_decode_region(const void *blob, int node,
int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
struct fmap_entry *entry)
{
+ const char *prop;
u32 reg[2];
if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) {
@@ -728,6 +722,13 @@ int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
}
entry->offset = reg[0];
entry->length = reg[1];
+ entry->used = fdtdec_get_int(blob, node, "used", entry->length);
+ prop = fdt_getprop(blob, node, "compress", NULL);
+ entry->compress_algo = prop && !strcmp(prop, "lzo") ?
+ FMAP_COMPRESS_LZO : FMAP_COMPRESS_NONE;
+ prop = fdt_getprop(blob, node, "hash", &entry->hash_size);
+ entry->hash_algo = prop ? FMAP_HASH_SHA256 : FMAP_HASH_NONE;
+ entry->hash = (uint8_t *)prop;
return 0;
}
@@ -802,4 +803,65 @@ int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf)
return 0;
}
+
+int fdtdec_decode_memory_region(const void *blob, int config_node,
+ const char *mem_type, const char *suffix,
+ fdt_addr_t *basep, fdt_size_t *sizep)
+{
+ char prop_name[50];
+ const char *mem;
+ fdt_size_t size, offset_size;
+ fdt_addr_t base, offset;
+ int node;
+
+ if (config_node == -1) {
+ config_node = fdt_path_offset(blob, "/config");
+ if (config_node < 0) {
+ debug("%s: Cannot find /config node\n", __func__);
+ return -ENOENT;
+ }
+ }
+ if (!suffix)
+ suffix = "";
+
+ snprintf(prop_name, sizeof(prop_name), "%s-memory%s", mem_type,
+ suffix);
+ mem = fdt_getprop(blob, config_node, prop_name, NULL);
+ if (!mem) {
+ debug("%s: No memory type for '%s', using /memory\n", __func__,
+ prop_name);
+ mem = "/memory";
+ }
+
+ node = fdt_path_offset(blob, mem);
+ if (node < 0) {
+ debug("%s: Failed to find node '%s': %s\n", __func__, mem,
+ fdt_strerror(node));
+ return -ENOENT;
+ }
+
+ /*
+ * Not strictly correct - the memory may have multiple banks. We just
+ * use the first
+ */
+ if (fdtdec_decode_region(blob, node, "reg", &base, &size)) {
+ debug("%s: Failed to decode memory region %s\n", __func__,
+ mem);
+ return -EINVAL;
+ }
+
+ snprintf(prop_name, sizeof(prop_name), "%s-offset%s", mem_type,
+ suffix);
+ if (fdtdec_decode_region(blob, config_node, prop_name, &offset,
+ &offset_size)) {
+ debug("%s: Failed to decode memory region '%s'\n", __func__,
+ prop_name);
+ return -EINVAL;
+ }
+
+ *basep = base + offset;
+ *sizep = offset_size;
+
+ return 0;
+}
#endif
diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile
index 6fe79e0..2f5413f 100644
--- a/lib/libfdt/Makefile
+++ b/lib/libfdt/Makefile
@@ -5,8 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
+obj-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
fdt_empty_tree.o fdt_addresses.o
-
-obj-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
-obj-$(CONFIG_FIT) += $(COBJS-libfdt)
diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h
index 556be32..af3703e 100644
--- a/lib/zlib/zlib.h
+++ b/lib/zlib/zlib.h
@@ -3,7 +3,7 @@
#define __GLUE_ZLIB_H__
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <asm/unaligned.h>
#include <watchdog.h>
#include "u-boot/zlib.h"
diff --git a/net/bootp.c b/net/bootp.c
index d4c86cf..8106601 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -145,8 +145,6 @@ static void BootpCopyNetParams(struct Bootp_t *bp)
if (tmp_ip != 0)
NetCopyIP(&NetServerIP, &bp->bp_siaddr);
memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6);
-#endif
- NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
if (strlen(bp->bp_file) > 0)
copy_filename(BootFile, bp->bp_file, sizeof(BootFile));
@@ -158,6 +156,8 @@ static void BootpCopyNetParams(struct Bootp_t *bp)
*/
if (*BootFile)
setenv("bootfile", BootFile);
+#endif
+ NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
}
static int truncate_sz(const char *name, int maxlen, int curlen)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 9d1383a..13af604 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -260,11 +260,13 @@ quiet_cmd_dt_S_dtb= DTB $@
cmd_dt_S_dtb= \
( \
echo '.section .dtb.init.rodata,"a"'; \
+ echo '.balign 16'; \
echo '.global __dtb_$(*F)_begin'; \
echo '__dtb_$(*F)_begin:'; \
echo '.incbin "$<" '; \
echo '__dtb_$(*F)_end:'; \
echo '.global __dtb_$(*F)_end'; \
+ echo '.balign 16'; \
) > $@
$(obj)/%.dtb.S: $(obj)/%.dtb
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 1905446..ecf3037 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -34,6 +34,7 @@ SPL_BIN := u-boot-spl
endif
include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
# Enable garbage collection of un-used sections for SPL
KBUILD_CFLAGS += -ffunction-sections -fdata-sections
@@ -45,21 +46,6 @@ cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
-ifdef CONFIG_SPL_START_S_PATH
-START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%)
-else
-START_PATH := $(CPUDIR)
-endif
-
-head-y := $(START_PATH)/start.o
-head-$(CONFIG_X86) += $(START_PATH)/start16.o $(START_PATH)/resetvec.o
-head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o
-head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o
-
-libs-y += arch/$(ARCH)/lib/
-
-libs-y += $(CPUDIR)/
-
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
@@ -94,13 +80,6 @@ libs-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/
libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-libs-y += arch/$(ARCH)/imx-common/
-endif
-
-libs-$(CONFIG_ARM) += arch/arm/cpu/
-libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-
head-y := $(addprefix $(obj)/,$(head-y))
libs-y := $(addprefix $(obj)/,$(libs-y))
u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y)))
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 7717d68..368a20e 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -835,8 +835,7 @@ sub top_of_kernel_tree {
if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") {
$lk_path .= "/";
}
- if ( (-f "${lk_path}CREDITS")
- && (-f "${lk_path}Kbuild")
+ if ( (-f "${lk_path}Kbuild")
&& (-f "${lk_path}MAINTAINERS")
&& (-f "${lk_path}Makefile")
&& (-f "${lk_path}README")
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index a26cc5d..72c9dba 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -548,7 +548,7 @@ static void get_prompt_str(struct gstr *r, struct property *prop,
{
int i, j;
struct menu *submenu[8], *menu, *location = NULL;
- struct jump_key *jump;
+ struct jump_key *jump = NULL;
str_printf(r, _("Prompt: %s\n"), _(prop->text));
menu = prop->menu->parent;
@@ -586,7 +586,7 @@ static void get_prompt_str(struct gstr *r, struct property *prop,
str_printf(r, _(" Location:\n"));
for (j = 4; --i >= 0; j += 2) {
menu = submenu[i];
- if (head && location && menu == location)
+ if (jump && menu == location)
jump->offset = strlen(r->s);
str_printf(r, "%*c-> %s", j, ' ',
_(menu_get_prompt(menu)));
diff --git a/tools/.gitignore b/tools/.gitignore
index e7f0f8f..9bc9fec 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -4,6 +4,7 @@
/fit_check_sign
/fit_info
/gen_eth_addr
+/ifdtool
/img2srec
/kwboot
/dumpimage
diff --git a/tools/buildman/README b/tools/buildman/README
index 8ba19ec..bfb2f18 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -85,10 +85,10 @@ branch. Put all your commits in a branch, set the branch's upstream to a
valid value, and all will be well. Otherwise buildman will perform random
actions. Use -n to check what the random actions might be.
-If you just want to build the current source tree, leave off the -b flag.
-This will display results and errors as they happen. You can still look
-at them later using -s. Note that buildman will assume that the source
-has changed, and will build all specified boards in this case.
+If you just want to build the current source tree, leave off the -b flag
+and add -e. This will display results and errors as they happen. You can
+still look at them later using -se. Note that buildman will assume that the
+source has changed, and will build all specified boards in this case.
Buildman is optimised for building many commits at once, for many boards.
On multi-core machines, Buildman is fast because it uses most of the
@@ -693,9 +693,9 @@ Quick Sanity Check
==================
If you have made changes and want to do a quick sanity check of the
-currently-checked-out source, run buildman without the -b flag. This will
-build the selected boards and display build status and errors as it runs
-(i.e. -v amd -e are enabled automatically).
+currently checked-out source, run buildman without the -b flag. This will
+build the selected boards and display build status as it runs (i.e. -v is
+enabled automatically). Use -e to see errors/warnings as well.
Other options
@@ -752,7 +752,7 @@ an error and green indicating that a commit fixed an error. Use the -e
flag to see the full errors and -l to see which boards caused which errors.
If you really want to see build results as they happen, use -v when doing a
-build (-e will be enabled automatically).
+build (and -e to see the errors/warnings too).
You don't need to stick around on that branch while buildman is running. It
checks out its own copy of the source code, so you can change branches,
@@ -816,11 +816,10 @@ TODO
This has mostly be written in my spare time as a response to my difficulties
in testing large series of patches. Apart from tidying up there is quite a
-bit of scope for improvement. Things like better error diffs, easier access
-to log files, error display while building. Also it would be nice it buildman
-could 'hunt' for problems, perhaps by building a few boards for each arch,
-or checking commits for changed files and building only boards which use
-those files.
+bit of scope for improvement. Things like better error diffs and easier
+access to log files. Also it would be nice it buildman could 'hunt' for
+problems, perhaps by building a few boards for each arch, or checking
+commits for changed files and building only boards which use those files.
Credits
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 8155c16..7002034 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -918,7 +918,8 @@ class Builder:
if self._list_error_boards:
names = []
for board in line_boards[line]:
- names.append(board.target)
+ if not board.target in names:
+ names.append(board.target)
names_str = '(%s) ' % ','.join(names)
else:
names_str = ''
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index a9cf68a..bc4541c 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -332,7 +332,7 @@ class BuilderThread(threading.Thread):
# Now write the actual build output
if keep_outputs:
- patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map',
+ patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img',
'include/autoconf.mk', 'spl/u-boot-spl',
'spl/u-boot-spl.bin']
for pattern in patterns:
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 8b8c826..2c3ba8b 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -70,7 +70,7 @@ def ShowActions(series, why_selected, boards_selected, builder, options):
if commits:
for upto in range(0, len(series.commits), options.step):
commit = series.commits[upto]
- print ' ', col.Color(col.YELLOW, commit.hash, bright=False),
+ print ' ', col.Color(col.YELLOW, commit.hash[:8], bright=False),
print commit.subject
print
for arg in why_selected:
@@ -188,7 +188,6 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
else:
series = None
options.verbose = True
- options.show_errors = True
# By default we have one thread per CPU. But if there are not enough jobs
# we can have fewer threads and use a high '-j' value for make.
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index d630157..da04883 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -248,8 +248,7 @@ class PatchStream:
# Detect the start of a new commit
elif commit_match:
self.CloseCommit()
- # TODO: We should store the whole hash, and just display a subset
- self.commit = commit.Commit(commit_match.group(1)[:8])
+ self.commit = commit.Commit(commit_match.group(1))
# Detect tags in the commit message
elif tag_match: