diff options
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/clock.c | 17 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/clock.h | 1 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board.c | 1 |
3 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index 47fc893..d13fbc1 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data) tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); - /* set PLL Select (bit 13) for PASS PLL */ - if (data->pll == PASS_PLL) - tmp |= PLLCTL_PAPLL; - __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* Reset bit: bit 14 for both DDR3 & PASS PLL */ @@ -261,3 +257,16 @@ inline int get_max_arm_speed(void) return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds); } #endif + +void pass_pll_pa_clk_enable(void) +{ + u32 reg; + + reg = readl(keystone_pll_regs[PASS_PLL].reg1); + + reg |= PLLCTL_PAPLL; + writel(reg, keystone_pll_regs[PASS_PLL].reg1); + + /* wait till clock is enabled */ + sdelay(15000); +} diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index 7218230..9f6cfb2 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -58,6 +58,7 @@ void init_pll(const struct pll_init_data *data); unsigned long clk_get_rate(unsigned int clk); unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); +void pass_pll_pa_clk_enable(void); int get_max_dev_speed(void); int get_max_arm_speed(void); diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 279ec8e..8991786 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -77,6 +77,7 @@ int board_eth_init(bd_t *bis) return -1; if (psc_enable_module(KS2_LPSC_CRYPTO)) return -1; + pass_pll_pa_clk_enable(); port_num = get_num_eth_ports(); |