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-rw-r--r--arch/arm/cpu/armv7/socfpga/misc.c2
-rw-r--r--arch/arm/cpu/armv7/socfpga/u-boot-spl.lds9
-rw-r--r--arch/arm/include/asm/arch-socfpga/spl.h15
-rw-r--r--arch/arm/include/asm/spl.h2
-rw-r--r--include/configs/socfpga_common.h34
-rw-r--r--include/configs/socfpga_cyclone5.h2
-rw-r--r--tools/socfpgaimage.c16
7 files changed, 37 insertions, 43 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 0eab264..8c3e5f7 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -176,7 +176,7 @@ static void socfpga_nic301_slave_ns(void)
static uint32_t iswgrp_handoff[8];
-int misc_init_r(void)
+int arch_early_init_r(void)
{
int i;
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index db9bdad..569fa41 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -42,13 +42,4 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
} >.sdram
-
- . = ALIGN(8);
- __malloc_start = .;
- . = . + CONFIG_SPL_MALLOC_SIZE;
- __malloc_end = .;
-
- . = . + CONFIG_SPL_STACK_SIZE;
- . = ALIGN(8);
- __stack_start = .;
}
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
deleted file mode 100644
index 7e310d5..0000000
--- a/arch/arm/include/asm/arch-socfpga/spl.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2012 Pavel Machek <pavel@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SOCFPGA_SPL_H_
-#define _SOCFPGA_SPL_H_
-
-/* Symbols from linker script */
-extern char __malloc_start, __malloc_end, __stack_start;
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index e5daf89..8acd7cd 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -7,7 +7,7 @@
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
-#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) \
+#if defined(CONFIG_OMAP) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 49504dc..83a1bcd 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -22,7 +22,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
@@ -157,6 +157,21 @@
#define CONFIG_BAUDRATE 115200
/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_STORAGE
+/*
+ * NOTE: User must define either of the following to select which
+ * of the two USB controllers available on SoCFPGA to use.
+ * The DWC2 driver doesn't support multiple USB controllers.
+ * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
+ * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+ */
+#endif
+
+/*
* U-Boot environment
*/
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -167,16 +182,21 @@
/*
* SPL
+ *
+ * SRAM Memory layout:
+ *
+ * 0xFFFF_0000 ...... Start of SRAM
+ * 0xFFFF_xxxx ...... Top of stack (grows down)
+ * 0xFFFF_yyyy ...... Malloc area
+ * 0xFFFF_zzzz ...... Global Data
+ * 0xFFFF_FF00 ...... End of SRAM
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_STACK_SIZE (4 * 1024)
-#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 60d7e20..942738c 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -55,10 +55,8 @@
#if defined(CONFIG_CMD_NET)
#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_EPHY0_PHY_ADDR 0
/* PHY */
-#define CONFIG_EPHY1_PHY_ADDR 4
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
index 396d8a5..917873e 100644
--- a/tools/socfpgaimage.c
+++ b/tools/socfpgaimage.c
@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socfpga_header *header)
static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
uint16_t length_bytes)
{
- header.validation = htole32(VALIDATION_WORD);
+ header.validation = cpu_to_le32(VALIDATION_WORD);
header.version = version;
header.flags = flags;
- header.length_u32 = htole16(length_bytes/4);
+ header.length_u32 = cpu_to_le16(length_bytes/4);
header.zero = 0;
- header.checksum = htole16(hdr_checksum(&header));
+ header.checksum = cpu_to_le16(hdr_checksum(&header));
memcpy(buf, &header, sizeof(header));
}
@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *buf)
{
memcpy(&header, buf, sizeof(header));
- if (le32toh(header.validation) != VALIDATION_WORD)
+ if (le32_to_cpu(header.validation) != VALIDATION_WORD)
return -1;
- if (le16toh(header.checksum) != hdr_checksum(&header))
+ if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
return -1;
- return le16toh(header.length_u32) * 4;
+ return le16_to_cpu(header.length_u32) * 4;
}
/* Sign the buffer and return the signed buffer size */
@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,
/* Calculate and apply the CRC */
calc_crc = ~pbl_crc32(0, (char *)buf, len);
- *((uint32_t *)(buf + len)) = htole32(calc_crc);
+ *((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
if (!pad_64k)
return len + 4;
@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *buf)
calc_crc = ~pbl_crc32(0, (const char *)buf, len);
- buf_crc = le32toh(*((uint32_t *)(buf + len)));
+ buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
if (buf_crc != calc_crc) {
fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
generated by cgit v1.1 at 2024-07-15 23:13:20 +0000