diff options
85 files changed, 1949 insertions, 775 deletions
@@ -537,3 +537,8 @@ N: Timo Tuunainen E: timo.tuunainen@sysart.fi D: Support for Artila M-501 starter kit W: http://www.sysart.fi/ + +N: Philip Balister +E: philip@opensdr.com +D: Port to Lyrtech SFFSDR development board. +W: www.opensdr.com @@ -749,7 +749,7 @@ LIST_sh3=" \ LIST_sh4=" \ ms7750se \ ms7722se \ - Migo-R \ + MigoR \ r7780mp \ r2dplus \ sh7763rdp \ @@ -220,6 +220,7 @@ LIBS += drivers/hwmon/libhwmon.a LIBS += drivers/i2c/libi2c.a LIBS += drivers/input/libinput.a LIBS += drivers/misc/libmisc.a +LIBS += drivers/mmc/libmmc.a LIBS += drivers/mtd/libmtd.a LIBS += drivers/mtd/nand/libnand.a LIBS += drivers/mtd/nand_legacy/libnand_legacy.a @@ -387,6 +388,7 @@ TAG_SUBDIRS += drivers/hwmon TAG_SUBDIRS += drivers/i2c TAG_SUBDIRS += drivers/input TAG_SUBDIRS += drivers/misc +TAG_SUBDIRS += drivers/mmc TAG_SUBDIRS += drivers/mtd TAG_SUBDIRS += drivers/mtd/nand TAG_SUBDIRS += drivers/mtd/nand_legacy @@ -74,7 +74,7 @@ git://www.denx.de/git/u-boot.git ; you can browse it online at http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary The "snapshot" links on this page allow you to download tarballs of -any version you might be interested in. Ofifcial releases are also +any version you might be interested in. Official releases are also available for FTP download from the ftp://ftp.denx.de/pub/u-boot/ directory. @@ -94,7 +94,7 @@ Where we come from: * Provide extended interface to Linux boot loader * S-Record download * network boot - * PCMCIA / CompactFLash / ATA disk / SCSI ... boot + * PCMCIA / CompactFlash / ATA disk / SCSI ... boot - create ARMBoot project (http://sourceforge.net/projects/armboot) - add other CPU families (starting with ARM) - create U-Boot project (http://sourceforge.net/projects/u-boot) @@ -230,7 +230,7 @@ Example: For a TQM823L module type: cd u-boot make TQM823L_config -For the Cogent platform, you need to specify the cpu type as well; +For the Cogent platform, you need to specify the CPU type as well; e.g. "make cogent_mpc8xx_config". And also configure the cogent directory according to the instructions in cogent/README. @@ -278,7 +278,7 @@ The following options need to be configured: - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) Define one or more of CONFIG_LCD_HEARTBEAT - update a character position on - the lcd display every second with + the LCD display every second with a "rotator" |\-/|\-/ - Board flavour: (if CONFIG_MPC8260ADS is defined) @@ -293,7 +293,7 @@ The following options need to be configured: Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 -- 8xx CPU Options: (if using an MPC8xx cpu) +- 8xx CPU Options: (if using an MPC8xx CPU) CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if get_gclk_freq() cannot work e.g. if there is no 32KHz @@ -346,7 +346,7 @@ The following options need to be configured: CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] - When transfering memsize parameter to linux, some versions + When transferring memsize parameter to linux, some versions expect it to be in bytes, others in MB. Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. @@ -366,7 +366,8 @@ The following options need to be configured: OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device - boards with QUICC Engines require OF_QE to set UCC mac addresses + boards with QUICC Engines require OF_QE to set UCC MAC + addresses CONFIG_OF_BOARD_SETUP @@ -375,7 +376,7 @@ The following options need to be configured: CONFIG_OF_BOOT_CPU - This define fills in the correct boot cpu in the boot + This define fills in the correct boot CPU in the boot param header, the default value is zero if undefined. - Serial Ports: @@ -445,7 +446,7 @@ The following options need to be configured: linux_logo.h for logo. Requires CONFIG_VIDEO_LOGO CONFIG_CONSOLE_EXTRA_INFO - addional board info beside + additional board info beside the logo When CONFIG_CFB_CONSOLE is defined, video console is @@ -515,7 +516,7 @@ The following options need to be configured: The value of these goes into the environment as "ramboot" and "nfsboot" respectively, and can be used as a convenience, when switching between booting from - ram and nfs. + RAM and NFS. - Pre-Boot Commands: CONFIG_PREBOOT @@ -735,11 +736,11 @@ The following options need to be configured: Support for Intel 8254x gigabit chips. CONFIG_E1000_FALLBACK_MAC - default MAC for empty eeprom after production. + default MAC for empty EEPROM after production. CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. - Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom + Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM write routine for first time initialisation. CONFIG_TULIP @@ -818,7 +819,7 @@ The following options need to be configured: Define the below if you wish to use the USB console. Once firmware is rebuilt from a serial console issue the command "setenv stdin usbtty; setenv stdout usbtty" and - attach your usb cable. The Unix command "dmesg" should print + attach your USB cable. The Unix command "dmesg" should print it has found a new device. The environment variable usbtty can be set to gserial or cdc_acm to enable your device to appear to a USB host as a Linux gserial device or a @@ -932,7 +933,7 @@ The following options need to be configured: assumed. For the CT69000 and SMI_LYNXEM drivers, videomode is - selected via environment 'videomode'. Two diferent ways + selected via environment 'videomode'. Two different ways are possible: - "videomode=num" 'num' is a standard LiLo mode numbers. Following standard modes are supported (* is default): @@ -1055,7 +1056,7 @@ The following options need to be configured: CONFIG_PHY_GIGE If this option is set, support for speed/duplex - detection of Gigabit PHY is included. + detection of gigabit PHY is included. CONFIG_PHY_RESET_DELAY @@ -1074,21 +1075,21 @@ The following options need to be configured: CONFIG_ETH2ADDR CONFIG_ETH3ADDR - Define a default value for ethernet address to use - for the respective ethernet interface, in case this + Define a default value for Ethernet address to use + for the respective Ethernet interface, in case this is not determined automatically. - IP address: CONFIG_IPADDR Define a default value for the IP address to use for - the default ethernet interface, in case this is not + the default Ethernet interface, in case this is not determined through e.g. bootp. - Server IP address: CONFIG_SERVERIP - Defines a default value for theIP address of a TFTP + Defines a default value for the IP address of a TFTP server to contact when using the "tftboot" command. - Multicast TFTP Mode: @@ -1096,7 +1097,7 @@ The following options need to be configured: Defines whether you want to support multicast TFTP as per rfc-2090; for example to work with atftp. Lets lots of targets - tftp down the same boot image concurrently. Note: the ethernet + tftp down the same boot image concurrently. Note: the Ethernet driver in use must provide a function: mcast() to join/leave a multicast group. @@ -1184,7 +1185,7 @@ The following options need to be configured: A printf format string which contains the ascii name of the port. Normally is set to "eth%d" which sets - eth0 for the first ethernet, eth1 for the second etc. + eth0 for the first Ethernet, eth1 for the second etc. CONFIG_CDP_CAPABILITIES @@ -1233,7 +1234,7 @@ The following options need to be configured: These enable I2C serial bus commands. Defining either of (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will - include the appropriate I2C driver for the selected cpu. + include the appropriate I2C driver for the selected CPU. This will allow you to use i2c commands at the u-boot command line (as long as you set CONFIG_CMD_I2C in @@ -1258,10 +1259,10 @@ The following options need to be configured: In both cases you will need to define CFG_I2C_SPEED to be the frequency (in Hz) at which you wish your i2c bus to run and CFG_I2C_SLAVE to be the address of this node (ie - the cpu's i2c node address). + the CPU's i2c node address). Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) - sets the cpu up as a master node and so its address should + sets the CPU up as a master node and so its address should therefore be cleared to 0 (See, eg, MPC823e User's Manual p.16-473). So, set CFG_I2C_SLAVE to 0. @@ -1480,17 +1481,17 @@ The following options need to be configured: Maximum time to wait for the INIT_B line to deassert after PROB_B has been deasserted during a Virtex II FPGA configuration sequence. The default time is 500 - mS. + ms. CFG_FPGA_WAIT_BUSY Maximum time to wait for BUSY to deassert during - Virtex II FPGA configuration. The default is 5 mS. + Virtex II FPGA configuration. The default is 5 ms. CFG_FPGA_WAIT_CONFIG Time to wait after FPGA configuration. The default is - 200 mS. + 200 ms. - Configuration Management: CONFIG_IDENT_STRING @@ -1507,7 +1508,7 @@ The following options need to be configured: protects these variables from casual modification by the user. Once set, these variables are read-only, and write or delete attempts are rejected. You can - change this behviour: + change this behaviour: If CONFIG_ENV_OVERWRITE is #defined in your config file, the write protection for vendor parameters is @@ -1516,7 +1517,7 @@ The following options need to be configured: Alternatively, if you #define _both_ CONFIG_ETHADDR _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default - ethernet address is installed in the environment, + Ethernet address is installed in the environment, which can be changed exactly ONCE by the user. [The serial# is unaffected by this, i. e. it remains read-only.] @@ -1560,7 +1561,7 @@ The following options need to be configured: Define this variable to stop the system in case of a fatal error, so that you have to reset it manually. This is probably NOT a good idea for an embedded - system where you want to system to reboot + system where you want the system to reboot automatically as fast as possible, but it may be useful during development since you can try to debug the conditions that lead to the situation. @@ -1627,7 +1628,7 @@ The following options need to be configured: - Commandline Editing and History: CONFIG_CMDLINE_EDITING - Enable editiong and History functions for interactive + Enable editing and History functions for interactive commandline input operations - Default Environment: @@ -1668,7 +1669,7 @@ The following options need to be configured: Adding this option adds support for Xilinx SystemACE chips attached via some sort of local bus. The address - of the chip must alsh be defined in the + of the chip must also be defined in the CFG_SYSTEMACE_BASE macro. For example: #define CONFIG_SYSTEMACE @@ -1734,7 +1735,7 @@ Legacy uImage format: -12 common/image.c Ramdisk data has bad checksum 11 common/image.c Ramdisk data has correct checksum 12 common/image.c Ramdisk verification complete, start loading - -13 common/image.c Wrong Image Type (not PPC Linux Ramdisk) + -13 common/image.c Wrong Image Type (not PPC Linux ramdisk) 13 common/image.c Start multifile image verification 14 common/image.c No initial ramdisk, no multifile, continue. @@ -1794,13 +1795,13 @@ Legacy uImage format: -60 common/env_common.c Environment has a bad CRC, using default - 64 net/eth.c starting with Ethernetconfiguration. + 64 net/eth.c starting with Ethernet configuration. -64 net/eth.c no Ethernet found. 65 net/eth.c Ethernet found. -80 common/cmd_net.c usage wrong 80 common/cmd_net.c before calling NetLoop() - -81 common/cmd_net.c some error in NetLoop() occured + -81 common/cmd_net.c some error in NetLoop() occurred 81 common/cmd_net.c NetLoop() back without error -82 common/cmd_net.c size == 0 (File with size 0 loaded) 82 common/cmd_net.c trying automatic boot @@ -1823,8 +1824,8 @@ FIT uImage format: 105 common/cmd_bootm.c Kernel subimage hash verification OK -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture 106 common/cmd_bootm.c Architecture check OK - -106 common/cmd_bootm.c Kernel subimage has wrong typea - 107 common/cmd_bootm.c Kernel subimge type OK + -106 common/cmd_bootm.c Kernel subimage has wrong type + 107 common/cmd_bootm.c Kernel subimage type OK -107 common/cmd_bootm.c Can't get kernel subimage data/size 108 common/cmd_bootm.c Got kernel subimage data/size -108 common/cmd_bootm.c Wrong image type (not legacy, FIT) @@ -1837,7 +1838,7 @@ FIT uImage format: 120 common/image.c Start initial ramdisk verification -120 common/image.c Ramdisk FIT image has incorrect format 121 common/image.c Ramdisk FIT image has correct format - 122 common/image.c No Ramdisk subimage unit name, using configuration + 122 common/image.c No ramdisk subimage unit name, using configuration -122 common/image.c Can't get configuration for ramdisk subimage 123 common/image.c Ramdisk unit name specified -124 common/image.c Can't get ramdisk subimage node offset @@ -1851,13 +1852,13 @@ FIT uImage format: 129 common/image.c Can't get ramdisk load address -129 common/image.c Got ramdisk load address - -130 common/cmd_doc.c Icorrect FIT image format + -130 common/cmd_doc.c Incorrect FIT image format 131 common/cmd_doc.c FIT image format OK - -140 common/cmd_ide.c Icorrect FIT image format + -140 common/cmd_ide.c Incorrect FIT image format 141 common/cmd_ide.c FIT image format OK - -150 common/cmd_nand.c Icorrect FIT image format + -150 common/cmd_nand.c Incorrect FIT image format 151 common/cmd_nand.c FIT image format OK @@ -1866,7 +1867,7 @@ Modem Support: [so far only for SMDK2400 and TRAB boards] -- Modem support endable: +- Modem support enable: CONFIG_MODEM_SUPPORT - RTS/CTS Flow control enable: @@ -1882,11 +1883,11 @@ Modem Support: There are common interrupt_init() and timer_interrupt() for all PPC archs. interrupt_init() calls interrupt_init_cpu() - for cpu specific initialization. interrupt_init_cpu() + for CPU specific initialization. interrupt_init_cpu() should set decrementer_count to appropriate value. If - cpu resets decrementer automatically after interrupt + CPU resets decrementer automatically after interrupt (ppc4xx) it should set decrementer_count to zero. - timer_interrupt() calls timer_interrupt_cpu() for cpu + timer_interrupt() calls timer_interrupt_cpu() for CPU specific handling. If board has watchdog / status_led / other_activity_monitor it works automatically from general timer_interrupt(). @@ -1896,7 +1897,7 @@ Modem Support: In the target system modem support is enabled when a specific key (key combination) is pressed during power-on. Otherwise U-Boot will boot normally - (autoboot). The key_pressed() fuction is called from + (autoboot). The key_pressed() function is called from board_init(). Currently key_pressed() is a dummy function, returning 1 and thus enabling modem initialization. @@ -1904,7 +1905,7 @@ Modem Support: If there are no modem init strings in the environment, U-Boot proceed to autoboot; the previous output (banner, info printfs) will be - supressed, though. + suppressed, though. See also: doc/README.Modem @@ -1960,7 +1961,7 @@ Configuration Settings: - CFG_MEM_TOP_HIDE (PPC only): If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top - (end) of ram and won't get "touched" at all by U-Boot. By + (end) of RAM and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux @@ -2055,8 +2056,8 @@ Configuration Settings: The two-step approach is usually more reliable, since you can check if the download worked before you erase - the flash, but in some situations (when sytem RAM is - too limited to allow for a tempory copy of the + the flash, but in some situations (when system RAM is + too limited to allow for a temporary copy of the downloaded image) this option may be very useful. - CFG_FLASH_CFI: @@ -2086,11 +2087,11 @@ Configuration Settings: column displays, 15 (3..1) for 40 column displays. - CFG_RX_ETH_BUFFER: - Defines the number of ethernet receive buffers. On some - ethernet controllers it is recommended to set this value + Defines the number of Ethernet receive buffers. On some + Ethernet controllers it is recommended to set this value to 8 or even higher (EEPRO100 or 405 EMAC), since all buffers can be full shortly after enabling the interface - on high ethernet traffic. + on high Ethernet traffic. Defaults to 4 if not defined. The following definitions that deal with the placement and management @@ -2158,7 +2159,7 @@ following configurations: CFG_ENV_SIZE_REDUND These settings describe a second storage area used to hold - a redundand copy of the environment data, so that there is + a redundant copy of the environment data, so that there is a valid backup copy in case there is a power failure during a "saveenv" operation. @@ -2176,14 +2177,14 @@ accordingly! - CFG_ENV_ADDR: - CFG_ENV_SIZE: - These two #defines are used to determin the memory area you + These two #defines are used to determine the memory area you want to use for environment. It is assumed that this memory can just be read and written to, without any special provision. BE CAREFUL! The first access to the environment happens quite early in U-Boot initalization (when we try to get the setting of for the -console baudrate). You *MUST* have mappend your NVRAM area then, or +console baudrate). You *MUST* have mapped your NVRAM area then, or U-Boot will hang. Please note that even with NVRAM we still use a copy of the @@ -2332,14 +2333,14 @@ Low Level (hardware related) configuration options: CFG_ISA_IO_STRIDE - defines the spacing between fdc chipset registers + defines the spacing between FDC chipset registers (default value 1) CFG_ISA_IO_OFFSET defines the offset of register from address. It depends on which part of the data bus is connected to - the fdc chipset. (default value 0) + the FDC chipset. (default value 0) If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and CFG_FDC_DRIVE_NUMBER are undefined, they take their @@ -2535,7 +2536,7 @@ Low Level (hardware related) configuration options: Normally these variables MUST NOT be defined. The only exception is when U-Boot is loaded (to RAM) by some other boot loader or by a debugger which - performs these intializations itself. + performs these initializations itself. Building the Software: @@ -2570,7 +2571,7 @@ Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for instance, the TQM823L systems are available without (standard) or with LCD support. You can select such additional "features" - when chosing the configuration, i. e. + when choosing the configuration, i. e. make TQM823L_config - will configure for a plain TQM823L, i. e. no LCD support @@ -2773,7 +2774,7 @@ Some configuration options can be set using Environment Variables: for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the descripton of CFG_BOOTMAPSZ. + kernel -- see the description of CFG_BOOTMAPSZ. bootm_size - Memory range available for image processing in the bootm command can be restricted. This variable is given as @@ -2880,7 +2881,7 @@ Some configuration options can be set using Environment Variables: themselves. npe_ucode - see CONFIG_IXP4XX_NPE_EXT_UCOD - if set load address for the npe microcode + if set load address for the NPE microcode tftpsrcport - If this is set, the value is used for TFTP's UDP source port. @@ -2889,7 +2890,7 @@ Some configuration options can be set using Environment Variables: destination port instead of the Well Know Port 69. vlan - When set to a value < 4095 the traffic over - ethernet is encapsulated/received over 802.1q + Ethernet is encapsulated/received over 802.1q VLAN tagged frames. The following environment variables may be used and automatically @@ -2967,14 +2968,14 @@ General rules: executed anyway. (2) If you execute several variables with one call to run (i. e. - calling run with a list af variables as arguments), any failing + calling run with a list of variables as arguments), any failing command will cause "run" to terminate, i. e. the remaining variables are not executed. Note for Redundant Ethernet Interfaces: ======================================= -Some boards come with redundant ethernet interfaces; U-Boot supports +Some boards come with redundant Ethernet interfaces; U-Boot supports such configurations and is capable of automatic selection of a "working" interface when needed. MAC assignment works as follows: @@ -3315,7 +3316,7 @@ parameters. You can check and modify this variable using the Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000] ... -If you want to boot a Linux kernel with initial ram disk, you pass +If you want to boot a Linux kernel with initial RAM disk, you pass the memory addresses of both the kernel and the initrd image (PPBCOOT format!) to the "bootm" command: @@ -3625,13 +3626,13 @@ locked as (mis-) used as memory, etc. require any physical RAM backing up the cache. The cleverness is that the cache is being used as a temporary supply of necessary storage before the SDRAM controller is setup. It's - beyond the scope of this list to expain the details, but you + beyond the scope of this list to explain the details, but you can see how this works by studying the cache architecture and operation in the architecture and processor-specific manuals. OCM is On Chip Memory, which I believe the 405GP has 4K. It is another option for the system designer to use as an - initial stack/ram area prior to SDRAM being available. Either + initial stack/RAM area prior to SDRAM being available. Either option should work for you. Using CS 4 should be fine if your board designers haven't used it for something that would cause you grief during the initial boot! It is frequently not @@ -3656,7 +3657,7 @@ code for the initialization procedures: * Initialized global data (data segment) is read-only. Do not attempt to write it. -* Do not use any unitialized global data (or implicitely initialized +* Do not use any uninitialized global data (or implicitely initialized as zero data - BSS segment) at all - this is undefined, initiali- zation is performed later (when relocating to RAM). @@ -3768,7 +3769,7 @@ System Initialization: ---------------------- In the reset configuration, U-Boot starts at the reset entry point -(on most PowerPC systens at address 0x00000100). Because of the reset +(on most PowerPC systems at address 0x00000100). Because of the reset configuration for CS0# this is a mirror of the onboard Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) diff --git a/board/MigoR/Makefile b/board/MigoR/Makefile index bced511..661b59d 100644 --- a/board/MigoR/Makefile +++ b/board/MigoR/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := migo_r.o +COBJS := migo_r.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 7e39817..8efa703 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -153,10 +153,8 @@ void ether_init(void) do { __raw_writew(0x1, LAN_RESET_REGISTER); udelay(100); - if (cnt == 0) { - printf("1. eth reset err\n"); + if (cnt == 0) goto eth_reset_err_out; - } --cnt; } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); @@ -165,10 +163,8 @@ void ether_init(void) do { __raw_writew(0x0, LAN_RESET_REGISTER); udelay(100); - if (cnt == 0) { - printf("2. eth reset err\n"); + if (cnt == 0) goto eth_reset_err_out; - } --cnt; } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); udelay(1000); diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 3e952d8..24e8db0 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -275,7 +275,7 @@ static void ft_blob_update(void *blob, bd_t *bd) ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); if (ret < 0) { - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } } diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile index 579efe2..fb31ee4 100644 --- a/board/davinci/sffsdr/Makefile +++ b/board/davinci/sffsdr/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := dv_board.o +COBJS := $(BOARD).o SOBJS := board_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk index e8a329c..f3b23d1 100644 --- a/board/davinci/sffsdr/config.mk +++ b/board/davinci/sffsdr/config.mk @@ -3,8 +3,10 @@ # Gary Jennejohn, DENX Software Engineering, <gj@denx.de> # David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> # +# Copyright (C) 2008 Lyrtech <www.lyrtech.com> +# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> +# # Lyrtech SFF SDR board (ARM926EJS) cpu -# see http://www.lyrtech.com/ for more information on Lyrtech # # SFF SDR board has 1 bank of 128 MB DDR RAM # Physical Address: @@ -16,9 +18,6 @@ # Integrity kernel is expected to be at 8000'0000, entry 8000'00D0, # up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc). # -# we load ourself to 8400'0000 -# -# - -# Provide at least 32MB spacing between us and the Integrity kernel image +# we load ourself to 8400'0000 to provide at least 32MB spacing +# between us and the Integrity kernel image TEXT_BASE = 0x84000000 diff --git a/board/davinci/sffsdr/dv_board.c b/board/davinci/sffsdr/dv_board.c deleted file mode 100644 index 0771b5b..0000000 --- a/board/davinci/sffsdr/dv_board.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * ----------------------------------------------------------------- - * - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * ---------------------------------------------------------------------------- - */ - -#include <common.h> -#include <i2c.h> -#include <asm/arch/hardware.h> -#include <asm/arch/emac_defs.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void timer_init(void); -extern int eth_hw_init(void); -extern phy_t phy; - - -/* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) -{ - dv_reg_p mdstat, mdctl; - - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - - while (REG(PSC_PTSTAT) & 0x01); - - if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ - - *mdctl |= 0x03; - - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - if ((id == DAVINCI_LPSC_VPSSSLV) || - (id == DAVINCI_LPSC_EMAC) || - (id == DAVINCI_LPSC_EMAC_WRAPPER) || - (id == DAVINCI_LPSC_MDIO) || - (id == DAVINCI_LPSC_USB) || - (id == DAVINCI_LPSC_ATA) || - (id == DAVINCI_LPSC_VLYNQ) || - (id == DAVINCI_LPSC_UHPI) || - (id == DAVINCI_LPSC_DDR_EMIF) || - (id == DAVINCI_LPSC_AEMIF) || - (id == DAVINCI_LPSC_MMC_SD) || - (id == DAVINCI_LPSC_MEMSTICK) || - (id == DAVINCI_LPSC_McBSP) || - (id == DAVINCI_LPSC_GPIO)) - * mdctl |= 0x200; - - REG(PSC_PTCMD) = 0x01; - - while (REG(PSC_PTSTAT) & 0x03); - while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ -} - -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} - - -int board_init(void) -{ - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* Workaround for TMS320DM6446 errata 1.3.22 */ - REG(PSC_SILVER_BULLET) = 0; - - /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - lpsc_on(DAVINCI_LPSC_I2C); - lpsc_on(DAVINCI_LPSC_UART0); - lpsc_on(DAVINCI_LPSC_TIMER1); - lpsc_on(DAVINCI_LPSC_GPIO); - - /* Powerup the DSP */ - dsp_on(); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= 1; - - /* Enable EMAC and AEMIF pins */ - REG(PINMUX0) = 0x80000c1f; - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= (1 << 7); - - /* Set the Bus Priority Register to appropriate value */ - REG(VBPR) = 0x20; - - timer_init(); - - return(0); -} - -int misc_init_r(void) -{ - u_int8_t tmp[20], buf[10]; - int i = 0; - int clk = 0; - - clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); - - printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); - printf("DDR Clock: %dMHz\n", (clk / 2)); - - /* Configure I2C switch (PCA9543) to enable channel 0. */ - tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0; - if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, - CFG_I2C_PCA9543_ADDR_LEN, tmp, 1)) - printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); - - /* Set Ethernet MAC address from EEPROM. - * We must read 8 bytes because data is stored in little-endian. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8, - CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) { - printf("Read from EEPROM @ 0x%02x failed\n", - CFG_I2C_EEPROM_ADDR); - } else { - tmp[0] = 0xff; - for (i = 0; i < 6; i++) - tmp[0] &= buf[i]; - - if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], - "%02x:%02x:%02x:%02x:%02x:%02x", - buf[3], buf[2], buf[1], buf[0], - buf[7], buf[6]); - setenv("ethaddr", (char *)&tmp[0]); - } - } - - if (!eth_hw_init()) { - printf("Ethernet init failed\n"); - } else { - printf("ETH PHY: %s\n", phy.name); - } - - return(0); -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return(0); -} diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c new file mode 100644 index 0000000..b73484a --- /dev/null +++ b/board/davinci/sffsdr/sffsdr.c @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ +#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ + +#define INTEGRITY_SYSCFG_OFFSET 0x7E8 +#define INTEGRITY_CHECKWORD_OFFSET 0x7F8 +#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF + +DECLARE_GLOBAL_DATA_PTR; + +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01); + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + switch (id) { + case DAVINCI_LPSC_VPSSSLV: + case DAVINCI_LPSC_EMAC: + case DAVINCI_LPSC_EMAC_WRAPPER: + case DAVINCI_LPSC_MDIO: + case DAVINCI_LPSC_USB: + case DAVINCI_LPSC_ATA: + case DAVINCI_LPSC_VLYNQ: + case DAVINCI_LPSC_UHPI: + case DAVINCI_LPSC_DDR_EMIF: + case DAVINCI_LPSC_AEMIF: + case DAVINCI_LPSC_MMC_SD: + case DAVINCI_LPSC_MEMSTICK: + case DAVINCI_LPSC_McBSP: + case DAVINCI_LPSC_GPIO: + *mdctl |= 0x200; + break; + } + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03); + while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ +} + +#if !defined(CFG_USE_DSPLINK) +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} +#endif /* CFG_USE_DSPLINK */ + +int board_init(void) +{ + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + +#if !defined(CFG_USE_DSPLINK) + /* Powerup the DSP */ + dsp_on(); +#endif /* CFG_USE_DSPLINK */ + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +/* Read ethernet MAC address from Integrity data structure inside EEPROM. */ +int read_mac_address(uint8_t *buf) +{ + u_int32_t value, mac[2], address; + + /* Read Integrity data structure checkword. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + if (value != INTEGRITY_CHECKWORD_VALUE) + return 1; + + /* Read SYSCFG structure offset. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + address = 0x800 + (int) value; /* Address of SYSCFG structure. */ + + /* Read NET CONFIG structure offset. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, address, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + address = 0x800 + (int) value; /* Address of NET CONFIG structure. */ + address += 12; /* Address of NET INTERFACE CONFIG structure. */ + + /* Read NET INTERFACE CONFIG 2 structure offset. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, address, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + goto err; + address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE + * CONFIG 2 structure. */ + + /* Read MAC address. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, address, + CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) + goto err; + + buf[0] = mac[0] >> 24; + buf[1] = mac[0] >> 16; + buf[2] = mac[0] >> 8; + buf[3] = mac[0]; + buf[4] = mac[1] >> 24; + buf[5] = mac[1] >> 16; + + return 0; + +err: + printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); + return 1; +} + +/* Platform dependent initialisation. */ +int misc_init_r(void) +{ + int i; + u_int8_t i2cbuf; + u_int8_t env_enetaddr[6], eeprom_enetaddr[6]; + char *tmp = getenv("ethaddr"); + char *end; + int clk; + + /* EMIF-A CS3 configuration for FPGA. */ + REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); + printf("DDR Clock: %dMHz\n", (clk / 2)); + + /* Configure I2C switch (PCA9543) to enable channel 0. */ + i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0; + if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, + CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { + printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); + return 1; + } + + /* Read Ethernet MAC address from the U-Boot environment. */ + for (i = 0; i < 6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* Read Ethernet MAC address from EEPROM. */ + if (read_mac_address(eeprom_enetaddr) == 0) { + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && + memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) { + printf("\nWarning: MAC addresses don't match:\n"); + printf("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + eeprom_enetaddr[0], eeprom_enetaddr[1], + eeprom_enetaddr[2], eeprom_enetaddr[3], + eeprom_enetaddr[4], eeprom_enetaddr[5]); + printf("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + env_enetaddr[0], env_enetaddr[1], + env_enetaddr[2], env_enetaddr[3], + env_enetaddr[4], env_enetaddr[5]) ; + debug("### Set MAC addr from environment\n"); + memcpy(eeprom_enetaddr, env_enetaddr, 6); + } + if (!tmp) { + char ethaddr[20]; + + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + eeprom_enetaddr[0], eeprom_enetaddr[1], + eeprom_enetaddr[2], eeprom_enetaddr[3], + eeprom_enetaddr[4], eeprom_enetaddr[5]) ; + debug("### Set environment from HW MAC addr = \"%s\"\n", + ethaddr); + setenv("ethaddr", ethaddr); + } + } + + if (!eth_hw_init()) { + printf("Ethernet init failed\n"); + } else { + printf("ETH PHY: %s\n", phy.name); + } + + /* On this platform, U-Boot is copied in RAM by the UBL, + * so we are always in the relocated state. */ + gd->flags |= GD_FLG_RELOC; + + return(0); +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index 6f683f0..8ab7d35 100644 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c @@ -46,6 +46,10 @@ #ifdef CONFIG_PCI #include <pci.h> #endif +#ifdef CONFIG_OF_LIBFDT +#include <libfdt.h> +#include <fdt_support.h> +#endif /* * I/O Port configuration table @@ -544,3 +548,26 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_blob_update(void *blob, bd_t *bd) +{ + int ret; + + ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + + if (ret < 0) { + printf("ft_blob_update(): cannot set /memory/reg " + "property err:%s\n", fdt_strerror(ret)); + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_blob_update(blob, bd); +} +#endif diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 8ec4cd7..44fc79c 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -334,7 +334,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); if (ret < 0) { - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } } diff --git a/board/mgcoge/mgcoge.c b/board/mgcoge/mgcoge.c index 89ced1e..51b6dc6 100644 --- a/board/mgcoge/mgcoge.c +++ b/board/mgcoge/mgcoge.c @@ -307,7 +307,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, sizeof(memory_data)); if (ret < 0) - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } else { @@ -327,7 +327,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, sizeof(flash_data)); if (ret < 0) - printf("ft_blob_update): cannot set /localbus/ranges " + printf("ft_blob_update(): cannot set /localbus/ranges " "property err:%s\n", fdt_strerror(ret)); } else { @@ -341,7 +341,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, sizeof(uchar) * 6); if (ret < 0) - printf("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " + printf("ft_blob_update(): cannot set /soc/cpm/ethernet/mac-address " "property err:%s\n", fdt_strerror(ret)); } else { diff --git a/board/mgsuvd/mgsuvd.c b/board/mgsuvd/mgsuvd.c index d81cafb..c51ea7e 100644 --- a/board/mgsuvd/mgsuvd.c +++ b/board/mgsuvd/mgsuvd.c @@ -164,7 +164,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, sizeof(memory_data)); if (ret < 0) - printf("ft_blob_update): cannot set /memory/reg " + printf("ft_blob_update(): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } else { @@ -180,7 +180,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, sizeof(flash_data)); if (ret < 0) - printf("ft_blob_update): cannot set /localbus/ranges " + printf("ft_blob_update(): cannot set /localbus/ranges " "property err:%s\n", fdt_strerror(ret)); } else { @@ -195,7 +195,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data, sizeof(brg_data)); if (ret < 0) - printf("ft_blob_update): cannot set /soc/cpm/brg-frequency " + printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency " "property err:%s\n", fdt_strerror(ret)); } else { @@ -209,7 +209,7 @@ void ft_blob_update(void *blob, bd_t *bd) ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, sizeof(uchar) * 6); if (ret < 0) - printf("ft_blob_update): cannot set /soc/cpm/scc/mac-address " + printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address " "property err:%s\n", fdt_strerror(ret)); } else { diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile index 080476b..9f8fb80 100644 --- a/board/mpr2/Makefile +++ b/board/mpr2/Makefile @@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := mpr2.o +COBJS := mpr2.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile index 545889f..18745ec 100644 --- a/board/ms7720se/Makefile +++ b/board/ms7720se/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := ms7720se.o +COBJS := ms7720se.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c index ad76c0b..af62cdf 100644 --- a/board/ms7720se/ms7720se.c +++ b/board/ms7720se/ms7720se.c @@ -40,7 +40,6 @@ int checkboard(void) int board_init(void) { - return 0; } diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile index 744744e..b203b6d 100644 --- a/board/ms7722se/Makefile +++ b/board/ms7722se/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := ms7722se.o +COBJS := ms7722se.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c index 0d3d55c..cf02242 100644 --- a/board/ms7722se/ms7722se.c +++ b/board/ms7722se/ms7722se.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 + * Copyright (C) 2007,2008 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * Copyright (C) 2007 @@ -43,7 +43,7 @@ int board_init(void) return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -53,7 +53,7 @@ int dram_init (void) return 0; } -void led_set_state (unsigned short value) +void led_set_state(unsigned short value) { - *((volatile unsigned short *) LED_BASE) = (value & 0xFF); + writew(value & 0xFF, LED_BASE); } diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile index d806101..01ddf69 100644 --- a/board/ms7750se/Makefile +++ b/board/ms7750se/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := ms7750se.o +COBJS := ms7750se.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile index 8529857..e96a8aa 100644 --- a/board/r2dplus/Makefile +++ b/board/r2dplus/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := r2dplus.o +COBJS := r2dplus.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c index 2ee3ea2..8fb8ff6 100644 --- a/board/r2dplus/r2dplus.c +++ b/board/r2dplus/r2dplus.c @@ -24,6 +24,7 @@ #include <common.h> #include <ide.h> #include <asm/processor.h> +#include <asm/io.h> #include <asm/pci.h> int checkboard(void) @@ -37,7 +38,7 @@ int board_init(void) return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -52,25 +53,26 @@ int board_late_init(void) return 0; } -#define FPGA_BASE 0xA4000000 -#define FPGA_CFCTL (FPGA_BASE + 0x04) -#define FPGA_CFPOW (FPGA_BASE + 0x06) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) +#define FPGA_BASE 0xA4000000 +#define FPGA_CFCTL (FPGA_BASE + 0x04) +#define CFCTL_EN (0x432) +#define FPGA_CFPOW (FPGA_BASE + 0x06) +#define CFPOW_ON (0x02) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) +#define CFCDINTCLR_EN (0x01) -void ide_set_reset (int idereset) +void ide_set_reset(int idereset) { /* if reset = 1 IDE reset will be asserted */ - if (idereset){ - (*(vu_short *)FPGA_CFCTL) = 0x432; - (*(vu_short *)FPGA_CFPOW) |= 0x02; - (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + if (idereset) { + outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ + outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ + outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ } } -#if defined(CONFIG_PCI) static struct pci_controller hose; void pci_init_board(void) { - pci_sh7751_init( &hose ); + pci_sh7751_init(&hose); } -#endif /* CONFIG_PCI */ diff --git a/board/r7780mp/Makefile b/board/r7780mp/Makefile index 0ab6d1d..c100e7e 100644 --- a/board/r7780mp/Makefile +++ b/board/r7780mp/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := r7780mp.o +COBJS := r7780mp.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c index 1a37711..19c35d3 100644 --- a/board/r7780mp/r7780mp.c +++ b/board/r7780mp/r7780mp.c @@ -38,12 +38,12 @@ int checkboard(void) int board_init(void) { /* SCIF Enable */ - *(vu_short*)PHCR = 0x0000; + writew(0x0, PHCR); return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -53,29 +53,27 @@ int dram_init (void) return 0; } -void led_set_state (unsigned short value) +void led_set_state(unsigned short value) { } -void ide_set_reset (int idereset) +void ide_set_reset(int idereset) { /* if reset = 1 IDE reset will be asserted */ - if (idereset){ - (*(vu_short *)FPGA_CFCTL) = 0x432; + if (idereset) { + writew(0x432, FPGA_CFCTL); #if defined(CONFIG_R7780MP) - (*(vu_short *)FPGA_CFPOW) |= 0x01; + writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); #else - (*(vu_short *)FPGA_CFPOW) |= 0x02; + writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); #endif - (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + writew(0x01, FPGA_CFCDINTCLR); } } -#if defined(CONFIG_PCI) static struct pci_controller hose; void pci_init_board(void) { - pci_sh7780_init( &hose ); + pci_sh7780_init(&hose); } -#endif diff --git a/board/sh7763rdp/Makefile b/board/sh7763rdp/Makefile index 8a04477..62a683d 100644 --- a/board/sh7763rdp/Makefile +++ b/board/sh7763rdp/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS := sh7763rdp.o +COBJS := sh7763rdp.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/sh7763rdp/sh7763rdp.c b/board/sh7763rdp/sh7763rdp.c index 6f9501b..92ac7b7 100644 --- a/board/sh7763rdp/sh7763rdp.c +++ b/board/sh7763rdp/sh7763rdp.c @@ -49,19 +49,20 @@ int board_init(void) { vu_short dat; - *(vu_short *)(CPU_CMDREG) |= 0x0001; + /* Enable mode */ + writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); /* GPIO Setting (eth1) */ - dat = *(vu_short *)(PSEL1); - *(vu_short *)PSEL1 = ((dat & ~0xff00) | 0x2400); - *(vu_short *)PFCR = 0; - *(vu_short *)PGCR = 0; - *(vu_short *)PHCR = 0; + dat = inw(PSEL1); + writew(((dat & ~0xff00) | 0x2400), PSEL1); + writew(0, PFCR); + writew(0, PGCR); + writew(0, PHCR); return 0; } -int dram_init (void) +int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -71,6 +72,6 @@ int dram_init (void) return 0; } -void led_set_state (unsigned short value) +void led_set_state(unsigned short value) { } diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 97b9dd7..d3b19dd 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -451,14 +451,14 @@ static int fdt_valid(void) if (err == -FDT_ERR_BADVERSION) { if (fdt_version(working_fdt) < FDT_FIRST_SUPPORTED_VERSION) { - printf (" - too old, fdt $d < %d", + printf (" - too old, fdt %d < %d", fdt_version(working_fdt), FDT_FIRST_SUPPORTED_VERSION); working_fdt = NULL; } if (fdt_last_comp_version(working_fdt) > FDT_LAST_SUPPORTED_VERSION) { - printf (" - too new, fdt $d > %d", + printf (" - too new, fdt %d > %d", fdt_version(working_fdt), FDT_LAST_SUPPORTED_VERSION); working_fdt = NULL; @@ -546,7 +546,7 @@ static int fdt_parse_prop(char **newval, int count, char *data, int *len) newp = newval[++stridx]; } if (*newp != ']') { - printf("Unexpected character '%c'\n", *newval); + printf("Unexpected character '%c'\n", *newp); return 1; } } else { @@ -763,7 +763,7 @@ static int fdt_print(const char *pathp, char *prop, int depth) } break; case FDT_NOP: - printf("/* NOP */\n", &tabs[MAX_LEVEL - level]); + printf("%s/* NOP */\n", &tabs[MAX_LEVEL - level]); break; case FDT_END: return 1; diff --git a/common/env_common.c b/common/env_common.c index e6df9a5..d51c211 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -50,7 +50,6 @@ extern void env_relocate_spec (void); extern uchar env_get_char_spec(int); static uchar env_get_char_init (int index); -uchar (*env_get_char)(int) = env_get_char_init; /************************************************************************ * Default settings to be used when no valid environment is found @@ -183,6 +182,19 @@ uchar env_get_char_memory (int index) } #endif +uchar env_get_char (int index) +{ + uchar c; + + /* if relocated to RAM */ + if (gd->flags & GD_FLG_RELOC) + c = env_get_char_memory(index); + else + c = env_get_char_init(index); + + return (c); +} + uchar *env_get_addr (int index) { if (gd->env_valid) { @@ -192,6 +204,23 @@ uchar *env_get_addr (int index) } } +void set_default_env(void) +{ + if (sizeof(default_environment) > ENV_SIZE) { + puts ("*** Error - default environment is too large\n\n"); + return; + } + + memset(env_ptr, 0, sizeof(env_t)); + memcpy(env_ptr->data, default_environment, + sizeof(default_environment)); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update (); + gd->env_valid = 1; +} + void env_relocate (void) { DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, @@ -216,11 +245,6 @@ void env_relocate (void) DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); #endif - /* - * After relocation to RAM, we can always use the "memory" functions - */ - env_get_char = env_get_char_memory; - if (gd->env_valid == 0) { #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ puts ("Using default environment\n\n"); @@ -228,22 +252,7 @@ void env_relocate (void) puts ("*** Warning - bad CRC, using default environment\n\n"); show_boot_progress (-60); #endif - - if (sizeof(default_environment) > ENV_SIZE) - { - puts ("*** Error - default environment is too large\n\n"); - return; - } - - memset (env_ptr, 0, sizeof(env_t)); - memcpy (env_ptr->data, - default_environment, - sizeof(default_environment)); -#ifdef CFG_REDUNDAND_ENVIRONMENT - env_ptr->flags = 0xFF; -#endif - env_crc_update (); - gd->env_valid = 1; + set_default_env(); } else { env_relocate_spec (); diff --git a/common/env_nand.c b/common/env_nand.c index 1fe874a..104f085 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -363,19 +363,7 @@ void env_relocate_spec (void) static void use_default() { puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); - - if (default_environment_size > CFG_ENV_SIZE){ - puts ("*** Error - default environment is too large\n\n"); - return; - } - - memset (env_ptr, 0, sizeof(env_t)); - memcpy (env_ptr->data, - default_environment, - default_environment_size); - env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); - gd->env_valid = 1; - + set_default_env(); } #endif diff --git a/common/main.c b/common/main.c index 046da6f..79ad291 100644 --- a/common/main.c +++ b/common/main.c @@ -509,7 +509,7 @@ void reset_cmd_timeout(void) */ #define putnstr(str,n) do { \ - printf ("%.*s", n, str); \ + printf ("%.*s", (int)n, str); \ } while (0) #define CTL_CH(c) ((c) - 'a' + 1) diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c index 4edcc9a..260d393 100644 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -29,6 +29,7 @@ #include <common.h> #include <at91rm9200_net.h> #include <net.h> +#include <miiphy.h> #include <lxt971a.h> #ifdef CONFIG_DRIVER_ETHER @@ -51,8 +52,8 @@ unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) unsigned short Id1, Id2; at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2); + at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1); + at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2); at91rm9200_EmacDisableMDIO (p_mac); if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) @@ -169,18 +170,18 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) unsigned short value; /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value)) + if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value)) return FALSE; /* Restart Auto_negotiation */ - value |= PHY_COMMON_CTRL_RES_AUTO; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value)) + value |= PHY_BMCR_RST_NEG; + if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value)) return FALSE; /*check AutoNegotiate complete */ udelay (10000); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value); - if (!(value & PHY_COMMON_STAT_AN_COMP)) + at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value); + if (!(value & PHY_BMSR_AUTN_COMP)) return FALSE; return (lxt972_GetLinkSpeed (p_mac)); diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c index 6eeb6e5..8130b48 100644 --- a/cpu/arm926ejs/davinci/lxt972.c +++ b/cpu/arm926ejs/davinci/lxt972.c @@ -27,6 +27,7 @@ #include <common.h> #include <net.h> +#include <miiphy.h> #include <lxt971a.h> #include <asm/arch/emac_defs.h> @@ -36,11 +37,11 @@ int lxt972_is_phy_connected(int phy_addr) { - u_int16_t id1, id2; + u_int16_t id1, id2; - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) + if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1)) return(0); - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) + if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2)) return(0); if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) @@ -51,8 +52,8 @@ int lxt972_is_phy_connected(int phy_addr) int lxt972_get_link_speed(int phy_addr) { - u_int16_t stat1, tmp; - volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + u_int16_t stat1, tmp; + volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) return(0); @@ -70,37 +71,23 @@ int lxt972_get_link_speed(int phy_addr) if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) return(0); - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (stat1 & PHY_LXT971_STAT2_100BTX) { - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE; } else { - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; } - return(0); + return(1); } int lxt972_init_phy(int phy_addr) { - int ret = 1; + int ret = 1; if (!lxt972_get_link_speed(phy_addr)) { /* Try another time */ @@ -116,22 +103,21 @@ int lxt972_init_phy(int phy_addr) int lxt972_auto_negotiate(int phy_addr) { - u_int16_t tmp; - + u_int16_t tmp; - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_COMMON_CTRL_RES_AUTO; - dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); + tmp |= PHY_BMCR_RST_NEG; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) return(0); - if (!(tmp & PHY_COMMON_STAT_AN_COMP)) + if (!(tmp & PHY_BMSR_AUTN_COMP)) return(0); return (lxt972_get_link_speed(phy_addr)); diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index d16c58b..33dc427 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -35,7 +35,6 @@ COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o COBJS-y += pio.o -COBJS-$(CONFIG_MMC) += atmel_mci.o SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 75c6ab2..940f5c0 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -33,6 +33,10 @@ #include <mpc8260.h> #include <asm/m8260_pci.h> #include <asm/io.h> +#ifdef CONFIG_OF_LIBFDT +#include <libfdt.h> +#include <fdt_support.h> +#endif #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 DECLARE_GLOBAL_DATA_PTR; @@ -449,4 +453,12 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); } +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "pci", 4, + "clock-frequency", bd->pci_clk, 1); +} +#endif + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index cc03f8a..52e4476 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -357,3 +357,23 @@ int dma_xfer(void *dest, u32 count, void *src) return ((int)dma_check()); } #endif /*CONFIG_DDR_ECC*/ + +#ifdef CONFIG_TSEC_ENET +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif + return 0; +} +#endif diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0f72051..0d50549 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -353,3 +353,33 @@ void upmconfig (uint upm, uint * table, uint size) } out_be32(mxmr, loopval); /* OP_NORMAL */ } + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC) +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif +#if defined(CONFIG_MPC85XX_FEC) + tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); +#else +#if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); +#endif +#if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#endif +#endif + return 0; +} +#endif diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index fd36658..0eab694 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -216,10 +216,10 @@ MachineCheckException(struct pt_regs *regs) if (machinecheck_count > 1) { regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08x\n", + printf("Skipping current instr, Returning to 0x%08lx\n", regs->nip); } else { - printf("Returning back to 0x%08x\n",regs->nip); + printf("Returning back to 0x%08lx\n",regs->nip); } } @@ -302,7 +302,7 @@ ExtIntException(struct pt_regs *regs) printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", regs->nip, regs->msr, regs->trap); vect = pic->iack0; - printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect); + printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); machinecheck_count++; @@ -310,7 +310,7 @@ ExtIntException(struct pt_regs *regs) printf("Returning back to 0x%08x\n",regs->nip); #else regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08x\n",regs->nip); + printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip); #endif } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index e26bf36..4eaed05 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -290,3 +290,30 @@ void mpc86xx_reginfo(void) printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); } + +#ifdef CONFIG_TSEC_ENET +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif +#if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); +#endif +#if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#endif + return 0; +} +#endif + diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 1cdb709..23005e2 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -128,7 +128,7 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ diff --git a/cpu/sh3/Makefile b/cpu/sh3/Makefile index a7eb1e2..587413d 100644 --- a/cpu/sh3/Makefile +++ b/cpu/sh3/Makefile @@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a SOBJS = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o cache.o +COBJS = cpu.o interrupts.o watchdog.o time.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile index e38e04f..d3c5eef 100644 --- a/cpu/sh4/Makefile +++ b/cpu/sh4/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a SOBJS = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o cache.o +COBJS = cpu.o interrupts.o watchdog.o time.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile new file mode 100644 index 0000000..3dc031b --- /dev/null +++ b/drivers/mmc/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libmmc.a + +COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/at32ap/atmel_mci.c b/drivers/mmc/atmel_mci.c index 61aa184..61aa184 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c diff --git a/cpu/at32ap/atmel_mci.h b/drivers/mmc/atmel_mci.h index 5b4f5c9..5b4f5c9 100644 --- a/cpu/at32ap/atmel_mci.h +++ b/drivers/mmc/atmel_mci.h diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index b958d17..9845e93 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -42,7 +42,7 @@ #define MANUFACTURER_SST 0x00BF /* AMD */ -#define AM29DL800BB 0x22C8 +#define AM29DL800BB 0x22CB #define AM29DL800BT 0x224A #define AM29F800BB 0x2258 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 84be288..bcf31cb 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -66,6 +66,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_SH_ETHER) += sh_eth.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index c31029a..060b518 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -75,6 +75,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, @@ -636,6 +637,7 @@ e1000_set_mac_type(struct e1000_hw *hw) hw->mac_type = e1000_82540; break; case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545GM_COPPER: case E1000_DEV_ID_82545EM_FIBER: hw->mac_type = e1000_82545; break; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 23b2eb9..c258bc2 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -217,13 +217,14 @@ struct e1000_phy_stats { #define E1000_DEV_ID_82544GC_LOM 0x100D #define E1000_DEV_ID_82540EM 0x100E #define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82545GM_COPPER 0x1026 #define E1000_DEV_ID_82545EM_COPPER 0x100F #define E1000_DEV_ID_82545EM_FIBER 0x1011 #define E1000_DEV_ID_82546EB_COPPER 0x1010 #define E1000_DEV_ID_82546EB_FIBER 0x1012 #define E1000_DEV_ID_82541ER 0x1078 #define E1000_DEV_ID_82541GI_LF 0x107C -#define NUM_DEV_IDS 15 +#define NUM_DEV_IDS 16 #define NODE_ADDRESS_SIZE 6 #define ETH_LENGTH_OF_ADDRESS 6 diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index 2da57b6..ec92485 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -758,8 +758,6 @@ static hw_info_t hw_info[] = { #define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t)) -u8 dev_addr[6]; - #define PCNET_CMD 0x00 #define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ #define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ @@ -769,14 +767,14 @@ static void pcnet_reset_8390(void) { int i, r; - PRINTK("nic base is %lx\n", nic_base); + PRINTK("nic base is %lx\n", nic.base); n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); @@ -852,8 +850,6 @@ int __get_prom(u8* mac_addr) return 0; } -u32 nic_base; - /* U-boot specific routines */ static u8 *pbuf = NULL; @@ -879,6 +875,7 @@ void uboot_push_tx_done(int key, int val) { int eth_init(bd_t *bd) { int r; + u8 dev_addr[6]; char ethaddr[20]; PRINTK("### eth_init\n"); @@ -901,7 +898,6 @@ int eth_init(bd_t *bd) { } #endif - nic_base = CONFIG_DRIVER_NE2000_BASE; nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; r = get_prom(dev_addr); diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c index 37411df..e19c223 100644 --- a/drivers/net/ns7520_eth.c +++ b/drivers/net/ns7520_eth.c @@ -387,8 +387,8 @@ static int ns7520_eth_reset(void) ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); /* reset PHY */ - ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); - ns7520_mii_write(PHY_COMMON_CTRL, 0); + ns7520_mii_write(PHY_BMCR, PHY_BMCR_RESET); + ns7520_mii_write(PHY_BMCR, 0); udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ @@ -438,26 +438,23 @@ static void ns7520_link_auto_negotiate(void) /* run auto-negotation */ /* define what we are capable of */ - ns7520_mii_write(PHY_COMMON_AUTO_ADV, - PHY_COMMON_AUTO_ADV_100BTXFD | - PHY_COMMON_AUTO_ADV_100BTX | - PHY_COMMON_AUTO_ADV_10BTFD | - PHY_COMMON_AUTO_ADV_10BT | - PHY_COMMON_AUTO_ADV_802_3); + ns7520_mii_write(PHY_ANAR, + PHY_ANLPAR_TXFD | + PHY_ANLPAR_TX | + PHY_ANLPAR_10FD | + PHY_ANLPAR_10 | + PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns7520_mii_write(PHY_COMMON_CTRL, - PHY_COMMON_CTRL_AUTO_NEG | - PHY_COMMON_CTRL_RES_AUTO); + ns7520_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* wait for completion */ ulStartJiffies = get_timer(0); while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { - uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + uiStatus = ns7520_mii_read(PHY_BMSR); if ((uiStatus & - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) - == - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { /* lucky we are, auto-negotiation succeeded */ ns7520_link_print_changed(); ns7520_link_update_egcr(); @@ -518,14 +515,13 @@ static void ns7520_link_print_changed(void) DEBUG_FN(DEBUG_LINK); - uiControl = ns7520_mii_read(PHY_COMMON_CTRL); + uiControl = ns7520_mii_read(PHY_BMCR); - if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == - PHY_COMMON_CTRL_AUTO_NEG) { - /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ - uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { + /* PHY_BMSR_LS is only set on autonegotiation */ + uiStatus = ns7520_mii_read(PHY_BMSR); - if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + if (!(uiStatus & PHY_BMSR_LS)) { printk(KERN_WARNING NS7520_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -586,12 +582,12 @@ static char ns7520_mii_identify_phy(void) DEBUG_FN(DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1); + phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_PHYIDR1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns7520_mii_read(PHY_COMMON_ID2); + uiID2 = ns7520_mii_read(PHY_PHYIDR2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c index 0559710..cade831 100644 --- a/drivers/net/ns9750_eth.c +++ b/drivers/net/ns9750_eth.c @@ -37,7 +37,7 @@ #include "ns9750_eth.h" /* for Ethernet and PHY */ -/* some definition to make transistion to linux easier */ +/* some definition to make transition to linux easier */ #define NS9750_DRIVER_NAME "eth" #define KERN_WARNING "Warning:" @@ -399,8 +399,8 @@ static int ns9750_eth_reset (void) ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); /* reset PHY */ - ns9750_mii_write (PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); - ns9750_mii_write (PHY_COMMON_CTRL, 0); + ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET); + ns9750_mii_write(PHY_BMCR, 0); /* @TODO check time */ udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But @@ -455,26 +455,26 @@ static void ns9750_link_force (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read (PHY_COMMON_CTRL); - uiControl &= ~(PHY_COMMON_CTRL_SPD_MA | - PHY_COMMON_CTRL_AUTO_NEG | PHY_COMMON_CTRL_DUPLEX); + uiControl = ns9750_mii_read(PHY_BMCR); + uiControl &= ~(PHY_BMCR_SPEED_MASK | + PHY_BMCR_AUTON | PHY_BMCR_DPLX); uiLastLinkStatus = 0; if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) == FS_EEPROM_AUTONEG_SPEED_100) { - uiControl |= PHY_COMMON_CTRL_SPD_100; + uiControl |= PHY_BMCR_100MB; uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX; } else - uiControl |= PHY_COMMON_CTRL_SPD_10; + uiControl |= PHY_BMCR_10_MBPS; if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) == FS_EEPROM_AUTONEG_DUPLEX_FULL) { - uiControl |= PHY_COMMON_CTRL_DUPLEX; + uiControl |= PHY_BMCR_DPLX; uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE; } - ns9750_mii_write (PHY_COMMON_CTRL, uiControl); + ns9750_mii_write(PHY_BMCR, uiControl); ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -495,25 +495,23 @@ static void ns9750_link_auto_negotiate (void) /* run auto-negotation */ /* define what we are capable of */ - ns9750_mii_write (PHY_COMMON_AUTO_ADV, - PHY_COMMON_AUTO_ADV_100BTXFD | - PHY_COMMON_AUTO_ADV_100BTX | - PHY_COMMON_AUTO_ADV_10BTFD | - PHY_COMMON_AUTO_ADV_10BT | - PHY_COMMON_AUTO_ADV_802_3); + ns9750_mii_write(PHY_ANAR, + PHY_ANLPAR_TXFD | + PHY_ANLPAR_TX | + PHY_ANLPAR_10FD | + PHY_ANLPAR_10 | + PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns9750_mii_write (PHY_COMMON_CTRL, - PHY_COMMON_CTRL_AUTO_NEG | - PHY_COMMON_CTRL_RES_AUTO); + ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* wait for completion */ ulStartJiffies = get_ticks (); while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) { - uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + uiStatus = ns9750_mii_read(PHY_BMSR); if ((uiStatus & - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) == - (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == + (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { /* lucky we are, auto-negotiation succeeded */ ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -571,14 +569,13 @@ static void ns9750_link_print_changed (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read (PHY_COMMON_CTRL); + uiControl = ns9750_mii_read(PHY_BMCR); - if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == - PHY_COMMON_CTRL_AUTO_NEG) { - /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ - uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { + /* PHY_BMSR_LS is only set on autonegotiation */ + uiStatus = ns9750_mii_read(PHY_BMSR); - if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + if (!(uiStatus & PHY_BMSR_LS)) { printk (KERN_WARNING NS9750_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -592,7 +589,7 @@ static void ns9750_link_print_changed (void) /* mask out all uninteresting parts */ } - /* other PHYs must store there link information in + /* other PHYs must store their link information in uiStatus as PHY_LXT971 */ } } else { @@ -637,12 +634,12 @@ static char ns9750_mii_identify_phy (void) DEBUG_FN (DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns9750_mii_read (PHY_COMMON_ID1); + phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns9750_mii_read (PHY_COMMON_ID2); + uiID2 = ns9750_mii_read(PHY_PHYIDR2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c new file mode 100644 index 0000000..9e3cf98 --- /dev/null +++ b/drivers/net/sh_eth.c @@ -0,0 +1,603 @@ +/* + * sh_eth.c - Driver for Renesas SH7763's ethernet controler. + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (c) 2008 Nobuhiro Iwamatsu + * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/errno.h> +#include <asm/io.h> + +#include "sh_eth.h" + +#ifndef CONFIG_SH_ETHER_USE_PORT +# error "Please define CONFIG_SH_ETHER_USE_PORT" +#endif +#ifndef CONFIG_SH_ETHER_PHY_ADDR +# error "Please define CONFIG_SH_ETHER_PHY_ADDR" +#endif + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + +static struct dev_info_s *dev; + +/* + * Bits are written to the PHY serially using the + * PIR register, just like a bit banger. + */ +static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) +{ + int i; + u32 pir; + + /* Bit positions is 1 less than the number of bits */ + for (i = len - 1; i >= 0; i--) { + /* Write direction, bit to write, clock is low */ + pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); + outl(pir, PIR(port)); + udelay(1); + /* Write direction, bit to write, clock is high */ + pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); + outl(pir, PIR(port)); + udelay(1); + /* Write direction, bit to write, clock is low */ + pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); + outl(pir, PIR(port)); + udelay(1); + } +} + +static void sh_eth_mii_bus_release(int port) +{ + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); + /* Read direction, clock is high */ + outl(1, PIR(port)); + udelay(1); + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); +} + +static void sh_eth_mii_ind_bus_release(int port) +{ + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); +} + +static int sh_eth_mii_read_phy_bits(int port, u32 * val, int len) +{ + int i; + u32 pir; + + *val = 0; + for (i = len - 1; i >= 0; i--) { + /* Read direction, clock is high */ + outl(1, PIR(port)); + udelay(1); + /* Read bit */ + pir = inl(PIR(port)); + *val |= (pir & 8) ? 1 << i : 0; + /* Read direction, clock is low */ + outl(0, PIR(port)); + udelay(1); + } + + return 0; +} + +#define PHY_INIT 0xFFFFFFFF +#define PHY_READ 0x02 +#define PHY_WRITE 0x01 +/* + * To read a phy register, mii managements frames are sent to the phy. + * The frames look like this: + * pre (32 bits): 0xffff ffff + * st (2 bits): 01 + * op (2bits): 10: read 01: write + * phyad (5 bits): xxxxx + * regad (5 bits): xxxxx + * ta (Bus release): + * data (16 bits): read data + */ +static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) +{ + u32 val; + + /* Sent mii management frame */ + /* pre */ + sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); + /* st (start of frame) */ + sh_eth_mii_write_phy_bits(port, 0x1, 2); + /* op (code) */ + sh_eth_mii_write_phy_bits(port, PHY_READ, 2); + /* phy address */ + sh_eth_mii_write_phy_bits(port, phy_addr, 5); + /* Register to read */ + sh_eth_mii_write_phy_bits(port, reg, 5); + + /* Bus release */ + sh_eth_mii_bus_release(port); + + /* Read register */ + sh_eth_mii_read_phy_bits(port, &val, 16); + + return val; +} + +/* + * To write a phy register, mii managements frames are sent to the phy. + * The frames look like this: + * pre (32 bits): 0xffff ffff + * st (2 bits): 01 + * op (2bits): 10: read 01: write + * phyad (5 bits): xxxxx + * regad (5 bits): xxxxx + * ta (2 bits): 10 + * data (16 bits): write data + * idle (Independent bus release) + */ +static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) +{ + /* Sent mii management frame */ + /* pre */ + sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); + /* st (start of frame) */ + sh_eth_mii_write_phy_bits(port, 0x1, 2); + /* op (code) */ + sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); + /* phy address */ + sh_eth_mii_write_phy_bits(port, phy_addr, 5); + /* Register to read */ + sh_eth_mii_write_phy_bits(port, reg, 5); + /* ta */ + sh_eth_mii_write_phy_bits(port, PHY_READ, 2); + /* Write register data */ + sh_eth_mii_write_phy_bits(port, val, 16); + + /* Independent bus release */ + sh_eth_mii_ind_bus_release(port); +} + +void eth_halt(void) +{ +} + +int eth_send(volatile void *packet, int len) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + int timeout; + int rc = 0; + + if (!packet || len > 0xffff) { + printf("eth_send: Invalid argument\n"); + return -EINVAL; + } + + /* packet must be a 4 byte boundary */ + if ((int)packet & (4 - 1)) { + printf("eth_send: packet not 4 byte alligned\n"); + return -EFAULT; + } + + /* Update tx descriptor */ + port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); + port_info->tx_desc_cur->td1 = len << 16; + /* Must preserve the end of descriptor list indication */ + if (port_info->tx_desc_cur->td0 & TD_TDLE) + port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; + else + port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; + + /* Restart the transmitter if disabled */ + if (!(inl(EDTRR(port)) & EDTRR_TRNS)) + outl(EDTRR_TRNS, EDTRR(port)); + + /* Wait until packet is transmitted */ + timeout = 1000; + while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) + udelay(100); + + if (timeout < 0) { + printf("eth_send: transmit timeout\n"); + rc = -1; + goto err; + } + +err: + port_info->tx_desc_cur++; + if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) + port_info->tx_desc_cur = port_info->tx_desc_base; + + return rc; +} + +int eth_rx(void) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + int len = 0; + volatile u8 *packet; + + /* Check if the rx descriptor is ready */ + if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { + /* Check for errors */ + if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { + len = port_info->rx_desc_cur->rd1 & 0xffff; + packet = (volatile u8 *) + ADDR_TO_P2(port_info->rx_desc_cur->rd2); + NetReceive(packet, len); + } + + /* Make current descriptor available again */ + if (port_info->rx_desc_cur->rd0 & RD_RDLE) + port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; + else + port_info->rx_desc_cur->rd0 = RD_RACT; + + /* Point to the next descriptor */ + port_info->rx_desc_cur++; + if (port_info->rx_desc_cur >= + port_info->rx_desc_base + NUM_RX_DESC) + port_info->rx_desc_cur = port_info->rx_desc_base; + } + + /* Restart the receiver if disabled */ + if (!(inl(EDRRR(port)) & EDRRR_R)) + outl(EDRRR_R, EDRRR(port)); + + return len; +} + +#define EDMR_INIT_CNT 1000 +static int sh_eth_reset(struct dev_info_s *dev) +{ + int port = dev->port; + int i; + + /* Start e-dmac transmitter and receiver */ + outl(EDSR_ENALL, EDSR(port)); + + /* Perform a software reset and wait for it to complete */ + outl(EDMR_SRST, EDMR(port)); + for (i = 0; i < EDMR_INIT_CNT; i++) { + if (!(inl(EDMR(port)) & EDMR_SRST)) + break; + udelay(1000); + } + + if (i == EDMR_INIT_CNT) { + printf("Error: Software reset timeout\n"); + return -1; + } + return 0; +} + +static int sh_eth_tx_desc_init(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + u32 tmp_addr; + struct tx_desc_s *cur_tx_desc; + int i; + + /* Allocate tx descriptors. They must be TX_DESC_SIZE bytes + aligned */ + if (!(port_info->tx_desc_malloc = malloc(NUM_TX_DESC * + sizeof(struct tx_desc_s) + + TX_DESC_SIZE - 1))) { + printf("Error: malloc failed\n"); + return -ENOMEM; + } + tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & + ~(TX_DESC_SIZE - 1)); + /* Make sure we use a P2 address (non-cacheable) */ + port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); + + port_info->tx_desc_cur = port_info->tx_desc_base; + + /* Initialize all descriptors */ + for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; + cur_tx_desc++, i++) { + cur_tx_desc->td0 = 0x00; + cur_tx_desc->td1 = 0x00; + cur_tx_desc->td2 = 0x00; + } + + /* Mark the end of the descriptors */ + cur_tx_desc--; + cur_tx_desc->td0 |= TD_TDLE; + + /* Point the controller to the tx descriptor list. Must use physical + addresses */ + outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); + outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); + outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); + outl(0x01, TDFFR(port));/* Last discriptor bit */ + + return 0; +} + +static int sh_eth_rx_desc_init(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + u32 tmp_addr; + struct rx_desc_s *cur_rx_desc; + u8 *rx_buf; + int i; + + /* Allocate rx descriptors. They must be RX_DESC_SIZE bytes + aligned */ + if (!(port_info->rx_desc_malloc = malloc(NUM_RX_DESC * + sizeof(struct rx_desc_s) + + RX_DESC_SIZE - 1))) { + printf("Error: malloc failed\n"); + return -ENOMEM; + } + tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & + ~(RX_DESC_SIZE - 1)); + /* Make sure we use a P2 address (non-cacheable) */ + port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); + + port_info->rx_desc_cur = port_info->rx_desc_base; + + /* Allocate rx data buffers. They must be 32 bytes aligned and in + P2 area */ + if (!(port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + + 31))) { + printf("Error: malloc failed\n"); + free(port_info->rx_desc_malloc); + port_info->rx_desc_malloc = NULL; + return -ENOMEM; + } + tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & + ~(32 - 1)); + port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); + + /* Initialize all descriptors */ + for (cur_rx_desc = port_info->rx_desc_base, + rx_buf = port_info->rx_buf_base, i = 0; + i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { + cur_rx_desc->rd0 = RD_RACT; + cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; + cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); + } + + /* Mark the end of the descriptors */ + cur_rx_desc--; + cur_rx_desc->rd0 |= RD_RDLE; + + /* Point the controller to the rx descriptor list */ + outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); + outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); + outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); + outl(RDFFR_RDLF, RDFFR(port)); + + return 0; +} + +static void sh_eth_desc_free(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + + if (port_info->tx_desc_malloc) { + free(port_info->tx_desc_malloc); + port_info->tx_desc_malloc = NULL; + } + + if (port_info->rx_desc_malloc) { + free(port_info->rx_desc_malloc); + port_info->rx_desc_malloc = NULL; + } + + if (port_info->rx_buf_malloc) { + free(port_info->rx_buf_malloc); + port_info->rx_buf_malloc = NULL; + } +} + +static int sh_eth_desc_init(struct dev_info_s *dev) +{ + int rc; + + if ((rc = sh_eth_tx_desc_init(dev)) || (rc = sh_eth_rx_desc_init(dev))) { + sh_eth_desc_free(dev); + return rc; + } + + return 0; +} + +static int sh_eth_phy_config(struct dev_info_s *dev) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + int timeout; + u32 val; + /* Reset phy */ + sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); + timeout = 10; + while (timeout--) { + val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, PHY_CTRL); + if (!(val & PHY_C_RESET)) + break; + udelay(50000); + } + if (timeout < 0) { + printf("%s phy reset timeout\n", __func__); + return -1; + } + + /* Advertise 100/10 baseT full/half duplex */ + sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, + (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); + /* Autonegotiation, normal operation, full duplex, enable tx */ + sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, + (PHY_C_ANEGEN|PHY_C_RANEG)); + /* Wait for autonegotiation to complete */ + timeout = 100; + while (timeout--) { + val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); + if (val & PHY_S_ANEGC) + break; + udelay(50000); + } + if (timeout < 0) { + printf("sh_eth_phy_config() phy auto-negotiation failed\n"); + return -1; + } + + return 0; +} + +static int sh_eth_config(struct dev_info_s *dev, bd_t * bd) +{ + int port = dev->port; + struct port_info_s *port_info = &dev->port_info[port]; + u32 val; + u32 phy_status; + int rc; + + /* Configure e-dmac registers */ + outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); + outl(0, EESIPR(port)); + outl(0, TRSCER(port)); + outl(0, TFTR(port)); + outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); + outl(RMCR_RST, RMCR(port)); + outl(0, RPADIR(port)); + outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); + + /* Configure e-mac registers */ + outl(0, ECSIPR(port)); + + /* Set Mac address */ + val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 | + bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3]; + outl(val, MAHR(port)); + + val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5]; + outl(val, MALR(port)); + + outl(RFLR_RFL_MIN, RFLR(port)); + outl(0, PIPR(port)); + outl(APR_AP, APR(port)); + outl(MPR_MP, MPR(port)); + outl(TPAUSER_TPAUSE, TPAUSER(port)); + + /* Configure phy */ + if ((rc = sh_eth_phy_config(dev))) + return rc; + + /* Read phy status to finish configuring the e-mac */ + phy_status = sh_eth_mii_read_phy_reg(dev->port, + dev->port_info[dev->port].phy_addr, + 1); + + /* Set the transfer speed */ + if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { + printf("100Base/"); + outl(GECMR_100B, GECMR(port)); + } else { + printf("10Base/"); + outl(GECMR_10B, GECMR(port)); + } + + /* Check if full duplex mode is supported by the phy */ + if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { + printf("Full\n"); + outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); + } else { + printf("Half\n"); + outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); + } + return 0; +} + +static int sh_eth_start(struct dev_info_s *dev) +{ + /* + * Enable the e-dmac receiver only. The transmitter will be enabled when + * we have something to transmit + */ + outl(EDRRR_R, EDRRR(dev->port)); + + return 0; +} + +static int sh_eth_get_mac(bd_t *bd) +{ + char *s, *e; + int i; + + s = getenv("ethaddr"); + if (s != NULL) { + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } else { + puts("Please set MAC address\n"); + } + return 0; +} + +int eth_init(bd_t *bd) +{ + int rc; + /* Allocate main device information structure */ + if (!(dev = malloc(sizeof(*dev)))) { + printf("eth_init: malloc failed\n"); + return -ENOMEM; + } + + memset(dev, 0, sizeof(*dev)); + + dev->port = CONFIG_SH_ETHER_USE_PORT; + dev->port_info[dev->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + + sh_eth_get_mac(bd); + + if ((rc = sh_eth_reset(dev)) || (rc = sh_eth_desc_init(dev))) + goto err; + + if ((rc = sh_eth_config(dev, bd)) || (rc = sh_eth_start(dev))) + goto err_desc; + + return 0; + +err_desc: + sh_eth_desc_free(dev); +err: + free(dev); + printf("eth_init: Failed\n"); + return rc; +} diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h new file mode 100644 index 0000000..9cf0ea0 --- /dev/null +++ b/drivers/net/sh_eth.h @@ -0,0 +1,446 @@ +/* + * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler. + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (c) 2008 Nobuhiro Iwamatsu + * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <asm/types.h> + +#define SHETHER_NAME "sh_eth" + +/* Malloc returns addresses in the P1 area (cacheable). However we need to + use area P2 (non-cacheable) */ +#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) + +/* The ethernet controller needs to use physical addresses */ +#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) + +/* Number of supported ports */ +#define MAX_PORT_NUM 2 + +/* Buffers must be big enough to hold the largest ethernet frame. Also, rx + buffers must be a multiple of 32 bytes */ +#define MAX_BUF_SIZE (48 * 32) + +/* The number of tx descriptors must be large enough to point to 5 or more + frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. + We use one descriptor per frame */ +#define NUM_TX_DESC 8 + +/* The size of the tx descriptor is determined by how much padding is used. + 4, 20, or 52 bytes of padding can be used */ +#define TX_DESC_PADDING 4 +#define TX_DESC_SIZE (12 + TX_DESC_PADDING) + +/* Tx descriptor. We always use 4 bytes of padding */ +struct tx_desc_s { + volatile u32 td0; + u32 td1; + u32 td2; /* Buffer start */ + u32 padding; +}; + +/* There is no limitation in the number of rx descriptors */ +#define NUM_RX_DESC 8 + +/* The size of the rx descriptor is determined by how much padding is used. + 4, 20, or 52 bytes of padding can be used */ +#define RX_DESC_PADDING 4 +#define RX_DESC_SIZE (12 + RX_DESC_PADDING) + +/* Rx descriptor. We always use 4 bytes of padding */ +struct rx_desc_s { + volatile u32 rd0; + volatile u32 rd1; + u32 rd2; /* Buffer start */ + u32 padding; +}; + +struct port_info_s { + struct tx_desc_s *tx_desc_malloc; + struct tx_desc_s *tx_desc_base; + struct tx_desc_s *tx_desc_cur; + struct rx_desc_s *rx_desc_malloc; + struct rx_desc_s *rx_desc_base; + struct rx_desc_s *rx_desc_cur; + u8 *rx_buf_malloc; + u8 *rx_buf_base; + u8 mac_addr[6]; + u8 phy_addr; +}; + +struct dev_info_s { + int port; + struct port_info_s port_info[MAX_PORT_NUM]; +}; + +/* Register Address */ +#define BASE_IO_ADDR 0xfee00000 + +#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) + +#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) +#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) +#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) +#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) + +#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) +#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) +#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) +#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) + +#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) +#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) +#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) +#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) +#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) +#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) +#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) +#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) +#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) +#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) +#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) +#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) +#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) +#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) +#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) +#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) +#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) +#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) +#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) +#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) +#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) +#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) + +/* + * Register's bits + * Copy from Linux driver source code + */ +#ifdef CONFIG_CPU_SH7763 +/* EDSR */ +enum EDSR_BIT { + EDSR_ENT = 0x01, EDSR_ENR = 0x02, +}; +#define EDSR_ENALL (EDSR_ENT|EDSR_ENR) +#endif + +/* EDMR */ +enum DMAC_M_BIT { + EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, +#ifdef CONFIG_CPU_SH7763 + EDMR_SRST = 0x03, + EMDR_DESC_R = 0x30, /* Descriptor reserve size */ + EDMR_EL = 0x40, /* Litte endian */ +#else /* CONFIG_CPU_SH7763 */ + EDMR_SRST = 0x01, +#endif +}; + +/* RFLR */ +#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ + +/* EDTRR */ +enum DMAC_T_BIT { +#ifdef CONFIG_CPU_SH7763 + EDTRR_TRNS = 0x03, +#else + EDTRR_TRNS = 0x01, +#endif +}; + +/* GECMR */ +enum GECMR_BIT { + GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00, +}; + +/* EDRRR*/ +enum EDRRR_R_BIT { + EDRRR_R = 0x01, +}; + +/* TPAUSER */ +enum TPAUSER_BIT { + TPAUSER_TPAUSE = 0x0000ffff, + TPAUSER_UNLIMITED = 0, +}; + +/* BCFR */ +enum BCFR_BIT { + BCFR_RPAUSE = 0x0000ffff, + BCFR_UNLIMITED = 0, +}; + +/* PIR */ +enum PIR_BIT { + PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, +}; + +/* PSR */ +enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; + +/* EESR */ +enum EESR_BIT { +#ifndef CONFIG_CPU_SH7763 + EESR_TWB = 0x40000000, +#else + EESR_TWB = 0xC0000000, + EESR_TC1 = 0x20000000, + EESR_TUC = 0x10000000, + EESR_ROC = 0x80000000, +#endif + EESR_TABT = 0x04000000, + EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, +#ifndef CONFIG_CPU_SH7763 + EESR_ADE = 0x00800000, +#endif + EESR_ECI = 0x00400000, + EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, + EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, + EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, +#ifndef CONFIG_CPU_SH7763 + EESR_CND = 0x00000800, +#endif + EESR_DLC = 0x00000400, + EESR_CD = 0x00000200, EESR_RTO = 0x00000100, + EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, + EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, + rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, + EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, +}; + + +#ifdef CONFIG_CPU_SH7763 +# define TX_CHECK (EESR_TC1 | EESR_FTC) +# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ + | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) +# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) + +#else +# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) +# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ + | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) +# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) +#endif + +/* EESIPR */ +enum DMAC_IM_BIT { + DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, + DMAC_M_RABT = 0x02000000, + DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, + DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, + DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, + DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, + DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, + DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, + DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, + DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, + DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, + DMAC_M_RINT1 = 0x00000001, +}; + +/* Receive descriptor bit */ +enum RD_STS_BIT { + RD_RACT = 0x80000000, RD_RDLE = 0x40000000, + RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, + RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, + RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, + RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, + RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, + RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, + RD_RFS1 = 0x00000001, +}; +#define RDF1ST RD_RFP1 +#define RDFEND RD_RFP0 +#define RD_RFP (RD_RFP1|RD_RFP0) + +/* RDFFR*/ +enum RDFFR_BIT { + RDFFR_RDLF = 0x01, +}; + +/* FCFTR */ +enum FCFTR_BIT { + FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, + FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, + FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, +}; +#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) +#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) + +/* Transfer descriptor bit */ +enum TD_STS_BIT { +#ifdef CONFIG_CPU_SH7763 + TD_TACT = 0x80000000, +#else + TD_TACT = 0x7fffffff, +#endif + TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, + TD_TFP0 = 0x10000000, +}; +#define TDF1ST TD_TFP1 +#define TDFEND TD_TFP0 +#define TD_TFP (TD_TFP1|TD_TFP0) + +/* RMCR */ +enum RECV_RST_BIT { RMCR_RST = 0x01, }; +/* ECMR */ +enum FELIC_MODE_BIT { +#ifdef CONFIG_CPU_SH7763 + ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, + ECMR_RZPF = 0x00100000, +#endif + ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, + ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, + ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, + ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, + ECMR_PRM = 0x00000001, +}; + +#ifdef CONFIG_CPU_SH7763 +#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ + ECMR_TXF | ECMR_MCT) +#else +#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT) +#endif + +/* ECSR */ +enum ECSR_STATUS_BIT { +#ifndef CONFIG_CPU_SH7763 + ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, +#endif + ECSR_LCHNG = 0x04, + ECSR_MPD = 0x02, ECSR_ICD = 0x01, +}; + +#ifdef CONFIG_CPU_SH7763 +# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) +#else +# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ + ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) +#endif + +/* ECSIPR */ +enum ECSIPR_STATUS_MASK_BIT { +#ifndef CONFIG_CPU_SH7763 + ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, +#endif + ECSIPR_LCHNGIP = 0x04, + ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, +}; + +#ifdef CONFIG_CPU_SH7763 +# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) +#else +# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ + ECSIPR_ICDIP | ECSIPR_MPDIP) +#endif + +/* APR */ +enum APR_BIT { + APR_AP = 0x00000004, +}; + +/* MPR */ +enum MPR_BIT { + MPR_MP = 0x00000006, +}; + +/* TRSCER */ +enum DESC_I_BIT { + DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, + DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, + DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, + DESC_I_RINT1 = 0x0001, +}; + +/* RPADIR */ +enum RPADIR_BIT { + RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, + RPADIR_PADR = 0x0003f, +}; + +#ifdef CONFIG_CPU_SH7763 +# define RPADIR_INIT (0x00) +#else +# define RPADIR_INIT (RPADIR_PADS1) +#endif + +/* FDR */ +enum FIFO_SIZE_BIT { + FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, +}; + +enum PHY_OFFSETS { + PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, + PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, + PHY_16 = 16, +}; + +/* PHY_CTRL */ +enum PHY_CTRL_BIT { + PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, + PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, + PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, +}; +#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ + +/* PHY_STAT */ +enum PHY_STAT_BIT { + PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, + PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, + PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, + PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, +}; + +/* PHY_ANA */ +enum PHY_ANA_BIT { + PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, + PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, + PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, + PHY_A_SEL = 0x001e, + PHY_A_EXT = 0x0001, +}; + +/* PHY_ANL */ +enum PHY_ANL_BIT { + PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, + PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, + PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, + PHY_L_SEL = 0x001f, +}; + +/* PHY_ANE */ +enum PHY_ANE_BIT { + PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, + PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, +}; + +/* DM9161 */ +enum PHY_16_BIT { + PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, + PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, + PHY_16_TXselect = 0x0400, + PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, + PHY_16_Force100LNK = 0x0080, + PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, + PHY_16_RPDCTR_EN = 0x0010, + PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, + PHY_16_Sleepmode = 0x0002, + PHY_16_RemoteLoopOut = 0x0001, +}; diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 76425d8..182ca2d 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -144,8 +144,13 @@ static int calc_divisor (NS16550_t port) #else #define MODE_X_DIV 16 #endif - return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate); + /* Compute divisor value. Normally, we should simply return: + * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate + * but we need to round that value by adding 0.5 or 8/16. + * Rounding is especially important at high baud rates. + */ + return (((16 * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate) + 8) / 16; } #if !defined(CONFIG_SERIAL_MULTI) diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h index 2a27d06..ede0b1a 100644 --- a/include/asm-sparc/io.h +++ b/include/asm-sparc/io.h @@ -70,7 +70,6 @@ * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h index 69f93d6..2cf974a 100644 --- a/include/asm-sparc/types.h +++ b/include/asm-sparc/types.h @@ -65,6 +65,9 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/common.h b/include/common.h index 10b997e..2fcb1fd 100644 --- a/include/common.h +++ b/include/common.h @@ -607,8 +607,10 @@ ulong simple_strtoul(const char *cp,char **endp,unsigned int base); unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); #endif long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...); -int sprintf(char * buf, const char *fmt, ...); +void panic(const char *fmt, ...) + __attribute__ ((format (__printf__, 1, 2))); +int sprintf(char * buf, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); int vsprintf(char *buf, const char *fmt, va_list args); /* lib_generic/crc32.c */ @@ -630,7 +632,8 @@ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ */ /* serial stuff */ -void serial_printf (const char *fmt, ...); +void serial_printf (const char *fmt, ...) + __attribute__ ((format (__printf__, 1, 2))); /* stdin */ int getc(void); @@ -639,7 +642,8 @@ int tstc(void); /* stdout */ void putc(const char c); void puts(const char *s); -void printf(const char *fmt, ...); +void printf(const char *fmt, ...) + __attribute__ ((format (__printf__, 1, 2))); void vprintf(const char *fmt, va_list args); /* stderr */ @@ -656,7 +660,8 @@ void vprintf(const char *fmt, va_list args); #define stderr 2 #define MAX_FILES 3 -void fprintf(int file, const char *fmt, ...); +void fprintf(int file, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); void fputs(int file, const char *s); void fputc(int file, const char c); int ftstc(int file); diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 23508f9..59d0bdb 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -197,6 +197,13 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#if defined(CONFIG_OF_LIBFDT) +#define OF_CPU "cpu@0" +#define OF_TBCLK (bd->bi_busfreq / 4) +#endif + /* * BOOTP options */ diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 99e1179..fa0e5db 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -45,10 +45,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.10.100 -#define CONFIG_SERVERIP 192.168.10.77 -#define CONFIG_GATEWAYIP 192.168.10.77 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 7ac51b5..84d235e 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -128,6 +128,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CONFIG_ATMEL_SPI 1 #define CONFIG_SPI_FLASH 1 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index ba18eb6..90910bb 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -153,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index a528ddf..03472a8 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -136,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index fc9585e..07add82 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -136,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 9fd49a5..f9af675 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -153,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 41a6763..0e49e6c 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -1,6 +1,9 @@ /* * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -21,30 +24,24 @@ #define __CONFIG_H #include <asm/sizes.h> -/*=======*/ /* Board */ -/*=======*/ #define SFFSDR #define CFG_NAND_LARGEPAGE #define CFG_USE_NAND -/*===================*/ +#define CFG_USE_DSPLINK /* This is to prevent U-Boot from + * powering ON the DSP. */ /* SoC Configuration */ -/*===================*/ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CFG_HZ 1000 -/*==================================================*/ -/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ -/*==================================================*/ +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ #define CFG_I2C_EEPROM_ADDR_LEN 2 #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_EEPROM_PAGE_WRITE_BITS 5 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ /* Memory Info */ -/*=============*/ #define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ #define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ #define CFG_MEMTEST_START 0x80000000 /* memtest start address */ @@ -54,9 +51,7 @@ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ /* Serial Driver info */ -/*====================*/ #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ @@ -65,16 +60,12 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/*===================*/ /* I2C Configuration */ -/*===================*/ #define CONFIG_HARD_I2C #define CONFIG_DRIVER_DAVINCI_I2C #define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ /* Network & Ethernet Configuration */ -/*==================================*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT @@ -83,9 +74,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE -/*=====================*/ /* Flash & Environment */ -/*=====================*/ #undef CFG_ENV_IS_IN_FLASH #define CFG_NO_FLASH #define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ @@ -98,28 +87,19 @@ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_MAX_CHIPS 1 #define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/*=====================*/ -/* Board related stuff */ -/*=====================*/ -/*==========================================*/ -/* I2C switch definitions for PCA9543 chip */ -/* on Lyrtech SFF SDR board. */ -/* This chip has a single register. */ -/*==========================================*/ +/* I2C switch definitions for PCA9543 chip */ #define CFG_I2C_PCA9543_ADDR 0x70 -#define CFG_I2C_PCA9543_ADDR_LEN 0 +#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ #define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ -/*==============================*/ /* U-Boot general configuration */ -/*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_PBSIZE \ + (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel @@ -133,25 +113,20 @@ #define CFG_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC -/* - * Define this to load an Integrity kernel. - * -#define CONFIG_CMD_ELF - */ - -/*===================*/ /* Linux Information */ -/*===================*/ #define LINUX_BOOT_PARAM_ADDR 0x80000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" - -/*=================*/ +#define CONFIG_BOOTARGS \ + "mem=56M " \ + "console=ttyS0,115200n8 " \ + "root=/dev/nfs rw noinitrd ip=dhcp " \ + "nfsroot=${serverip}:/nfsroot/sffsdr " \ + "eth0=${ethaddr}" +#define CONFIG_BOOTCOMMAND \ + "nand read 87A00000 100000 300000;" \ + "bootelf 87A00000" /* U-Boot commands */ -/*=================*/ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP @@ -167,9 +142,7 @@ #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS -/*=======================*/ /* KGDB support (if any) */ -/*=======================*/ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 8d92a13..7298e55 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -40,10 +40,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.22 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index c20baca..e269336 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -35,12 +35,6 @@ #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_ENV_OVERWRITE 1 -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.51 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (0x04000000) @@ -60,45 +54,27 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1024 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) #define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* - * NOR Flash + * NOR Flash ( Spantion S29GL256P ) */ #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER - -#if defined(CONFIG_R2DPLUS_OLD) -#define CFG_FLASH_BASE (0xA0000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of - * Flash memory banks - */ -#define CFG_MAX_FLASH_SECT 142 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#else /* CONFIG_R2DPLUS_OLD */ - #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */ -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ - CFG_FLASH_BASE + 0x100000,\ - CFG_FLASH_BASE + 0x400000,\ - CFG_FLASH_BASE + 0x700000, } -#endif /* CONFIG_R2DPLUS_OLD */ +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 -#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_ENV_SECT_SIZE 0x40000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) /* * SuperH Clock setting diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 4e89580..4c82c5a 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Renesas R7780MP board * - * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> * * See file CREDITS for list of people who contributed to this @@ -31,7 +31,8 @@ #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7780 1 #define CONFIG_R7780MP 1 -#define __LITTLE_ENDIAN 1 +#define CFG_R7780MP_OLD_FLASH 1 +#define __LITTLE_ENDIAN__ 1 /* * Command line configuration. @@ -59,12 +60,6 @@ /* check for keypress on bootdelay==0 */ /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.82 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - #define CFG_SDRAM_BASE (0x08000000) #define CFG_SDRAM_SIZE (128 * 1024 * 1024) @@ -80,22 +75,30 @@ #define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000) -/* NOR Flash (S29PL127J60TFI130) */ +/* Flash board support */ #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ +#ifdef CFG_R7780MP_OLD_FLASH +/* NOR Flash (S29PL127J60TFI130) */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +# define CFG_MAX_FLASH_BANKS (2) +# define CFG_MAX_FLASH_SECT 270 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ CFG_FLASH_BASE + 0x100000,\ CFG_FLASH_BASE + 0x400000,\ CFG_FLASH_BASE + 0x700000, } +#else /* CFG_R7780MP_OLD_FLASH */ +/* NOR Flash (Spantion S29GL256P) */ +# define CFG_MAX_FLASH_BANKS (1) +# define CFG_MAX_FLASH_SECT 256 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /* CFG_R7780MP_OLD_FLASH */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (112 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1204 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) @@ -110,7 +113,7 @@ #define CFG_FLASH_EMPTY_INFO #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE (16 * 1024) +#define CFG_ENV_SECT_SIZE (256 * 1024) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_FLASH_ERASE_TOUT 120000 @@ -141,8 +144,10 @@ #endif /* CONFIG_CMD_PCI */ #if defined(CONFIG_CMD_NET) -/* #define CONFIG_NET_MULTI - #define CONFIG_RTL8169 */ +/* +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 +*/ /* AX88696L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index d537071..7713eaa 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -38,11 +38,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING #define CONFIG_CMD_ENV -#define CONFIG_CMD_NFS -#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" @@ -66,12 +62,6 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ -/* Ethernet */ -#define CONFIG_SH_ETHER 1 -#define CONFIG_SH_ETHER_USE_PORT (1) -#define CONFIG_SH_ETHER_PHY_ADDR (0x01) -#define CFG_RX_ETH_BUFFER (8) - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (64 * 1024 * 1024) diff --git a/include/environment.h b/include/environment.h index bf9f669..481ea73 100644 --- a/include/environment.h +++ b/include/environment.h @@ -107,8 +107,8 @@ typedef struct environment_s { unsigned char data[ENV_SIZE]; /* Environment data */ } env_t; -/* Pointer to function that returns a character from the environment */ -extern unsigned char (*env_get_char)(int); +/* Function that returns a character from the environment */ +unsigned char env_get_char (int); /* Function that returns a pointer to a value from the environment */ unsigned char *env_get_addr(int); @@ -117,4 +117,7 @@ unsigned char env_get_char_memory (int index); /* Function that updates CRC of the enironment */ void env_crc_update (void); +/* [re]set to the default environment */ +void set_default_env(void); + #endif /* _ENVIRONMENT_H_ */ diff --git a/include/lmb.h b/include/lmb.h index 0283075..14e8727 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -43,7 +43,7 @@ extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr); extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); -extern long lmb_free(struct lmb *lmb, u64 base, u64 size); +extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern void lmb_dump_all(struct lmb *lmb); diff --git a/include/lxt971a.h b/include/lxt971a.h index f76c336..72145e0 100644 --- a/include/lxt971a.h +++ b/include/lxt971a.h @@ -30,15 +30,6 @@ #define __LXT971A_H__ /* PHY definitions (LXT971A) [2] */ -#define PHY_COMMON_CTRL (0x00) -#define PHY_COMMON_STAT (0x01) -#define PHY_COMMON_ID1 (0x02) -#define PHY_COMMON_ID2 (0x03) -#define PHY_COMMON_AUTO_ADV (0x04) -#define PHY_COMMON_AUTO_LNKB (0x05) -#define PHY_COMMON_AUTO_EXP (0x06) -#define PHY_COMMON_AUTO_NEXT (0x07) -#define PHY_COMMON_AUTO_LNKN (0x08) #define PHY_LXT971_PORT_CFG (0x10) #define PHY_LXT971_STAT2 (0x11) #define PHY_LXT971_INT_ENABLE (0x12) @@ -47,97 +38,6 @@ #define PHY_LXT971_DIG_CFG (0x1A) #define PHY_LXT971_TX_CTRL (0x1E) -/* CTRL PHY Control Register Bit Fields */ -#define PHY_COMMON_CTRL_RESET (0x8000) -#define PHY_COMMON_CTRL_LOOPBACK (0x4000) -#define PHY_COMMON_CTRL_SPD_MA (0x2040) -#define PHY_COMMON_CTRL_SPD_10 (0x0000) -#define PHY_COMMON_CTRL_SPD_100 (0x2000) -#define PHY_COMMON_CTRL_SPD_1000 (0x0040) -#define PHY_COMMON_CTRL_SPD_RES (0x2040) -#define PHY_COMMON_CTRL_AUTO_NEG (0x1000) -#define PHY_COMMON_CTRL_POWER_DN (0x0800) -#define PHY_COMMON_CTRL_ISOLATE (0x0400) -#define PHY_COMMON_CTRL_RES_AUTO (0x0200) -#define PHY_COMMON_CTRL_DUPLEX (0x0100) -#define PHY_COMMON_CTRL_COL_TEST (0x0080) -#define PHY_COMMON_CTRL_RES1 (0x003F) - -/* STAT Status Register Bit Fields */ -#define PHY_COMMON_STAT_100BT4 (0x8000) -#define PHY_COMMON_STAT_100BXFD (0x4000) -#define PHY_COMMON_STAT_100BXHD (0x2000) -#define PHY_COMMON_STAT_10BTFD (0x1000) -#define PHY_COMMON_STAT_10BTHD (0x0800) -#define PHY_COMMON_STAT_100BT2FD (0x0400) -#define PHY_COMMON_STAT_100BT2HD (0x0200) -#define PHY_COMMON_STAT_EXT_STAT (0x0100) -#define PHY_COMMON_STAT_RES1 (0x0080) -#define PHY_COMMON_STAT_MF_PSUP (0x0040) -#define PHY_COMMON_STAT_AN_COMP (0x0020) -#define PHY_COMMON_STAT_RMT_FLT (0x0010) -#define PHY_COMMON_STAT_AN_CAP (0x0008) -#define PHY_COMMON_STAT_LNK_STAT (0x0004) -#define PHY_COMMON_STAT_JAB_DTCT (0x0002) -#define PHY_COMMON_STAT_EXT_CAP (0x0001) - -/* AUTO_ADV Auto-neg Advert Register Bit Fields */ -#define PHY_COMMON_AUTO_ADV_NP (0x8000) -#define PHY_COMMON_AUTO_ADV_RES1 (0x4000) -#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000) -#define PHY_COMMON_AUTO_ADV_RES2 (0x1000) -#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800) -#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400) -#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200) -#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100) -#define PHY_COMMON_AUTO_ADV_100BTX (0x0080) -#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040) -#define PHY_COMMON_AUTO_ADV_10BT (0x0020) -#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F) -#define PHY_COMMON_AUTO_ADV_802_9 (0x0002) -#define PHY_COMMON_AUTO_ADV_802_3 (0x0001) - -/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */ -#define PHY_COMMON_AUTO_LNKB_NP (0x8000) -#define PHY_COMMON_AUTO_LNKB_ACK (0x4000) -#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000) -#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000) -#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800) -#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400) -#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200) -#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100) -#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080) -#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040) -#define PHY_COMMON_AUTO_LNKB_10BT (0x0020) -#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F) -#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002) -#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001) - -/* AUTO_EXP Auto-neg Expansion Register Bit Fields */ -#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0) -#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020) -#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010) -#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008) -#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004) -#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002) -#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001) - -/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */ -#define PHY_COMMON_AUTO_NEXT_NP (0x8000) -#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000) -#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000) -#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000) -#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800) -#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF) - -/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */ -#define PHY_COMMON_AUTO_LNKN_NP (0x8000) -#define PHY_COMMON_AUTO_LNKN_ACK (0x4000) -#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000) -#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000) -#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800) -#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF) - /* PORT_CFG Port Configuration Register Bit Fields */ #define PHY_LXT971_PORT_CFG_RES1 (0x8000) #define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h index 123e6f4..b509697 100644 --- a/include/ns7520_eth.h +++ b/include/ns7520_eth.h @@ -24,6 +24,7 @@ #ifdef CONFIG_DRIVER_NS7520_ETHERNET +#include <miiphy.h> #include "lxt971a.h" /* The port addresses */ diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h index a6e5889..80c721b 100644 --- a/include/ns9750_eth.h +++ b/include/ns9750_eth.h @@ -31,6 +31,7 @@ #ifdef CONFIG_DRIVER_NS9750_ETHERNET +#include <miiphy.h> #include "lxt971a.h" #define NS9750_ETH_MODULE_BASE (0xA0600000) diff --git a/include/pci_ids.h b/include/pci_ids.h index d061017..165456b 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1827,6 +1827,7 @@ #define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011 #define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012 #define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015 +#define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026 #define PCI_DEVICE_ID_INTEL_82559 0x1030 #define PCI_DEVICE_ID_INTEL_82562ET 0x1031 diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c index a52fa04..2dc2567 100644 --- a/lib_generic/display_options.c +++ b/lib_generic/display_options.c @@ -39,27 +39,35 @@ int display_options (void) } /* - * print sizes as "xxx kB", "xxx.y kB", "xxx MB" or "xxx.y MB" as needed; - * allow for optional trailing string (like "\n") + * print sizes as "xxx kB", "xxx.y kB", "xxx MB", "xxx.y MB", + * xxx GB, or xxx.y GB as needed; allow for optional trailing string + * (like "\n") */ void print_size (phys_size_t size, const char *s) { - ulong m, n; - ulong d = 1 << 20; /* 1 MB */ - char c = 'M'; - - if (size < d) { /* print in kB */ - c = 'k'; - d = 1 << 10; + ulong m = 0, n; + phys_size_t d = 1 << 30; /* 1 GB */ + char c = 'G'; + + if (size < d) { /* try MB */ + c = 'M'; + d = 1 << 20; + if (size < d) { /* print in kB */ + c = 'k'; + d = 1 << 10; + } } n = size / d; - m = (10 * (size - (n * d)) + (d / 2) ) / d; + /* If there's a remainder, deal with it */ + if(size % d) { + m = (10 * (size - (n * d)) + (d / 2) ) / d; - if (m >= 10) { - m -= 10; - n += 1; + if (m >= 10) { + m -= 10; + n += 1; + } } printf ("%2ld", n); diff --git a/lib_generic/lmb.c b/lib_generic/lmb.c index 93264c1..6b46fa8 100644 --- a/lib_generic/lmb.c +++ b/lib_generic/lmb.c @@ -181,11 +181,11 @@ long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) return lmb_add_region(_rgn, base, size); } -long lmb_free(struct lmb *lmb, u64 base, u64 size) +long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) { struct lmb_region *rgn = &(lmb->reserved); - u64 rgnbegin, rgnend; - u64 end = base + size; + phys_addr_t rgnbegin, rgnend; + phys_addr_t end = base + size; int i; rgnbegin = rgnend = 0; /* supress gcc warnings */ diff --git a/lib_mips/bootm.c b/lib_mips/bootm.c index f813fc5..8fe3782 100644 --- a/lib_mips/bootm.c +++ b/lib_mips/bootm.c @@ -54,6 +54,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], char *commandline = getenv ("bootargs"); char env_buf[12]; int ret; + const char *cp; /* find kernel entry point */ if (images->legacy_hdr_valid) { @@ -113,6 +114,16 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); linux_env_set ("flash_size", env_buf); + cp = getenv("ethaddr"); + if (cp != NULL) { + linux_env_set("ethaddr", cp); + } + + cp = getenv("eth1addr"); + if (cp != NULL) { + linux_env_set("eth1addr", cp); + } + if (!images->autostart) return ; diff --git a/lib_ppc/bootm.c b/lib_ppc/bootm.c index 3c1c18b..81803dd 100644 --- a/lib_ppc/bootm.c +++ b/lib_ppc/bootm.c @@ -105,7 +105,7 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (size < bootm_size) { ulong base = bootmap_base + size; - printf("WARNING: adjusting available memory to %x\n", size); + printf("WARNING: adjusting available memory to %lx\n", size); lmb_reserve(lmb, base, bootm_size - size); } @@ -205,14 +205,15 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], for (j = 0; j < total; j++) { fdt_get_mem_rsv(of_flat_tree, j, &addr, &size); - if (addr == (uint64_t)of_flat_tree) { + if (addr == (uint64_t)(u32)of_flat_tree) { fdt_del_mem_rsv(of_flat_tree, j); break; } } /* Delete the old LMB reservation */ - lmb_free(lmb, (uint64_t)of_flat_tree, fdt_totalsize(of_flat_tree)); + lmb_free(lmb, (phys_addr_t)(u32)of_flat_tree, + (phys_size_t)fdt_totalsize(of_flat_tree)); /* Calculate the actual size of the fdt */ actualsize = fdt_off_dt_strings(of_flat_tree) + @@ -672,7 +673,7 @@ static int boot_get_fdt (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], */ fdt_blob = (char *)fdt_addr; debug ("* fdt: raw FDT blob\n"); - printf ("## Flattened Device Tree blob at %08lx\n", fdt_blob); + printf ("## Flattened Device Tree blob at %08lx\n", (long)fdt_blob); } break; default: @@ -680,7 +681,7 @@ static int boot_get_fdt (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], goto error; } - printf (" Booting using the fdt blob at 0x%x\n", fdt_blob); + printf (" Booting using the fdt blob at 0x%x\n", (int)fdt_blob); } else if (images->legacy_hdr_valid && image_check_type (&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) { @@ -699,7 +700,7 @@ static int boot_get_fdt (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (fdt_len) { fdt_blob = (char *)fdt_data; - printf (" Booting using the fdt at 0x%x\n", fdt_blob); + printf (" Booting using the fdt at 0x%x\n", (int)fdt_blob); if (fdt_check_header (fdt_blob) != 0) { fdt_error ("image is not a fdt"); diff --git a/lib_sh/Makefile b/lib_sh/Makefile index 0e4fdee..4034381 100644 --- a/lib_sh/Makefile +++ b/lib_sh/Makefile @@ -26,7 +26,7 @@ SOBJS-y += COBJS-y += board.o COBJS-y += bootm.o -#COBJS-y += time.o +# COBJS-y += time.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/lib_sh/board.c b/lib_sh/board.c index 807415c..eb81bd9 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -112,6 +112,7 @@ static int sh_mem_env_init(void) return 0; } +#if defined(CONFIG_CMD_NET) static int sh_net_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -127,6 +128,7 @@ static int sh_net_init(void) return 0; } +#endif typedef int (init_fnc_t) (void); @@ -170,8 +172,8 @@ void sh_generic_init (void) bd_t *bd; init_fnc_t **init_fnc_ptr; - char *s; int i; + char *s; memset (gd, 0, CFG_GBL_DATA_SIZE); diff --git a/lib_sh/time.c b/lib_sh/time.c index 3d33918..9c1dc50 100644 --- a/lib_sh/time.c +++ b/lib_sh/time.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <asm/processer.h> +#include <asm/processor.h> static void tmu_timer_start (unsigned int timer) { @@ -28,6 +28,17 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +/* + * CPU and board-specific Ethernet initializations. Aliased function + * signals caller to move on + */ +static int __def_eth_init(bd_t *bis) +{ + return -1; +} +int cpu_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init"))); +int board_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init"))); + #ifdef CFG_GT_6426x extern int gt6426x_eth_initialize(bd_t *bis); #endif @@ -55,7 +66,6 @@ extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); extern int tsi108_eth_initialize(bd_t*); extern int uli526x_initialize(bd_t *); -extern int tsec_initialize(bd_t*, int, char *); extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); @@ -165,6 +175,10 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_init(); #endif + /* Try board-specific initialization first. If it fails or isn't + * present, try the cpu-specific initialization */ + if (board_eth_init(bis) < 0) + cpu_eth_init(bis); #if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750) mv6436x_eth_initialize(bis); @@ -196,22 +210,6 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_SK98) skge_initialize(bis); #endif -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif -#if defined(CONFIG_MPC85XX_FEC) - tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); -#else -# if defined(CONFIG_TSEC3) - tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); -# endif -# if defined(CONFIG_TSEC4) - tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); -# endif -#endif #if defined(CONFIG_UEC_ETH1) uec_initialize(0); #endif @@ -178,7 +178,7 @@ TftpSend (void) pkt += 5 /*strlen("octet")*/ + 1; strcpy ((char *)pkt, "timeout"); pkt += 7 /*strlen("timeout")*/ + 1; - sprintf((char *)pkt, "%d", TIMEOUT); + sprintf((char *)pkt, "%lu", TIMEOUT); #ifdef ET_DEBUG printf("send option \"timeout %s\"\n", (char *)pkt); #endif |