diff options
45 files changed, 5097 insertions, 1362 deletions
@@ -160,6 +160,11 @@ N: Thomas Frieden E: ThomasF@hyperion-entertainment.com D: Support for AmigaOne +N: Niklaus Giger +E: niklaus.giger@netstal.com +D: Support for HCU(x) boards +W: www.netstal.com + N: Paul Gortmaker E: paul.gortmaker@windriver.com D: Support for WRS SBC8347/8349 boards diff --git a/MAINTAINERS b/MAINTAINERS index 853afeb..eec50a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -160,6 +160,11 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> WUH405 PPC405EP CMS700 PPC405EP +Niklaus Giger <niklaus.giger@netstal.com> + + HCU4 PPC405GPr + HCU5 PPC440EPx + Frank Gottschling <fgottschling@eltec.de> MHPC MPC8xx @@ -82,16 +82,17 @@ LIST_4xx=" \ CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ csb272 csb472 DASA_SIM DP405 \ DU405 ebony ERIC EXBITGEN \ - G2000 HH405 HUB405 JSE \ - KAREF katmai luan lwmon5 \ - METROBOX MIP405 MIP405T ML2 \ - ml300 ocotea OCRTC ORSG \ - p3p440 PCI405 pcs440ep PIP405 \ - PLU405 PMC405 PPChameleonEVB sbc405 \ - sc3 sequoia sequoia_nand taihu \ - taishan VOH405 VOM405 W7OLMC \ - W7OLMG walnut WUH405 XPEDITE1K \ - yellowstone yosemite yucca zeus \ + G2000 HH405 hcu4 hcu5 \ + HUB405 JSE KAREF katmai \ + luan lwmon5 METROBOX MIP405 \ + MIP405T ML2 ml300 ocotea \ + OCRTC ORSG p3p440 PCI405 \ + pcs440ep PIP405 PLU405 PMC405 \ + PPChameleonEVB sbc405 sc3 sequoia \ + sequoia_nand taihu taishan VOH405 \ + VOM405 W7OLMC W7OLMG walnut \ + WUH405 XPEDITE1K yellowstone yosemite \ + yucca zeus \ " ######################################################################### @@ -1040,7 +1040,7 @@ ADCIOP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd alpr_config: unconfig - @./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive + @$(MKCONFIG) $(@:_config=) ppc ppc4xx alpr prodrive AP1000_config:unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix @@ -1134,6 +1134,12 @@ EXBITGEN_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +hcu4_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal + +hcu5_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal + HH405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd @@ -1252,7 +1258,7 @@ rainier_nand_config: unconfig @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk sc3_config:unconfig - @./mkconfig $(@:_config=) ppc ppc4xx sc3 + @$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3 taihu_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index caf6690..00c793a 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -unsigned char cfg_simulate_spd_eeprom[128]; +#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) +/************************************************************************* + * + * Bamboo has one bank onboard sdram (plus DIMM) + * + * Fixed memory is composed of : + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data + * + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module + * + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +const unsigned char cfg_simulate_spd_eeprom[128] = { + 0x80, /* number of SPD bytes used: 128 */ + 0x08, /* total number bytes in SPD device = 256 */ + 0x07, /* DDR ram */ +#ifdef CONFIG_DDR_ECC + 0x0C, /* num Row Addr: 12 */ +#else + 0x0D, /* num Row Addr: 13 */ +#endif + 0x09, /* numColAddr: 9 */ + 0x01, /* numBanks: 1 */ + 0x20, /* Module data width: 32 bits */ + 0x00, /* Module data width continued: +0 */ + 0x04, /* 2.5 Volt */ + 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ +#ifdef CONFIG_DDR_ECC + 0x02, /* ECC ON : 02 OFF : 00 */ +#else + 0x00, /* ECC ON : 02 OFF : 00 */ +#endif + 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ + 0, + 0, + 0, + 0x01, /* wcsbc = 1 */ + 0, + 0, + 0x0C, /* casBit (2,2.5) */ + 0, + 0, + 0x00, /* not registered: 0 registered : 0x02*/ + 0, + 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ + 0, + 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ + 0, + 0x50, /* tRpNs = 20 ns */ + 0, + 0x50, /* tRcdNs = 20 ns */ + 45, /* tRasNs */ +#ifdef CONFIG_DDR_ECC + 0x08, /* bankSizeID: 32MB */ +#else + 0x10, /* bankSizeID: 64MB */ +#endif + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; +#endif -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ { @@ -291,73 +452,12 @@ int checkboard(void) return (0); } -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) -/************************************************************************* - * - * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -static void init_spd_array(void) -{ - cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */ - cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */ - -#ifdef CONFIG_DDR_ECC - cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */ - cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */ -#else - cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */ - cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */ -#endif - - cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */ - cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */ - cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */ - cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */ - cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/ - cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */ - cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */ - cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */ - cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */ - cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */ - - cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */ - - cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */ - - cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */ -} -#endif long int initdram (int board_type) { #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; - /* - * First write simulated values in eeprom array for onboard bank 0 - */ - init_spd_array(); - dram_size = spd_sdram(); return dram_size; @@ -371,11 +471,12 @@ int testdram(void) { unsigned long *mem = (unsigned long *)0; const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; + unsigned long k, n, *p32, ctr; + const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024; mtmsr(0); - for (k = 0; k < CFG_KBYTES_SDRAM; + for (k = 0; k < CFG_MBYTES_SDRAM*1024; ++k, mem += (1024 / sizeof(unsigned long))) { if ((k & 1023) == 0) { printf("%3d MB\r", k / 1024); @@ -399,6 +500,34 @@ int testdram(void) } } } + + /* + * Perform a sequence test to ensure that all + * memory locations are uniquely addressable + */ + ctr = 0; + p32 = 0; + while ((unsigned long)p32 != bend) { + if (0 == ((unsigned long)p32 & ((1<<20)-1))) + printf("Writing %3d MB\r", (unsigned long)p32 >> 20); + *p32++ = ctr++; + } + + ctr = 0; + p32 = 0; + while ((unsigned long)p32 != bend) { + if (0 == ((unsigned long)p32 & ((1<<20)-1))) + printf("Verifying %3d MB\r", (unsigned long)p32 >> 20); + + if (*p32 != ctr) { + printf("SDRAM test fails at: %08x\n", p32); + return 1; + } + + ctr++; + p32++; + } + printf("SDRAM test passes\n"); return 0; } @@ -1211,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | init_default_gpio +----------------------------------------------------------------------------*/ -void init_default_gpio(void) +void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) { int i; @@ -1281,7 +1410,7 @@ void init_default_gpio(void) | +----------------------------------------------------------------------------*/ -void update_uart_ios(uart_config_nb_t uart_config) +void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) { switch (uart_config) { @@ -1409,7 +1538,7 @@ void update_uart_ios(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | update_ndfc_ios(void). +----------------------------------------------------------------------------*/ -void update_ndfc_ios(void) +void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ @@ -1427,7 +1556,7 @@ void update_ndfc_ios(void) /*----------------------------------------------------------------------------+ | update_zii_ios(void). +----------------------------------------------------------------------------*/ -void update_zii_ios(void) +void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ @@ -1477,7 +1606,7 @@ void update_zii_ios(void) /*----------------------------------------------------------------------------+ | update_uic_0_3_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_0_3_irq_ios(void) +void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; @@ -1495,7 +1624,7 @@ void update_uic_0_3_irq_ios(void) /*----------------------------------------------------------------------------+ | update_uic_4_9_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_4_9_irq_ios(void) +void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; @@ -1516,7 +1645,7 @@ void update_uic_4_9_irq_ios(void) /*----------------------------------------------------------------------------+ | update_dma_a_b_ios(). +----------------------------------------------------------------------------*/ -void update_dma_a_b_ios(void) +void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; @@ -1537,7 +1666,7 @@ void update_dma_a_b_ios(void) /*----------------------------------------------------------------------------+ | update_dma_c_d_ios(). +----------------------------------------------------------------------------*/ -void update_dma_c_d_ios(void) +void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; @@ -1562,7 +1691,7 @@ void update_dma_c_d_ios(void) /*----------------------------------------------------------------------------+ | update_ebc_master_ios(). +----------------------------------------------------------------------------*/ -void update_ebc_master_ios(void) +void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; @@ -1580,7 +1709,7 @@ void update_ebc_master_ios(void) /*----------------------------------------------------------------------------+ | update_usb2_device_ios(). +----------------------------------------------------------------------------*/ -void update_usb2_device_ios(void) +void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; @@ -1611,20 +1740,21 @@ void update_usb2_device_ios(void) /*----------------------------------------------------------------------------+ | update_pci_patch_ios(). +----------------------------------------------------------------------------*/ -void update_pci_patch_ios(void) +void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; } /*----------------------------------------------------------------------------+ - | set_chip_gpio_configuration(unsigned char gpio_core) + | set_chip_gpio_configuration(unsigned char gpio_core, + | gpio_param_s (*gpio_tab)[GPIO_MAX]) | Put the core impacted by clock modification and sharing in reset. | Config the select registers to resolve the sharing depending of the config. | Configure the GPIO registers. | +----------------------------------------------------------------------------*/ -void set_chip_gpio_configuration(unsigned char gpio_core) +void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) { unsigned char i=0, j=0, reg_offset = 0; unsigned long gpio_reg, gpio_core_add; @@ -1778,11 +1908,12 @@ void configure_ppc440ep_pins(void) CORE_NOT_SELECTED /* PCI_PATCH */ }; + gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; /* Table Default Initialisation + FPGA Access */ - init_default_gpio(); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); + init_default_gpio(gpio_tab); + set_chip_gpio_configuration(GPIO0, gpio_tab); + set_chip_gpio_configuration(GPIO1, gpio_tab); /* Update Table */ force_bup_core_selection(ppc440ep_core_selection, &config_val); @@ -1817,7 +1948,7 @@ void configure_ppc440ep_pins(void) /* UIC 0:3 Selection */ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) { - update_uic_0_3_irq_ios(); + update_uic_0_3_irq_ios(gpio_tab); dma_a_b_unselect_in_fpga(); } @@ -1825,21 +1956,21 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(); + update_uic_4_9_irq_ios(gpio_tab); } /* DMA AB Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(); + update_dma_a_b_ios(gpio_tab); dma_a_b_selection_in_fpga(); } /* DMA CD Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) { - update_dma_c_d_ios(); + update_dma_c_d_ios(gpio_tab); dma_c_d_selection_in_fpga(); } @@ -1848,14 +1979,14 @@ void configure_ppc440ep_pins(void) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(); + update_ebc_master_ios(gpio_tab); } /* PCI Patch Enable */ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(); + update_pci_patch_ios(gpio_tab); } /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ @@ -1871,7 +2002,7 @@ void configure_ppc440ep_pins(void) /* USB2.0 Device Selection */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) { - update_usb2_device_ios(); + update_usb2_device_ios(gpio_tab); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; @@ -1904,7 +2035,7 @@ void configure_ppc440ep_pins(void) /* NAND Flash Selection */ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { - update_ndfc_ios(); + update_ndfc_ios(gpio_tab); #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | @@ -1933,7 +2064,7 @@ void configure_ppc440ep_pins(void) /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; mtsdr(sdr_mfr, sdr0_mfr); @@ -1944,7 +2075,7 @@ void configure_ppc440ep_pins(void) /* RMII Selection */ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; mtsdr(sdr_mfr, sdr0_mfr); @@ -1955,7 +2086,7 @@ void configure_ppc440ep_pins(void) /* SMII Selection */ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; mtsdr(sdr_mfr, sdr0_mfr); @@ -1992,7 +2123,7 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; break; } - update_uart_ios(uart_configuration); + update_uart_ios(uart_configuration, gpio_tab); /* UART Selection in all cases */ uart_selection_in_fpga(uart_configuration); @@ -2014,8 +2145,8 @@ void configure_ppc440ep_pins(void) /* Perform effective access to hardware */ mtsdr(sdr_pfc1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); + set_chip_gpio_configuration(GPIO0, gpio_tab); + set_chip_gpio_configuration(GPIO1, gpio_tab); /* USB2.0 Device Reset must be done after GPIO setting */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index 1459eec..f4d2ae3 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -51,13 +51,12 @@ tlbtab: tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #else tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - /* PCI base & peripherals */ tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds index f6d7183..0375618 100644 --- a/board/amcc/bamboo/u-boot.lds +++ b/board/amcc/bamboo/u-boot.lds @@ -141,8 +141,6 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); - _end = . ; PROVIDE (end = .); } diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index e6429ec..eba0511 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000a000; + info->start[6] = base + 0x0000c000; + info->start[7] = base + 0x0000e000; + for (i = 8; i < info->sector_count; i++) { info->start[i] = - base + (i * 0x00010000) - 0x00030000; + base + ((i-7) * 0x00010000); } } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; for (; i >= 0; i--) { info->start[i] = base + i * 0x00010000; } diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c index f6656c1..dc8c88b 100644 --- a/board/esd/plu405/fpgadata.c +++ b/board/esd/plu405/fpgadata.c @@ -1,1160 +1,1179 @@ - 0x1f,0x8b,0x08,0x08,0x9d,0x76,0x5c,0x3f,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x6c,0x1d,0x55, - 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0xb0,0xf0,0x81,0x1c,0xe3,0x43,0xec,0x3f,0x9d,0x8b,0xc1,0x8c,0xec,0x9e,0xf6,0xfd, + 0x4e,0xec,0x37,0x64,0x57,0x04,0xca,0x1a,0x08,0x3a,0x32,0x0e,0x6c,0xc4,0xa9,0x1f, + 0x2a,0xc0,0xfc,0xb9,0x83,0xbf,0x36,0x81,0x25,0x09,0xb6,0x36,0x45,0x6e,0x8a,0x7a, + 0x00,0x69,0xb1,0x50,0x95,0xf9,0xb0,0x9f,0x19,0x1b,0x71,0xeb,0x67,0xa5,0x7a,0x41, + 0xdd,0x7b,0xde,0x3a,0xaa,0x57,0x2a,0x55,0xf5,0xdb,0xf3,0x83,0x47,0x27,0x57,0xc4, + 0x05,0x34,0xc7,0xd0,0x54,0x53,0xe3,0xe4,0x23,0x90,0x07,0x90,0x0f,0xf1,0xa6,0xff, + 0xf3,0x1c,0xdd,0xfd,0x2f,0x37,0x0b,0x0c,0x78,0x2b,0x0f,0x1c,0xc9,0xf8,0x70,0xf7, + 0xd9,0xb3,0xc4,0x87,0xcf,0xae,0x1d,0x31,0x7c,0xf8,0xc4,0xf0,0xe1,0xef,0x64,0x96, + 0x9d,0xe5,0x70,0x2a,0xe3,0xc3,0x93,0x37,0xce,0x13,0x1f,0x6e,0xbf,0x3e,0x65,0xc0, + 0xec,0x95,0xe5,0xc3,0x5f,0xb7,0x5f,0x6d,0x97,0x78,0xec,0x7d,0x65,0xb0,0xf0,0xe5, + 0x3a,0x1e,0xf6,0xdf,0x14,0x14,0xe7,0x1e,0x2f,0x93,0x31,0x7c,0x68,0x22,0xdf,0xba, + 0xeb,0x0d,0x16,0xfe,0xf3,0x37,0xa5,0x91,0x81,0xe2,0x0d,0x63,0x2c,0x1f,0x52,0xa4, + 0xc4,0xab,0x27,0x33,0x3e,0x3c,0xb0,0xef,0xdc,0x9f,0x77,0xda,0xb4,0xfe,0xbb,0x73, + 0xa3,0xcf,0xe9,0x85,0x39,0x6a,0x7e,0x78,0xf6,0x11,0x8e,0x58,0xf8,0xb6,0xc6,0xbf, + 0x8b,0xf5,0x0f,0x3f,0x0a,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0xfa,0xd4, + 0x65,0x66,0x07,0xc9,0xb3,0x03,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x7a, + 0xb7,0xcc,0xec,0x50,0xe3,0xd9,0x81,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62, + 0xbd,0x5b,0x66,0x76,0xf0,0xcc,0xec,0xf0,0xb1,0x53,0x61,0xb1,0x58,0x2c,0x16,0x8b, + 0xc5,0x62,0xb1,0x58,0xff,0xa3,0x22,0xfa,0x7d,0x1c,0x3c,0xfb,0x23,0x02,0x4d,0xbf, + 0x5a,0xa9,0x46,0xa0,0xde,0xfb,0xf3,0x84,0xf4,0xb5,0x13,0x11,0x6c,0x88,0xe2,0x98, + 0x7f,0x7d,0xb9,0x73,0xdd,0x1b,0x3b,0x1c,0x29,0xc2,0xf0,0x33,0x01,0x00, diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 66cef2f..830ec19 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -221,8 +221,8 @@ int misc_init_r(void) udelay(500); gpio_write_bit(CFG_GPIO_LIME_RST, 1); - /* Lime memory clock adjusted to 133MHz */ - out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ); + /* Lime memory clock adjusted to 100MHz */ + out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ); /* Wait untill time expired. Because of requirements in lime manual */ udelay(300); /* Write lime controller memory parameters */ @@ -237,6 +237,64 @@ int misc_init_r(void) gpio_write_bit(CFG_GPIO_PHY0_RST, 1); gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + /* + * Init display controller + */ + /* Setup dot clock (internal PLL, division rate 1/16) */ + out_be32((void *)0xc1fd0100, 0x00000f00); + + /* Lime L0 init (16 bpp, 640x480) */ + out_be32((void *)0xc1fd0020, 0x801401df); + out_be32((void *)0xc1fd0024, 0x0); + out_be32((void *)0xc1fd0028, 0x0); + out_be32((void *)0xc1fd002c, 0x0); + out_be32((void *)0xc1fd0110, 0x0); + out_be32((void *)0xc1fd0114, 0x0); + out_be32((void *)0xc1fd0118, 0x01df0280); + + /* Display timing init */ + out_be32((void *)0xc1fd0004, 0x031f0000); + out_be32((void *)0xc1fd0008, 0x027f027f); + out_be32((void *)0xc1fd000c, 0x015f028f); + out_be32((void *)0xc1fd0010, 0x020c0000); + out_be32((void *)0xc1fd0014, 0x01df01ea); + out_be32((void *)0xc1fd0018, 0x0); + out_be32((void *)0xc1fd001c, 0x01e00280); + +#if 1 + /* + * Clear framebuffer using Lime's drawing engine + * (draw blue rect. with white border around it) + */ + /* Setup mode and fbbase, xres, fg, bg */ + out_be32((void *)0xc1ff0420, 0x8300); + out_be32((void *)0xc1ff0440, 0x0000); + out_be32((void *)0xc1ff0444, 0x0280); + out_be32((void *)0xc1ff0480, 0x7fff); + out_be32((void *)0xc1ff0484, 0x0000); + /* Reset clipping rectangle */ + out_be32((void *)0xc1ff0454, 0x0000); + out_be32((void *)0xc1ff0458, 0x0280); + out_be32((void *)0xc1ff045c, 0x0000); + out_be32((void *)0xc1ff0460, 0x01e0); + /* Draw white rect. */ + out_be32((void *)0xc1ff04a0, 0x09410000); + out_be32((void *)0xc1ff04a0, 0x00000000); + out_be32((void *)0xc1ff04a0, 0x01e00280); + udelay(2000); + /* Draw blue rect. */ + out_be32((void *)0xc1ff0480, 0x001f); + out_be32((void *)0xc1ff04a0, 0x09410000); + out_be32((void *)0xc1ff04a0, 0x00010001); + out_be32((void *)0xc1ff04a0, 0x01de027e); +#endif + /* Display enable, L0 layer */ + out_be32((void *)0xc1fd0100, 0x80010f00); + + /* TFT-LCD enable - PWM duty, lamp on */ + out_be32((void *)0xc4000024, 0x64); + out_be32((void *)0xc4000020, 0x701); + return 0; } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index b6863b6..f906b85 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -473,7 +473,7 @@ static void program_ecc(u32 start_address, blank_string(strlen(str)); } else { /* ECC bit set method for cached memory */ -#if 1 /* test-only: will remove this define later, when ECC problems are solved! */ +#if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* * Some boards (like lwmon5) need to preserve the memory * content upon ECC generation (for the log-buffer). @@ -486,6 +486,11 @@ static void program_ecc(u32 start_address, current_address = start_address; while (current_address < end_address) { + /* + * TODO: Th following sequence doesn't work correctly. + * Just invalidating and flushing the cache doesn't + * seem to trigger the re-write of the memory. + */ ppcDcbi(current_address); ppcDcbf(current_address); current_address += CFG_CACHELINE_SIZE; @@ -514,19 +519,6 @@ static void program_ecc(u32 start_address, } #endif -static __inline__ u32 get_mcsr(void) -{ - u32 val; - - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; -} - -static __inline__ void set_mcsr(u32 val) -{ - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); -} - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -534,8 +526,6 @@ static __inline__ void set_mcsr(u32 val) ************************************************************************/ long int initdram (int board_type) { - u32 val; - #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* CL=3 */ mtsdram(DDR0_02, 0x00000000); @@ -640,14 +630,6 @@ long int initdram (int board_type) * Perform data eye search if requested. */ denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20); - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - val = get_mcsr(); - set_mcsr(val); #endif #ifdef CONFIG_DDR_ECC @@ -657,5 +639,12 @@ long int initdram (int board_type) program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); #endif + /* + * Clear possible errors resulting from data-eye-search. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + return (CFG_MBYTES_SDRAM << 20); } diff --git a/board/netstal/common/flash.c b/board/netstal/common/flash.c new file mode 100644 index 0000000..be2cb37 --- /dev/null +++ b/board/netstal/common/flash.c @@ -0,0 +1,528 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + * + * Modified 6/6/2007 + * Added isync + * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com + * + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#if CFG_MAX_FLASH_BANKS != 1 +#error "CFG_MAX_FLASH_BANKS must be 1" +#endif +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*-----------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + + /* Init: no FLASHes known */ + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, + &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM + monitor_flash_len - 1, + &flash_info[0]); + flash_info[0].size = size_b0; + + return size_b0; +} + + +/*-----------------------------------------------------------------------*/ +/* + * This implementation assumes that the flash chips are uniform sector + * devices. This is true for all likely flash devices on a HCUx. + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + unsigned idx; + unsigned long sector_size = info->size / info->sector_count; + + for (idx = 0; idx < info->sector_count; idx += 1) { + info->start[idx] = base + (idx * sector_size); + } +} + +/*-----------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("ST Micro "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* (Reduced table of only parts expected in HCUx boards.) */ + switch (info->flash_id) { + case FLASH_MAN_AMD | FLASH_AM040: + printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_MAN_STM | FLASH_AM040: + printf ("MM29W040W (512 Kbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; +} + +/*-----------------------------------------------------------------------*/ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write auto select command: read Manufacturer ID */ + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + asm("isync"); + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + asm("isync"); + + value = addr2[0]; + asm("isync"); + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + printf("Unknown flash manufacturer code: 0x%x at %p\n", + value, addr); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* Calculate the sector offsets (Use HCUx Optimized code). */ + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, + *(A7 .. A0) = 0x02 + * D0 = 1 if protected + */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*-----------------------------------------------------------------------*/ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors not erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf ("Erasing sector %p\n", addr2); /* CLH */ + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* block erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; + for (i = 0; i < 50; i++) udelay (1000); + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* sector erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7 (info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c new file mode 100644 index 0000000..1e06780 --- /dev/null +++ b/board/netstal/common/nm_bsp.c @@ -0,0 +1,41 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include <common.h> +#include <command.h> + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +/* + * Command nm_bsp: Netstal Maschinen BSP specific command + */ +int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__, + flag, argc, argv[0]); + printf("Netstal Maschinen BSP specific command. None at the moment.\n"); + return 0; +} + +U_BOOT_CMD( + nm_bsp, 1, 1, nm_bsp, + "nm_bsp - Netstal Maschinen BSP specific command. \n", + "Help for Netstal Maschinen BSP specific command.\n" + ); +#endif diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile new file mode 100644 index 0000000..d9825a5 --- /dev/null +++ b/board/netstal/hcu4/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2007 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +vpath flash.c ../common +COBJS = $(BOARD).o flash.o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/hcu4/README.txt b/board/netstal/hcu4/README.txt new file mode 100644 index 0000000..1e9c64a --- /dev/null +++ b/board/netstal/hcu4/README.txt @@ -0,0 +1,59 @@ +HCU4 Configuration Details + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xf4000000 - 0xf4000fff + +The 405GPr includes a 4K on-chip memory that can be placed however +software chooses. I choose to place the memory at this address, to +keep it out of the cachable areas. + + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC405GPr +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +0x70000000 + +Chip-Select 3: CAN Interface +---------------------------- +0x7800000 + + +Chip-Select 4: IMC-bus standard +------------------------------- + +Our IO-Bus (slow version) + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +Our IO-Bus (fast, but not yet use) + + +Memory Bank 1 -- SDRAM +------------------------------------- + +0x00000000 - 0x1ffffff # Default 32 MB diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk new file mode 100644 index 0000000..376609a --- /dev/null +++ b/board/netstal/hcu4/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: HCU4 boards +# + +TEXT_BASE = 0xFFFa0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c new file mode 100644 index 0000000..252aaa7 --- /dev/null +++ b/board/netstal/hcu4/hcu4.c @@ -0,0 +1,403 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm-ppc/u-boot.h> +#include "../common/nm_bsp.c" + +DECLARE_GLOBAL_DATA_PTR; + +#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000) + +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } + +#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ + +#define DO_UGLY_SDRAM_WORKAROUND + +enum { + /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + +void sysLedSet(u32 value); +long int spd_sdram(int(read_spd)(uint addr)); + +#ifdef CONFIG_SPD_EEPROM +#define DEBUG +#endif + +#if defined(DEBUG) +void show_sdram_registers(void); +#endif + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +#define CPC0_CR0 0xb1 /* Chip control register 0 */ +#define CPC0_CR1 0xb2 /* Chip control register 1 */ +/* Attention: If you want 1 microsecs times from the external oscillator + * use 0x00804051. But this causes problems with u-boot and linux! + */ +#define CPC0_CR1_VALUE 0x00004051 +#define CPC0_ECR 0xaa /* Edge condition register */ +#define EBC0_CFG 0x23 /* External Peripheral Control Register */ +#define CPC0_EIRR 0xb6 /* External Interrupt Register */ + + +int board_early_init_f (void) +{ + /*-------------------------------------------------------------------+ + | Interrupt controller setup for the HCU4 board. + | Note: IRQ 0-15 405GP internally generated; high; level sensitive + | IRQ 16 405GP internally generated; low; level sensitive + | IRQ 17-24 RESERVED/UNUSED + | IRQ 31 (EXT IRQ 6) (unused) + +-------------------------------------------------------------------*/ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtdcr(CPC0_CR1, CPC0_CR1_VALUE); + mtdcr(CPC0_ECR, 0x60606000); + mtdcr(CPC0_EIRR, 0x7c000000); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} +#endif + +int checkboard (void) +{ + unsigned int j; + u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER; + u16 generation = *boardVersReg & 0xf0; + u16 index = *boardVersReg & 0x0f; + + /* Force /RTS to active. The board it not wired quite + correctly to use cts/rtc flow control, so just force the + /RST active and forget about it. */ + writeb (readb (0xef600404) | 0x03, 0xef600404); + printf ("\nNetstal Maschinen AG "); + if (generation == HW_GENERATION_HCU3) + printf ("HCU3: index %d\n\n", index); + else if (generation == HW_GENERATION_HCU4) + printf ("HCU4: index %d\n\n", index); + /* GPIO here noch nicht richtig initialisert !!! */ + sysLedSet(0); + for (j = 0; j < 7; j++) { + sysLedSet(1 << j); + udelay(50 * 1000); + } + + return 0; +} + +u32 sysLedGet(void) +{ + return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; +} + +void sysLedSet(u32 value /* value to place in LEDs */) +{ + u32 tmp = ~value; + u32 *ledReg; + + tmp = (tmp << 23) | 0x7FFFFF; + ledReg = (u32 *)GPIO0_OR; + *ledReg = tmp; +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram or initdram + * used for HCUx + */ +void sdram_init(void) +{ + return; +} + +#if defined(DEBUG) +void show_sdram_registers(void) +{ + u32 value; + + printf ("SDRAM Controller Registers --\n"); + mfsdram(value, mem_mcopt1); + printf (" SDRAM0_CFG : 0x%08x\n", value); + mfsdram(value, mem_status); + printf (" SDRAM0_STATUS: 0x%08x\n", value); + mfsdram(value, mem_mb0cf); + printf (" SDRAM0_B0CR : 0x%08x\n", value); + mfsdram(value, mem_mb1cf); + printf (" SDRAM0_B1CR : 0x%08x\n", value); + mfsdram(value, mem_sdtr1); + printf (" SDRAM0_TR : 0x%08x\n", value); + mfsdram(value, mem_rtr); + printf (" SDRAM0_RTR : 0x%08x\n", value); +} +#endif + +/* + * this is even after checkboard. It returns the size of the SDRAM + * that we have installed. This function is called by board_init_f + * in lib_ppc/board.c to initialize the memory and return what I + * found. These are default value, which will be overridden later. + */ + +long int fixed_hcu4_sdram (int board_type) +{ +#ifdef DEBUG + printf (__FUNCTION__); +#endif + /* disable memory controller */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x00000000); + + udelay (500); + + /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besra); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besrb); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_ECCCFG (disable ECC) */ + mtdcr (memcfga, mem_ecccf); + mtdcr (memcfgd, 0x00000000); + + /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ + mtdcr (memcfga, mem_eccerr); + mtdcr (memcfgd, 0xffffffff); + + /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 + * TODO ngngng + */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, 0x008a4015); + + /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 + * TODO ngngng + */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, 0x00062001); + + /* refresh timer = 0x400 */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, 0x04000000); + + /* Power management idle timer set to the default. */ + mtdcr (memcfga, mem_pmit); + mtdcr (memcfgd, 0x07c00000); + + udelay (500); + + /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x90800000); + +#ifdef DEBUG + printf ("%s: done\n", __FUNCTION__); +#endif + return SDRAM_LEN; +} + +/*---------------------------------------------------------------------------+ + * getSerialNr + *---------------------------------------------------------------------------*/ +static u32 getSerialNr(void) +{ + u32 *serial = (u32 *)CFG_FLASH_BASE; + + if (*serial == 0xffffffff) + return get_ticks(); + + return *serial; +} + + +/*---------------------------------------------------------------------------+ + * misc_init_r. + *---------------------------------------------------------------------------*/ + +int misc_init_r(void) +{ + char *s = getenv("ethaddr"); + char *e; + int i; + u32 serial = getSerialNr(); + + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + if (gd->bd->bi_enetaddr[3] == 0 && + gd->bd->bi_enetaddr[4] == 0 && + gd->bd->bi_enetaddr[5] == 0) { + char ethaddr[22]; + /* [0..3] Must be in sync with CONFIG_ETHADDR */ + gd->bd->bi_enetaddr[0] = 0x00; + gd->bd->bi_enetaddr[1] = 0x60; + gd->bd->bi_enetaddr[2] = 0x13; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, + ethaddr, serial); + setenv ("ethaddr", ethaddr); + } + return 0; +} + +#ifdef DO_UGLY_SDRAM_WORKAROUND +#include "i2c.h" + +void set_spd_default_value(unsigned int spd_addr,uchar def_val) +{ + uchar value; + int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ; + + if (res == 0 && value == 0xff) { + res = i2c_write(SPD_EEPROM_ADDRESS, + spd_addr, 1, &def_val, 1) ; +#ifdef DEBUG + printf("%s: Setting spd offset %3d to %3d res %d\n", + __FUNCTION__, spd_addr, def_val, res); +#endif + } +} +#endif + +long int initdram(int board_type) +{ + long dram_size = 0; + +#if !defined(CONFIG_SPD_EEPROM) + dram_size = fixed_hcu4_sdram(); +#else +#ifdef DO_UGLY_SDRAM_WORKAROUND + /* Workaround if you have no working I2C-EEPROM-SPD-configuration */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + set_spd_default_value(2, 4); /* SDRAM Type */ + set_spd_default_value(7, 0); /* module width, high byte */ + set_spd_default_value(12, 1); /* Refresh or 0x81 */ + + /* Only correct for HCU3 with 32 MB RAM*/ + /* Number of bytes used by module manufacturer */ + set_spd_default_value( 0, 128); + set_spd_default_value( 1, 11 ); /* Total SPD memory size */ + set_spd_default_value( 2, 4 ); /* Memory type */ + set_spd_default_value( 3, 12 ); /* Number of row address bits */ + set_spd_default_value( 4, 9 ); /* Number of column address bits */ + set_spd_default_value( 5, 1 ); /* Number of module rows */ + set_spd_default_value( 6, 32 ); /* Module data width, LSB */ + set_spd_default_value( 7, 0 ); /* Module data width, MSB */ + set_spd_default_value( 8, 1 ); /* Module interface signal levels */ + /* SDRAM cycle time for highest CL (Tclk) */ + set_spd_default_value( 9, 112); + /* SDRAM access time from clock for highest CL (Tac) */ + set_spd_default_value(10, 84 ); + set_spd_default_value(11, 2 ); /* Module configuration type */ + set_spd_default_value(12, 128); /* Refresh rate/type */ + set_spd_default_value(13, 16 ); /* Primary SDRAM width */ + set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */ + /* SDRAM device attributes, min clock delay for back to back */ + /*random column addresses (Tccd) */ + set_spd_default_value(15, 1 ); + /* SDRAM device attributes, burst lengths supported */ + set_spd_default_value(16, 143); + /* SDRAM device attributes, number of banks on SDRAM device */ + set_spd_default_value(17, 4 ); + /* SDRAM device attributes, CAS latency */ + set_spd_default_value(18, 6 ); + /* SDRAM device attributes, CS latency */ + set_spd_default_value(19, 1 ); + /* SDRAM device attributes, WE latency */ + set_spd_default_value(20, 1 ); + set_spd_default_value(21, 0 ); /* SDRAM module attributes */ + /* SDRAM device attributes, general */ + set_spd_default_value(22, 14 ); + /* SDRAM cycle time for 2nd highest CL (Tclk) */ + set_spd_default_value(23, 117); + /* SDRAM access time from clock for2nd highest CL (Tac) */ + set_spd_default_value(24, 84 ); + /* SDRAM cycle time for 3rd highest CL (Tclk) */ + set_spd_default_value(25, 0 ); + /* SDRAM access time from clock for3rd highest CL (Tac) */ + set_spd_default_value(26, 0 ); + set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */ + /* Minimum row active to row active delay (Trrd) */ + set_spd_default_value(28, 14 ); + set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */ + set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */ + set_spd_default_value(31, 8 ); /* Module bank density */ + /* Command and Address signal input setup time */ + set_spd_default_value(32, 21 ); + /* Command and Address signal input hold time */ + set_spd_default_value(33, 8 ); + set_spd_default_value(34, 21 ); /* Data signal input setup time */ + set_spd_default_value(35, 8 ); /* Data signal input hold time */ +#endif /* DO_UGLY_SDRAM_WORKAROUND */ + dram_size = spd_sdram(0); +#endif + +#ifdef DEBUG + show_sdram_registers(); +#endif + +#if defined(CFG_DRAM_TEST) + bcu4_testdram(dram_size); + printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024)); +#endif + + return dram_size; +} diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds new file mode 100644 index 0000000..b6e28f8 --- /dev/null +++ b/board/netstal/hcu4/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : { + /* The start.o file includes the initial jump vector that + must be located in the beginning. It is the basic run- + time function that calls all other functions. */ + cpu/ppc4xx/start.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile new file mode 100644 index 0000000..eee310b --- /dev/null +++ b/board/netstal/hcu5/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2007 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +vpath flash.c ../common +COBJS = $(BOARD).o sdram.o flash.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt new file mode 100644 index 0000000..3118da9 --- /dev/null +++ b/board/netstal/hcu5/README.txt @@ -0,0 +1,174 @@ +HCU5 configuration details and startup sequence + +(C) Copyright 2007 Netstal Maschinen AG + Niklaus Giger (Niklaus.Giger@netstal.com) + +TODO: +----- +- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT ! + - Does not occur if both EMAC are connected +- Fix RTS/CTS problem (HW?) + CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after + Switching to interrupt driven serial input mode +- Make vxWorks start from u-boot. Possible reasons + - Does vxWorks need an entry for the Machine Check interrupt like this + tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ? + +Caveats: +-------- +Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c) +see hcu5.c. + + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xe0010000- 0xe0013fff CFG_OCM_BASE +The 440EPx includes a 16K on-chip memory that can be placed however +software chooses. + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC440EPX +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +Not used + +Chip-Select 3: CAN Interface +---------------------------- +0xc800000: 2 Intel 82527 CAN-Controller + + +Chip-Select 4: IMC-bus standard +------------------------------- + +0xcc00000: Netstal specific IO-Bus + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +0xce00000: Netstal specific IO-Bus (fast, but not yet used) + + +Memory Bank 1 -- DDR2 +------------------------------------- + +0x00000000 - 0xfffffff # Default 256 MB + +PCI ?? + +USB ?? +Only USB_STORAGE is enabled to load vxWorks +from a memory stick. + +System-LEDs ??? (Analog zu HCU4 ???) + +Startup sequence +---------------- + +(cpu/ppc4xx/resetvec.S) +depending on configs option +call _start_440 _start_pci oder _start + +(cpu/ppc4xx/start.S) + +_start_440: + initialize register like + CCR0 + debug + setup interrupt vectors + configure cache regions + clear and setup TLB + enable internal RAM + jump start_ram + which in turn will jump to start +_start: + Clear and set up some registers. + Debug setup + Setup the internal SRAM + Setup the stack in internal SRAM + setup stack pointer (r1) + setup GOT + call cpu_init_f /* run low-level CPU init code (from Flash) */ + + call cpu_init_f + board_init_f: (lib_ppc\board.c) + init_sequence defines a list of function to be called + board_early_init_f: (board/netstal/hcu5/hcu5.c) + We are using Bootstrap-Option A + if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot + Setup the GPIO pins + Setup the interrupt controller polarities, triggers, etc. + Ethernet, PCI, USB enable + setup BOOT FLASH (Chip timing) + init_baudrate, + serial_init + checkcpu + misc_init_f #ifdef + init_func_i2c #ifdef + post_init_f #ifdef + init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c + (EYE function removed!!) + test_dram call + + * Reserve memory at end of RAM for (top down in that order): + * - kernel log buffer + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + Save local variables to board info struct + call relocate_code() does not return + relocate_code: (cpu/ppc4xx/start.S) +------------------------------------------------------- +From now on our copy is in RAM and we will run from there, + starting with board_init_r +------------------------------------------------------- + board_init_r: (lib_ppc\board.c) + setup bd function pointers + trap_init + flash_init: (board/netstal/hcu5/flash.c) + /* setup for u-boot erase, update */ + setup bd flash info + cpu_init_r: (cpu/ppc4xx/cpu_init.c) + peripheral chip select in using defines like + CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h + mem_malloc_init + malloc_bin_reloc + spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + env_relocated + misc_init_r(bd): (board/netstal/hcu5.c) + ethaddr mit serial number ergänzen + Then we will somehow go into the command loop + +Most of the HW specific code for the HCU5 may be found in +include/configs/hcu5.h +board/netstal/hcu5/* +cpu/ppc4xx/* +lib_ppc/* +include/ppc440.h + +Drivers for serial etc are found under drivers/ + +Don't ask question if you did not look at the README !! +Most CFG_* and CONFIG_* switches are mentioned/explained there. diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk new file mode 100644 index 0000000..cfd5744 --- /dev/null +++ b/board/netstal/hcu5/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: HCU5 boards +# + +TEXT_BASE = 0xFFFa0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c new file mode 100644 index 0000000..23df081 --- /dev/null +++ b/board/netstal/hcu5/hcu5.c @@ -0,0 +1,525 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <ppc440.h> +#include <asm/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sysLedSet(u32 value); + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#undef BOOTSTRAP_OPTION_A_ACTIVE + +#define SDR0_CP440 0x0180 + +#define SYSTEM_RESET 0x30000000 +#define CHIP_RESET 0x20000000 + +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +#define SYS_IO_ADDRESS 0xcce00000 + +#define DEFAULT_ETH_ADDR "ethaddr" +/* ethaddr for first or etha1ddr for second ethernet */ + +enum { + /* HW_GENERATION_HCU1 is no longer supported */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_HCU5 = 0x30, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +int board_early_init_f(void) +{ + u32 reg; + +#ifdef BOOTSTRAP_OPTION_A_ACTIVE + /* Booting with Bootstrap Option A + * First boot, with CPR0_ICFG_RLI_MASK == 0 + * no we setup varios boot strapping register, + * then we do reset the PPC440 using a chip reset + * Unfortunately, we cannot use this option, as Nto1 is not set + * with Bootstrap Option A and cannot be changed later on by SW + * There are no other possible boostrap options with a 8 bit ROM + * See Errata (Version 1.04) CHIP_9 + */ + + u32 cpr0icfg; + u32 dbcr; + + mfcpr(CPR0_ICFG, cpr0icfg); + if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { + mtcpr(CPR0_MALD, 0x02000000); + mtcpr(CPR0_OPBD, 0x02000000); + mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ + mtcpr(CPR0_PLLC, 0x40000238); + mtcpr(CPR0_PLLD, 0x01010414); + mtcpr(CPR0_PRIMAD, 0x01000000); + mtcpr(CPR0_PRIMBD, 0x01000000); + mtcpr(CPR0_SPCID, 0x03000000); + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ + mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); + + /* + * Initiate system reset in debug control register DBCR + */ + dbcr = mfspr(dbcr0); + mtspr(dbcr0, dbcr | CHIP_RESET); + } + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ +#endif + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /* test-only: take GPIO init from pcs440ep ???? in config file */ + out32(GPIO0_OR, 0x00000000); + out32(GPIO0_TCR, 0x7C2FF1CF); + out32(GPIO0_OSRL, 0x40055000); + out32(GPIO0_OSRH, 0x00000000); + out32(GPIO0_TSRL, 0x40055000); + out32(GPIO0_TSRH, 0x00000400); + out32(GPIO0_ISR1L, 0x40000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2H, 0x00000000); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OR, 0x00000000); + out32(GPIO1_TCR, 0xC6007FFF); + out32(GPIO1_OSRL, 0x00140000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x00000000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x05415555); + out32(GPIO1_ISR1H, 0x40000000); + out32(GPIO1_ISR2L, 0x00000000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x00000000); + out32(GPIO1_ISR3H, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ + mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ + + /* PCI arbiter enabled */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); + + pci_pre_init(0); + + /* setup BOOT FLASH */ + mtsdr(SDR0_CUST0, 0xC0082350); + + return 0; +} + +int board_pre_init(void) +{ + return board_early_init_f(); +} + +int checkboard(void) +{ + unsigned int j; + u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; + u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; + u16 generation = *boardVersReg & 0xf0; + u16 index = *boardVersReg & 0x0f; + u32 ecid0, ecid1, ecid2, ecid3; + + printf("Netstal Maschinen AG: "); + if (generation == HW_GENERATION_HCU3) + printf("HCU3: index %d", index); + else if (generation == HW_GENERATION_HCU4) + printf("HCU4: index %d", index); + else if (generation == HW_GENERATION_HCU5) + printf("HCU5: index %d", index); + printf(" HW 0x%02x\n", *hwVersReg & 0xff); + mfsdr(SDR0_ECID0, ecid0); + mfsdr(SDR0_ECID1, ecid1); + mfsdr(SDR0_ECID2, ecid2); + mfsdr(SDR0_ECID3, ecid3); + + printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); + for (j = 0;j < 6; j++) { + sysLedSet(1 << j); + udelay(200 * 1000); + } + + return 0; +} + +u32 sysLedGet(void) +{ + return in16(SYS_IO_ADDRESS) & 0x3f; +} + +void sysLedSet(u32 value /* value to place in LEDs */) +{ + out16(SYS_IO_ADDRESS, value); +} + +/*---------------------------------------------------------------------------+ + * getSerialNr + *---------------------------------------------------------------------------*/ +static u32 getSerialNr(void) +{ + u32 *serial = (u32 *)CFG_FLASH_BASE; + + if (*serial == 0xffffffff) + return get_ticks(); + + return *serial; +} + + +/*---------------------------------------------------------------------------+ + * misc_init_r. + *---------------------------------------------------------------------------*/ +int misc_init_r(void) +{ + char *s = getenv(DEFAULT_ETH_ADDR); + char *e; + int i; + u32 serial = getSerialNr(); + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + if (gd->bd->bi_enetaddr[3] == 0 && + gd->bd->bi_enetaddr[4] == 0 && + gd->bd->bi_enetaddr[5] == 0) { + char ethaddr[22]; + + /* Must be in sync with CONFIG_ETHADDR */ + gd->bd->bi_enetaddr[0] = 0x00; + gd->bd->bi_enetaddr[1] = 0x60; + gd->bd->bi_enetaddr[2] = 0x13; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + /* byte[5].bit 0 must be zero */ + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, + ethaddr, serial); + setenv(DEFAULT_ETH_ADDR, ethaddr); + } + +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + /* + * USB stuff... + */ + + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ + + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets*/ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + return 0; +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------+ + * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. + * Workaround: Disable write pipelining to DDR SDRAM by setting + * PLB0_ACR[WRP] = 0. + *-------------------------------------------------------------------*/ + + /*-------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ + mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ + + /*-------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ + mtdcr(plb4_acr, addr); /* Sequoia */ + + /*-------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */ + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ + + /* mtdcr(plb0_acr, addr); */ /* Sequoia */ + mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) ; + /* mtdcr(plb1_acr, addr); */ /* Sequoia */ + mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*-------------------------------------------------------------+ + * Set up Direct MMIO registers + *-------------------------------------------------------------*/ + /*-------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address + | 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +-------------------------------------------------------------*/ + /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0MA, 0x00000000); + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM0MA, 0xE0000001); + + /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1MA, 0x00000000); + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM1MA, 0xE0000001); + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*------------------------------------------------------------------+ + * Set up Configuration registers + *------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*---------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif +/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S new file mode 100644 index 0000000..5ab6cd2 --- /dev/null +++ b/board/netstal/hcu5/init.S @@ -0,0 +1,79 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* vxWorks needs this entry for the Machine Check interrupt, */ + /* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ + + /* + * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for EBC (CFG_CPLD) */ + /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ + /* CAN */ + tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* IMC + CPLD */ + tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* IMC-Fast */ + tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB for SDRAM will be added by initdram (sdram.c) */ + + tlbtab_end diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c new file mode 100644 index 0000000..4039195 --- /dev/null +++ b/board/netstal/hcu5/sdram.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2007 + * Niklaus Giger (Niklaus.Giger@netstal.com) + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debug output */ +#undef DEBUG + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <ppc440.h> + +void sysLedSet(u32 value); +void dcbz_area(u32 start_address, u32 num_bytes); +void dflush(void); + +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) + +#ifdef CFG_ENABLE_SDRAM_CACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ +#endif + +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); + +#ifdef CONFIG_ADD_RAM_INFO +void board_add_ram_info(int use_default) +{ + PPC440_SYS_INFO board_cfg; + u32 val; + mfsdram(DDR0_22, val); + val &= DDR0_22_CTRL_RAW_MASK; + switch (val) { + case DDR0_22_CTRL_RAW_ECC_DISABLE: + puts(" (ECC disabled"); + break; + case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY: + puts(" (ECC check only"); + break; + case DDR0_22_CTRL_RAW_NO_ECC_RAM: + puts(" (no ECC ram"); + break; + case DDR0_22_CTRL_RAW_ECC_ENABLE: + puts(" (ECC enabled"); + break; + } + + get_sys_info(&board_cfg); + printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000); + + mfsdram(DDR0_03, val); + val = DDR0_03_CASLAT_DECODE(val); + printf(", CL%d)", val); +} +#endif + +/*-------------------------------------------------------------------- + * wait_for_dlllock. + *--------------------------------------------------------------------*/ +static int wait_for_dlllock(void) +{ + unsigned long val; + int wait = 0; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_17); + val = DDR0_17_DLLLOCKREG_UNLOCKED; + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_17_DLLLOCKREG_MASK) == + DDR0_17_DLLLOCKREG_LOCKED) + /* dlllockreg bit on */ + return 0; + else + wait++; + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + + return -1; +} + +/*********************************************************************** + * + * sdram_panic -- Panic if we cannot configure the sdram correctly + * + ************************************************************************/ +void sdram_panic(const char *reason) +{ + printf("\n%s: reason %s", __FUNCTION__, reason); + sysLedSet(0xff); + while (1) { + } + /* Never return */ +} + +#ifdef CONFIG_DDR_ECC +static void blank_string(int size) +{ + int i; + + for (i=0; i<size; i++) + putc('\b'); + for (i=0; i<size; i++) + putc(' '); + for (i=0; i<size; i++) + putc('\b'); +} +/*---------------------------------------------------------------------------+ + * program_ecc. + *---------------------------------------------------------------------------*/ +static void program_ecc(unsigned long start_address, unsigned long num_bytes, + unsigned long tlb_word2_i_value) +{ + unsigned long current_address= start_address; + int loopi = 0; + u32 val; + + char str[] = "ECC generation -"; + char slash[] = "\\|/-\\|/-"; + + sync(); + eieio(); + + puts(str); + + if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { + /* ECC bit set method for non-cached memory */ + /* This takes various seconds */ + for(current_address = 0; current_address < num_bytes; + current_address += sizeof(u32)) { + *(u32 *)current_address = 0; + if ((current_address % (2 << 20)) == 0) { + putc('\b'); + putc(slash[loopi++ % 8]); + } + } + } else { + /* ECC bit set method for cached memory */ + /* Fast method, no noticeable delay */ + dcbz_area(start_address, num_bytes); + dflush(); + } + blank_string(strlen(str)); + + /* Clear error status */ + mfsdram(DDR0_00, val); + mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + + /* Set 'int_mask' parameter to functionnal value */ + mfsdram(DDR0_01, val); + mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | + DDR0_01_INT_MASK_ALL_OFF)); + + return; +} + +#endif + +/*********************************************************************** + * + * initdram -- 440EPx's DDR controller is a DENALI Core + * + ************************************************************************/ +long int initdram (int board_type) +{ +#define HCU_HW_SDRAM_CONFIG_MASK 0x7 +#define INVALID_HW_CONFIG "Invalid HW-Config" + u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; + unsigned int dram_size = 0; + + mtsdram(DDR0_02, 0x00000000); + + /* Values must be kept in sync with Excel-table <<A0001492.>> ! */ + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02030602); + mtsdram(DDR0_04, 0x0A020200); + mtsdram(DDR0_05, 0x02020307); + switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { + case 0: + dram_size = 128 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ + mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ + mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ + break; + case 1: + dram_size = 256 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ + mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ + mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ + break; + default: + sdram_panic(INVALID_HW_CONFIG); + break; + } + dram_size -= 16 * 1024 * 1024; + mtsdram(DDR0_07, 0x00090100); + /* + * TCPD=200 cycles of clock input is required to lock the DLL. + * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + */ + mtsdram(DDR0_08, 0x02C80001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000100); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x1D000000); + mtsdram(DDR0_18, 0x1D1D1D1D); + mtsdram(DDR0_19, 0x1D1D1D1D); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); + #define ECC_RAM 0x03267F0B + #define NO_ECC_RAM 0x00267F0B +#ifdef CONFIG_DDR_ECC + mtsdram(DDR0_22, ECC_RAM); +#else + mtsdram(DDR0_22, NO_ECC_RAM); +#endif + + mtsdram(DDR0_23, 0x00000000); + mtsdram(DDR0_24, 0x01020001); + mtsdram(DDR0_26, 0x2D930517); + mtsdram(DDR0_27, 0x00008236); + mtsdram(DDR0_28, 0x00000000); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000006); + mtsdram(DDR0_44, 0x00000003); + mtsdram(DDR0_02, 0x00000001); + wait_for_dlllock(); + mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ + + /* + * Program tlb entries for this size (dynamic) + */ + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + + /* + * Setup 2nd TLB with same physical address but different virtual + * address with cache enabled. This is done for fast ECC generation. + */ + program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + +#ifdef CONFIG_DDR_ECC + /* + * If ECC is enabled, initialize the parity bits. + */ + program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0); +#endif + + return (dram_size); +} diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds new file mode 100644 index 0000000..6d255a9 --- /dev/null +++ b/board/netstal/hcu5/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); + +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/common/flash.c b/common/flash.c index a64bc98..888ff9c 100644 --- a/common/flash.c +++ b/common/flash.c @@ -47,16 +47,16 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info) short s_end = info->sector_count - 1; /* index of last sector */ int i; - debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n", - (flag & FLAG_PROTECT_SET) ? "ON" : - (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???", - from, to); - /* Do nothing if input data is bad. */ if (info->sector_count == 0 || info->size == 0 || to < from) { return; } + debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n", + (flag & FLAG_PROTECT_SET) ? "ON" : + (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???", + from, to); + /* There is nothing to do if we have no data about the flash * or the protect range and flash range don't overlap. */ diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index d6c4be5..bf68cc1 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006 - 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Copyright (c) 2005 Cisco Systems. All rights reserved. @@ -40,6 +40,34 @@ enum { LNKW_X8 = 0x8 }; +static inline int pcie_in_8(const volatile unsigned char __iomem *addr) +{ + int ret; + + PCIE_IN(lbzx, ret, addr); + + return ret; +} + +static inline int pcie_in_le16(const volatile unsigned short __iomem *addr) +{ + int ret; + + PCIE_IN(lhbrx, ret, addr) + + return ret; +} + +static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + PCIE_IN(lwbrx, ret, addr); + + return ret; +} + + static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { @@ -55,13 +83,13 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, switch (len) { case 1: - *val = in_8(hose->cfg_data + offset); + *val = pcie_in_8(hose->cfg_data + offset); break; case 2: - *val = in_le16((u16 *)(hose->cfg_data + offset)); + *val = pcie_in_le16((u16 *)(hose->cfg_data + offset)); break; default: - *val = in_le32((u32 *)(hose->cfg_data + offset)); + *val = pcie_in_le32((u32*)(hose->cfg_data + offset)); break; } return 0; @@ -783,9 +811,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + if (ppc440spe_revB()) { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + } else { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); + } /* * Set up outbound translation to hose->mem_space from PLB diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index 2becc77..eb7cecf 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -145,8 +145,8 @@ #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 #define PECFG_PIM0LAH 0x344 -#define PECFG_PIM1LAL 0x348 -#define PECFG_PIM1LAH 0x34c +#define PECFG_PIM1LAL 0x348 +#define PECFG_PIM1LAH 0x34c #define PECFG_PIM01SAL 0x350 #define PECFG_PIM01SAH 0x354 @@ -161,6 +161,21 @@ mtdcr(DCRN_SDR0_CFGADDR, offset); \ mtdcr(DCRN_SDR0_CFGDATA,data);}) +#define PCIE_IN(opcode, ret, addr) \ + __asm__ __volatile__( \ + "sync\n" \ + #opcode " %0,0,%1\n" \ + "1: twi 0,%0,0\n" \ + "isync\n" \ + "b 3f\n" \ + "2: li %0,-1\n" \ + "3:\n" \ + ".section __ex_table,\"a\"\n" \ + ".balign 4\n" \ + ".long 1b,2b\n" \ + ".previous\n" \ + : "=r" (ret) : "r" (addr), "m" (*addr)); + int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); void yucca_setup_pcie_fpga_rootpoint(int port); diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index e5f296e..4a4c6f2 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -269,7 +269,7 @@ struct bank_param { typedef struct bank_param BANKPARMS; #ifdef CFG_SIMULATE_SPD_EEPROM -extern unsigned char cfg_simulate_spd_eeprom[128]; +extern const unsigned char cfg_simulate_spd_eeprom[128]; #endif static unsigned char spd_read(uchar chip, uint addr); diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index e62dd9d..a75e5ee 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -448,12 +448,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv, unsigned long i; unsigned long est; /* current estimate */ unsigned long plloutb; + unsigned long cpr_pllc; u32 reg; + /* check the pll feedback source */ + mfcpr(cprpllc, cpr_pllc); + get_sys_info(&sysinfo); - plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv) - / sysinfo.pllFwdDivB); + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / + sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 028b11a..da5330a 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -771,6 +771,7 @@ ulong get_PCI_freq (void) void get_sys_info (PPC405_SYS_INFO * sysInfo) { unsigned long cpr_plld; + unsigned long cpr_pllc; unsigned long cpr_primad; unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); unsigned long primad_cpudv; @@ -780,6 +781,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Read PLL Mode registers */ mfcpr(cprplld, cpr_plld); + mfcpr(cprpllc, cpr_pllc); /* * Determine forward divider A @@ -787,20 +789,18 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); /* - * Determine forward divider B (should be equal to A) + * Determine forward divider B */ sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); - if (sysInfo->pllFwdDivB == 0) { + if (sysInfo->pllFwdDivB == 0) sysInfo->pllFwdDivB = 8; - } /* * Determine FBK_DIV. */ sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (sysInfo->pllFbkDiv == 0) { + if (sysInfo->pllFbkDiv == 0) sysInfo->pllFbkDiv = 256; - } /* * Read CPR_PRIMAD register @@ -810,30 +810,30 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine PLB_DIV. */ sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); - if (sysInfo->pllPlbDiv == 0) { + if (sysInfo->pllPlbDiv == 0) sysInfo->pllPlbDiv = 16; - } /* * Determine EXTBUS_DIV. */ sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); - if (sysInfo->pllExtBusDiv == 0) { + if (sysInfo->pllExtBusDiv == 0) sysInfo->pllExtBusDiv = 16; - } /* * Determine OPB_DIV. */ sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); - if (sysInfo->pllOpbDiv == 0) { + if (sysInfo->pllOpbDiv == 0) sysInfo->pllOpbDiv = 16; - } /* * Determine the M factor */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + if (cpr_pllc & PLLC_SRC_MASK) + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + else + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; /* * Determine VCO clock frequency @@ -845,16 +845,17 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine CPU clock frequency */ primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) { + if (primad_cpudv == 0) primad_cpudv = 16; - } - sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv; + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) / + sysInfo->pllFwdDiv / primad_cpudv; /* * Determine PLB clock frequency */ - sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv; + sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / + sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; } /******************************************** diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index eb9420e..de5fde9 100755 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -147,14 +147,21 @@ MachineCheckException(struct pt_regs *regs) unsigned long fixup, val; #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) u32 value2; + int corr_ecc = 0; + int uncorr_ecc = 0; #endif - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. + /* Probing PCI(E) using config cycles may cause this exception + * when a device is not present. To gracefully recover in such + * scenarios config read/write routines need to be instrumented in + * order to return via fixup handler. For examples refer to + * pcie_in_8(), pcie_in_le16() and pcie_in_le32() */ if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; + val = mfspr(MCSR); + /* Clear MCSR */ + mtspr(SPRN_MCSR, val); return; } @@ -214,14 +221,22 @@ MachineCheckException(struct pt_regs *regs) printf("DDR0: At least one interrupt active\n"); if (val & 0x40) printf("DDR0: DRAM initialization complete.\n"); - if (val & 0x20) + if (val & 0x20) { printf("DDR0: Multiple uncorrectable ECC events.\n"); - if (val & 0x10) + uncorr_ecc = 1; + } + if (val & 0x10) { printf("DDR0: Single uncorrectable ECC event.\n"); - if (val & 0x08) + uncorr_ecc = 1; + } + if (val & 0x08) { printf("DDR0: Multiple correctable ECC events.\n"); - if (val & 0x04) + corr_ecc = 1; + } + if (val & 0x04) { printf("DDR0: Single correctable ECC event.\n"); + corr_ecc = 1; + } if (val & 0x02) printf("Multiple accesses outside the defined" " physical memory space detected\n"); @@ -252,11 +267,11 @@ MachineCheckException(struct pt_regs *regs) printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2); } mfsdram(DDR0_23, val); - if ( (val >> 16) & 0xff) + if (((val >> 16) & 0xff) && corr_ecc) printf("DDR0: Syndrome for correctable ECC event 0x%x\n", (val >> 16) & 0xff); mfsdram(DDR0_23, val); - if ( (val >> 8) & 0xff) + if (((val >> 8) & 0xff) && uncorr_ecc) printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n", (val >> 8) & 0xff); mfsdram(DDR0_33, val); @@ -264,28 +279,28 @@ MachineCheckException(struct pt_regs *regs) printf("DDR0: Address of command that caused an " "Out-of-Range interrupt %p\n", val); mfsdram(DDR0_34, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Address of uncorrectable ECC event %p\n", val); mfsdram(DDR0_35, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Address of uncorrectable ECC event %p\n", val); mfsdram(DDR0_36, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); mfsdram(DDR0_37, val); - if (val) + if (val && uncorr_ecc) printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); mfsdram(DDR0_38, val); - if (val) + if (val && corr_ecc) printf("DDR0: Address of correctable ECC event %p\n", val); mfsdram(DDR0_39, val); - if (val) + if (val && corr_ecc) printf("DDR0: Address of correctable ECC event %p\n", val); mfsdram(DDR0_40, val); - if (val) + if (val && corr_ecc) printf("DDR0: Data of correctable ECC event 0x%08x\n", val); mfsdram(DDR0_41, val); - if (val) + if (val && corr_ecc) printf("DDR0: Data of correctable ECC event 0x%08x\n", val); #endif /* CONFIG_440EPX */ #endif /* CONFIG_440 */ diff --git a/doc/README.bamboo b/doc/README.bamboo index b50be01..e139c6d 100644 --- a/doc/README.bamboo +++ b/doc/README.bamboo @@ -1,3 +1,65 @@ +The 2 important dipswitches are configured as shown below: + +SW1 (for 33MHz SysClk) +---------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF OFF OFF OFF OFF ON + +SW7 (for Op-Code Flash and Boot Option H) +----------------------------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF ON OFF OFF OFF OFF + +The EEPROM at location 0x52 is loaded with these 16 bytes: +C47042A6 05D7A190 40082350 0d050000 + +SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors +SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB +SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output +SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz +SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor +SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A +SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B +SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B +SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor +SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor +SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 +SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 +SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 +SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer +SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit +SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC +SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled +SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled +SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 +SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled +SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 +SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled +SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC +SDR0_SDSTP0[NE]: 0 : NDFC: disabled +SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit +SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection +SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) +SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled +SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready +SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter +SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC +SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC +SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC +SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC +SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count + +PPC440EP Clocking Configuration + +SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz +OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz + +The above information is reported by Eugene O'Brien +<Eugene.O'Brien@advantechamt.com>. Thanks a lot. + +2007-08-06, Stefan Roese <sr@denx.de> +--------------------------------------------------------------------- + The configuration for the AMCC 440EP eval board "Bamboo" was changed to only use 384 kbytes of FLASH for the U-Boot image. This way the redundant environment can be saved in the remaining 2 sectors of the diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9780fe1..4898dd4 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -628,6 +628,12 @@ #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 +#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) +#define DAR_DEAR DEAR +#else +#define DAR_DEAR DAR +#endif + /* Device Control Registers */ #define DCRN_BEAR 0x090 /* Bus Error Address Register */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index d58344d..4e00b9f 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -222,6 +222,8 @@ #define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ +#define CONFIG_PROG_SDRAM_TLB +#undef CFG_DRAM_TEST /*----------------------------------------------------------------------- * I2C diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h new file mode 100644 index 0000000..9e45e90 --- /dev/null +++ b/include/configs/hcu4.h @@ -0,0 +1,341 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu4.h - configuration for HCU4 board (similar to hcu5.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU4 1 /* Board is HCU4 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */ +#define CONFIG_405GP 1 +#define CONFIG_4xx 1 + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) +*----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE + +/* ... with on-chip memory here (4KBytes) */ +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 +/* Do not set up locked dcache as init ram. */ +#undef CFG_INIT_DCACHE_CS + +/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ +#define CFG_TEMP_STACK_OCM 1 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* Set console baudrate to 9600 */ +#define CONFIG_BAUDRATE 9600 + + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM configuration */ +#define PROM_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the first internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 0 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu4 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/home/diagnose/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/hcu4/uImage\0" \ + "load=tftp 100000 hcu4/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu4_vx_rom;" \ + "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* SPD EEPROM (sdram speed config) disabled */ +#define CONFIG_SPD_EEPROM 1 +#define SPD_EEPROM_ADDRESS 0x50 + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB1AP 0x03041200 +#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB2AP 0x02054500 +#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB3AP 0x01840300 +#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB4AP 0x01800300 +#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h new file mode 100644 index 0000000..fa6ca37 --- /dev/null +++ b/include/configs/hcu5.h @@ -0,0 +1,388 @@ +/* + * (C) Copyright 2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu5.h - configuration for HCU5 board (derived from sequoia.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU5 1 /* Board is HCU5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xfff00000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CONFIG_BAUDRATE 9600 +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO, but + CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM and bootstrap configuration */ +#define PROM_SIZE 2048 +#define CFG_BOOSTRAP_OPTION_OFFSET 512 +#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ +#define CONFIG_DDR_ECC 1 /* enable ECC */ + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the second internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 1 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu5 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "bootfile=hcu5/uImage\0" \ + "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ + "load=tftp 100000 hcu5/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \ + "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +#define CMD_USB CFG_CMD_USB + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CMD_USB) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CS_1 0xC8000000 /* CAN */ +#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ +#define CFG_CPLD CFG_CS_2 +#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */ + +/*----------------------------------------------------------------------- + * FLASH organization + * Memory Bank 0 (BOOT-FLASH) initialization + */ +#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Memory Bank 1 CAN-Chips initialization */ +#define CFG_EBC_PB1AP 0x02054500 +#define CFG_EBC_PB1CR 0xC8018000 + +/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ +#define CFG_EBC_PB2AP 0x01840300 +#define CFG_EBC_PB2CR 0xCC0BA000 + +/* Memory Bank 3 IMC-Bus fast mode initialization */ +#define CFG_EBC_PB3AP 0x01800300 +#define CFG_EBC_PB3CR 0xCE0BA000 + +/* Memory Bank 4 (not used) initialization */ +#undef CFG_EBC_PB4AP +#undef CFG_EBC_PB4CR + +/* Memory Bank 5 (not used) initialization */ +#undef CFG_EBC_PB5AP +#undef CFG_EBC_PB5CR + +#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) +#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 55e2c94..52db71e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -137,11 +137,25 @@ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ #if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ +#define CFG_POST_ECC_ON CFG_POST_ECC +#else +#define CFG_POST_ECC_ON 0 +#endif /* POST support */ -#define CONFIG_POST (CFG_POST_ECC) - -#endif +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_ECC_ON | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) + +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CONFIG_LOGBUFFER +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ /*----------------------------------------------------------------------- * I2C @@ -171,6 +185,7 @@ "hostname=lwmon5\0" \ "netdev=eth0\0" \ "unlock=yes\0" \ + "logversion=2\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -245,6 +260,7 @@ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_FAT | \ + CFG_CMD_LOG | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -341,14 +357,24 @@ * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ /* SDRAM Clock frequency adjustment register */ -#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 -/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038 +/* Lime Clock frequency is to set 100MHz */ +#define CFG_LIME_CLOCK_100MHZ 0x00000 +#if 0 +/* Lime Clock frequency for 133MHz */ #define CFG_LIME_CLOCK_133MHZ 0x10000 +#endif /* SDRAM Parameter register */ #define CFG_LIME_MMR 0xC1FCFFFC -/* SDRAM parameter value */ +/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + and pixel flare on display when 133MHz was configured. According to + SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ +#ifdef CFG_LIME_CLOCK_133MHZ +#define CFG_LIME_MMR_VALUE 0x414FB7F3 +#else #define CFG_LIME_MMR_VALUE 0x414FB7F2 +#endif /*----------------------------------------------------------------------- * GPIO Setup diff --git a/include/ppc405.h b/include/ppc405.h index 4fc5283..0c7bf3e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -629,6 +629,8 @@ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ diff --git a/include/ppc440.h b/include/ppc440.h index 93c10f1..38809f3 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3354,6 +3354,19 @@ typedef struct { unsigned long pciClkSync; /* PCI clock is synchronous */ } PPC440_SYS_INFO; +static inline u32 get_mcsr(void) +{ + u32 val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(u32 val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + #endif /* _ASMLANGUAGE */ #define RESET_VECTOR 0xfffffffc diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 9f4029f..ac8f317 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -235,7 +235,7 @@ stw r22,_CTR(r21); \ mfspr r20,XER; \ stw r20,_XER(r21); \ - mfspr r20,DEAR; \ + mfspr r20, DAR_DEAR; \ stw r20,_DAR(r21); \ mfspr r22,reg1; \ mfspr r23,reg2; \ diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index 8354411..2d995fa 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -89,7 +89,7 @@ search_exception_table(unsigned long addr) /* if the serial port does not hang in exception, printf can be used */ #if !defined(CFG_SERIAL_HANG_IN_EXCEPTION) if (ex_tab_message) - printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); + debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); #endif if (ret) return ret; diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c index 7f04f9a..3fa3ba6 100644 --- a/post/board/lwmon5/ecc.c +++ b/post/board/lwmon5/ecc.c @@ -236,7 +236,6 @@ int ecc_post_test (int flags) mfsdram(DDR0_00, value); mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* enable full support of ECC */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) @@ -247,6 +246,17 @@ int ecc_post_test (int flags) if (ret) break; } + + /* clear error status */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); + + /* + * Clear possible errors resulting from ECC testing. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); #endif return ret; diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index 27e9ed0..0c26fe0 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -29,8 +29,8 @@ #if defined(CONFIG_440EP) || \ defined(CONFIG_440EPX) -#include <ppc4xx.h> #include <asm/processor.h> +#include <ppc4xx.h> int fpu_status(void) diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 0cffda5..5f14967 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -137,7 +137,53 @@ DECLARE_GLOBAL_DATA_PTR; +<<<<<<< master +#if !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + + get_sys_info(&sysinfo); + + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (32) to minimize serial clock and constrain + * search to umin. + */ + for (i = 32; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + *pbdiv = div / udiv; +} +#endif + +======= #if defined(CONFIG_440) +>>>>>>> zeus static int uart_post_init (unsigned long dev_base) { unsigned long reg; |