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-rw-r--r--CREDITS5
-rw-r--r--MAINTAINERS7
-rwxr-xr-xMAKEALL3
-rw-r--r--Makefile16
-rw-r--r--README2
-rw-r--r--board/amcc/katmai/katmai.c72
-rw-r--r--board/amcc/ocotea/ocotea.c50
-rw-r--r--board/amcc/redwood/Makefile50
-rw-r--r--board/amcc/redwood/config.mk42
-rw-r--r--board/amcc/redwood/init.S77
-rw-r--r--board/amcc/redwood/redwood.c456
-rw-r--r--board/amcc/redwood/redwood.h50
-rw-r--r--board/amcc/redwood/u-boot.lds147
-rw-r--r--board/amcc/sequoia/sequoia.c5
-rw-r--r--board/amcc/taishan/taishan.c50
-rw-r--r--board/amcc/yucca/yucca.c62
-rw-r--r--board/delta/nand.c2
-rw-r--r--board/esd/common/auto_update.c12
-rw-r--r--board/freescale/mx31ads/Makefile (renamed from board/mx31ads/Makefile)0
-rw-r--r--board/freescale/mx31ads/config.mk (renamed from board/mx31ads/config.mk)0
-rw-r--r--board/freescale/mx31ads/lowlevel_init.S (renamed from board/mx31ads/lowlevel_init.S)0
-rw-r--r--board/freescale/mx31ads/mx31ads.c (renamed from board/mx31ads/mx31ads.c)0
-rw-r--r--board/freescale/mx31ads/u-boot.lds (renamed from board/mx31ads/u-boot.lds)10
-rw-r--r--board/icecube/flash.c4
-rw-r--r--board/korat/korat.c4
-rw-r--r--board/netta/netta.c2
-rw-r--r--board/prodrive/alpr/alpr.c50
-rw-r--r--board/prodrive/pdnb3/flash.c4
-rw-r--r--board/sandburst/karef/karef.c50
-rw-r--r--board/sandburst/metrobox/metrobox.c50
-rw-r--r--board/tqc/tqm8xx/flash.c4
-rw-r--r--board/xilinx/ml507/Makefile58
-rw-r--r--board/xilinx/ml507/config.mk27
-rw-r--r--board/xilinx/ml507/init.S53
-rw-r--r--board/xilinx/ml507/ml507.c47
-rw-r--r--board/xilinx/ml507/u-boot-ram.lds134
-rw-r--r--board/xilinx/ml507/u-boot-rom.lds144
-rw-r--r--board/xilinx/ml507/xparameters.h35
-rw-r--r--board/xpedite1k/xpedite1k.c50
-rw-r--r--common/ACEX1K.c4
-rw-r--r--common/Makefile42
-rw-r--r--common/altera.c4
-rw-r--r--common/bedbug.c4
-rw-r--r--common/cmd_jffs2.c12
-rw-r--r--common/cmd_nand.c6
-rw-r--r--common/cmd_onenand.c4
-rw-r--r--common/cmd_reginfo.c5
-rw-r--r--common/cyclon2.c4
-rw-r--r--common/docecc.c4
-rw-r--r--common/fpga.c4
-rw-r--r--common/lcd.c4
-rw-r--r--common/lynxkdi.c3
-rw-r--r--common/miiphybb.c5
-rw-r--r--common/soft_i2c.c5
-rw-r--r--common/soft_spi.c4
-rw-r--r--common/spartan2.c4
-rw-r--r--common/spartan3.c4
-rw-r--r--common/stratixII.c4
-rw-r--r--common/usb.c4
-rw-r--r--common/usb_kbd.c5
-rw-r--r--common/usb_storage.c7
-rw-r--r--common/virtex2.c3
-rw-r--r--common/xilinx.c4
-rw-r--r--cpu/arm920t/s3c24x0/nand.c2
-rw-r--r--cpu/arm926ejs/davinci/nand.c2
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c276
-rw-r--r--cpu/ppc4xx/4xx_enet.c492
-rw-r--r--cpu/ppc4xx/4xx_uart.c2
-rw-r--r--cpu/ppc4xx/Makefile13
-rw-r--r--cpu/ppc4xx/cpu.c41
-rw-r--r--cpu/ppc4xx/cpu_init.c15
-rw-r--r--cpu/ppc4xx/interrupts.c237
-rw-r--r--cpu/ppc4xx/iop480_uart.c1
-rw-r--r--cpu/ppc4xx/ndfc.c2
-rw-r--r--cpu/ppc4xx/speed.c9
-rw-r--r--cpu/ppc4xx/start.S19
-rw-r--r--cpu/ppc4xx/uic.c180
-rw-r--r--cpu/ppc4xx/usbdev.c4
-rw-r--r--cpu/ppc4xx/xilinx_irq.c100
-rw-r--r--doc/README.nand2
-rw-r--r--drivers/block/Makefile10
-rw-r--r--drivers/block/ahci.c3
-rw-r--r--drivers/block/ata_piix.c4
-rw-r--r--drivers/block/sil680.c5
-rw-r--r--drivers/block/sym53c8xx.c5
-rw-r--r--drivers/block/systemace.c3
-rw-r--r--drivers/dma/MCD_dmaApi.c3
-rw-r--r--drivers/dma/MCD_tasks.c4
-rw-r--r--drivers/dma/MCD_tasksInit.c4
-rw-r--r--drivers/dma/Makefile2
-rw-r--r--drivers/input/Makefile8
-rw-r--r--drivers/input/i8042.c4
-rw-r--r--drivers/input/keyboard.c4
-rw-r--r--drivers/input/pc_keyb.c4
-rw-r--r--drivers/input/ps2mult.c4
-rw-r--r--drivers/input/ps2ser.c4
-rw-r--r--drivers/misc/Makefile6
-rw-r--r--drivers/misc/ali512x.c5
-rw-r--r--drivers/misc/ns87308.c4
-rw-r--r--drivers/misc/status_led.c4
-rw-r--r--drivers/mtd/Makefile6
-rw-r--r--drivers/mtd/at45.c3
-rw-r--r--drivers/mtd/cfi_flash.c3
-rw-r--r--drivers/mtd/mw_eeprom.c5
-rw-r--r--drivers/mtd/nand/Makefile10
-rw-r--r--drivers/mtd/nand/diskonchip.c2
-rw-r--r--drivers/mtd/nand/fsl_upm.c3
-rw-r--r--drivers/mtd/nand/nand.c5
-rw-r--r--drivers/mtd/nand/nand_base.c5
-rw-r--r--drivers/mtd/nand/nand_bbt.c5
-rw-r--r--drivers/mtd/nand/nand_ecc.c4
-rw-r--r--drivers/mtd/nand/nand_ids.c4
-rw-r--r--drivers/mtd/nand/nand_util.c5
-rw-r--r--drivers/mtd/nand_legacy/Makefile5
-rw-r--r--drivers/mtd/nand_legacy/nand_legacy.c5
-rw-r--r--drivers/mtd/onenand/Makefile3
-rw-r--r--drivers/mtd/onenand/onenand_base.c5
-rw-r--r--drivers/mtd/onenand/onenand_bbt.c5
-rw-r--r--drivers/mtd/onenand/onenand_uboot.c5
-rw-r--r--drivers/pci/Makefile10
-rw-r--r--drivers/pci/fsl_pci_init.c4
-rw-r--r--drivers/pci/pci.c4
-rw-r--r--drivers/pci/pci_auto.c4
-rw-r--r--drivers/pci/pci_indirect.c2
-rw-r--r--drivers/pci/tsi108_pci.c4
-rw-r--r--drivers/pci/w83c553f.c4
-rw-r--r--drivers/qe/Makefile3
-rw-r--r--drivers/qe/qe.c3
-rw-r--r--drivers/qe/uccf.c2
-rw-r--r--drivers/qe/uec.c5
-rw-r--r--drivers/qe/uec_phy.c3
-rw-r--r--drivers/serial/Makefile4
-rw-r--r--drivers/serial/ns9750_serial.c4
-rw-r--r--drivers/serial/serial.c4
-rw-r--r--drivers/serial/serial_sh.c4
-rw-r--r--fs/jffs2/jffs2_1pass.c6
-rw-r--r--fs/jffs2/jffs2_nand_1pass.c2
-rw-r--r--include/asm-ppc/interrupt.h36
-rw-r--r--include/asm-ppc/ppc4xx-ebc.h156
-rw-r--r--include/asm-ppc/ppc4xx-intvec.h474
-rw-r--r--include/asm-ppc/ppc4xx-sdram.h326
-rw-r--r--include/asm-ppc/ppc4xx-uic.h316
-rw-r--r--include/asm-ppc/processor.h6
-rw-r--r--include/asm-ppc/xilinx_irq.h36
-rw-r--r--include/configs/APC405.h2
-rw-r--r--include/configs/ATUM8548.h2
-rw-r--r--include/configs/Adder.h2
-rw-r--r--include/configs/BAB7xx.h4
-rw-r--r--include/configs/BC3450.h2
-rw-r--r--include/configs/BMW.h2
-rw-r--r--include/configs/CPCI750.h2
-rw-r--r--include/configs/CPU87.h2
-rw-r--r--include/configs/DU440.h2
-rw-r--r--include/configs/EP88x.h2
-rw-r--r--include/configs/FPS850L.h2
-rw-r--r--include/configs/FPS860L.h2
-rw-r--r--include/configs/GEN860T.h2
-rw-r--r--include/configs/HH405.h2
-rw-r--r--include/configs/HIDDEN_DRAGON.h4
-rw-r--r--include/configs/HMI10.h2
-rw-r--r--include/configs/IDS8247.h4
-rw-r--r--include/configs/ISPAN.h2
-rw-r--r--include/configs/IceCube.h2
-rw-r--r--include/configs/M52277EVB.h2
-rw-r--r--include/configs/M5235EVB.h2
-rw-r--r--include/configs/M5249EVB.h2
-rw-r--r--include/configs/M5253EVBE.h2
-rw-r--r--include/configs/M5271EVB.h2
-rw-r--r--include/configs/M5275EVB.h2
-rw-r--r--include/configs/M5282EVB.h2
-rw-r--r--include/configs/M5329EVB.h2
-rw-r--r--include/configs/M5373EVB.h2
-rw-r--r--include/configs/M54455EVB.h2
-rw-r--r--include/configs/M5475EVB.h2
-rw-r--r--include/configs/M5485EVB.h2
-rw-r--r--include/configs/MIP405.h2
-rw-r--r--include/configs/MPC8313ERDB.h2
-rw-r--r--include/configs/MPC8315ERDB.h2
-rw-r--r--include/configs/MPC8323ERDB.h2
-rw-r--r--include/configs/MPC832XEMDS.h2
-rw-r--r--include/configs/MPC8349EMDS.h2
-rw-r--r--include/configs/MPC8349ITX.h4
-rw-r--r--include/configs/MPC8360EMDS.h2
-rw-r--r--include/configs/MPC8360ERDK.h2
-rw-r--r--include/configs/MPC837XEMDS.h2
-rw-r--r--include/configs/MPC837XERDB.h2
-rw-r--r--include/configs/MPC8540ADS.h2
-rw-r--r--include/configs/MPC8541CDS.h2
-rw-r--r--include/configs/MPC8544DS.h2
-rw-r--r--include/configs/MPC8548CDS.h2
-rw-r--r--include/configs/MPC8555CDS.h2
-rw-r--r--include/configs/MPC8560ADS.h2
-rw-r--r--include/configs/MPC8568MDS.h2
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/MPC8641HPCN.h2
-rw-r--r--include/configs/MVBC_P.h2
-rw-r--r--include/configs/MVBLM7.h2
-rw-r--r--include/configs/MigoR.h4
-rw-r--r--include/configs/NETPHONE.h2
-rw-r--r--include/configs/NETTA.h2
-rw-r--r--include/configs/NETTA2.h2
-rw-r--r--include/configs/NETVIA.h2
-rw-r--r--include/configs/NSCU.h2
-rw-r--r--include/configs/PCIPPC2.h2
-rw-r--r--include/configs/PCIPPC6.h2
-rw-r--r--include/configs/PIP405.h2
-rw-r--r--include/configs/PM520.h2
-rw-r--r--include/configs/PM826.h2
-rw-r--r--include/configs/PM828.h2
-rw-r--r--include/configs/PM854.h2
-rw-r--r--include/configs/PM856.h2
-rw-r--r--include/configs/PMC405.h2
-rw-r--r--include/configs/PMC440.h2
-rw-r--r--include/configs/Rattler.h2
-rw-r--r--include/configs/SBC8540.h2
-rw-r--r--include/configs/SX1.h2
-rw-r--r--include/configs/SXNI855T.h2
-rw-r--r--include/configs/Sandpoint8240.h4
-rw-r--r--include/configs/Sandpoint8245.h4
-rw-r--r--include/configs/TB5200.h2
-rw-r--r--include/configs/TK885D.h2
-rw-r--r--include/configs/TQM5200.h2
-rw-r--r--include/configs/TQM823L.h2
-rw-r--r--include/configs/TQM823M.h2
-rw-r--r--include/configs/TQM8272.h2
-rw-r--r--include/configs/TQM834x.h2
-rw-r--r--include/configs/TQM850L.h2
-rw-r--r--include/configs/TQM850M.h2
-rw-r--r--include/configs/TQM855L.h2
-rw-r--r--include/configs/TQM855M.h2
-rw-r--r--include/configs/TQM85xx.h4
-rw-r--r--include/configs/TQM860L.h2
-rw-r--r--include/configs/TQM860M.h2
-rw-r--r--include/configs/TQM862L.h2
-rw-r--r--include/configs/TQM862M.h2
-rw-r--r--include/configs/TQM866M.h2
-rw-r--r--include/configs/TQM885D.h2
-rw-r--r--include/configs/Total5200.h2
-rw-r--r--include/configs/VCMA9.h2
-rw-r--r--include/configs/ZPC1900.h2
-rw-r--r--include/configs/acadia.h2
-rw-r--r--include/configs/actux1.h2
-rw-r--r--include/configs/actux2.h2
-rw-r--r--include/configs/actux3.h2
-rw-r--r--include/configs/actux4.h2
-rw-r--r--include/configs/ads5121.h2
-rw-r--r--include/configs/aev.h2
-rw-r--r--include/configs/alpr.h2
-rw-r--r--include/configs/apollon.h2
-rw-r--r--include/configs/assabet.h2
-rw-r--r--include/configs/at91cap9adk.h2
-rw-r--r--include/configs/at91rm9200dk.h2
-rw-r--r--include/configs/at91sam9263ek.h2
-rw-r--r--include/configs/atngw100.h2
-rw-r--r--include/configs/atstk1002.h2
-rw-r--r--include/configs/atstk1003.h2
-rw-r--r--include/configs/atstk1004.h2
-rw-r--r--include/configs/atstk1006.h2
-rw-r--r--include/configs/bf533-stamp.h2
-rw-r--r--include/configs/bf537-stamp.h2
-rw-r--r--include/configs/bf561-ezkit.h2
-rw-r--r--include/configs/canmb.h2
-rw-r--r--include/configs/canyonlands.h2
-rw-r--r--include/configs/cm5200.h2
-rw-r--r--include/configs/csb272.h2
-rw-r--r--include/configs/csb472.h2
-rw-r--r--include/configs/csb637.h2
-rw-r--r--include/configs/davinci_dvevm.h2
-rw-r--r--include/configs/davinci_sonata.h2
-rw-r--r--include/configs/dbau1x00.h2
-rw-r--r--include/configs/delta.h2
-rw-r--r--include/configs/eXalion.h2
-rw-r--r--include/configs/ep8248.h2
-rw-r--r--include/configs/ep82xxm.h2
-rw-r--r--include/configs/gcplus.h2
-rw-r--r--include/configs/gr_cpci_ax2000.h2
-rw-r--r--include/configs/gr_ep2s60.h2
-rw-r--r--include/configs/gr_xc3s_1500.h2
-rw-r--r--include/configs/grsim.h2
-rw-r--r--include/configs/grsim_leon2.h2
-rw-r--r--include/configs/hcu4.h2
-rw-r--r--include/configs/hcu5.h2
-rw-r--r--include/configs/hmi1001.h2
-rw-r--r--include/configs/imx31_litekit.h2
-rw-r--r--include/configs/imx31_phycore.h2
-rw-r--r--include/configs/inka4x0.h2
-rw-r--r--include/configs/ixdp425.h2
-rw-r--r--include/configs/ixdpg425.h2
-rw-r--r--include/configs/jupiter.h2
-rw-r--r--include/configs/katmai.h3
-rw-r--r--include/configs/kb9202.h2
-rw-r--r--include/configs/kilauea.h148
-rw-r--r--include/configs/korat.h2
-rw-r--r--include/configs/kvme080.h2
-rw-r--r--include/configs/linkstation.h2
-rw-r--r--include/configs/lwmon5.h2
-rw-r--r--include/configs/m501sk.h2
-rw-r--r--include/configs/makalu.h3
-rw-r--r--include/configs/mcc200.h2
-rw-r--r--include/configs/mcu25.h2
-rw-r--r--include/configs/mecp5200.h2
-rw-r--r--include/configs/mgcoge.h2
-rw-r--r--include/configs/mgsuvd.h2
-rw-r--r--include/configs/ml401.h2
-rw-r--r--include/configs/ml507.h122
-rw-r--r--include/configs/motionpro.h2
-rw-r--r--include/configs/mpc7448hpc2.h2
-rw-r--r--include/configs/mpr2.h4
-rw-r--r--include/configs/ms7720se.h4
-rw-r--r--include/configs/ms7722se.h4
-rw-r--r--include/configs/ms7750se.h4
-rw-r--r--include/configs/munices.h2
-rw-r--r--include/configs/mx31ads.h2
-rw-r--r--include/configs/ns9750dev.h2
-rw-r--r--include/configs/omap1510inn.h2
-rw-r--r--include/configs/omap2420h4.h4
-rw-r--r--include/configs/omap5912osk.h2
-rw-r--r--include/configs/p3mx.h2
-rw-r--r--include/configs/p3p440.h2
-rw-r--r--include/configs/pdnb3.h2
-rw-r--r--include/configs/ppmc8260.h2
-rw-r--r--include/configs/pxa255_idp.h2
-rw-r--r--include/configs/qemu-mips.h2
-rw-r--r--include/configs/quad100hd.h2
-rw-r--r--include/configs/quantum.h6
-rw-r--r--include/configs/r2dplus.h4
-rw-r--r--include/configs/r7780mp.h4
-rw-r--r--include/configs/redwood.h186
-rw-r--r--include/configs/sbc8349.h2
-rw-r--r--include/configs/sbc8548.h2
-rw-r--r--include/configs/sbc8560.h2
-rw-r--r--include/configs/sbc8641d.h2
-rw-r--r--include/configs/sc3.h2
-rw-r--r--include/configs/sc520_cdp.h2
-rw-r--r--include/configs/sequoia.h2
-rw-r--r--include/configs/sh7763rdp.h4
-rw-r--r--include/configs/smmaco4.h2
-rw-r--r--include/configs/socrates.h2
-rw-r--r--include/configs/sorcery.h2
-rw-r--r--include/configs/spc1920.h2
-rw-r--r--include/configs/spieval.h2
-rw-r--r--include/configs/stxssa.h2
-rw-r--r--include/configs/stxxtc.h4
-rw-r--r--include/configs/svm_sc8xx.h2
-rw-r--r--include/configs/taishan.h2
-rw-r--r--include/configs/trizepsiv.h2
-rw-r--r--include/configs/uc100.h2
-rw-r--r--include/configs/uc101.h2
-rw-r--r--include/configs/v38b.h2
-rw-r--r--include/configs/virtlab2.h2
-rw-r--r--include/configs/voiceblue.h2
-rw-r--r--include/configs/yosemite.h2
-rw-r--r--include/configs/zeus.h2
-rw-r--r--include/linux/mtd/nand_ids.h2
-rw-r--r--include/linux/mtd/nand_legacy.h2
-rw-r--r--include/nand.h4
-rw-r--r--include/ppc405.h397
-rw-r--r--include/ppc440.h1112
-rw-r--r--include/ppc4xx.h7
-rw-r--r--include/ppc4xx_enet.h16
-rw-r--r--lib_generic/crc32.c2
361 files changed, 3900 insertions, 3530 deletions
diff --git a/CREDITS b/CREDITS
index 2b0dab7..63b16a9 100644
--- a/CREDITS
+++ b/CREDITS
@@ -399,6 +399,11 @@ N: Stelian Pop
E: stelian.pop@leadtechdesign.com
D: Atmel AT91CAP9ADK support
+N: Ricardo Ribalda Delgado
+E: ricardo.ribalda@uam.es
+D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
+W: http://www.ii.uam.es/~rribalda
+
N: Stefan Roese
E: sr@denx.de
D: AMCC PPC4xx Support
diff --git a/MAINTAINERS b/MAINTAINERS
index 777d141..7efef6a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -315,6 +315,10 @@ Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
sbc405 PPC405GP
+Ricardo Ribalda <ricardo.ribalda@uam.es>
+
+ ml507 PPC440x5
+
Stefan Roese <sr@denx.de>
P3M7448 MPC7448
@@ -424,6 +428,9 @@ John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
+Feng Kan <fkan@amcc.com>
+
+ redwood PPC4xx
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index ee83cca..ac4195f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -209,6 +209,8 @@ LIST_4xx=" \
MIP405T \
ML2 \
ml300 \
+ ml507 \
+ ml507_flash \
ocotea \
OCRTC \
ORSG \
@@ -222,6 +224,7 @@ LIST_4xx=" \
PPChameleonEVB \
quad100hd \
rainier \
+ redwood \
sbc405 \
sc3 \
sequoia \
diff --git a/Makefile b/Makefile
index 6624370..a384d16 100644
--- a/Makefile
+++ b/Makefile
@@ -1349,6 +1349,17 @@ ML2_config: unconfig
ml300_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
+ml507_flash_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/xilinx/ml507
+ @cp $(obj)board/xilinx/ml507/u-boot-rom.lds $(obj)board/xilinx/ml507/u-boot.lds
+ @echo "TEXT_BASE = 0xFE360000" > $(obj)board/xilinx/ml507/config.tmp
+ @$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
+
+ml507_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/xilinx/ml507
+ @cp $(obj)board/xilinx/ml507/u-boot-ram.lds $(obj)board/xilinx/ml507/u-boot.lds
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
+
ocotea_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
@@ -1410,6 +1421,9 @@ PPChameleonEVB_HI_33_config: unconfig
quad100hd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
+redwood_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx redwood amcc
+
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@@ -2681,7 +2695,7 @@ imx31_phycore_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
mx31ads_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
+ @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
diff --git a/README b/README
index d4456e5..37449d1 100644
--- a/README
+++ b/README
@@ -2064,7 +2064,7 @@ Configuration Settings:
Define if the flash driver uses extra elements in the
common flash structure for storing flash geometry.
-- CFG_FLASH_CFI_DRIVER
+- CONFIG_FLASH_CFI_DRIVER
This option also enables the building of the cfi_flash driver
in the drivers directory
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index f2bed5c..08d89d7 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -349,7 +349,7 @@ int is_pci_host(struct pci_controller *hose)
return 1;
}
-int katmai_pcie_card_present(int port)
+static int katmai_pcie_card_present(int port)
{
u32 val;
@@ -437,76 +437,6 @@ void pcie_setup_hoses(int busno)
}
#endif /* defined(CONFIG_PCI) */
-int misc_init_f (void)
-{
- uint reg;
-#if defined(CONFIG_STRESS)
- uint i ;
- uint disp;
-#endif
-
- /* minimal init for PCIe */
-#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
- /* pci express 0 Endpoint Mode */
- mfsdr(SDR0_PE0DLPSET, reg);
- reg &= (~0x00400000);
- mtsdr(SDR0_PE0DLPSET, reg);
-#else
- /* pci express 0 Rootpoint Mode */
- mfsdr(SDR0_PE0DLPSET, reg);
- reg |= 0x00400000;
- mtsdr(SDR0_PE0DLPSET, reg);
-#endif
- /* pci express 1 Rootpoint Mode */
- mfsdr(SDR0_PE1DLPSET, reg);
- reg |= 0x00400000;
- mtsdr(SDR0_PE1DLPSET, reg);
- /* pci express 2 Rootpoint Mode */
- mfsdr(SDR0_PE2DLPSET, reg);
- reg |= 0x00400000;
- mtsdr(SDR0_PE2DLPSET, reg);
-
-#if defined(CONFIG_STRESS)
- /*
- * All this setting done by linux only needed by stress an charac. test
- * procedure
- * PCIe 1 Rootpoint PCIe2 Endpoint
- * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
- */
- for (i=0,disp=0; i<8; i++,disp+=3) {
- mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
- reg |= 0x33000000;
- mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
- }
-
- /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
- for (i=0,disp=0; i<4; i++,disp+=3) {
- mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
- reg |= 0x33000000;
- mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
- }
-
- /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
- for (i=0,disp=0; i<4; i++,disp+=3) {
- mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
- reg |= 0x33000000;
- mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
- }
-
- reg = 0x21242222;
- mtsdr(SDR0_PE2UTLSET1, reg);
- reg = 0x11000000;
- mtsdr(SDR0_PE2UTLSET2, reg);
- /* pci express 1 Endpoint Mode */
- reg = 0x00004000;
- mtsdr(SDR0_PE2DLPSET, reg);
-
- mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
-#endif
-
- return 0;
-}
-
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index eea1e1e..4d1d093 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -147,36 +147,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000); /* */
- mtdcr (uicb0tr, 0x00000000); /* */
- mtdcr (uicb0vr, 0x00000001); /* */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+ mtdcr (uic3er, 0x00000000); /* disable all */
+ mtdcr (uic3cr, 0x00000000); /* all non-critical */
+ mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic0sr, 0xfc000000); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non-critical */
+ mtdcr (uic0pr, 0xfc000000); /* */
+ mtdcr (uic0tr, 0x00000000); /* */
+ mtdcr (uic0vr, 0x00000001); /* */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(sdr_mfr, mfr); */
diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile
new file mode 100644
index 0000000..5793307
--- /dev/null
+++ b/board/amcc/redwood/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk
new file mode 100644
index 0000000..f33336d
--- /dev/null
+++ b/board/amcc/redwood/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 460SX Reference Platform (redwood) board
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S
new file mode 100644
index 0000000..fcffada
--- /dev/null
+++ b/board/amcc/redwood/init.S
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ /* Although 512 KB, map 256k at a time */
+ tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+
+ tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /*
+ * Peripheral base
+ */
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
new file mode 100644
index 0000000..37a0c31
--- /dev/null
+++ b/board/amcc/redwood/redwood.c
@@ -0,0 +1,456 @@
+/*
+ * This is the main board level file for the Redwood AMCC board.
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include "redwood.h"
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm-ppc/io.h>
+
+int compare_to_true(char *str);
+char *remove_l_w_space(char *in_str);
+char *remove_t_w_space(char *in_str);
+int get_console_port(void);
+
+static void early_init_EBC(void);
+static int bootdevice_selected(void);
+static void early_reinit_EBC(int);
+static void early_init_UIC(void);
+
+/*
+ * Define Boot devices
+ */
+#define BOOT_FROM_8BIT_SRAM 0x00
+#define BOOT_FROM_16BIT_SRAM 0x01
+#define BOOT_FROM_32BIT_SRAM 0x02
+#define BOOT_FROM_8BIT_NAND 0x03
+#define BOOT_FROM_16BIT_NOR 0x04
+#define BOOT_DEVICE_UNKNOWN 0xff
+
+/*
+ * EBC Devices Characteristics
+ * Peripheral Bank Access Parameters - EBC_BxAP
+ * Peripheral Bank Configuration Register - EBC_BxCR
+ */
+
+/*
+ * 8 bit width SRAM
+ * BU Value
+ * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_8BIT_SRAM \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
+#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
+
+/*
+ * NAND flash
+ * BU Value
+ * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NAND \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+/*
+ * NOR flash
+ * BU Value
+ * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NOR \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_8BIT_SRAM_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_32BIT_SRAM_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_NAND_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_16BIT_SRAM_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS1 \
+ EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NAND_CS1 \
+ EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_NAND_CS2 \
+ EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SRAM_CS2 \
+ EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2 \
+ EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_FPGA_CS3 \
+ EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+/*****************************************************************************
+ * UBOOT initiated board specific function calls
+ ****************************************************************************/
+
+int board_early_init_f(void)
+{
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+ /*
+ * Initialise EBC
+ */
+ early_init_EBC();
+
+ /*
+ * Determine which boot device was selected
+ */
+ computed_boot_device = bootdevice_selected();
+
+ /*
+ * Reinit EBC based on selected boot device
+ */
+ early_reinit_EBC(computed_boot_device);
+
+ /*
+ * Setup for UIC on 460SX redwood board
+ */
+ early_init_UIC();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Redwood - AMCC 460SX Reference Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+static void early_init_EBC(void)
+{
+ /*
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value :
+ * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ */
+ mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_16PERCLK |
+ EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_OEO_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
+
+ /*
+ * PART 1 : Initialize EBC Bank 3
+ * ==============================
+ * Bank1 is always associated to the EPLD.
+ * It has to be initialized prior to other banks settings computation
+ * since some board registers values may be needed to determine the
+ * boot type
+ */
+ mtebc(pb1ap, EBC_BXAP_FPGA);
+ mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
+
+}
+
+static int bootdevice_selected(void)
+{
+ unsigned long sdr0_pinstp;
+ unsigned long bootstrap_settings;
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+ /*
+ * Determine which boot device was selected
+ * =================================================
+ *
+ * Read Pin Strap Register in PPC460SX
+ * Result can either be :
+ * - Boot strap = boot from EBC 8bits => Small Flash
+ * - Boot strap = boot from PCI
+ * - Boot strap = IIC
+ * In case of boot from IIC, read Serial Device Strap Register1
+ *
+ * Result can either be :
+ * - Boot from EBC - EBC Bus Width = 8bits => Small Flash
+ * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
+ * - Boot from PCI
+ */
+
+ /* Read Pin Strap Register in PPC460SX */
+ mfsdr(SDR0_PINSTP, sdr0_pinstp);
+ bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+ switch (bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /*
+ * Boot from SRAM, 8bit width
+ */
+ computed_boot_device = BOOT_FROM_8BIT_SRAM;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /*
+ * Boot from SRAM, 32bit width
+ */
+ computed_boot_device = BOOT_FROM_32BIT_SRAM;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /*
+ * Boot from NAND, 8bit width
+ */
+ computed_boot_device = BOOT_FROM_8BIT_NAND;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+ /*
+ * Boot from SRAM, 16bit width
+ * Boot setting in IIC EEPROM 0x50
+ */
+ computed_boot_device = BOOT_FROM_16BIT_SRAM;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
+ /*
+ * Boot from NOR, 16bit width
+ * Boot setting in IIC EEPROM 0x54
+ */
+ computed_boot_device = BOOT_FROM_16BIT_NOR;
+ break;
+ default:
+ /* should not be */
+ computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ break;
+ }
+
+ return computed_boot_device;
+}
+
+static void early_reinit_EBC(int computed_boot_device)
+{
+ /*
+ * Compute EBC settings depending on selected boot device
+ * ======================================================
+ *
+ * Resulting EBC init will be among following configurations :
+ *
+ * - Boot from EBC 8bits => boot from Small Flash selected
+ * EBC-CS0 = Small Flash
+ * EBC-CS2 = Large Flash and SRAM
+ *
+ * - Boot from EBC 16bits => boot from Large Flash or SRAM
+ * EBC-CS0 = Large Flash or SRAM
+ * EBC-CS2 = Small Flash
+ *
+ * - Boot from PCI
+ * EBC-CS0 = not initialized to avoid address contention
+ * EBC-CS2 = same as boot from Small Flash selected
+ */
+
+ unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+ unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
+ unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+ switch (computed_boot_device) {
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_8BIT_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
+ ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_16BIT_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
+ ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_32BIT_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
+ ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_16BIT_NOR:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+ ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_8BIT_NAND:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+ ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ default:
+ /*-------------------------------------------------------------------*/
+ /* BOOT_DEVICE_UNKNOWN */
+ break;
+ }
+
+ mtebc(pb0ap, ebc0_cs0_bxap_value);
+ mtebc(pb0cr, ebc0_cs0_bxcr_value);
+ mtebc(pb1ap, ebc0_cs1_bxap_value);
+ mtebc(pb1cr, ebc0_cs1_bxcr_value);
+ mtebc(pb2ap, ebc0_cs2_bxap_value);
+ mtebc(pb2cr, ebc0_cs2_bxcr_value);
+}
+
+static void early_init_UIC(void)
+{
+ /*
+ * Initialise UIC registers. Clear all interrupts. Disable all
+ * interrupts.
+ * Set critical interrupt values. Set interrupt polarities. Set
+ * interrupt trigger levels. Make bit 0 High priority. Clear all
+ * interrupts again.
+ */
+ mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr(uic3er, 0x00000000); /* disable all interrupts */
+ mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr(uic2er, 0x00000000); /* disable all interrupts */
+ mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
+ mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr(uic1er, 0x00000000); /* disable all interrupts */
+ mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
+ * cascade to be checked */
+ mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
+
+}
diff --git a/board/amcc/redwood/redwood.h b/board/amcc/redwood/redwood.h
new file mode 100644
index 0000000..89b87e6
--- /dev/null
+++ b/board/amcc/redwood/redwood.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REDWOOD_H_
+#define __REDWOOD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+/* Pin Straps Reg */
+#define SDR0_PSTRP0 0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __REDWOOD_H_ */
diff --git a/board/amcc/redwood/u-boot.lds b/board/amcc/redwood/u-boot.lds
new file mode 100644
index 0000000..2104cc2
--- /dev/null
+++ b/board/amcc/redwood/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/redwood/init.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 198db1a..176d5cf 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -25,12 +25,11 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
-#include <ppc440.h>
+#include <ppc4xx.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/bitops.h>
-#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -340,7 +339,7 @@ int checkboard(void)
*/
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index b6c3065..fdd82e7 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -119,36 +119,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000); /* */
- mtdcr (uicb0tr, 0x00000000); /* */
- mtdcr (uicb0vr, 0x00000001); /* */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+ mtdcr (uic3er, 0x00000000); /* disable all */
+ mtdcr (uic3cr, 0x00000000); /* all non-critical */
+ mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic0sr, 0xfc000000); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non-critical */
+ mtdcr (uic0pr, 0xfc000000); /* */
+ mtdcr (uic0tr, 0x00000000); /* */
+ mtdcr (uic0vr, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(sdr_pfc0,reg);
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 6608893..84c3938 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -677,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
return 1;
}
-int yucca_pcie_card_present(int port)
+static int yucca_pcie_card_present(int port)
{
u16 reg;
@@ -879,10 +879,6 @@ void pcie_setup_hoses(int busno)
int misc_init_f (void)
{
uint reg;
-#if defined(CONFIG_STRESS)
- uint i ;
- uint disp;
-#endif
out16(FPGA_REG10, (in16(FPGA_REG10) &
~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@@ -897,67 +893,23 @@ int misc_init_f (void)
/* minimal init for PCIe */
/* pci express 0 Endpoint Mode */
- mfsdr(SDR0_PE0DLPSET, reg);
+ mfsdr(SDRN_PESDR_DLPSET(0), reg);
reg &= (~0x00400000);
- mtsdr(SDR0_PE0DLPSET, reg);
+ mtsdr(SDRN_PESDR_DLPSET(0), reg);
/* pci express 1 Rootpoint Mode */
- mfsdr(SDR0_PE1DLPSET, reg);
+ mfsdr(SDRN_PESDR_DLPSET(1), reg);
reg |= 0x00400000;
- mtsdr(SDR0_PE1DLPSET, reg);
+ mtsdr(SDRN_PESDR_DLPSET(1), reg);
/* pci express 2 Rootpoint Mode */
- mfsdr(SDR0_PE2DLPSET, reg);
+ mfsdr(SDRN_PESDR_DLPSET(2), reg);
reg |= 0x00400000;
- mtsdr(SDR0_PE2DLPSET, reg);
+ mtsdr(SDRN_PESDR_DLPSET(2), reg);
out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
~FPGA_REG1C_PE0_ROOTPOINT &
~FPGA_REG1C_PE1_ENDPOINT &
~FPGA_REG1C_PE2_ENDPOINT));
-#if defined(CONFIG_STRESS)
- /*
- * all this setting done by linux only needed by stress an charac. test
- * procedure
- * PCIe 1 Rootpoint PCIe2 Endpoint
- * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
- * Power Level
- */
- for (i = 0, disp = 0; i < 8; i++, disp += 3) {
- mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
- reg |= 0x33000000;
- mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
- }
-
- /*
- * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
- * Power Level
- */
- for (i = 0, disp = 0; i < 4; i++, disp += 3) {
- mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
- reg |= 0x33000000;
- mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
- }
-
- /*
- * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
- * Power Level
- */
- for (i = 0, disp = 0; i < 4; i++, disp += 3) {
- mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
- reg |= 0x33000000;
- mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
- }
-
- reg = 0x21242222;
- mtsdr(SDR0_PE2UTLSET1, reg);
- reg = 0x11000000;
- mtsdr(SDR0_PE2UTLSET2, reg);
- /* pci express 1 Endpoint Mode */
- reg = 0x00004000;
- mtsdr(SDR0_PE2DLPSET, reg);
-
- mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
-#endif
return 0;
}
diff --git a/board/delta/nand.c b/board/delta/nand.c
index b007b09..4ce78a1 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -23,7 +23,7 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND)
-#if !defined(CFG_NAND_LEGACY)
+#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/pxa-regs.h>
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 7e6eea0..a1e0ce5 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -27,7 +27,7 @@
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
-#if defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#endif
#include <fat.h>
@@ -58,7 +58,7 @@ extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
/* references to names in cmd_nand.c */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
@@ -158,7 +158,7 @@ int au_do_update(int i, long sz)
int off, rc;
uint nbytes;
int k;
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
int total;
#endif
@@ -241,7 +241,7 @@ int au_do_update(int i, long sz)
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase (start, end);
} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
printf ("Updating NAND FLASH with image %s\n",
au_image[i].name);
debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
@@ -273,7 +273,7 @@ int au_do_update(int i, long sz)
rc = flash_write ((char *)addr, start,
(nbytes + 1) & ~1);
} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
debug ("nand_legacy_rw(%p, %lx, %x)\n",
addr, start, nbytes);
rc = nand_legacy_rw (nand_dev_desc,
@@ -298,7 +298,7 @@ int au_do_update(int i, long sz)
rc = crc32 (0, (uchar *)(start + off),
image_get_data_size (hdr));
} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
rc = nand_legacy_rw (nand_dev_desc,
NANDRW_READ | NANDRW_JFFS2 |
NANDRW_JFFS2_SKIP,
diff --git a/board/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
index a12f391..a12f391 100644
--- a/board/mx31ads/Makefile
+++ b/board/freescale/mx31ads/Makefile
diff --git a/board/mx31ads/config.mk b/board/freescale/mx31ads/config.mk
index d34dc02..d34dc02 100644
--- a/board/mx31ads/config.mk
+++ b/board/freescale/mx31ads/config.mk
diff --git a/board/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
index e166058..e166058 100644
--- a/board/mx31ads/lowlevel_init.S
+++ b/board/freescale/mx31ads/lowlevel_init.S
diff --git a/board/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
index c24c47c..c24c47c 100644
--- a/board/mx31ads/mx31ads.c
+++ b/board/freescale/mx31ads/mx31ads.c
diff --git a/board/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 49713d4..c379460 100644
--- a/board/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/arm1136/start.o (.text)
- board/mx31ads/libmx31ads.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
+ cpu/arm1136/start.o (.text)
+ board/freescale/mx31ads/libmx31ads.a (.text)
+ lib_arm/libarm.a (.text)
+ net/libnet.a (.text)
+ drivers/mtd/libmtd.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o(.text)
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
index 15e86d3..2d4026a 100644
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -23,7 +23,7 @@
#include <common.h>
-#ifndef CFG_FLASH_CFI_DRIVER
+#ifndef CONFIG_FLASH_CFI_DRIVER
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
@@ -490,4 +490,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
return (res);
}
-#endif /*CFG_FLASH_CFI_DRIVER*/
+#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 51874ea..0d90fb3 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -33,7 +33,7 @@
#include <asm/bitops.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/ppc4xx-intvec.h>
+#include <asm/ppc4xx-uic.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -575,7 +575,7 @@ int checkboard(void)
*/
void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
diff --git a/board/netta/netta.c b/board/netta/netta.c
index 1183f33..bc31386 100644
--- a/board/netta/netta.c
+++ b/board/netta/netta.c
@@ -555,7 +555,7 @@ int board_early_init_f(void)
return 0;
}
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index 131a62d..cc491d0 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -48,36 +48,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe03); /* per manual */
- mtdcr (uic0tr, 0x01c00000); /* per manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (uic1pr, 0xfffffe03); /* per manual */
+ mtdcr (uic1tr, 0x01c00000); /* per manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000); /* */
- mtdcr (uicb0tr, 0x00000000); /* */
- mtdcr (uicb0vr, 0x00000001); /* */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+ mtdcr (uic3er, 0x00000000); /* disable all */
+ mtdcr (uic3cr, 0x00000000); /* all non-critical */
+ mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic0sr, 0xfc000000); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non-critical */
+ mtdcr (uic0pr, 0xfc000000); /* */
+ mtdcr (uic0tr, 0x00000000); /* */
+ mtdcr (uic0vr, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index 518ea9c..0786324 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/arch/ixp425.h>
-#if !defined(CFG_FLASH_CFI_DRIVER)
+#if !defined(CONFIG_FLASH_CFI_DRIVER)
/*
* include common flash code (for esd boards)
@@ -86,4 +86,4 @@ unsigned long flash_init(void)
return size;
}
-#endif /* CFG_FLASH_CFI_DRIVER */
+#endif /* CONFIG_FLASH_CFI_DRIVER */
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index 2d71d3b..72ce976 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -195,36 +195,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
+-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non- critical */
- mtdcr (uic0pr, 0xfffffe03); /* polarity */
- mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffc8ff); /* polarity */
- mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (uic1cr, 0x00000000); /* all non- critical */
+ mtdcr (uic1pr, 0xfffffe03); /* polarity */
+ mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffff83ff); /* polarity */
- mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic2pr, 0xffffc8ff); /* polarity */
+ mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000);
- mtdcr (uicb0tr, 0x00000000);
- mtdcr (uicb0vr, 0x00000001);
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+ mtdcr (uic3er, 0x00000000); /* disable all */
+ mtdcr (uic3cr, 0x00000000); /* all non-critical */
+ mtdcr (uic3pr, 0xffff83ff); /* polarity */
+ mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic0sr, 0xfc000000); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non-critical */
+ mtdcr (uic0pr, 0xfc000000);
+ mtdcr (uic0tr, 0x00000000);
+ mtdcr (uic0vr, 0x00000001);
fpga_init();
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 66cdfb1..c38850d 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -185,36 +185,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
+-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non- critical */
- mtdcr (uic0pr, 0xfffffe03); /* polarity */
- mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffc8ff); /* polarity */
- mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (uic1cr, 0x00000000); /* all non- critical */
+ mtdcr (uic1pr, 0xfffffe03); /* polarity */
+ mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffff83ff); /* polarity */
- mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic2pr, 0xffffc8ff); /* polarity */
+ mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000);
- mtdcr (uicb0tr, 0x00000000);
- mtdcr (uicb0vr, 0x00000001);
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+ mtdcr (uic3er, 0x00000000); /* disable all */
+ mtdcr (uic3cr, 0x00000000); /* all non-critical */
+ mtdcr (uic3pr, 0xffff83ff); /* polarity */
+ mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic0sr, 0xfc000000); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non-critical */
+ mtdcr (uic0pr, 0xfc000000);
+ mtdcr (uic0tr, 0x00000000);
+ mtdcr (uic0vr, 0x00000001);
fpga_init();
diff --git a/board/tqc/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c
index 4342ebc..1231c7c 100644
--- a/board/tqc/tqm8xx/flash.c
+++ b/board/tqc/tqm8xx/flash.c
@@ -33,7 +33,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
+#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
&& !defined(CONFIG_TQM885D)
@@ -831,4 +831,4 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/*-----------------------------------------------------------------------
*/
-#endif /* !defined(CFG_FLASH_CFI_DRIVER) */
+#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */
diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile
new file mode 100644
index 0000000..7283704
--- /dev/null
+++ b/board/xilinx/ml507/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+endif
+
+INCS :=
+CFLAGS += $(INCS)
+HOST_CFLAGS += $(INCS)
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xilinx/ml507/config.mk b/board/xilinx/ml507/config.mk
new file mode 100644
index 0000000..e827e8a
--- /dev/null
+++ b/board/xilinx/ml507/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0x04000000
+endif
diff --git a/board/xilinx/ml507/init.S b/board/xilinx/ml507/init.S
new file mode 100644
index 0000000..3228a65
--- /dev/null
+++ b/board/xilinx/ml507/init.S
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+.section .bootpg,"ax"
+.globl tlbtab
+
+tlbtab:
+tlbtab_start
+ /* SDRAM */
+tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0,
+ AC_R | AC_W | AC_X | SA_G | SA_I)
+ /* UART */
+tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0,
+ AC_R | AC_W | SA_G | SA_I)
+ /* PIC */
+tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0,
+ AC_R | AC_W | SA_G | SA_I)
+#ifdef XPAR_IIC_EEPROM_BASEADDR
+ /* I2C */
+tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0,
+ AC_R | AC_W | SA_G | SA_I)
+#endif
+#ifdef XPAR_LLTEMAC_0_BASEADDR
+ /* Net */
+tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0,
+ AC_R | AC_W | SA_G | SA_I)
+#endif
+#ifdef XPAR_FLASH_MEM0_BASEADDR
+ /*Flash*/
+tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0,
+ AC_R | AC_W | AC_X | SA_G | SA_I)
+#endif
+tlbtab_end
diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c
new file mode 100644
index 0000000..d499303
--- /dev/null
+++ b/board/xilinx/ml507/ml507.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int board_pre_init(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("ML507 Board\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+ CFG_SDRAM_SIZE_MB * 1024 * 1024);
+}
+
+void get_sys_info(sys_info_t * sysInfo)
+{
+ sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sysInfo->freqPCI = 0;
+
+ return;
+}
diff --git a/board/xilinx/ml507/u-boot-ram.lds b/board/xilinx/ml507/u-boot-ram.lds
new file mode 100644
index 0000000..2c98d27
--- /dev/null
+++ b/board/xilinx/ml507/u-boot-ram.lds
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start_440)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/xilinx/ml507/u-boot-rom.lds b/board/xilinx/ml507/u-boot-rom.lds
new file mode 100644
index 0000000..d5da018
--- /dev/null
+++ b/board/xilinx/ml507/u-boot-rom.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start_440)
+
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h
new file mode 100644
index 0000000..77d2ddf
--- /dev/null
+++ b/board/xilinx/ml507/xparameters.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_LLTEMAC_0_BASEADDR 0x81C00000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+
+#endif
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index bc7e3bd..c94a345 100644
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -59,36 +59,48 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */
+ mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
+ mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */
+ mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */
+ mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000); /* */
- mtdcr (uicb0tr, 0x00000000); /* */
- mtdcr (uicb0vr, 0x00000001); /* */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+ mtdcr (uic3er, 0x00000000); /* disable all */
+ mtdcr (uic3cr, 0x00000000); /* all non-critical */
+ mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic0sr, 0xfc000000); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non-critical */
+ mtdcr (uic0pr, 0xfc000000); /* */
+ mtdcr (uic0tr, 0x00000000); /* */
+ mtdcr (uic0vr, 0x00000001); /* */
LED0_ON();
diff --git a/common/ACEX1K.c b/common/ACEX1K.c
index 76dc166..53677b8 100644
--- a/common/ACEX1K.c
+++ b/common/ACEX1K.c
@@ -28,8 +28,6 @@
#include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
-
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -362,5 +360,3 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
return ret_val;
}
-
-#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */
diff --git a/common/Makefile b/common/Makefile
index ecf755f..c2b381b 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -28,9 +28,7 @@ LIB = $(obj)libcommon.a
AOBJS =
COBJS-y += main.o
-COBJS-y += ACEX1K.o
-COBJS-y += altera.o
-COBJS-y += bedbug.o
+COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o
COBJS-y += circbuf.o
COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
COBJS-y += cmd_autoscript.o
@@ -64,7 +62,18 @@ COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
ifdef CONFIG_FPGA
+COBJS-y += fpga.o
COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
+COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
+COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
+COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
+COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
+ifdef CONFIG_FPGA_ALTERA
+COBJS-y += altera.o
+COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
+COBJS-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
+COBJS-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
+endif
endif
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
@@ -80,7 +89,7 @@ COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
COBJS-y += cmd_nand.o
COBJS-$(CONFIG_CMD_NET) += cmd_net.o
COBJS-y += cmd_nvedit.o
-COBJS-y += cmd_onenand.o
+COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
ifdef CONFIG_PCI
COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
@@ -102,11 +111,9 @@ COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
COBJS-y += cmd_vfd.o
COBJS-y += command.o
COBJS-y += console.o
-COBJS-y += cyclon2.o
-COBJS-y += stratixII.o
COBJS-y += devices.o
COBJS-y += dlmalloc.o
-COBJS-y += docecc.o
+COBJS-$(CONFIG_CMD_DOC) += docecc.o
COBJS-y += environment.o
COBJS-y += env_common.o
COBJS-y += env_nand.o
@@ -119,26 +126,23 @@ COBJS-y += env_nvram.o
COBJS-y += env_nowhere.o
COBJS-y += exports.o
COBJS-y += flash.o
-COBJS-y += fpga.o
COBJS-y += hush.o
COBJS-y += kgdb.o
-COBJS-y += lcd.o
+COBJS-$(CONFIG_LCD) += lcd.o
COBJS-y += lists.o
-COBJS-y += lynxkdi.o
+COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-y += memsize.o
-COBJS-y += miiphybb.o
+COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
COBJS-y += miiphyutil.o
COBJS-y += s_record.o
COBJS-y += serial.o
-COBJS-y += soft_i2c.o
-COBJS-y += soft_spi.o
-COBJS-y += spartan2.o
-COBJS-y += spartan3.o
+COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
+COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
+ifdef CONFIG_CMD_USB
COBJS-y += usb.o
-COBJS-y += usb_kbd.o
-COBJS-y += usb_storage.o
-COBJS-y += virtex2.o
-COBJS-y += xilinx.o
+COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
+endif
+COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
COBJS-y += crc16.o
COBJS-y += xyzModem.o
COBJS-y += cmd_mac.o
diff --git a/common/altera.c b/common/altera.c
index a2b5967..09dc0b2 100644
--- a/common/altera.c
+++ b/common/altera.c
@@ -41,8 +41,6 @@
#define PRINTF(fmt,args...)
#endif
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
-
/* Local Static Functions */
static int altera_validate (Altera_desc * desc, const char *fn);
@@ -283,5 +281,3 @@ static int altera_validate (Altera_desc * desc, const char *fn)
}
/* ------------------------------------------------------------------------- */
-
-#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */
diff --git a/common/bedbug.c b/common/bedbug.c
index 3bf1fc3..60109cf 100644
--- a/common/bedbug.c
+++ b/common/bedbug.c
@@ -2,8 +2,6 @@
#include <common.h>
-#if defined(CONFIG_CMD_BEDBUG)
-
#include <linux/ctype.h>
#include <bedbug/bedbug.h>
#include <bedbug/ppc.h>
@@ -1252,5 +1250,3 @@ int find_next_address (unsigned char *nextaddr, int step_over,
* warranties of merchantability and fitness for a particular
* purpose.
*/
-
-#endif
diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index b4698be..c031d80 100644
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -96,12 +96,12 @@
#include <cramfs/cramfs_fs.h>
#if defined(CONFIG_CMD_NAND)
-#ifdef CFG_NAND_LEGACY
+#ifdef CONFIG_NAND_LEGACY
#include <linux/mtd/nand_legacy.h>
-#else /* !CFG_NAND_LEGACY */
+#else /* !CONFIG_NAND_LEGACY */
#include <linux/mtd/nand.h>
#include <nand.h>
-#endif /* !CFG_NAND_LEGACY */
+#endif /* !CONFIG_NAND_LEGACY */
#endif
/* enable/disable debugging messages */
#define DEBUG_JFFS
@@ -476,7 +476,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
}
}
-#ifdef CFG_NAND_LEGACY
+#ifdef CONFIG_NAND_LEGACY
jffs2_free_cache(part);
#endif
list_del(&part->link);
@@ -505,7 +505,7 @@ static void part_delall(struct list_head *head)
list_for_each_safe(entry, n, head) {
part_tmp = list_entry(entry, struct part_info, link);
-#ifdef CFG_NAND_LEGACY
+#ifdef CONFIG_NAND_LEGACY
jffs2_free_cache(part_tmp);
#endif
list_del(entry);
@@ -741,7 +741,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
if (num < CFG_MAX_NAND_DEVICE) {
-#ifndef CFG_NAND_LEGACY
+#ifndef CONFIG_NAND_LEGACY
*size = nand_info[num].size;
#else
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 520c152..fa7a438 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -11,7 +11,7 @@
#include <common.h>
-#ifndef CFG_NAND_LEGACY
+#ifndef CONFIG_NAND_LEGACY
/*
*
* New NAND support
@@ -667,7 +667,7 @@ U_BOOT_CMD(nboot, 4, 1, do_nandboot,
#endif
-#else /* CFG_NAND_LEGACY */
+#else /* CONFIG_NAND_LEGACY */
/*
*
* Legacy NAND support - to be phased out
@@ -1077,4 +1077,4 @@ U_BOOT_CMD(
#endif
-#endif /* CFG_NAND_LEGACY */
+#endif /* CONFIG_NAND_LEGACY */
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index 419bf70..5e2062b 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -12,8 +12,6 @@
#include <common.h>
#include <command.h>
-#ifdef CONFIG_CMD_ONENAND
-
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
@@ -159,5 +157,3 @@ U_BOOT_CMD(
"onenand block[.oob] addr block [page] [len] - "
"read data with (block [, page]) to addr"
);
-
-#endif /* CONFIG_CMD_ONENAND */
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index 0657e4b..c0a1459 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -93,11 +93,10 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
- "uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
+ "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"\n"
- "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ "%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
- mfdcr(uicsrs),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
diff --git a/common/cyclon2.c b/common/cyclon2.c
index 06f5e8a..479bebb 100644
--- a/common/cyclon2.c
+++ b/common/cyclon2.c
@@ -27,8 +27,6 @@
#include <altera.h>
#include <ACEX1K.h> /* ACEX device family */
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
-
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -301,5 +299,3 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
return ret_val;
}
-
-#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */
diff --git a/common/docecc.c b/common/docecc.c
index 5daa6fc..3412aff 100644
--- a/common/docecc.c
+++ b/common/docecc.c
@@ -31,8 +31,6 @@
#undef ECC_DEBUG
#undef PSYCHO_DEBUG
-#if defined(CONFIG_CMD_DOC)
-
#include <linux/mtd/doc2000.h>
/* need to undef it (from asm/termbits.h) */
@@ -513,5 +511,3 @@ int doc_decode_ecc(unsigned char sector[SECTOR_SIZE], unsigned char ecc1[6])
free(Index_of);
return nb_errors;
}
-
-#endif
diff --git a/common/fpga.c b/common/fpga.c
index d16a92d..67a6c30 100644
--- a/common/fpga.c
+++ b/common/fpga.c
@@ -29,8 +29,6 @@
#include <xilinx.h> /* xilinx specific definitions */
#include <altera.h> /* altera specific definitions */
-#if defined(CONFIG_FPGA)
-
#if 0
#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
#endif
@@ -335,5 +333,3 @@ int fpga_info( int devnum )
}
/* ------------------------------------------------------------------------- */
-
-#endif /* CONFIG_FPGA */
diff --git a/common/lcd.c b/common/lcd.c
index 8d770f3..25f8664 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -55,8 +55,6 @@
#include <nand.h>
#endif
-#ifdef CONFIG_LCD
-
/************************************************************************/
/* ** FONT DATA */
/************************************************************************/
@@ -867,5 +865,3 @@ static void *lcd_logo (void)
/************************************************************************/
/************************************************************************/
-
-#endif /* CONFIG_LCD */
diff --git a/common/lynxkdi.c b/common/lynxkdi.c
index a5dc887..5f12b0d 100644
--- a/common/lynxkdi.c
+++ b/common/lynxkdi.c
@@ -17,7 +17,6 @@
#include <asm/processor.h>
#include <image.h>
-#if defined(CONFIG_LYNXKDI)
#include <lynxkdi.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,5 +65,3 @@ void lynxkdi_boot (image_header_t *hdr)
#else
#error "Lynx KDI support not implemented for configured CPU"
#endif
-
-#endif /* CONFIG_LYNXKDI */
diff --git a/common/miiphybb.c b/common/miiphybb.c
index 537c15d..6446012 100644
--- a/common/miiphybb.c
+++ b/common/miiphybb.c
@@ -30,9 +30,6 @@
#include <ioports.h>
#include <ppc_asm.tmpl>
-#ifdef CONFIG_BITBANGMII
-
-
/*****************************************************************************
*
* Utility to send the preamble, address, and register (common to read
@@ -236,5 +233,3 @@ int bb_miiphy_write (char *devname, unsigned char addr,
return 0;
}
-
-#endif /* CONFIG_BITBANGMII */
diff --git a/common/soft_i2c.c b/common/soft_i2c.c
index 5ef7f30..23db2ee 100644
--- a/common/soft_i2c.c
+++ b/common/soft_i2c.c
@@ -41,8 +41,6 @@
#endif
#include <i2c.h>
-#if defined(CONFIG_SOFT_I2C)
-
/* #define DEBUG_I2C */
#ifdef DEBUG_I2C
@@ -423,6 +421,3 @@ void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
i2c_write(i2c_addr, reg, 1, &val, 1);
}
-
-
-#endif /* CONFIG_SOFT_I2C */
diff --git a/common/soft_spi.c b/common/soft_spi.c
index c131650..25b589a 100644
--- a/common/soft_spi.c
+++ b/common/soft_spi.c
@@ -27,8 +27,6 @@
#include <common.h>
#include <spi.h>
-#if defined(CONFIG_SOFT_SPI)
-
#include <malloc.h>
/*-----------------------------------------------------------------------
@@ -193,5 +191,3 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return(0);
}
-
-#endif /* CONFIG_SOFT_SPI */
diff --git a/common/spartan2.c b/common/spartan2.c
index 2f1ea2c..ebac388 100644
--- a/common/spartan2.c
+++ b/common/spartan2.c
@@ -25,8 +25,6 @@
#include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
-
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -663,5 +661,3 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
return ret_val;
}
-
-#endif
diff --git a/common/spartan3.c b/common/spartan3.c
index d329e70..8f1ab80 100644
--- a/common/spartan3.c
+++ b/common/spartan3.c
@@ -30,8 +30,6 @@
#include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
-
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -668,5 +666,3 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
return ret_val;
}
-
-#endif
diff --git a/common/stratixII.c b/common/stratixII.c
index 85c461c..7556dbf 100644
--- a/common/stratixII.c
+++ b/common/stratixII.c
@@ -25,8 +25,6 @@
#include <common.h> /* core U-Boot definitions */
#include <altera.h>
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II)
-
int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
int isSerial, int isSecure);
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
@@ -231,5 +229,3 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
return FPGA_SUCCESS;
}
-
-#endif /* defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II) */
diff --git a/common/usb.c b/common/usb.c
index a45d113..9502f39 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -50,8 +50,6 @@
#include <linux/ctype.h>
#include <asm/byteorder.h>
-#if defined(CONFIG_CMD_USB)
-
#include <usb.h>
#ifdef CONFIG_4xx
#include <asm/4xx_pci.h>
@@ -1247,6 +1245,4 @@ int usb_hub_probe(struct usb_device *dev, int ifnum)
return ret;
}
-#endif
-
/* EOF */
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index c876495..04d9730e 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -28,8 +28,6 @@
#include <devices.h>
#include <asm/byteorder.h>
-#ifdef CONFIG_USB_KEYBOARD
-
#include <usb.h>
#undef USB_KBD_DEBUG
@@ -746,7 +744,4 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev)
}
-
#endif
-
-#endif /* CONFIG_USB_KEYBOARD */
diff --git a/common/usb_storage.c b/common/usb_storage.c
index d8fbb69..94f659f 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -55,13 +55,9 @@
#include <asm/byteorder.h>
#include <asm/processor.h>
-
-#if defined(CONFIG_CMD_USB)
#include <part.h>
#include <usb.h>
-#ifdef CONFIG_USB_STORAGE
-
#undef USB_STOR_DEBUG
#undef BBB_COMDAT_TRACE
#undef BBB_XPORT_TRACE
@@ -1242,6 +1238,3 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type);
return 1;
}
-
-#endif /* CONFIG_USB_STORAGE */
-#endif
diff --git a/common/virtex2.c b/common/virtex2.c
index 665a503..52da1b2 100644
--- a/common/virtex2.c
+++ b/common/virtex2.c
@@ -31,8 +31,6 @@
#include <common.h>
#include <virtex2.h>
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
-
#if 0
#define FPGA_DEBUG
#endif
@@ -552,6 +550,5 @@ static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
}
return ret_val;
}
-#endif
/* vim: set ts=4 tw=78: */
diff --git a/common/xilinx.c b/common/xilinx.c
index c898238..7b5e8c5 100644
--- a/common/xilinx.c
+++ b/common/xilinx.c
@@ -32,8 +32,6 @@
#include <spartan2.h>
#include <spartan3.h>
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
-
#if 0
#define FPGA_DEBUG
#endif
@@ -307,5 +305,3 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
return ret_val;
}
-
-#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */
diff --git a/cpu/arm920t/s3c24x0/nand.c b/cpu/arm920t/s3c24x0/nand.c
index 9d63243..60174fb 100644
--- a/cpu/arm920t/s3c24x0/nand.c
+++ b/cpu/arm920t/s3c24x0/nand.c
@@ -27,7 +27,7 @@
#endif
#if defined(CONFIG_CMD_NAND)
-#if !defined(CFG_NAND_LEGACY)
+#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <s3c2410.h>
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 8fd784e..2aa01d6 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -45,7 +45,7 @@
#include <asm/io.h>
#ifdef CFG_USE_NAND
-#if !defined(CFG_NAND_LEGACY)
+#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/nand_defs.h>
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index e9940e8..1c36324 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -50,9 +50,19 @@
#include "ecc.h"
-#if defined(CONFIG_SPD_EEPROM) && \
- (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT))
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+
+#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
+ do { \
+ u32 data; \
+ mfsdram(SDRAM_##mnemonic, data); \
+ printf("%20s[%02x] = 0x%08X\n", \
+ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
+ } while (0)
+
+static inline void ppc4xx_ibm_ddr2_register_dump(void);
+
+#if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+
* Defines
@@ -257,7 +267,6 @@ static void test(void);
#else
static void DQS_calibration_process(void);
#endif
-static void ppc440sp_sdram_register_dump(void);
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
@@ -607,7 +616,7 @@ phys_size_t initdram(int board_type)
remove_tlb(0, dram_size);
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
- ppc440sp_sdram_register_dump();
+ ppc4xx_ibm_ddr2_register_dump();
/*
* Clear potential errors resulting from auto-calibration.
@@ -2760,7 +2769,7 @@ calibration_loop:
printf("\nERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
- ppc440sp_sdram_register_dump();
+ ppc4xx_ibm_ddr2_register_dump();
spd_ddr_init_hang ();
}
@@ -2946,169 +2955,8 @@ static void test(void)
}
#endif
-#if defined(DEBUG)
-static void ppc440sp_sdram_register_dump(void)
-{
- unsigned int sdram_reg;
- unsigned int sdram_data;
- unsigned int dcr_data;
-
- printf("\n Register Dump:\n");
- sdram_reg = SDRAM_MCSTAT;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
- sdram_reg = SDRAM_MCOPT1;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_MCOPT2;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_MODT0;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_MODT1;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_MODT2;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_MODT3;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_CODT;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_VVPR;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_VVPR = 0x%08X", sdram_data);
- sdram_reg = SDRAM_OPARS;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
- /*
- * OPAR2 is only used as a trigger register.
- * No data is contained in this register, and reading or writing
- * to is can cause bad things to happen (hangs). Just skip it
- * and report NA
- * sdram_reg = SDRAM_OPAR2;
- * mfsdram(sdram_reg, sdram_data);
- * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
- */
- printf(" SDRAM_OPART = N/A ");
- sdram_reg = SDRAM_RTR;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_MB0CF;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
- sdram_reg = SDRAM_MB1CF;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_MB2CF;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
- sdram_reg = SDRAM_MB3CF;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR0;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR1;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR2;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR3;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR4;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR5;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR6;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR7;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR8;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR9;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR10;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR11;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR12;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR13;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_INITPLR14;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_INITPLR15;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_RQDC;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_RQDC = 0x%08X", sdram_data);
- sdram_reg = SDRAM_RFDC;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_RDCC;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_RDCC = 0x%08X", sdram_data);
- sdram_reg = SDRAM_DLCR;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_CLKTR;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
- sdram_reg = SDRAM_WRDTR;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_SDTR1;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_SDTR2;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_SDTR3;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
- sdram_reg = SDRAM_MMODE;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
- sdram_reg = SDRAM_MEMODE;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
- sdram_reg = SDRAM_ECCCR;
- mfsdram(sdram_reg, sdram_data);
- printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
-
- dcr_data = mfdcr(SDRAM_R0BAS);
- printf(" MQ0_B0BAS = 0x%08X", dcr_data);
- dcr_data = mfdcr(SDRAM_R1BAS);
- printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
- dcr_data = mfdcr(SDRAM_R2BAS);
- printf(" MQ2_B0BAS = 0x%08X", dcr_data);
- dcr_data = mfdcr(SDRAM_R3BAS);
- printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
-}
-#else /* !defined(DEBUG) */
-static void ppc440sp_sdram_register_dump(void)
-{
-}
-#endif /* defined(DEBUG) */
-#elif defined(CONFIG_405EX)
+#else /* CONFIG_SPD_EEPROM */
+
/*-----------------------------------------------------------------------------
* Function: initdram
* Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
@@ -3222,8 +3070,96 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_DDR_ECC)
ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
+
+ ppc4xx_ibm_ddr2_register_dump();
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CFG_MBYTES_SDRAM << 20);
}
-#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */
+#endif /* CONFIG_SPD_EEPROM */
+
+static inline void ppc4xx_ibm_ddr2_register_dump(void)
+{
+#if defined(DEBUG)
+ printf("\nPPC4xx IBM DDR2 Register Dump:\n");
+
+#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT))
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
+#endif /* (defined(CONFIG_440SP) || ... */
+#if defined(CONFIG_405EX)
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
+#endif /* defined(CONFIG_405EX) */
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
+#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT))
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
+ /*
+ * OPART is only used as a trigger register.
+ *
+ * No data is contained in this register, and reading or writing
+ * to is can cause bad things to happen (hangs). Just skip it and
+ * report "N/A".
+ */
+ printf("%20s = N/A\n", "SDRAM_OPART");
+#endif /* defined(CONFIG_440SP) || ... */
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
+#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT))
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
+#endif /* defined(CONFIG_440SP) || ... */
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
+#endif /* defined(DEBUG) */
+}
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 4e863dc..8a38335 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -90,7 +90,6 @@
#include <405_mal.h>
#include <miiphy.h>
#include <malloc.h>
-#include <asm/ppc4xx-intvec.h>
/*
* Only compile for platform with AMCC EMAC ethernet controller and
@@ -122,11 +121,65 @@
* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
* Interrupt Controller).
*-----------------------------------------------------------------------------*/
-#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
-#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
-#define EMAC_UIC_DEF UIC_ENET
-#define EMAC_UIC_DEF1 UIC_ENET1
-#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
+#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
+
+#if defined(CONFIG_HAS_ETH3)
+#if !defined(CONFIG_440GX)
+#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
+ UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
+#else
+/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
+#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
+#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
+#endif /* !defined(CONFIG_440GX) */
+#elif defined(CONFIG_HAS_ETH2)
+#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
+ UIC_MASK(ETH_IRQ_NUM(2)))
+#elif defined(CONFIG_HAS_ETH1)
+#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
+#else
+#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
+#endif
+
+/*
+ * Define a default version for UIC_ETHxB for non 440GX so that we can
+ * use common code for all 4xx variants
+ */
+#if !defined(UIC_ETHxB)
+#define UIC_ETHxB 0
+#endif
+
+#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
+#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
+#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
+#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
+#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
+
+#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
+#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
+
+/*
+ * We have 3 different interrupt types:
+ * - MAL interrupts indicating successful transfer
+ * - MAL error interrupts indicating MAL related errors
+ * - EMAC interrupts indicating EMAC related errors
+ *
+ * All those interrupts can be on different UIC's, but since
+ * now at least all interrupts from one type are on the same
+ * UIC. Only exception is 440GX where the EMAC interrupts are
+ * spread over two UIC's!
+ */
+#if defined(CONFIG_440GX)
+#define UIC_BASE_MAL UIC1_DCR_BASE
+#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
+#define UIC_BASE_EMAC UIC2_DCR_BASE
+#define UIC_BASE_EMAC_B UIC3_DCR_BASE
+#else
+#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
+#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
+#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
+#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
+#endif
#undef INFO_4XX_ENET
@@ -166,9 +219,6 @@
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
-/* IER globals */
-static uint32_t mal_ier;
-
#if !defined(CONFIG_NET_MULTI)
struct eth_device *emac0_dev = NULL;
#endif
@@ -200,12 +250,6 @@ struct eth_device *emac0_dev = NULL;
#define CONFIG_EMAC_NR_START 0
#endif
-#if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
-#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
-#else
-#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
-#endif
-
#define MAL_RX_DESC_SIZE 2048
#define MAL_TX_DESC_SIZE 2048
#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
@@ -465,30 +509,88 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
#if defined(CONFIG_405EX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
- u32 gmiifer = 0;
+ u32 rgmiifer = 0;
/*
- * Right now only 2*RGMII is supported. Please extend when needed.
- * sr - 2007-09-19
+ * The 405EX(r)'s RGMII bridge can operate in one of several
+ * modes, only one of which (2 x RGMII) allows the
+ * simultaneous use of both EMACs on the 405EX.
*/
- switch (1) {
- case 1:
+
+ switch (CONFIG_EMAC_PHY_MODE) {
+
+ case EMAC_PHY_MODE_NONE:
+ /* No ports */
+ rgmiifer |= RGMII_FER_DIS << 0;
+ rgmiifer |= RGMII_FER_DIS << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_NONE;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
+ break;
+ case EMAC_PHY_MODE_NONE_RGMII:
+ /* 1 x RGMII port on channel 0 */
+ rgmiifer |= RGMII_FER_RGMII << 0;
+ rgmiifer |= RGMII_FER_DIS << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
+ break;
+ case EMAC_PHY_MODE_RGMII_NONE:
+ /* 1 x RGMII port on channel 1 */
+ rgmiifer |= RGMII_FER_DIS << 0;
+ rgmiifer |= RGMII_FER_RGMII << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_NONE;
+ bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+ break;
+ case EMAC_PHY_MODE_RGMII_RGMII:
/* 2 x RGMII ports */
- out_be32((void *)RGMII_FER, 0x00000055);
+ rgmiifer |= RGMII_FER_RGMII << 0;
+ rgmiifer |= RGMII_FER_RGMII << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
- case 2:
- /* 2 x SMII ports */
+ case EMAC_PHY_MODE_NONE_GMII:
+ /* 1 x GMII port on channel 0 */
+ rgmiifer |= RGMII_FER_GMII << 0;
+ rgmiifer |= RGMII_FER_DIS << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_GMII;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
+ break;
+ case EMAC_PHY_MODE_NONE_MII:
+ /* 1 x MII port on channel 0 */
+ rgmiifer |= RGMII_FER_MII << 0;
+ rgmiifer |= RGMII_FER_DIS << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_MII;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
+ break;
+ case EMAC_PHY_MODE_GMII_NONE:
+ /* 1 x GMII port on channel 1 */
+ rgmiifer |= RGMII_FER_DIS << 0;
+ rgmiifer |= RGMII_FER_GMII << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_NONE;
+ bis->bi_phymode[1] = BI_PHYMODE_GMII;
+ break;
+ case EMAC_PHY_MODE_MII_NONE:
+ /* 1 x MII port on channel 1 */
+ rgmiifer |= RGMII_FER_DIS << 0;
+ rgmiifer |= RGMII_FER_MII << 4;
+ out_be32((void *)RGMII_FER, rgmiifer);
+ bis->bi_phymode[0] = BI_PHYMODE_NONE;
+ bis->bi_phymode[1] = BI_PHYMODE_MII;
break;
default:
break;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
- gmiifer = in_be32((void *)RGMII_FER);
- gmiifer |= (1 << (19-devnum));
- out_be32((void *)RGMII_FER, gmiifer);
+ rgmiifer = in_be32((void *)RGMII_FER);
+ rgmiifer |= (1 << (19-devnum));
+ out_be32((void *)RGMII_FER, rgmiifer);
return ((int)0x0);
}
@@ -1377,59 +1479,17 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
}
}
-
-#if defined (CONFIG_440) || defined(CONFIG_405EX)
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-/*
- * Hack: On 440SP all enet irq sources are located on UIC1
- * Needs some cleanup. --sr
- */
-#define UIC0MSR uic1msr
-#define UIC0SR uic1sr
-#define UIC1MSR uic1msr
-#define UIC1SR uic1sr
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-/*
- * Hack: On 460EX/GT all enet irq sources are located on UIC2
- * Needs some cleanup. --ag
- */
-#define UIC0MSR uic2msr
-#define UIC0SR uic2sr
-#define UIC1MSR uic2msr
-#define UIC1SR uic2sr
-#else
-#define UIC0MSR uic0msr
-#define UIC0SR uic0sr
-#define UIC1MSR uic1msr
-#define UIC1SR uic1sr
-#endif
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
-#define UICMSR_ETHX uic0msr
-#define UICSR_ETHX uic0sr
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UICMSR_ETHX uic2msr
-#define UICSR_ETHX uic2sr
-#else
-#define UICMSR_ETHX uic1msr
-#define UICSR_ETHX uic1sr
-#endif
-
int enetInt (struct eth_device *dev)
{
int serviced;
int rc = -1; /* default to not us */
- unsigned long mal_isr;
- unsigned long emac_isr = 0;
- unsigned long mal_rx_eob;
- unsigned long my_uic0msr, my_uic1msr;
- unsigned long my_uicmsr_ethx;
-
-#if defined(CONFIG_440GX)
- unsigned long my_uic2msr;
-#endif
+ u32 mal_isr;
+ u32 emac_isr = 0;
+ u32 mal_eob;
+ u32 uic_mal;
+ u32 uic_mal_err;
+ u32 uic_emac;
+ u32 uic_emac_b;
EMAC_4XX_HW_PST hw_p;
/*
@@ -1448,256 +1508,79 @@ int enetInt (struct eth_device *dev)
do {
serviced = 0;
- my_uic0msr = mfdcr (UIC0MSR);
- my_uic1msr = mfdcr (UIC1MSR);
-#if defined(CONFIG_440GX)
- my_uic2msr = mfdcr (uic2msr);
-#endif
- my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
+ uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
+ uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
+ uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
+ uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
- if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
- && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
- && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
- /* not for us */
- return (rc);
- }
-#if defined (CONFIG_440GX)
- if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
- && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
+ if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
+ && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
+ && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
/* not for us */
return (rc);
}
-#endif
+
/* get and clear controller status interrupts */
- /* look at Mal and EMAC interrupts */
- if ((my_uic0msr & (UIC_MRE | UIC_MTE))
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* we have a MAL interrupt */
- mal_isr = mfdcr (malesr);
- /* look for mal error */
- if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
- mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
- serviced = 1;
- rc = 0;
- }
- }
+ /* look at MAL and EMAC error interrupts */
+ if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
+ /* we have a MAL error interrupt */
+ mal_isr = mfdcr(malesr);
+ mal_err(dev, mal_isr, uic_mal_err,
+ MAL_UIC_DEF, MAL_UIC_ERR);
- /* port by port dispatch of emac interrupts */
- if (hw_p->devnum == 0) {
- if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if ((hw_p->emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
- mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
- return (rc); /* we had errors so get out */
- }
- }
+ /* clear MAL error interrupt status bits */
+ mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
+ UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
-#if !defined(CONFIG_440SP)
- if (hw_p->devnum == 1) {
- if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if ((hw_p->emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
- mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
- return (rc); /* we had errors so get out */
- }
- }
-#if defined (CONFIG_440GX)
- if (hw_p->devnum == 2) {
- if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if ((hw_p->emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
- mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- mtdcr (uic2sr, UIC_ETH2);
- return (rc); /* we had errors so get out */
- }
+ return -1;
}
- if (hw_p->devnum == 3) {
- if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if ((hw_p->emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
- mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- mtdcr (uic2sr, UIC_ETH3);
- return (rc); /* we had errors so get out */
- }
- }
-#endif /* CONFIG_440GX */
-#endif /* !CONFIG_440SP */
+ /* look for EMAC errors */
+ if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
+ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
+ emac_err(dev, emac_isr);
- /* handle MAX TX EOB interrupt from a tx */
- if (my_uic0msr & UIC_MTE) {
- mal_rx_eob = mfdcr (maltxeobisr);
- mtdcr (maltxeobisr, mal_rx_eob);
- mtdcr (UIC0SR, UIC_MTE);
- }
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (my_uic0msr & UIC_MRE) {
- mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob &
- (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)))
- != 0) { /* call emac routine for channel x */
- /* clear EOB
- mtdcr(malrxeobisr, mal_rx_eob); */
- enet_rcv (dev, emac_isr);
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
+ /* clear EMAC error interrupt status bits */
+ mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
+ mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
- mtdcr (UIC0SR, UIC_MRE); /* Clear */
- mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- switch (hw_p->devnum) {
- case 0:
- mtdcr (UICSR_ETHX, UIC_ETH0);
- break;
- case 1:
- mtdcr (UICSR_ETHX, UIC_ETH1);
- break;
-#if defined (CONFIG_440GX)
- case 2:
- mtdcr (uic2sr, UIC_ETH2);
- break;
- case 3:
- mtdcr (uic2sr, UIC_ETH3);
- break;
-#endif /* CONFIG_440GX */
- default:
- break;
+ return -1;
}
- } while (serviced);
-
- return (rc);
-}
-
-#else /* CONFIG_440 */
-
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- unsigned long mal_isr;
- unsigned long emac_isr = 0;
- unsigned long mal_rx_eob;
- unsigned long my_uicmsr;
-
- EMAC_4XX_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
-#if defined(CONFIG_NET_MULTI)
- dev = eth_get_dev();
-#else
- dev = emac0_dev;
-#endif
-
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
- my_uicmsr = mfdcr (uicmsr);
-
- if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
- return (rc);
- }
- /* get and clear controller status interrupts */
- /* look at Mal and EMAC interrupts */
- if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
- mal_isr = mfdcr (malesr);
- /* look for mal error */
- if ((my_uicmsr & MAL_UIC_ERR) != 0) {
- mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
- serviced = 1;
- rc = 0;
- }
+ /* handle MAX TX EOB interrupt from a tx */
+ if (uic_mal & UIC_MAL_TXEOB) {
+ /* clear MAL interrupt status bits */
+ mal_eob = mfdcr(maltxeobisr);
+ mtdcr(maltxeobisr, mal_eob);
+ mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
+
+ /* indicate that we serviced an interrupt */
+ serviced = 1;
+ rc = 0;
}
- /* port by port dispatch of emac interrupts */
+ /* handle MAL RX EOB interupt from a receive */
+ /* check for EOB on valid channels */
+ if (uic_mal & UIC_MAL_RXEOB) {
+ mal_eob = mfdcr(malrxeobisr);
+ if (mal_eob &
+ (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
+ /* push packet to upper layer */
+ enet_rcv(dev, emac_isr);
- if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
- mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
- return (rc); /* we had errors so get out */
- }
+ /* clear MAL interrupt status bits */
+ mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
- /* handle MAX TX EOB interrupt from a tx */
- if (my_uicmsr & UIC_MAL_TXEOB) {
- mal_rx_eob = mfdcr (maltxeobisr);
- mtdcr (maltxeobisr, mal_rx_eob);
- mtdcr (uicsr, UIC_MAL_TXEOB);
- }
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (my_uicmsr & UIC_MAL_RXEOB)
- {
- mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
- /* clear EOB
- mtdcr(malrxeobisr, mal_rx_eob); */
- enet_rcv (dev, emac_isr);
/* indicate that we serviced an interrupt */
serviced = 1;
rc = 0;
}
}
- mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
-#if defined(CONFIG_405EZ)
- mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
-#endif /* defined(CONFIG_405EZ) */
- }
- while (serviced);
+ } while (serviced);
return (rc);
}
-#endif /* CONFIG_440 */
-
/*-----------------------------------------------------------------------------+
* MAL Error Routine
*-----------------------------------------------------------------------------*/
@@ -1883,6 +1766,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
EMAC_4XX_HW_PST hw = NULL;
u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
u32 hw_addr[4];
+ u32 mal_ier;
#if defined(CONFIG_440GX)
unsigned long pfc1;
@@ -2020,19 +1904,19 @@ int ppc_4xx_eth_initialize (bd_t * bis)
mtdcr (malier, mal_ier);
/* install MAL interrupt handler */
- irq_install_handler (VECNUM_MS,
+ irq_install_handler (VECNUM_MAL_SERR,
(interrupt_handler_t *) enetInt,
dev);
- irq_install_handler (VECNUM_MTE,
+ irq_install_handler (VECNUM_MAL_TXEOB,
(interrupt_handler_t *) enetInt,
dev);
- irq_install_handler (VECNUM_MRE,
+ irq_install_handler (VECNUM_MAL_RXEOB,
(interrupt_handler_t *) enetInt,
dev);
- irq_install_handler (VECNUM_TXDE,
+ irq_install_handler (VECNUM_MAL_TXDE,
(interrupt_handler_t *) enetInt,
dev);
- irq_install_handler (VECNUM_RXDE,
+ irq_install_handler (VECNUM_MAL_RXDE,
(interrupt_handler_t *) enetInt,
dev);
virgin = 1;
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index a7587d4..766e586 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -46,7 +46,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
-#include <asm/ppc4xx-intvec.h>
+#include <ppc4xx.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 800bb41..c773400 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -35,10 +35,8 @@ SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
-COBJS += 4xx_enet.o
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
-COBJS += 4xx_uart.o
COBJS += bedbug_405.o
COBJS += commproc.o
COBJS += cpu.o
@@ -47,11 +45,9 @@ COBJS += denali_data_eye.o
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
COBJS += fdt.o
-COBJS += gpio.o
COBJS += i2c.o
COBJS += interrupts.o
COBJS += iop480_uart.o
-COBJS += miiphy.o
COBJS += ndfc.o
COBJS += sdram.o
COBJS += speed.o
@@ -60,6 +56,15 @@ COBJS += traps.o
COBJS += usb.o
COBJS += usb_ohci.o
COBJS += usbdev.o
+ifndef CONFIG_XILINX_440
+COBJS += 4xx_enet.o
+COBJS += 4xx_uart.o
+COBJS += gpio.o
+COBJS += miiphy.o
+COBJS += uic.o
+else
+COBJS += xilinx_irq.o
+endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 39f439d..bc9335a 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -184,6 +184,19 @@ static char *bootstrap_str[] = {
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
+#if defined(CONFIG_460SX)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "EBC (8 bits)",
+ "EBC (16 bits)",
+ "EBC (32 bits)",
+ "NAND (8 bits)",
+ "I2C (Addr 0x54)", /* A8 */
+ "I2C (Addr 0x52)", /* A4 */
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
+#endif
+
#if defined(CONFIG_405EZ)
#define SDR0_PINSTP_SHIFT 28
static char *bootstrap_str[] = {
@@ -266,7 +279,11 @@ int checkcpu (void)
get_sys_info(&sys_info);
+#if defined(CONFIG_XILINX_440)
+ puts("IBM PowerPC 4");
+#else
puts("AMCC PowerPC 4");
+#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
@@ -509,6 +526,30 @@ int checkcpu (void)
strcpy(addstr, "Security/Kasumi support");
break;
+ case PVR_460SX_RA:
+ puts("SX Rev. A");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_460SX_RA_V1:
+ puts("SX Rev. A");
+ strcpy(addstr, "No Security support");
+ break;
+
+ case PVR_460GX_RA:
+ puts("GX Rev. A");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_460GX_RA_V1:
+ puts("GX Rev. A");
+ strcpy(addstr, "No Security support");
+ break;
+
+ case PVR_VIRTEX5:
+ puts("x5 VIRTEX5");
+ break;
+
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index ac64279..e2d0402 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -138,9 +138,10 @@ void reconfigure_pll(u32 new_cpu_freq)
void
cpu_init_f (void)
{
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
u32 val;
#endif
+
reconfigure_pll(CFG_PLL_RECONFIG);
#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
@@ -273,6 +274,18 @@ cpu_init_f (void)
reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
+#if defined(CONFIG_440GX)
+ /* Take the GX out of compatibility mode
+ * Travis Sawyer, 9 Mar 2004
+ * NOTE: 440gx user manual inconsistency here
+ * Compatibility mode and Ethernet Clock select are not
+ * correct in the manual
+ */
+ mfsdr(sdr_mfr, val);
+ val &= ~0x10000000;
+ mtsdr(sdr_mfr,val);
+#endif /* CONFIG_440GX */
+
#if defined(CONFIG_460EX)
/*
* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 8620e2b..494bd8c 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -8,6 +8,10 @@
* (C) Copyright 2003 (440GX port)
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
+ * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
+ * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Work supported by Qtechnology (htpp://qtec.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,31 +35,14 @@
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
+#include <asm/interrupt.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
-#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
/*
- * Define the number of UIC's
- */
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UIC_MAX 4
-#elif defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
-#define UIC_MAX 3
-#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define UIC_MAX 2
-#else
-#define UIC_MAX 1
-#endif
-
-/*
* CPM interrupt vector functions.
*/
struct irq_action {
@@ -63,15 +50,7 @@ struct irq_action {
void *arg;
int count;
};
-
-static struct irq_action irq_vecs[UIC_MAX * 32];
-
-u32 get_dcr(u16);
-void set_dcr(u16, u32);
-
-#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
-static void uic_cascade_interrupt(void *para);
-#endif
+static struct irq_action irq_vecs[IRQ_MAX];
#if defined(CONFIG_440)
@@ -112,7 +91,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/*
* Mark all irqs as free
*/
- for (vec = 0; vec < (UIC_MAX * 32); vec++) {
+ for (vec = 0; vec < IRQ_MAX; vec++) {
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
irq_vecs[vec].count = 0;
@@ -156,160 +135,38 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
set_evpr(0x00000000);
-#if !defined(CONFIG_440GX)
-#if (UIC_MAX > 1)
- /* Install the UIC1 handlers */
- irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0);
- irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0);
-#endif
-#if (UIC_MAX > 2)
- irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0);
- irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0);
-#endif
-#if (UIC_MAX > 3)
- irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0);
- irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0);
-#endif
-#else /* !defined(CONFIG_440GX) */
- /* Take the GX out of compatibility mode
- * Travis Sawyer, 9 Mar 2004
- * NOTE: 440gx user manual inconsistency here
- * Compatibility mode and Ethernet Clock select are not
- * correct in the manual
+ /*
+ * Call uic or xilinx_irq pic_enable
*/
- mfsdr(sdr_mfr, val);
- val &= ~0x10000000;
- mtsdr(sdr_mfr,val);
-
- /* Enable UIC interrupts via UIC Base Enable Register */
- mtdcr(uicb0sr, UICB0_ALL);
- mtdcr(uicb0er, 0x54000000);
- /* None are critical */
- mtdcr(uicb0cr, 0);
-#endif /* !defined(CONFIG_440GX) */
+ pic_enable();
return (0);
}
-/* Handler for UIC interrupt */
-static void uic_interrupt(u32 uic_base, int vec_base)
+void timer_interrupt_cpu(struct pt_regs *regs)
{
- u32 uic_msr;
- u32 msr_shift;
- int vec;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = get_dcr(uic_base + UIC_MSR);
- msr_shift = uic_msr;
- vec = vec_base;
-
- while (msr_shift != 0) {
- if (msr_shift & 0x80000000) {
- /*
- * Increment irq counter (for debug purpose only)
- */
- irq_vecs[vec].count++;
-
- if (irq_vecs[vec].handler != NULL) {
- /* call isr */
- (*irq_vecs[vec].handler)(irq_vecs[vec].arg);
- } else {
- set_dcr(uic_base + UIC_ER,
- get_dcr(uic_base + UIC_ER) &
- ~(0x80000000 >> (vec & 0x1f)));
- printf("Masking bogus interrupt vector %d"
- " (UIC_BASE=0x%x)\n", vec, uic_base);
- }
-
- /*
- * After servicing the interrupt, we have to remove the
- * status indicator
- */
- set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f)));
- }
-
- /*
- * Shift msr to next position and increment vector
- */
- msr_shift <<= 1;
- vec++;
- }
+ /* nothing to do here */
+ return;
}
-#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
-static void uic_cascade_interrupt(void *para)
+void interrupt_run_handler(int vec)
{
- external_interrupt(para);
-}
-#endif
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_440GX)
-/* 440GX uses base uic register */
-#define UIC_BMSR uicb0msr
-#define UIC_BSR uicb0sr
-#else
-#define UIC_BMSR uic0msr
-#define UIC_BSR uic0sr
-#endif
-#else /* CONFIG_440 */
-#define UIC_BMSR uicmsr
-#define UIC_BSR uicsr
-#endif /* CONFIG_440 */
-
-/*
- * Handle external interrupts
- */
-void external_interrupt(struct pt_regs *regs)
-{
- u32 uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = mfdcr(UIC_BMSR);
-
-#if (UIC_MAX > 1)
- if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr))
- uic_interrupt(UIC1_DCR_BASE, 32);
-#endif
-
-#if (UIC_MAX > 2)
- if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr))
- uic_interrupt(UIC2_DCR_BASE, 64);
-#endif
-
-#if (UIC_MAX > 3)
- if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr))
- uic_interrupt(UIC3_DCR_BASE, 96);
-#endif
-
-#if defined(CONFIG_440)
-#if !defined(CONFIG_440GX)
- if (uic_msr & ~(UICB0_ALL))
- uic_interrupt(UIC0_DCR_BASE, 0);
-#else
- if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr))
- uic_interrupt(UIC0_DCR_BASE, 0);
-#endif
-#else /* CONFIG_440 */
- uic_interrupt(UIC0_DCR_BASE, 0);
-#endif /* CONFIG_440 */
-
- mtdcr(UIC_BSR, uic_msr);
+ irq_vecs[vec].count++;
+
+ if (irq_vecs[vec].handler != NULL) {
+ /* call isr */
+ (*irq_vecs[vec].handler) (irq_vecs[vec].arg);
+ } else {
+ pic_irq_disable(vec);
+ printf("Masking bogus interrupt vector %d\n", vec);
+ }
+ pic_irq_ack(vec);
return;
}
-/*
- * Install and free a interrupt handler.
- */
void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
{
- int i;
-
/*
* Print warning when replacing with a different irq vector
*/
@@ -320,55 +177,19 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
irq_vecs[vec].handler = handler;
irq_vecs[vec].arg = arg;
- i = vec & 0x1f;
- if ((vec >= 0) && (vec < 32))
- mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
-#if (UIC_MAX > 1)
- else if ((vec >= 32) && (vec < 64))
- mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
-#endif
-#if (UIC_MAX > 2)
- else if ((vec >= 64) && (vec < 96))
- mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i));
-#endif
-#if (UIC_MAX > 3)
- else if (vec >= 96)
- mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i));
-#endif
-
- debug("Install interrupt for vector %d ==> %p\n", vec, handler);
+ pic_irq_enable(vec);
+ return;
}
-void irq_free_handler (int vec)
+void irq_free_handler(int vec)
{
- int i;
-
debug("Free interrupt for vector %d ==> %p\n",
vec, irq_vecs[vec].handler);
- i = vec & 0x1f;
- if ((vec >= 0) && (vec < 32))
- mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
-#if (UIC_MAX > 1)
- else if ((vec >= 32) && (vec < 64))
- mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
-#endif
-#if (UIC_MAX > 2)
- else if ((vec >= 64) && (vec < 96))
- mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i));
-#endif
-#if (UIC_MAX > 3)
- else if (vec >= 96)
- mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i));
-#endif
+ pic_irq_disable(vec);
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
-}
-
-void timer_interrupt_cpu (struct pt_regs *regs)
-{
- /* nothing to do here */
return;
}
@@ -380,7 +201,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("Interrupt-Information:\n");
printf ("Nr Routine Arg Count\n");
- for (vec = 0; vec < (UIC_MAX * 32); vec++) {
+ for (vec = 0; vec < IRQ_MAX; vec++) {
if (irq_vecs[vec].handler != NULL) {
printf ("%02d %08lx %08lx %d\n",
vec,
diff --git a/cpu/ppc4xx/iop480_uart.c b/cpu/ppc4xx/iop480_uart.c
index 3af0767..0e3423f 100644
--- a/cpu/ppc4xx/iop480_uart.c
+++ b/cpu/ppc4xx/iop480_uart.c
@@ -26,7 +26,6 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
-#include <asm/ppc4xx-intvec.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 4f083d9..72acfd0 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -31,7 +31,7 @@
#include <common.h>
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
+#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 34bd721..d21bd82 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -205,7 +205,8 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
static u8 pll_fwdv_multi_bits[] = {
/* values for: 1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -415,7 +416,8 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
-#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \
+ && !defined(CONFIG_XILINX_440)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
@@ -448,6 +450,8 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqUART = sysInfo->freqPLB;
}
#else
+
+#if !defined(CONFIG_XILINX_440)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
@@ -534,6 +538,7 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
+#endif /* CONFIG_XILINX_440 */
#if defined(CONFIG_YUCCA)
unsigned long determine_sysper(void)
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 426bf3c..97411bd 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -677,7 +677,8 @@ _start:
/* not all PPC's have internal SRAM usable as L2-cache */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
@@ -720,6 +721,19 @@ _start:
lis r1,0x4000 /* BAS = 8000_0000 */
ori r1,r1,0x4580 /* 16k */
mtdcr isram0_sb0cr,r1
+#elif defined(CONFIG_460SX)
+ lis r1,0x0000 /* BAS = 0000_0000 */
+ ori r1,r1,0x0B84 /* first 128k */
+ mtdcr isram0_sb0cr,r1
+ lis r1,0x0001
+ ori r1,r1,0x0B84 /* second 128k */
+ mtdcr isram0_sb1cr,r1
+ lis r1, 0x0002
+ ori r1,r1, 0x0B84 /* third 128k */
+ mtdcr isram0_sb2cr,r1
+ lis r1, 0x0003
+ ori r1,r1, 0x0B84 /* fourth 128k */
+ mtdcr isram0_sb3cr,r1
#elif defined(CONFIG_440GP)
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
@@ -1415,7 +1429,8 @@ relocate_code:
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
/*
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
* to speed up the boot process. Now this cache needs to be disabled.
diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c
new file mode 100644
index 0000000..7944c6c
--- /dev/null
+++ b/cpu/ppc4xx/uic.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 (440 port)
+ * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
+ *
+ * (C) Copyright 2003 (440GX port)
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
+ * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Work supported by Qtechnology (htpp://qtec.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/interrupt.h>
+#include <ppc4xx.h>
+#include <ppc_asm.tmpl>
+#include <commproc.h>
+
+#if (UIC_MAX > 3)
+#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
+ UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
+ UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
+#elif (UIC_MAX > 2)
+#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
+ UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
+#elif (UIC_MAX > 1)
+#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
+#else
+#define UICB0_ALL 0
+#endif
+
+u32 get_dcr(u16);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void pic_enable(void)
+{
+#if (UIC_MAX > 1)
+ /* Install the UIC1 handlers */
+ irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
+ irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
+#endif
+#if (UIC_MAX > 2)
+ irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
+ irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
+#endif
+#if (UIC_MAX > 3)
+ irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
+ irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
+#endif
+}
+
+/* Handler for UIC interrupt */
+static void uic_interrupt(u32 uic_base, int vec_base)
+{
+ u32 uic_msr;
+ u32 msr_shift;
+ int vec;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ uic_msr = get_dcr(uic_base + UIC_MSR);
+ msr_shift = uic_msr;
+ vec = vec_base;
+
+ while (msr_shift != 0) {
+ if (msr_shift & 0x80000000)
+ interrupt_run_handler(vec);
+ /*
+ * Shift msr to next position and increment vector
+ */
+ msr_shift <<= 1;
+ vec++;
+ }
+}
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
+{
+ u32 uic_msr;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ uic_msr = mfdcr(uic0msr);
+
+#if (UIC_MAX > 1)
+ if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
+ (UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
+ uic_interrupt(UIC1_DCR_BASE, 32);
+#endif
+
+#if (UIC_MAX > 2)
+ if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
+ (UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
+ uic_interrupt(UIC2_DCR_BASE, 64);
+#endif
+
+#if (UIC_MAX > 3)
+ if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
+ (UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
+ uic_interrupt(UIC3_DCR_BASE, 96);
+#endif
+
+ if (uic_msr & ~(UICB0_ALL))
+ uic_interrupt(UIC0_DCR_BASE, 0);
+
+ mtdcr(uic0sr, uic_msr);
+
+ return;
+}
+
+void pic_irq_ack(unsigned int vec)
+{
+ if ((vec >= 0) && (vec < 32))
+ mtdcr(uicsr, UIC_MASK(vec));
+ else if ((vec >= 32) && (vec < 64))
+ mtdcr(uic1sr, UIC_MASK(vec));
+ else if ((vec >= 64) && (vec < 96))
+ mtdcr(uic2sr, UIC_MASK(vec));
+ else if (vec >= 96)
+ mtdcr(uic3sr, UIC_MASK(vec));
+}
+
+/*
+ * Install and free a interrupt handler.
+ */
+void pic_irq_enable(unsigned int vec)
+{
+
+ if ((vec >= 0) && (vec < 32))
+ mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
+ else if ((vec >= 32) && (vec < 64))
+ mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
+ else if ((vec >= 64) && (vec < 96))
+ mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
+ else if (vec >= 96)
+ mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
+
+ debug("Install interrupt for vector %d ==> %p\n", vec, handler);
+}
+
+void pic_irq_disable(unsigned int vec)
+{
+ if ((vec >= 0) && (vec < 32))
+ mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
+ else if ((vec >= 32) && (vec < 64))
+ mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
+ else if ((vec >= 64) && (vec < 96))
+ mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
+ else if (vec >= 96)
+ mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
+}
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index d71ba77..faf7f08 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -6,8 +6,8 @@
#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && defined(CONFIG_CMD_USB)
#include <usb.h>
+#include <asm/ppc4xx-uic.h>
#include "usbdev.h"
-#include <asm/ppc4xx-intvec.h>
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
@@ -197,7 +197,7 @@ void usb_dev_init()
/*enable interrupts */
*(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
- irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt,
+ irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
NULL);
}
#else
diff --git a/cpu/ppc4xx/xilinx_irq.c b/cpu/ppc4xx/xilinx_irq.c
new file mode 100644
index 0000000..7108777
--- /dev/null
+++ b/cpu/ppc4xx/xilinx_irq.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/interrupt.h>
+#include <ppc4xx.h>
+#include <ppc_asm.tmpl>
+#include <commproc.h>
+#include <asm/io.h>
+#include <asm/xilinx_irq.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void pic_enable(void)
+{
+ debug("Xilinx PIC at 0x%8x\n", intc);
+
+ /*
+ * Disable all external interrupts until they are
+ * explicitly requested.
+ */
+ out_be32((u32 *) IER, 0);
+
+ /* Acknowledge any pending interrupts just in case. */
+ out_be32((u32 *) IAR, 0xffffffff);
+
+ /* Turn on the Master Enable. */
+ out_be32((u32 *) MER, 0x3UL);
+
+ return;
+}
+
+int xilinx_pic_irq_get(void)
+{
+ u32 irq;
+ irq = in_be32((u32 *) IVR);
+
+ /* If no interrupt is pending then all bits of the IVR are set to 1. As
+ * the IVR is as many bits wide as numbers of inputs are available.
+ * Therefore, if all bits of the IVR are set to one, its content will
+ * be bigger than XPAR_INTC_MAX_NUM_INTR_INPUTS.
+ */
+ if (irq >= XPAR_INTC_MAX_NUM_INTR_INPUTS)
+ irq = -1; /* report no pending interrupt. */
+
+ debug("get_irq: %d\n", irq);
+ return (irq);
+}
+
+void pic_irq_enable(unsigned int irq)
+{
+ u32 mask = IRQ_MASK(irq);
+ debug("enable: %d\n", irq);
+ out_be32((u32 *) SIE, mask);
+}
+
+void pic_irq_disable(unsigned int irq)
+{
+ u32 mask = IRQ_MASK(irq);
+ debug("disable: %d\n", irq);
+ out_be32((u32 *) CIE, mask);
+}
+
+void pic_irq_ack(unsigned int irq)
+{
+ u32 mask = IRQ_MASK(irq);
+ debug("ack: %d\n", irq);
+ out_be32((u32 *) IAR, mask);
+}
+
+void external_interrupt(struct pt_regs *regs)
+{
+ int irq;
+
+ irq = xilinx_pic_irq_get();
+ if (irq < 0)
+ return;
+
+ interrupt_run_handler(irq);
+
+ return;
+}
diff --git a/doc/README.nand b/doc/README.nand
index 0ad5e18..171380e 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -184,7 +184,7 @@ We now use a complete rewrite of the NAND code based on what is in
The old NAND handling code has been re-factored and is now confined
to only board-specific files and - unfortunately - to the DoC code
(see below). A new configuration variable has been introduced:
-CFG_NAND_LEGACY, which has to be defined in the board config file if
+CONFIG_NAND_LEGACY, which has to be defined in the board config file if
that board uses legacy code.
The necessary changes have been made to all affected boards, and no
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index a09cd2a..642582b 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -25,14 +25,14 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libblock.a
-COBJS-y += ahci.o
-COBJS-y += ata_piix.o
+COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
+COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
COBJS-$(CONFIG_LIBATA) += libata.o
COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
-COBJS-y += sil680.o
-COBJS-y += sym53c8xx.o
-COBJS-y += systemace.o
+COBJS-$(CONFIG_IDE_SIL680) += sil680.o
+COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
+COBJS-$(CONFIG_SYSTEMACE) += systemace.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 3d82c62..52fd108 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -26,8 +26,6 @@
*/
#include <common.h>
-#ifdef CONFIG_SCSI_AHCI
-
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
@@ -700,4 +698,3 @@ void scsi_print_error(ccb * pccb)
{
/*The ahci error info can be read in the ahci driver*/
}
-#endif
diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c
index 441a4dc..4c26b36 100644
--- a/drivers/block/ata_piix.c
+++ b/drivers/block/ata_piix.c
@@ -35,8 +35,6 @@
#include <ide.h>
#include <ata.h>
-#ifdef CFG_ATA_PIIX /*ata_piix driver */
-
extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE];
extern int curr_device;
@@ -756,5 +754,3 @@ int scan_sata(int dev)
{
return 0;
}
-
-#endif
diff --git a/drivers/block/sil680.c b/drivers/block/sil680.c
index a6143df..052c3d3 100644
--- a/drivers/block/sil680.c
+++ b/drivers/block/sil680.c
@@ -27,7 +27,7 @@
* The following parameters must be defined in the configuration file
* of the target board:
*
- * #define CFG_IDE_SIL680
+ * #define CONFIG_IDE_SIL680
*
* #define CONFIG_PCI_PNP
* NOTE it may also be necessary to define this if the default of 8 is
@@ -54,7 +54,6 @@
*/
#include <common.h>
-#if defined(CFG_IDE_SIL680)
#include <ata.h>
#include <ide.h>
#include <pci.h>
@@ -106,5 +105,3 @@ int ide_preinit (void)
void ide_set_reset (int flag) {
return;
}
-
-#endif /* CFG_IDE_SIL680 */
diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index b880435..44e998b 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -35,8 +35,6 @@
#include <common.h>
-#ifdef CONFIG_SCSI_SYM53C8XX
-
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
@@ -870,6 +868,3 @@ void scsi_chip_init(void)
#endif
}
#endif
-
-
-#endif /* CONFIG_SCSI_SYM53C8XX */
diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 7d82c27..dfaab52 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -44,8 +44,6 @@
#include <part.h>
#include <asm/io.h>
-#ifdef CONFIG_SYSTEMACE
-
/*
* The ace_readw and writew functions read/write 16bit words, but the
* offset value is the BYTE offset as most used in the Xilinx
@@ -255,4 +253,3 @@ static unsigned long systemace_read(int dev, unsigned long start,
return blkcnt;
}
-#endif /* CONFIG_SYSTEMACE */
diff --git a/drivers/dma/MCD_dmaApi.c b/drivers/dma/MCD_dmaApi.c
index b0062b7..5c95651 100644
--- a/drivers/dma/MCD_dmaApi.c
+++ b/drivers/dma/MCD_dmaApi.c
@@ -24,8 +24,6 @@
#include <common.h>
-#ifdef CONFIG_FSLDMAFEC
-
#include <MCD_dma.h>
#include <MCD_tasksInit.h>
#include <MCD_progCheck.h>
@@ -1023,4 +1021,3 @@ static void MCD_memcpy(int *dest, int *src, u32 size)
for (i = 0; i < size; i += sizeof(int), dest++, src++)
*dest = *src;
}
-#endif /* CONFIG_FSLDMAFEC */
diff --git a/drivers/dma/MCD_tasks.c b/drivers/dma/MCD_tasks.c
index 06a2d53..4f6e346 100644
--- a/drivers/dma/MCD_tasks.c
+++ b/drivers/dma/MCD_tasks.c
@@ -24,8 +24,6 @@
#include <common.h>
-#ifdef CONFIG_FSLDMAFEC
-
#include <MCD_dma.h>
u32 MCD_varTab0[];
@@ -2430,5 +2428,3 @@ u32 MCD_ENetXmit_TDT[] = {
#ifdef MCD_INCLUDE_EU
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#endif
-
-#endif /* CONFIG_FSLDMAFEC */
diff --git a/drivers/dma/MCD_tasksInit.c b/drivers/dma/MCD_tasksInit.c
index cf567db..2f19875 100644
--- a/drivers/dma/MCD_tasksInit.c
+++ b/drivers/dma/MCD_tasksInit.c
@@ -28,8 +28,6 @@
* Do not edit!
*/
-#ifdef CONFIG_FSLDMAFEC
-
#include <MCD_dma.h>
extern dmaRegs *MCD_dmaBar;
@@ -242,5 +240,3 @@ void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
-
-#endif /* CONFIG_FSLDMAFEC */
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7e17360..cf29efa 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libdma.a
-COBJS-y += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
+COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 2933cb6..9a14407 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -25,9 +25,11 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libinput.a
-COBJS-y += i8042.o
-COBJS-y += keyboard.o
-COBJS-y += pc_keyb.o ps2ser.o ps2mult.o
+COBJS-$(CONFIG_I8042_KBD) += i8042.o
+ifdef CONFIG_PS2KBD
+COBJS-y += keyboard.o pc_keyb.o
+COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
+endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 22c2a4e..d152768 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -27,8 +27,6 @@
#include <common.h>
-#ifdef CONFIG_I8042_KBD
-
#ifdef CONFIG_USE_CPCIDVI
extern u8 gt_cpcidvi_in8(u32 offset);
extern void gt_cpcidvi_out8(u32 offset, u8 data);
@@ -670,5 +668,3 @@ static int kbd_reset (void)
return 0;
}
-
-#endif /* CONFIG_I8042_KBD */
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index 54182a7..a634d76 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -11,8 +11,6 @@
#include <common.h>
-#ifdef CONFIG_PS2KBD
-
#include <devices.h>
#include <keyboard.h>
@@ -301,5 +299,3 @@ int kbd_init (void)
}
return error;
}
-
-#endif /* CONFIG_PS2KBD */
diff --git a/drivers/input/pc_keyb.c b/drivers/input/pc_keyb.c
index 33e7c5f..25ad3e4 100644
--- a/drivers/input/pc_keyb.c
+++ b/drivers/input/pc_keyb.c
@@ -13,8 +13,6 @@
#include <common.h>
-#ifdef CONFIG_PS2KBD
-
#include <keyboard.h>
#include <pc_keyb.h>
@@ -252,5 +250,3 @@ void pckbd_leds(unsigned char leds)
kbd_send_data(KBD_CMD_SET_LEDS);
kbd_send_data(leds);
}
-
-#endif /* CONFIG_PS2KBD */
diff --git a/drivers/input/ps2mult.c b/drivers/input/ps2mult.c
index 9515a0f..ecd5853 100644
--- a/drivers/input/ps2mult.c
+++ b/drivers/input/ps2mult.c
@@ -16,8 +16,6 @@
#include <common.h>
-#ifdef CONFIG_PS2MULT
-
#include <pc_keyb.h>
#include <asm/atomic.h>
#include <ps2mult.h>
@@ -462,5 +460,3 @@ int ps2mult_request_irq(void (*handler)(void *))
return 0;
}
-
-#endif /* CONFIG_PS2MULT */
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index c1741ea..480ffa2 100644
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
@@ -15,8 +15,6 @@
#include <common.h>
-#ifdef CONFIG_PS2SERIAL
-
#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
@@ -326,5 +324,3 @@ static void ps2ser_interrupt(void *dev_id)
ps2mult_callback(atomic_read(&ps2buf_cnt));
}
}
-
-#endif /* CONFIG_PS2SERIAL */
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index fe8d3d8..01e0f39 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -25,10 +25,10 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmisc.a
-COBJS-y += ali512x.o
-COBJS-y += ns87308.o
-COBJS-y += status_led.o
+COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
+COBJS-$(CONFIG_NS87308) += ns87308.o
+COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/misc/ali512x.c b/drivers/misc/ali512x.c
index 90b45d9..d6a2c1f 100644
--- a/drivers/misc/ali512x.c
+++ b/drivers/misc/ali512x.c
@@ -32,8 +32,6 @@
#include <config.h>
-#ifdef CONFIG_ALI152X
-
#include <common.h>
#include <asm/io.h>
#include <asm/ic/ali512x.h>
@@ -418,6 +416,3 @@ int ali512x_cio_in(int pin)
return data & bit;
}
-
-
-#endif
diff --git a/drivers/misc/ns87308.c b/drivers/misc/ns87308.c
index cf4d359..6642c2e 100644
--- a/drivers/misc/ns87308.c
+++ b/drivers/misc/ns87308.c
@@ -23,8 +23,6 @@
#include <config.h>
-#ifdef CFG_NS87308
-
#include <ns87308.h>
void initialise_ns87308 (void)
@@ -117,5 +115,3 @@ void initialise_ns87308 (void)
PNP_PGCS_CSLINE_CONF(2, CFG_NS87308_CS2_CONF);
#endif
}
-
-#endif
diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c
index ddb6c22..4ba3e18 100644
--- a/drivers/misc/status_led.c
+++ b/drivers/misc/status_led.c
@@ -35,8 +35,6 @@
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_STATUS_LED
-
typedef struct {
led_id_t mask;
int state;
@@ -127,5 +125,3 @@ void status_led_set (int led, int state)
}
__led_set (ld->mask, state);
}
-
-#endif /* CONFIG_STATUS_LED */
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index ff932a1..6538f7a 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -25,11 +25,11 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmtd.a
-COBJS-y += at45.o
-COBJS-y += cfi_flash.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
+COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
-COBJS-y += mw_eeprom.o
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
+COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mtd/at45.c b/drivers/mtd/at45.c
index a9d13ff..d1a60aa 100644
--- a/drivers/mtd/at45.c
+++ b/drivers/mtd/at45.c
@@ -20,8 +20,6 @@
#include <config.h>
#include <common.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
/*
@@ -559,4 +557,3 @@ int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
AT91F_DataFlashGetStatus(pDesc);
return ((pDesc->command[1] == 0xFF) ? 0 : pDesc->command[1] & 0x3C);
}
-#endif
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 479075c..402d835 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -39,7 +39,6 @@
#include <asm/io.h>
#include <asm/byteorder.h>
#include <environment.h>
-#ifdef CFG_FLASH_CFI_DRIVER
/*
* This file implements a Common Flash Interface (CFI) driver for
@@ -2015,5 +2014,3 @@ unsigned long flash_init (void)
#endif
return (size);
}
-
-#endif /* CFG_FLASH_CFI */
diff --git a/drivers/mtd/mw_eeprom.c b/drivers/mtd/mw_eeprom.c
index 2b33488..f32ced4 100644
--- a/drivers/mtd/mw_eeprom.c
+++ b/drivers/mtd/mw_eeprom.c
@@ -1,9 +1,6 @@
/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */
#include <common.h>
-
-#ifdef CONFIG_MW_EEPROM
-
#include <ssi.h>
/*
@@ -237,5 +234,3 @@ int mw_eeprom_probe(int dev)
}
return 0;
}
-
-#endif
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index ffb3169..1923310 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -25,15 +25,19 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libnand.a
+ifdef CONFIG_CMD_NAND
+ifndef CONFIG_NAND_LEGACY
COBJS-y += nand.o
COBJS-y += nand_base.o
-COBJS-y += nand_ids.o
-COBJS-y += nand_ecc.o
COBJS-y += nand_bbt.o
+COBJS-y += nand_ecc.o
+COBJS-y += nand_ids.o
COBJS-y += nand_util.o
+endif
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
-COBJS-y += fsl_upm.o
+COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index ce197f5..4cba810 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -21,7 +21,7 @@
#include <common.h>
-#if !defined(CFG_NAND_LEGACY)
+#if !defined(CONFIG_NAND_LEGACY)
#include <linux/kernel.h>
#include <linux/init.h>
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index e651903..1a1d8c4 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -11,8 +11,6 @@
*/
#include <config.h>
-
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM)
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
@@ -150,4 +148,3 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
return 0;
}
-#endif /* CONFIG_CMD_NAND */
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index e44470e..ebd2acd 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -22,9 +22,6 @@
*/
#include <common.h>
-
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
#include <nand.h>
#ifndef CFG_NAND_BASE_LIST
@@ -79,5 +76,3 @@ void nand_init(void)
board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
#endif
}
-
-#endif
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index a29ff11..0913bb8 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -59,8 +59,6 @@
#define ENOTSUPP 524 /* Operation is not supported */
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
#include <malloc.h>
#include <watchdog.h>
#include <linux/err.h>
@@ -2822,6 +2820,3 @@ MODULE_LICENSE("GPL");
MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
MODULE_DESCRIPTION("Generic NAND flash driver code");
#endif
-
-#endif
-
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 8447947..b3b740d 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -53,9 +53,6 @@
*/
#include <common.h>
-
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
#include <malloc.h>
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
@@ -1237,5 +1234,3 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
EXPORT_SYMBOL(nand_scan_bbt);
EXPORT_SYMBOL(nand_default_bbt);
#endif
-
-#endif
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index e1d5154..ee1f6cc 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -39,8 +39,6 @@
#include <common.h>
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
/* XXX U-BOOT XXX */
#if 0
#include <linux/types.h>
@@ -215,5 +213,3 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat,
#if 0
EXPORT_SYMBOL(nand_correct_data);
#endif
-
-#endif
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index f8b96cf..2ff75c9 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -12,9 +12,6 @@
*/
#include <common.h>
-
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
#include <linux/mtd/nand.h>
/*
* Chip ID list
@@ -147,4 +144,3 @@ struct nand_manufacturers nand_manuf_ids[] = {
{NAND_MFR_MICRON, "Micron"},
{0x0, "Unknown"}
};
-#endif
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 02fe914..22820d5 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -31,9 +31,6 @@
*/
#include <common.h>
-
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
#include <command.h>
#include <watchdog.h>
#include <malloc.h>
@@ -606,5 +603,3 @@ int nand_read_skip_bad(nand_info_t *nand, size_t offset, size_t *length,
return 0;
}
-
-#endif /* defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */
diff --git a/drivers/mtd/nand_legacy/Makefile b/drivers/mtd/nand_legacy/Makefile
index 4e29c36..a1a9cc9 100644
--- a/drivers/mtd/nand_legacy/Makefile
+++ b/drivers/mtd/nand_legacy/Makefile
@@ -25,8 +25,11 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libnand_legacy.a
-COBJS := nand_legacy.o
+ifdef CONFIG_CMD_NAND
+COBJS-$(CONFIG_NAND_LEGACY) := nand_legacy.o
+endif
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/mtd/nand_legacy/nand_legacy.c b/drivers/mtd/nand_legacy/nand_legacy.c
index fafefad..bf5565a 100644
--- a/drivers/mtd/nand_legacy/nand_legacy.c
+++ b/drivers/mtd/nand_legacy/nand_legacy.c
@@ -14,9 +14,6 @@
#include <malloc.h>
#include <asm/io.h>
#include <watchdog.h>
-
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
-
#include <linux/mtd/nand_legacy.h>
#include <linux/mtd/nand_ids.h>
#include <jffs2/jffs2.h>
@@ -1608,5 +1605,3 @@ int read_jffs2_nand(size_t start, size_t len,
start, len, retlen, buf);
}
#endif /* CONFIG_JFFS2_NAND */
-
-#endif
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
index 92074b2..1d35a57 100644
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -25,8 +25,9 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libonenand.a
-COBJS := onenand_uboot.o onenand_base.o onenand_bbt.o
+COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index eaa48f9..8f12fa2 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -10,9 +10,6 @@
*/
#include <common.h>
-
-#ifdef CONFIG_CMD_ONENAND
-
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
@@ -1361,5 +1358,3 @@ int onenand_scan(struct mtd_info *mtd, int maxchips)
void onenand_release(struct mtd_info *mtd)
{
}
-
-#endif /* CONFIG_CMD_ONENAND */
diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
index 318d877..d13d277 100644
--- a/drivers/mtd/onenand/onenand_bbt.c
+++ b/drivers/mtd/onenand/onenand_bbt.c
@@ -15,9 +15,6 @@
*/
#include <common.h>
-
-#ifdef CONFIG_CMD_ONENAND
-
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
@@ -261,5 +258,3 @@ int onenand_default_bbt(struct mtd_info *mtd)
return onenand_scan_bbt(mtd, bbm->badblock_pattern);
}
-
-#endif /* CFG_CMD_ONENAND */
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index bd7466a..d614450 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -14,9 +14,6 @@
*/
#include <common.h>
-
-#ifdef CONFIG_CMD_ONENAND
-
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
@@ -37,5 +34,3 @@ void onenand_init(void)
puts("OneNAND: ");
print_size(onenand_mtd.size, "\n");
}
-
-#endif /* CONFIG_CMD_ONENAND */
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index dec93b9..bffb1eb 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -25,15 +25,13 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libpci.a
-COBJS-y += fsl_pci_init.o
-COBJS-y += pci.o
-COBJS-y += pci_auto.o
-COBJS-y += pci_indirect.o
-COBJS-y += tsi108_pci.o
-COBJS-y += w83c553f.o
+COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
+COBJS-$(CONFIG_PCI) += pci.o pci_auto.o pci_indirect.o
COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
+COBJS-$(CONFIG_TSI108_PCI) += tsi108_pci.o
+COBJS-$(CONFIG_WINBOND_83C553) += w83c553f.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index a7afa90..bb2813f 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -18,8 +18,6 @@
#include <common.h>
-#ifdef CONFIG_FSL_PCI_INIT
-
/*
* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
*
@@ -197,5 +195,3 @@ fsl_pci_init(struct pci_controller *hose)
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
-
-#endif /* CONFIG_FSL_PCI */
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 16180cb..b5eea89 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -30,8 +30,6 @@
#include <common.h>
-#ifdef CONFIG_PCI
-
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
@@ -544,5 +542,3 @@ void pci_init(void)
/* now call board specific pci_init()... */
pci_init_board();
}
-
-#endif /* CONFIG_PCI */
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index eb69593..2acf9bf 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -15,8 +15,6 @@
#include <common.h>
-#ifdef CONFIG_PCI
-
#include <pci.h>
#undef DEBUG
@@ -408,5 +406,3 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
return sub_bus;
}
-
-#endif /* CONFIG_PCI */
diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c
index 55517a8..ab51f8d 100644
--- a/drivers/pci/pci_indirect.c
+++ b/drivers/pci/pci_indirect.c
@@ -11,7 +11,6 @@
#include <common.h>
-#ifdef CONFIG_PCI
#if (!defined(__I386__) && !defined(CONFIG_IXDP425))
#include <asm/processor.h>
@@ -135,4 +134,3 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
}
#endif /* !__I386__ && !CONFIG_IXDP425 */
-#endif /* CONFIG_PCI */
diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c
index 4f02cb8..edd614f 100644
--- a/drivers/pci/tsi108_pci.c
+++ b/drivers/pci/tsi108_pci.c
@@ -27,8 +27,6 @@
#include <config.h>
-#ifdef CONFIG_TSI108_PCI
-
#include <common.h>
#include <pci.h>
#include <asm/io.h>
@@ -182,5 +180,3 @@ void ft_pci_setup(void *blob, bd_t *bd)
}
}
#endif /* CONFIG_OF_LIBFDT */
-
-#endif /* CONFIG_TSI108_PCI */
diff --git a/drivers/pci/w83c553f.c b/drivers/pci/w83c553f.c
index 9ea08a2..d7355a4 100644
--- a/drivers/pci/w83c553f.c
+++ b/drivers/pci/w83c553f.c
@@ -30,8 +30,6 @@
#include <common.h>
#include <config.h>
-#ifdef CFG_WINBOND_83C553
-
#include <asm/io.h>
#include <pci.h>
@@ -222,5 +220,3 @@ void initialise_dma(void)
out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
}
-
-#endif /* CFG_WINBOND_83C553 */
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 45a2fff..18fe9ce 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -25,8 +25,9 @@ include $(TOPDIR)/config.mk
LIB := $(obj)qe.a
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS := qe.o uccf.o uec.o uec_phy.o $(COBJS-y)
+COBJS-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7b6ecd7..e914d01 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -27,7 +27,6 @@
#include "asm/immap_qe.h"
#include "qe.h"
-#if defined(CONFIG_QE)
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
@@ -466,5 +465,3 @@ U_BOOT_CMD(
"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
"the QE,\n\twith optional length <length> verification.\n"
);
-
-#endif /* CONFIG_QE */
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index 4a327ab..7f6337b 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c
@@ -28,7 +28,6 @@
#include "qe.h"
#include "uccf.h"
-#if defined(CONFIG_QE)
void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
{
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
@@ -401,4 +400,3 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
*uccf_ret = uccf;
return 0;
}
-#endif /* CONFIG_QE */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index ba89247..344c649 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -31,8 +31,6 @@
#include "uec_phy.h"
#include "miiphy.h"
-#if defined(CONFIG_QE)
-
#ifdef CONFIG_UEC_ETH1
static uec_info_t eth1_uec_info = {
.uf_info = {
@@ -1406,6 +1404,3 @@ int uec_initialize(int index)
return 1;
}
-
-
-#endif /* CONFIG_QE */
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 423ba78..186922e 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -26,8 +26,6 @@
#include "uec_phy.h"
#include "miiphy.h"
-#if defined(CONFIG_QE)
-
#define ugphy_printk(format, arg...) \
printf(format "\n", ## arg)
@@ -677,4 +675,3 @@ void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
marvell_phy_interface_mode (dev, mode);
#endif
}
-#endif /* CONFIG_QE */
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index de6fbab..2384735 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -27,7 +27,7 @@ LIB := $(obj)libserial.a
COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
COBJS-$(CONFIG_MCFUART) += mcfuart.o
-COBJS-y += ns9750_serial.o
+COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
COBJS-y += ns16550.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-y += serial.o
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-y += serial_pl010.o
COBJS-y += serial_pl011.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
-COBJS-y += serial_sh.o
+COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_USB_TTY) += usbtty.o
COBJS := $(COBJS-y)
diff --git a/drivers/serial/ns9750_serial.c b/drivers/serial/ns9750_serial.c
index 02c0d39..e9645a0 100644
--- a/drivers/serial/ns9750_serial.c
+++ b/drivers/serial/ns9750_serial.c
@@ -28,8 +28,6 @@
#include <common.h>
-#ifdef CFG_NS9750_UART
-
#include "ns9750_bbus.h" /* for GPIOs */
#include "ns9750_ser.h" /* for serial configuration */
@@ -210,5 +208,3 @@ static unsigned int calcRxCharGapRegister( void )
{
return NS9750_SER_RX_CHAR_TIMER_TRUN;
}
-
-#endif /* CFG_NS9750_UART */
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 8bbfcf9..b361eef 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -26,7 +26,7 @@
#ifdef CFG_NS16550_SERIAL
#include <ns16550.h>
-#ifdef CFG_NS87308
+#ifdef CONFIG_NS87308
#include <ns87308.h>
#endif
@@ -159,7 +159,7 @@ int serial_init (void)
{
int clock_divisor;
-#ifdef CFG_NS87308
+#ifdef CONFIG_NS87308
initialise_ns87308();
#endif
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 0801ac4..2b9eeed 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -20,8 +20,6 @@
#include <common.h>
#include <asm/processor.h>
-#ifdef CFG_SCIF_CONSOLE
-
#if defined (CONFIG_CONS_SCIF0)
#define SCIF_BASE SCIF0_BASE
#elif defined (CONFIG_CONS_SCIF1)
@@ -215,5 +213,3 @@ int serial_getc(void)
return ch;
}
-
-#endif /* CFG_SCIF_CONSOLE */
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index 8a06777..b5e7ab8 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -146,7 +146,7 @@ static struct part_info *current_part;
#if (defined(CONFIG_JFFS2_NAND) && \
defined(CONFIG_CMD_NAND) )
-#if defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#else
#include <nand.h>
@@ -161,7 +161,7 @@ static struct part_info *current_part;
*
*/
-#if defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_NAND_LEGACY)
/* this one defined in nand_legacy.c */
int read_jffs2_nand(size_t start, size_t len,
size_t * retlen, u_char * buf, int nanddev);
@@ -201,7 +201,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
}
}
-#if defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_NAND_LEGACY)
if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE,
&retlen, nand_cache, id->num) < 0 ||
retlen != NAND_CACHE_SIZE) {
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
index 3ce9c98..9f6de7d 100644
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -1,6 +1,6 @@
#include <common.h>
-#if !defined(CFG_NAND_LEGACY) && defined(CONFIG_CMD_JFFS2)
+#if !defined(CONFIG_NAND_LEGACY) && defined(CONFIG_CMD_JFFS2)
#include <malloc.h>
#include <linux/stat.h>
diff --git a/include/asm-ppc/interrupt.h b/include/asm-ppc/interrupt.h
new file mode 100644
index 0000000..792836b
--- /dev/null
+++ b/include/asm-ppc/interrupt.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+#ifndef INTERRUPT_H
+#define INTERRUPT_H
+
+#if defined(CONFIG_XILINX_440)
+#include <asm/xilinx_irq.h>
+#else
+#include <asm/ppc4xx-uic.h>
+#endif
+
+void pic_enable(void);
+void pic_irq_enable(unsigned int irq);
+void pic_irq_disable(unsigned int irq);
+void pic_irq_ack(unsigned int irq);
+void external_interrupt(struct pt_regs *regs);
+void interrupt_run_handler(int vec);
+
+#endif
diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
new file mode 100644
index 0000000..d180e04
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_EBC_H_
+#define _PPC4xx_EBC_H_
+
+/*
+ * Currently there are two register layout versions for the
+ * IBM EBC core used on 4xx PPC's:
+ */
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+ defined(CONFIG_405EP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define CONFIG_EBC_PPC4xx_IBM_VER1
+#endif
+
+/* Bank Configuration Register */
+#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
+#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
+#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
+#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
+#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
+#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
+#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
+#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
+#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
+#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
+#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
+#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
+#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
+#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
+#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
+#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
+#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2)
+#else
+#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
+#endif
+
+/* Bank Access Parameter Register */
+#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
+#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
+#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
+#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
+#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
+#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
+#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
+#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
+#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
+#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
+#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
+#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
+#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
+#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
+#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
+#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
+#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
+#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
+#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
+
+/* Common fields in EBC0_CFG register */
+#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
+#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
+#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
+#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
+#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
+#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
+#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
+#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
+#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
+#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
+#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
+
+/* Now the two versions of the other bits */
+#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
+#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3)
+#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3)
+#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3)
+#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0)
+#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1)
+#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2)
+#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3)
+#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0)
+#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1)
+#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2)
+#else
+#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
+#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
+#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
+#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0)
+#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
+#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
+#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
+#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
+#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
+#endif
+
+#endif /* _PPC4xx_EBC_H_ */
diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h
deleted file mode 100644
index 5b45de4..0000000
--- a/include/asm-ppc/ppc4xx-intvec.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-/*
- * Interrupt vector number definitions to ease the
- * 405 -- 440 porting pain ;-)
- *
- * NOTE: They're not all here yet ... update as needed.
- *
- */
-
-#ifndef _VECNUMS_H_
-#define _VECNUMS_H_
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART 0 */
-#define VECNUM_U1 1 /* UART 1 */
-#define VECNUM_IIC0 2 /* IIC */
-#define VECNUM_KRD 3 /* Kasumi Ready for data */
-#define VECNUM_KDA 4 /* Kasumi Data Available */
-#define VECNUM_PCRW 5 /* PCI command register write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_IIC1 7 /* IIC */
-#define VECNUM_SPI 8 /* SPI */
-#define VECNUM_EPCISER 9 /* External PCI SERR */
-#define VECNUM_MTE 10 /* MAL TXEOB */
-#define VECNUM_MRE 11 /* MAL RXEOB */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_UD0 16 /* UDMA irq 0 */
-#define VECNUM_UD1 17 /* UDMA irq 1 */
-#define VECNUM_UD2 18 /* UDMA irq 2 */
-#define VECNUM_UD3 19 /* UDMA irq 3 */
-#define VECNUM_HSB2D 20 /* USB2.0 Device */
-#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
-#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
-#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
-#define VECNUM_EIP94 23 /* Security EIP94 */
-#define VECNUM_ETH0 24 /* Emac 0 */
-#define VECNUM_ETH1 25 /* Emac 1 */
-#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
-#define VECNUM_EIR4 27 /* External interrupt 4 */
-#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
-#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 0) /* MAL SERR */
-#define VECNUM_MTDE (32 + 1) /* MAL TXDE */
-#define VECNUM_MRDE (32 + 2) /* MAL RXDE */
-#define VECNUM_U2 (32 + 3) /* UART 2 */
-#define VECNUM_U3 (32 + 4) /* UART 3 */
-#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */
-#define VECNUM_NDFC (32 + 6) /* NDFC */
-#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */
-#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
-#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
-#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
-#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
-#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
-#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
-#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
-#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
-#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
-#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
-#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
-#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
-#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
-#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
-#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
-#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
-#define VECNUM_SRE (32 + 24) /* Serial ROM error */
-#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
-#define VECNUM_RSVD0 (32 + 26) /* Reserved */
-#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
-#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
-#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
-#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
-#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
-
-#define VECNUM_TXDE VECNUM_MTDE
-#define VECNUM_RXDE VECNUM_MRDE
-
-/* UIC 2 */
-#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */
-#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */
-#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */
-#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */
-#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */
-#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */
-#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */
-#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */
-#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */
-#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-/* UIC 0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_MSI0 8 /* PCI MSI level 0 */
-#define VECNUM_EIR0 9 /* External interrupt 0 */
-#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */
-#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */
-#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */
-#define VECNUM_EIR1 9 /* External interrupt 1 */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */
-#define VECNUM_U0 (32 + 1) /* UART0 */
-#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */
-#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */
-#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */
-#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */
-#define VECNUM_U2 (32 + 28) /* UART2 */
-#define VECNUM_U3 (32 + 29) /* UART3 */
-#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */
-#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */
-
-/* UIC 2 */
-#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */
-#define VECNUM_MS (64 + 3) /* MAL SERR */
-#define VECNUM_TXDE (64 + 4) /* MAL TXDE */
-#define VECNUM_RXDE (64 + 5) /* MAL RXDE */
-#define VECNUM_MTE (64 + 6) /* MAL TXEOB */
-#define VECNUM_MRE (64 + 7) /* MAL RXEOB */
-#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */
-#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */
-#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */
-#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */
-#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */
-#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */
-#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */
-#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */
-#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */
-#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */
-
-/* UIC 3 */
-#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */
-#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */
-#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */
-#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */
-#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */
-#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */
-#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */
-#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */
-#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */
-#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */
-#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */
-#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */
-
-#elif defined(CONFIG_440SPE)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_MSI0 7 /* PCI MSI level 0 */
-#define VECNUM_MSI1 8 /* PCI MSI level 0 */
-#define VECNUM_MSI2 9 /* PCI MSI level 0 */
-#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */
-#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */
-#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 1 ) /* MAL SERR */
-#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
-#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
-#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
-#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
-#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
-#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
-#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
-#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
-#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
-#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
-
-/* UIC 2 */
-#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */
-#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */
-#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */
-#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */
-#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */
-#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */
-
-#elif defined(CONFIG_440SP)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
-#define VECNUM_MS (32 + 1) /* MAL SERR */
-#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
-#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
-#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
-#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
-#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
-#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
-#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
-#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
-#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
-#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
-
-#elif defined(CONFIG_440)
-
-/* UIC 0 */
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_IIC0 2 /* IIC0 */
-#define VECNUM_IIC1 3 /* IIC1 */
-#define VECNUM_PIM 4 /* PCI inbound message */
-#define VECNUM_PCRW 5 /* PCI command reg write */
-#define VECNUM_PPM 6 /* PCI power management */
-#define VECNUM_MSI0 7 /* PCI MSI level 0 */
-#define VECNUM_MSI1 8 /* PCI MSI level 0 */
-#define VECNUM_MSI2 9 /* PCI MSI level 0 */
-#define VECNUM_MTE 10 /* MAL TXEOB */
-#define VECNUM_MRE 11 /* MAL RXEOB */
-#define VECNUM_D0 12 /* DMA channel 0 */
-#define VECNUM_D1 13 /* DMA channel 1 */
-#define VECNUM_D2 14 /* DMA channel 2 */
-#define VECNUM_D3 15 /* DMA channel 3 */
-#define VECNUM_CT0 18 /* GPT compare timer 0 */
-#define VECNUM_CT1 19 /* GPT compare timer 1 */
-#define VECNUM_CT2 20 /* GPT compare timer 2 */
-#define VECNUM_CT3 21 /* GPT compare timer 3 */
-#define VECNUM_CT4 22 /* GPT compare timer 4 */
-#define VECNUM_EIR0 23 /* External interrupt 0 */
-#define VECNUM_EIR1 24 /* External interrupt 1 */
-#define VECNUM_EIR2 25 /* External interrupt 2 */
-#define VECNUM_EIR3 26 /* External interrupt 3 */
-#define VECNUM_EIR4 27 /* External interrupt 4 */
-#define VECNUM_EIR5 28 /* External interrupt 5 */
-#define VECNUM_EIR6 29 /* External interrupt 6 */
-#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 0 ) /* MAL SERR */
-#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
-#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
-#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
-#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
-
-#else /* !defined(CONFIG_440) */
-
-#if defined(CONFIG_405EZ)
-#define VECNUM_D0 0 /* DMA channel 0 */
-#define VECNUM_D1 1 /* DMA channel 1 */
-#define VECNUM_D2 2 /* DMA channel 2 */
-#define VECNUM_D3 3 /* DMA channel 3 */
-#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
-#define VECNUM_U0 5 /* UART0 */
-#define VECNUM_U1 6 /* UART1 */
-#define VECNUM_CAN0 7 /* CAN 0 */
-#define VECNUM_CAN1 8 /* CAN 1 */
-#define VECNUM_SPI 9 /* SPI */
-#define VECNUM_IIC0 10 /* I2C */
-#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
-#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
-#define VECNUM_USBH1 13 /* USB Host 1 */
-#define VECNUM_USBH2 14 /* USB Host 2 */
-#define VECNUM_USBDEV 15 /* USB Device */
-#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
-#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
-
-#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
-#define VECNUM_MS 18 /* MAL_SERR_INT */
-#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
-#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
-
-#define VECNUM_MTE 19 /* MAL TXEOB */
-#define VECNUM_MTE1 20 /* MAL TXEOB1 */
-#define VECNUM_MRE 21 /* MAL RXEOB */
-#define VECNUM_NAND 22 /* NAND Flash controller */
-#define VECNUM_ADC 23 /* ADC */
-#define VECNUM_DAC 24 /* DAC */
-#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
-#define VECNUM_RESERVED0 26 /* Reserved */
-#define VECNUM_EIR0 27 /* External interrupt 0 */
-#define VECNUM_EIR1 28 /* External interrupt 1 */
-#define VECNUM_EIR2 29 /* External interrupt 2 */
-#define VECNUM_EIR3 30 /* External interrupt 3 */
-#define VECNUM_EIR4 31 /* External interrupt 4 */
-
-#elif defined(CONFIG_405EX)
-
-/* UIC 0 */
-#define VECNUM_U0 00
-#define VECNUM_U1 01
-#define VECNUM_IIC0 02
-#define VECNUM_PKA 03
-#define VECNUM_TRNG 04
-#define VECNUM_EBM 05
-#define VECNUM_BGI 06
-#define VECNUM_IIC1 07
-#define VECNUM_SPI 08
-#define VECNUM_EIR0 09
-#define VECNUM_MTE 10 /* MAL Tx EOB */
-#define VECNUM_MRE 11 /* MAL Rx EOB */
-#define VECNUM_DMA0 12
-#define VECNUM_DMA1 13
-#define VECNUM_DMA2 14
-#define VECNUM_DMA3 15
-#define VECNUM_PCIE0AL 16
-#define VECNUM_PCIE0VPD 17
-#define VECNUM_RPCIE0HRST 18
-#define VECNUM_FPCIE0HRST 19
-#define VECNUM_PCIE0TCR 20
-#define VECNUM_PCIEMSI0 21
-#define VECNUM_PCIEMSI1 22
-#define VECNUM_SECURITY 23
-#define VECNUM_ETH0 24
-#define VECNUM_ETH1 25
-#define VECNUM_PCIEMSI2 26
-#define VECNUM_EIR4 27
-#define VECNUM_UIC2NC 28
-#define VECNUM_UIC2C 29
-#define VECNUM_UIC1NC 30
-#define VECNUM_UIC1C 31
-
-/* UIC 1 */
-#define VECNUM_MS (32 + 00) /* MAL SERR */
-#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
-#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
-#define VECNUM_PCIE0BMVC0 (32 + 03)
-#define VECNUM_PCIE0DCRERR (32 + 04)
-#define VECNUM_EBC (32 + 05)
-#define VECNUM_NDFC (32 + 06)
-#define VECNUM_PCEI1DCRERR (32 + 07)
-#define VECNUM_CT8 (32 + 08)
-#define VECNUM_CT9 (32 + 09)
-#define VECNUM_PCIE1AL (32 + 10)
-#define VECNUM_PCIE1VPD (32 + 11)
-#define VECNUM_RPCE1HRST (32 + 12)
-#define VECNUM_FPCE1HRST (32 + 13)
-#define VECNUM_PCIE1TCR (32 + 14)
-#define VECNUM_PCIE1VC0 (32 + 15)
-#define VECNUM_CT3 (32 + 16)
-#define VECNUM_CT4 (32 + 17)
-#define VECNUM_EIR7 (32 + 18)
-#define VECNUM_EIR8 (32 + 19)
-#define VECNUM_EIR9 (32 + 20)
-#define VECNUM_CT5 (32 + 21)
-#define VECNUM_CT6 (32 + 22)
-#define VECNUM_CT7 (32 + 23)
-#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
-#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
-#define VECNUM_EIR2 (32 + 26)
-#define VECNUM_EIR5 (32 + 27)
-#define VECNUM_EIR6 (32 + 28)
-#define VECNUM_EMAC0WAKE (32 + 29)
-#define VECNUM_EIR1 (32 + 30)
-#define VECNUM_EMAC1WAKE (32 + 31)
-
-/* UIC 2 */
-#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
-#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
-#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
-#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
-#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
-#define VECNUM_DDRMCUE (64 + 05)
-#define VECNUM_DDRMCCE (64 + 06)
-#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
-#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
-#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
-#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
-#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
-#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
-#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
-#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
-#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
-#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
-#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
-#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
-#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
-#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
-#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
-#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
-#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
-#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
-#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
-#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
-#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
-#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
-#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
-#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
-#define VECNUM_USBOTG (64 + 31) /* USB OTG */
-
-#else /* !CONFIG_405EZ */
-
-#define VECNUM_U0 0 /* UART0 */
-#define VECNUM_U1 1 /* UART1 */
-#define VECNUM_D0 5 /* DMA channel 0 */
-#define VECNUM_D1 6 /* DMA channel 1 */
-#define VECNUM_D2 7 /* DMA channel 2 */
-#define VECNUM_D3 8 /* DMA channel 3 */
-#define VECNUM_EWU0 9 /* Ethernet wakeup */
-#define VECNUM_MS 10 /* MAL SERR */
-#define VECNUM_MTE 11 /* MAL TXEOB */
-#define VECNUM_MRE 12 /* MAL RXEOB */
-#define VECNUM_TXDE 13 /* MAL TXDE */
-#define VECNUM_RXDE 14 /* MAL RXDE */
-#define VECNUM_ETH0 15 /* Ethernet interrupt status */
-#define VECNUM_EIR0 25 /* External interrupt 0 */
-#define VECNUM_EIR1 26 /* External interrupt 1 */
-#define VECNUM_EIR2 27 /* External interrupt 2 */
-#define VECNUM_EIR3 28 /* External interrupt 3 */
-#define VECNUM_EIR4 29 /* External interrupt 4 */
-#define VECNUM_EIR5 30 /* External interrupt 5 */
-#define VECNUM_EIR6 31 /* External interrupt 6 */
-#endif /* defined(CONFIG_405EZ) */
-
-#endif /* defined(CONFIG_440) */
-
-#endif /* _VECNUMS_H_ */
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index e151f0c..df787b3 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -282,7 +282,8 @@
* Memory Bank 0-7 configuration
*/
#if defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -353,7 +354,19 @@
/*
* Memory controller registers
*/
+#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
+#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
+#define SDRAM_BEARL 0x02 /* PLB bus error address low */
+#define SDRAM_BEARH 0x03 /* PLB bus error address high */
+#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */
+#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
+#define SDRAM_PLBOPT 0x08 /* PLB slave options */
+#define SDRAM_PUABA 0x09 /* PLB upper address base */
+#ifndef CONFIG_405EX
#define SDRAM_MCSTAT 0x14 /* memory controller status */
+#else
+#define SDRAM_MCSTAT 0x1F /* memory controller status */
+#endif
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
@@ -398,9 +411,35 @@
#define SDRAM_MMODE 0x88 /* memory mode */
#define SDRAM_MEMODE 0x89 /* memory extended mode */
#define SDRAM_ECCCR 0x98 /* ECC error status */
+#define SDRAM_ECCES SDRAM_ECCCR
#define SDRAM_CID 0xA4 /* core ID */
+#ifndef CONFIG_405EX
#define SDRAM_RID 0xA8 /* revision ID */
+#endif
+#define SDRAM_FCSR 0xB0 /* feedback calibration status */
#define SDRAM_RTSR 0xB1 /* run time status tracking */
+#ifdef CONFIG_405EX
+#define SDRAM_RID 0xF8 /* revision ID */
+#endif
+
+/*
+ * Memory Controller Bus Error Status
+ */
+#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
+#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
+#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0)
+#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1)
+#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2)
+#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3)
+#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4)
+#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5)
+#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6)
+#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7)
+#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
+#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0)
+#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1)
+#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
+#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1)
/*
* Memory Controller Status
@@ -523,7 +562,7 @@
* SDRAM Delay Line Calibration Register
*/
#define SDRAM_DLCR_DCLM_MASK 0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
+#define SDRAM_DLCR_DCLM_MANUAL 0x80000000
#define SDRAM_DLCR_DCLM_AUTO 0x00000000
#define SDRAM_DLCR_DLCR_MASK 0x08000000
#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
@@ -539,59 +578,234 @@
#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
/*
+ * SDRAM Memory On Die Terimination Control Register
+ */
+#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0)
+#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1)
+#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0)
+#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1)
+#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0)
+#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1)
+#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0)
+#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1)
+#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0)
+#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1)
+
+/*
* SDRAM Controller On Die Termination Register
*/
-#define SDRAM_CODT_ODT_ON 0x80000000
-#define SDRAM_CODT_ODT_OFF 0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
-#define SDRAM_CODT_DQS_MASK 0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
+#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1)
+#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0)
+#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1)
+#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0)
+#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1)
+#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0)
+#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1)
+#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0)
+#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1)
+#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0)
+#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0)
+#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1)
+#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2)
+#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3)
+#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0)
+#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1)
+#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0)
+#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1)
+#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0)
+#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1)
+#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0)
+#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1)
+#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0)
+#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1)
+#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0)
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1)
+#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0)
+#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1)
+#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1)
+#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0)
+#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1)
+#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0)
+#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1)
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1)
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1)
+#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0)
+#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1)
/*
- * SDRAM Mode Register
+ * SDRAM Initialization Preload Register
*/
-#define SDRAM_MMODE_WR_MASK 0x00000E00
-#define SDRAM_MMODE_WR_DDR1 0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
-#define SDRAM_MMODE_DCL_MASK 0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
+#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1)
+#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0)
+#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF)
+#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \
+ (static_cast(u32, \
+ n)) \
+ & 0xFF)
+#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7)
+#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \
+ (static_cast(u32, \
+ n)) \
+ & 0x7)
+#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7)
+#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \
+ (static_cast(u32, \
+ n)) \
+ & 0x7)
+#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF)
+#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \
+ (static_cast(u32, \
+ n)) \
+ & 0x7FFF)
/*
- * SDRAM Extended Mode Register
+ * JEDEC DDR Initialization Commands
*/
-#define SDRAM_MEMODE_DIC_MASK 0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
-#define SDRAM_MEMODE_DIC_WEAK 0x00000002
-#define SDRAM_MEMODE_DLL_MASK 0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
-#define SDRAM_MEMODE_RTT_MASK 0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
-#define SDRAM_MEMODE_RTT_75OHM 0x00000004
-#define SDRAM_MEMODE_RTT_150OHM 0x00000040
-#define SDRAM_MEMODE_DQS_MASK 0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
+#define JEDEC_CMD_NOP 7
+#define JEDEC_CMD_PRECHARGE 2
+#define JEDEC_CMD_REFRESH 1
+#define JEDEC_CMD_EMR 0
+#define JEDEC_CMD_READ 5
+#define JEDEC_CMD_WRITE 4
+
+/*
+ * JEDEC Precharge Command Memory Address Arguments
+ */
+#define JEDEC_MA_PRECHARGE_ONE (0 << 10)
+#define JEDEC_MA_PRECHARGE_ALL (1 << 10)
+
+/*
+ * JEDEC DDR EMR Command Bank Address Arguments
+ */
+#define JEDEC_BA_MR 0
+#define JEDEC_BA_EMR 1
+#define JEDEC_BA_EMR2 2
+#define JEDEC_BA_EMR3 3
+
+/*
+ * JEDEC DDR Mode Register
+ */
+#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12)
+#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12)
+#define JEDEC_MA_MR_WR_MASK (0x7 << 9)
+#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9)
+#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9)
+#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9)
+#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9)
+#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9)
+#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9)
+#define JEDEC_MA_MR_DLL_RESET (1 << 8)
+#define JEDEC_MA_MR_MODE_NORMAL (0 << 8)
+#define JEDEC_MA_MR_MODE_TEST (1 << 8)
+#define JEDEC_MA_MR_CL_MASK (0x7 << 4)
+#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4)
+#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4)
+#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4)
+#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4)
+#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4)
+#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4)
+#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4)
+#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4)
+#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4)
+#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3)
+#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3)
+#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0)
+#define JEDEC_MA_MR_BLEN_4 (2 << 0)
+#define JEDEC_MA_MR_BLEN_8 (3 << 0)
+
+/*
+ * JEDEC DDR Extended Mode Register
+ */
+#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12)
+#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12)
+#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12)
+#define JEDEC_MA_EMR_RQDS_MASK (1 << 11)
+#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11)
+#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11)
+#define JEDEC_MA_EMR_DQS_MASK (1 << 10)
+#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10)
+#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10)
+#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7)
+#define JEDEC_MA_EMR_OCD_EXIT (0 << 7)
+#define JEDEC_MA_EMR_OCD_ENTER (7 << 7)
+#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3)
+#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2)
+#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2)
+#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2)
+#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2)
+#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2)
+#define JEDEC_MA_EMR_ODS_MASK (1 << 1)
+#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1)
+#define JEDEC_MA_EMR_ODS_WEAK (1 << 1)
+#define JEDEC_MA_EMR_DLL_MASK (1 << 0)
+#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0)
+#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0)
+
+/*
+ * JEDEC DDR Extended Mode Register 2
+ */
+#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7)
+#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7)
+
+/*
+ * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
+ */
+#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK
+#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1
+#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC
+#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC
+#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC
+#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC
+#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC
+#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK
+#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL
+#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED
+#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK
+#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4
+#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8
+
+/*
+ * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
+ * Mode Register)
+ */
+#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK
+#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE
+#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE
+#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK
+#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE
+#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE
+#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK
+#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE
+#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE
+#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC
+#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC
+#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC
+#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC
+#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC
+#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK
+#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED
+#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM
+#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM
+#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM
+#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK
+#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL
+#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK
+#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK
+#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE
+#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE
/*
* SDRAM Clock Timing Register
@@ -684,6 +898,24 @@
#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
/*
+ * ECC Error Status
+ */
+#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
+#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
+#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
+#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
+#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
+#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
+#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
+#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
+#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
+#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
+#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
+#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
+#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
+#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
+
+/*
* Memory Bank 0-1 configuration
*/
#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h
new file mode 100644
index 0000000..c908d42
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-uic.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_UIC_H_
+#define _PPC4xx_UIC_H_
+
+/*
+ * Define the number of UIC's
+ */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
+#define UIC_MAX 4
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
+#define UIC_MAX 3
+#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define UIC_MAX 2
+#else
+#define UIC_MAX 1
+#endif
+
+#define IRQ_MAX UIC_MAX * 32
+
+/*
+ * UIC register
+ */
+#define UIC_SR 0x0 /* UIC status */
+#define UIC_ER 0x2 /* UIC enable */
+#define UIC_CR 0x3 /* UIC critical */
+#define UIC_PR 0x4 /* UIC polarity */
+#define UIC_TR 0x5 /* UIC triggering */
+#define UIC_MSR 0x6 /* UIC masked status */
+#define UIC_VR 0x7 /* UIC vector */
+#define UIC_VCR 0x8 /* UIC vector configuration */
+
+/*
+ * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
+ * are cascaded on. With this trick we can use the common UIC code for 440GX
+ * too.
+ */
+#if defined(CONFIG_440GX)
+#define UIC0_DCR_BASE 0x200
+#define UIC1_DCR_BASE 0xc0
+#define UIC2_DCR_BASE 0xd0
+#define UIC3_DCR_BASE 0x210
+#else
+#define UIC0_DCR_BASE 0xc0
+#define UIC1_DCR_BASE 0xd0
+#define UIC2_DCR_BASE 0xe0
+#define UIC3_DCR_BASE 0xf0
+#endif
+
+#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
+#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
+#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
+#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
+#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
+#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
+#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
+#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
+
+#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
+#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
+#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
+#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
+#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
+#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
+#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
+#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
+
+#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
+#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
+#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
+#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
+#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
+#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
+#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
+#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
+#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
+
+#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
+#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
+#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
+#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
+#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
+#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
+#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
+#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
+#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
+
+/* The following is for compatibility with 405 code */
+#define uicsr uic0sr
+#define uicer uic0er
+#define uiccr uic0cr
+#define uicpr uic0pr
+#define uictr uic0tr
+#define uicmsr uic0msr
+#define uicvr uic0vr
+#define uicvcr uic0vcr
+
+/*
+ * Now the interrupt vector definitions. They are different for most of
+ * the 4xx variants, so we need some more #ifdef's here. No mask
+ * definitions anymore here. For this please use the UIC_MASK macro below.
+ *
+ * Note: Please only define the interrupts really used in U-Boot here.
+ * Those are the cascading and EMAC/MAL related interrupt.
+ */
+
+#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
+#define VECNUM_MAL_SERR 10
+#define VECNUM_MAL_TXEOB 11
+#define VECNUM_MAL_RXEOB 12
+#define VECNUM_MAL_TXDE 13
+#define VECNUM_MAL_RXDE 14
+#define VECNUM_ETH0 15
+#define VECNUM_ETH1_OFFS 2
+#define VECNUM_EIRQ6 29
+#endif /* defined(CONFIG_405EP) */
+
+#if defined(CONFIG_405EZ)
+#define VECNUM_USBDEV 15
+#define VECNUM_ETH0 16
+#define VECNUM_MAL_SERR 18
+#define VECNUM_MAL_TXDE 18
+#define VECNUM_MAL_RXDE 18
+#define VECNUM_MAL_TXEOB 19
+#define VECNUM_MAL_RXEOB 21
+#endif /* CONFIG_405EX */
+
+#if defined(CONFIG_405EX)
+/* UIC 0 */
+#define VECNUM_MAL_TXEOB 10
+#define VECNUM_MAL_RXEOB 11
+#define VECNUM_ETH0 24
+#define VECNUM_ETH1_OFFS 1
+#define VECNUM_UIC2NCI 28
+#define VECNUM_UIC2CI 29
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 0)
+#define VECNUM_MAL_TXDE (32 + 1)
+#define VECNUM_MAL_RXDE (32 + 2)
+#endif /* CONFIG_405EX */
+
+#if defined(CONFIG_440GP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
+/* UIC 0 */
+#define VECNUM_MAL_TXEOB 10
+#define VECNUM_MAL_RXEOB 11
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 0)
+#define VECNUM_MAL_TXDE (32 + 1)
+#define VECNUM_MAL_RXDE (32 + 2)
+#define VECNUM_USBDEV (32 + 23)
+#define VECNUM_ETH0 (32 + 28)
+#define VECNUM_ETH1_OFFS 2
+#endif /* CONFIG_440GP */
+
+#if defined(CONFIG_440GX)
+/* UICB 0 (440GX only) */
+/*
+ * All those defines below are off-by-one, so that the common UIC code
+ * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
+ */
+#define VECNUM_UIC1CI 0
+#define VECNUM_UIC1NCI 1
+#define VECNUM_UIC2CI 2
+#define VECNUM_UIC2NCI 3
+#define VECNUM_UIC3CI 4
+#define VECNUM_UIC3NCI 5
+
+/* UIC 0, used as UIC1 on 440GX because of UICB0 */
+#define VECNUM_MAL_TXEOB (32 + 10)
+#define VECNUM_MAL_RXEOB (32 + 11)
+
+/* UIC 1, used as UIC2 on 440GX because of UICB0 */
+#define VECNUM_MAL_SERR (64 + 0)
+#define VECNUM_MAL_TXDE (64 + 1)
+#define VECNUM_MAL_RXDE (64 + 2)
+#define VECNUM_ETH0 (64 + 28)
+#define VECNUM_ETH1_OFFS 2
+#endif /* CONFIG_440GX */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+/* UIC 0 */
+#define VECNUM_MAL_TXEOB 10
+#define VECNUM_MAL_RXEOB 11
+#define VECNUM_USBDEV 20
+#define VECNUM_ETH0 24
+#define VECNUM_ETH1_OFFS 1
+#define VECNUM_UIC2NCI 28
+#define VECNUM_UIC2CI 29
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 0)
+#define VECNUM_MAL_TXDE (32 + 1)
+#define VECNUM_MAL_RXDE (32 + 2)
+
+/* UIC 2 */
+#define VECNUM_EIRQ2 (64 + 3)
+#endif /* CONFIG_440EPX */
+
+#if defined(CONFIG_440SP)
+/* UIC 0 */
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 1)
+#define VECNUM_MAL_TXDE (32 + 2)
+#define VECNUM_MAL_RXDE (32 + 3)
+#define VECNUM_MAL_TXEOB (32 + 6)
+#define VECNUM_MAL_RXEOB (32 + 7)
+#define VECNUM_ETH0 (32 + 28)
+#endif /* CONFIG_440SP */
+
+#if defined(CONFIG_440SPE)
+/* UIC 0 */
+#define VECNUM_UIC2NCI 10
+#define VECNUM_UIC2CI 11
+#define VECNUM_UIC3NCI 16
+#define VECNUM_UIC3CI 17
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 1)
+#define VECNUM_MAL_TXDE (32 + 2)
+#define VECNUM_MAL_RXDE (32 + 3)
+#define VECNUM_MAL_TXEOB (32 + 6)
+#define VECNUM_MAL_RXEOB (32 + 7)
+#define VECNUM_ETH0 (32 + 28)
+#endif /* CONFIG_440SPE */
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+/* UIC 0 */
+#define VECNUM_UIC2NCI 10
+#define VECNUM_UIC2CI 11
+#define VECNUM_UIC3NCI 16
+#define VECNUM_UIC3CI 17
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 2 */
+#define VECNUM_MAL_SERR (64 + 3)
+#define VECNUM_MAL_TXDE (64 + 4)
+#define VECNUM_MAL_RXDE (64 + 5)
+#define VECNUM_MAL_TXEOB (64 + 6)
+#define VECNUM_MAL_RXEOB (64 + 7)
+#define VECNUM_ETH0 (64 + 16)
+#define VECNUM_ETH1_OFFS 1
+#endif /* CONFIG_460EX */
+
+#if defined(CONFIG_460SX)
+/* UIC 0 */
+#define VECNUM_UIC2NCI 10
+#define VECNUM_UIC2CI 11
+#define VECNUM_UIC3NCI 16
+#define VECNUM_UIC3CI 17
+#define VECNUM_ETH0 19
+#define VECNUM_ETH1_OFFS 1
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 1)
+#define VECNUM_MAL_TXDE (32 + 2)
+#define VECNUM_MAL_RXDE (32 + 3)
+#define VECNUM_MAL_TXEOB (32 + 6)
+#define VECNUM_MAL_RXEOB (32 + 7)
+#endif /* CONFIG_460EX */
+
+#if !defined(VECNUM_ETH1_OFFS)
+#define VECNUM_ETH1_OFFS 1
+#endif
+
+/*
+ * Mask definitions (used for example in 4xx_enet.c)
+ */
+#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
+/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
+#define UIC_NR(vec) ((vec) >> 5)
+
+#endif /* _PPC4xx_UIC_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index e617868..dce4717 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -830,6 +830,10 @@
#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
+#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
+#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
+#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
@@ -855,6 +859,8 @@
#define PVR_86xx 0x80040000
#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
+#define PVR_VIRTEX5 0x7ff21912
+
/*
* For the 8xx processors, all of them report the same PVR family for
* the PowerPC core. The various versions of these processors must be
diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h
new file mode 100644
index 0000000..61171c2
--- /dev/null
+++ b/include/asm-ppc/xilinx_irq.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+#ifndef XILINX_IRQ_H
+#define XILINX_IRQ_H
+
+#define intc XPAR_INTC_0_BASEADDR
+#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
+#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
+#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
+#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
+#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
+#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
+#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
+#define MER (intc + (7 * 4)) /* Master Enable Register */
+
+#define IRQ_MASK(irq) (1 << (irq & 0x1f))
+
+#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
+
+#endif
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 2f266a2..6ee0a36 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -269,7 +269,7 @@ extern int flash_banks;
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CFG_MAX_FLASH_BANKS flash_banks /* max num of flash banks */
/* updated in board_early_init_r */
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index f05c1d5..6aa881c 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -182,7 +182,7 @@
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_CFI 1
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index cefdd29..07a9f4e 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -143,7 +143,7 @@
*/
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index 8ec70aa..26a1a2d 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -338,7 +338,7 @@ extern unsigned char scsi_sym53c8xx_ccf;
/*
* Winbond Configuration
*/
-#define CFG_WINBOND_83C553 1 /* has a winbond bridge */
+#define CONFIG_WINBOND_83C553 1 /* has a winbond bridge */
#define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
@@ -346,7 +346,7 @@ extern unsigned char scsi_sym53c8xx_ccf;
/*
* NS87308 Configuration
*/
-#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */
+#define CONFIG_NS87308 /* Nat Semi super-io cntr on ISA bus */
#define CFG_NS87308_BADDR_10 1
#define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \
CFG_NS87308_UART2 | \
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index b7574bf..3c5d038 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -328,7 +328,7 @@
/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index bb7856f..11d19c6 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -86,7 +86,7 @@
/* CONFIG_CMD_DOC required legacy NAND support */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#if 0
#define CONFIG_PCI 1
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 89edbde..03756c3 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -294,7 +294,7 @@
* FLASH related
*----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 3879d9b..d325c4d 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -191,7 +191,7 @@
#endif
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 64c9ac0..c757523 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -119,7 +119,7 @@
* FLASH related
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index 7824b90..5f1743b 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -138,7 +138,7 @@
*/
#define CFG_FLASH_BASE 0xFC000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index 79b71db..e694a02 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -194,7 +194,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index ec757e2..84b6824 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -194,7 +194,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 037b115..422ed32 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -280,7 +280,7 @@
#define CFG_FPGA_PROG_FEEDBACK
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
/*
* Verbose help from command monitor.
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 8ea1ac3..9bcbfe3 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -407,7 +407,7 @@
/*
* define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
*/
-#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6)
+#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
/*-----------------------------------------------------------------------
* FPGA stuff
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index 26dd954..5deb84d 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -201,7 +201,7 @@
*/
-#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
+#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
@@ -214,7 +214,7 @@
/*
* NS87308 Configuration
*/
-#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
+#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
#define CFG_NS87308_BADDR_10 1
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
index 081ca6c..a7e7c57 100644
--- a/include/configs/HMI10.h
+++ b/include/configs/HMI10.h
@@ -227,7 +227,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index f7d4499..029bb99 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -227,7 +227,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { 0xFF800000 }
#define CFG_MAX_FLASH_BANKS_DETECT 1
/* What should the base address of the main FLASH be and how big is
@@ -262,7 +262,7 @@
*/
#if defined(CONFIG_CMD_NAND)
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_NAND0_BASE 0xE1000000
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 760f7cc..27e46a4 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -180,7 +180,7 @@
*/
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */
#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 3a347ea..0b90946 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -246,7 +246,7 @@
#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
#if defined(CONFIG_LITE5200B)
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
#endif
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 3d28913..8713b02 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -207,7 +207,7 @@
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 8af1c52..e836132 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -200,7 +200,7 @@
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index de7ea42..c2f5dd9 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -150,7 +150,7 @@
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index f5e1b64..9dbd129 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -172,7 +172,7 @@
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_SIZE 0x200000
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index a6fac4c..12f9783 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -210,7 +210,7 @@
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_SIZE 0x200000
/* Cache Configuration */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 283c873..30c70e5 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -197,7 +197,7 @@
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index df46ee4..c2c7fab 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -194,7 +194,7 @@
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index b30d99c..58948a2 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -202,7 +202,7 @@
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index a710c6d..814c3a6 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -202,7 +202,7 @@
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 3a022af..6620f03 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -302,7 +302,7 @@
#undef CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index e8804b5..4037efb 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -259,7 +259,7 @@
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_BASE (CFG_CS0_BASE)
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 0f957ff..a14c55b 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -245,7 +245,7 @@
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_BASE (CFG_CS0_BASE)
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index d683b87..66235e3 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -88,7 +88,7 @@
#endif
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 37f8cff..a4c4240 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -171,7 +171,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 8 /* flash size in MB */
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 095f665..b0cc36d 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -188,7 +188,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 977c041..94b3d5a 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -178,7 +178,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 9ca2a2b..401d0af 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -166,7 +166,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 8705838..a53f5cd 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -148,7 +148,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 32 /* max flash size in MB */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 82d0686..45ddd5c 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -175,7 +175,7 @@
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_EMPTY_INFO
#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
@@ -419,7 +419,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
- #undef CFG_FLASH_CFI_DRIVER
+ #undef CONFIG_FLASH_CFI_DRIVER
#define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index b4bff9a..43d4118 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -191,7 +191,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index ca8d53c..6898495 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -184,7 +184,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
#define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 0dd0279..f9c1b17 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -226,7 +226,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 29c2490..82b3353 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -249,7 +249,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d1d3cc3..6351925 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -152,7 +152,7 @@
#undef CFG_RAMBOOT
#endif
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index a64565d..d948d76 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -154,7 +154,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 091fd2e..9a77b7b 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -168,7 +168,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index acf6f0d..33c5c93 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -172,7 +172,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 1948c0d..85c235c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -154,7 +154,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 27212162..3567d1ce 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -148,7 +148,7 @@
#undef CFG_RAMBOOT
#endif
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 9e6bb44..a82d528 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -167,7 +167,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 06899b1..e9371a2 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -192,7 +192,7 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index cd35494..468fd08 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -214,7 +214,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 2c27b97..0ce88d6 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -198,7 +198,7 @@
*/
#undef CONFIG_FLASH_16BIT
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI_AMD_RESET 1
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index b412655..0dce9b4 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -104,7 +104,7 @@
/* Flash */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CFG_FLASH_BASE 0xFF800000
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index fa0e5db..40cf275 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -67,7 +67,7 @@
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
/* SCIF */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console
information at boot */
@@ -103,7 +103,7 @@
/* FLASH */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 27e7ab9..6c18b81 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -502,7 +502,7 @@
/****************************************************************/
/* NAND */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 56c76d3..1f1bc54 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -621,7 +621,7 @@
/****************************************************************/
/* NAND */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index b8c4848..9a1f1d6 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -503,7 +503,7 @@
/****************************************************************/
/* NAND */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index 1293fb0..c029594 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -397,7 +397,7 @@
/*****************************************************************************/
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 21d90c3..31762b9 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -200,7 +200,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 268b034..6ebaa85 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -84,7 +84,7 @@
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 250b586..9202794 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -86,7 +86,7 @@
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 5890012..2ceda00 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -77,7 +77,7 @@
#define CONFIG_CMD_BSP
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 259178f..5e0bb05 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -88,7 +88,7 @@
#if !defined(CONFIG_BOOT_ROM)
/* DoC requires legacy NAND for now */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#endif
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 36e9aa5..190e2a4 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -180,7 +180,7 @@
#endif
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
/*
* Disk-On-Chip configuration
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index abf593c..96c0edf 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -183,7 +183,7 @@
/*
* Disk-On-Chip configuration
*/
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index bd058fc..f2c11b0 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -148,7 +148,7 @@
#undef CFG_RAMBOOT
#endif
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 9355aaf..b2cf060 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -149,7 +149,7 @@
#undef CFG_RAMBOOT
#endif
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index adbe8a9..966bbf9 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -214,7 +214,7 @@
#define CFG_FLASH_INCREMENT 0x01000000
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 42f1d8d..9140287 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -120,7 +120,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 01ebc8f..e8ed095 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -187,7 +187,7 @@
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 8a53fdd..6033d93 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -291,7 +291,7 @@
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION /* use hardware protection */
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
index 50ad7dd..d233679 100644
--- a/include/configs/SX1.h
+++ b/include/configs/SX1.h
@@ -181,7 +181,7 @@
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index aefc7ee..c5d5386 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -195,7 +195,7 @@
*/
/* NAND flash support */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index 5bbe3c5..cfd16d3 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -235,7 +235,7 @@
*/
-#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
+#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
@@ -246,7 +246,7 @@
/*
* NS87308 Configuration
*/
-#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
+#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
#define CFG_NS87308_BADDR_10 1
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index a08451e..c0f2c57 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -203,7 +203,7 @@
*/
-#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
+#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
@@ -214,7 +214,7 @@
/*
* NS87308 Configuration
*/
-#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
+#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
#define CFG_NS87308_BADDR_10 1
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index d21783b..3b68166 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -255,7 +255,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h
index 7310abf..8073b7e 100644
--- a/include/configs/TK885D.h
+++ b/include/configs/TK885D.h
@@ -247,7 +247,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index bfb478a..992439f 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -386,7 +386,7 @@
#else
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 9cc1964..839b6be 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -208,7 +208,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 5edd379..b9a7a59 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -203,7 +203,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index ba0402d..039ecf1 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -372,7 +372,7 @@
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 0d2ca72..e8f69f6 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -78,7 +78,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
#define CFG_FLASH_SIZE 8 /* FLASH size in MB */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 9edf0d8..388fafc 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -193,7 +193,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index e2c1ce8..6f0864f 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -192,7 +192,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index dd19d4e..093d659 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -198,7 +198,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 8a1c350..64bbc39 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -232,7 +232,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index d18f234..d84554e 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -204,7 +204,7 @@
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
@@ -345,7 +345,7 @@
/* NAND FLASH */
#ifdef CONFIG_NAND
-#undef CFG_NAND_LEGACY
+#undef CONFIG_NAND_LEGACY
#define CONFIG_NAND_FSL_UPM 1
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 803cdb8..dacc340 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -197,7 +197,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 071da1e..3ec849c 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -197,7 +197,7 @@
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index d34f6be..6c610ee 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -201,7 +201,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 9270e44..2eca59b 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -201,7 +201,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index d916d53..4683286 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -241,7 +241,7 @@
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index f075442..5daaf04 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -244,7 +244,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 598fe7b..25e98e2 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -204,7 +204,7 @@
* Flash configuration
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#if CONFIG_TOTAL5200_REV==2
# define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */
# define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index ad8db61..02cabb2 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -254,7 +254,7 @@
*/
#if defined(CONFIG_CMD_NAND)
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index b04be76..388c747 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -179,7 +179,7 @@
#define CFG_FLSIMM_BASE 0xFF000000
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 9092a7c..ed2754d 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -107,7 +107,7 @@
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/actux1.h b/include/configs/actux1.h
index 4c4b1d1..33a7494 100644
--- a/include/configs/actux1.h
+++ b/include/configs/actux1.h
@@ -162,7 +162,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
diff --git a/include/configs/actux2.h b/include/configs/actux2.h
index 873fced..75aaa11 100644
--- a/include/configs/actux2.h
+++ b/include/configs/actux2.h
@@ -136,7 +136,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
diff --git a/include/configs/actux3.h b/include/configs/actux3.h
index 5e468e6..693c284 100644
--- a/include/configs/actux3.h
+++ b/include/configs/actux3.h
@@ -135,7 +135,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
diff --git a/include/configs/actux4.h b/include/configs/actux4.h
index e4dca2a..7f8e0f4 100644
--- a/include/configs/actux4.h
+++ b/include/configs/actux4.h
@@ -134,7 +134,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY 1
/* no byte writes on IXP4xx */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 091da80..d129ea3 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -183,7 +183,7 @@
*/
#undef CONFIG_BKUP_FLASH
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#ifdef CONFIG_BKUP_FLASH
#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
#define CFG_FLASH_SIZE 0x00800000 /* max flash size in bytes */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index c5e4759..f27cc4a 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -225,7 +225,7 @@
/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index fb6feb5..f342c7a 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -86,7 +86,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index 5884611..c93e77a 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -215,7 +215,7 @@
* CFI FLASH driver setup
*/
# define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-# define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
# define CFG_FLASH_PROTECTION 1 /* Use h/w sector protection*/
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index d10f092..ed7b5ef 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -152,7 +152,7 @@
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_FLASH_SIZE PHYS_FLASH_SIZE
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index 342ce2a..520c676 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -109,7 +109,7 @@
/* NOR flash */
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define PHYS_FLASH_1 0x10000000
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MAX_FLASH_SECT 256
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index cd2eae2..fca431e 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -116,7 +116,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index a8194b5..5f90d39 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -113,7 +113,7 @@
#define CFG_NO_FLASH 1
#else
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define PHYS_FLASH_1 0x10000000
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MAX_FLASH_SECT 256
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index f040b86..6d8c1b2 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -140,7 +140,7 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_BASE 0x00000000
#define CFG_FLASH_SIZE 0x800000
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 68f0cec..3a7d273 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -163,7 +163,7 @@
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#endif
#define CFG_FLASH_BASE 0x00000000
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index d3a2f69..55ea7f2 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -146,7 +146,7 @@
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#endif
#define CFG_FLASH_BASE 0x00000000
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index a37ba92..369c619 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -146,7 +146,7 @@
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#endif
#define CFG_FLASH_BASE 0x00000000
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index a6c5b6e..902f822 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -163,7 +163,7 @@
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#endif
#define CFG_FLASH_BASE 0x00000000
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index d70aa10..9f5667b 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -94,7 +94,7 @@
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET
#define CFG_FLASH_BASE 0x20000000
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index a881d53..a06c1dc 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -221,7 +221,7 @@
#define CFG_FLASH_BASE 0x20000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_PROTECTION
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index e99e979..e4a7f9d 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -77,7 +77,7 @@
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_FLASH_BASE 0x20000000
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index f097e2c..38714cc 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -130,7 +130,7 @@
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index ac2e5d9..3b5b280 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -188,7 +188,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index ef50c7c..0221dfe 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -177,7 +177,7 @@
* Flash configuration
*/
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_BASE 0xfc000000
/* we need these despite using CFI */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index 15bf177..5145c00 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -264,7 +264,7 @@
*
*/
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index b06c0a2..d3e5ea8 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -263,7 +263,7 @@
*
*/
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 735a211..88c8fdb 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -179,7 +179,7 @@
#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 632c4c2..c27ce18 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -140,7 +140,7 @@
#endif
#define CFG_ENV_IS_IN_FLASH
#undef CFG_NO_FLASH
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index ba68605..c55766c 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -135,7 +135,7 @@
#endif
#define CFG_ENV_IS_IN_FLASH
#undef CFG_NO_FLASH
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 0e10396..8941c5e 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -183,7 +183,7 @@
#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
/* The following #defines are needed to get flash environment right */
#define CFG_MONITOR_BASE TEXT_BASE
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 14fde1a..1db962a 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -217,7 +217,7 @@
/*
* NAND Flash
*/
-#undef CFG_NAND_LEGACY
+#undef CONFIG_NAND_LEGACY
#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
#undef CFG_NAND1_BASE
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index f8e2c88..6ba0d3f 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -170,7 +170,7 @@
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index 8a220b6..ccc0d5d 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -186,7 +186,7 @@
#define CFG_FLASH_BASE 0xFF800000
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index ac5847c..ac68c86 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -202,7 +202,7 @@
*----------------------------------------------------------------------*/
#define CFG_FLASH_BASE 0xFC000000
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index 3b1b4ab..1d9c05b 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -169,7 +169,7 @@
#else
/* REVISIT: This doesn't work on ADS GCPlus just yet: */
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index ffe7671..942609f 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -208,7 +208,7 @@
/*** CFI CONFIG ***/
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
/* Bypass cache when reading regs from flash memory */
#define CFG_FLASH_CFI_BYPASS_READ
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 7b1d582..ae25fb2 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -196,7 +196,7 @@
/*** CFI CONFIG ***/
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
/* Bypass cache when reading regs from flash memory */
#define CFG_FLASH_CFI_BYPASS_READ
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 6fe2b7c..f019bb4 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -172,7 +172,7 @@
/*** CFI CONFIG ***/
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
/* Bypass cache when reading regs from flash memory */
#define CFG_FLASH_CFI_BYPASS_READ
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 3fb8eb3..f880a7b 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -202,7 +202,7 @@
/*** CFI CONFIG ***/
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#endif
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 406ce3d..e5af9a6 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -199,7 +199,7 @@
/*** CFI CONFIG ***/
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#endif
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index 13b0358..d99ac53 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -105,7 +105,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY 1
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index 2080868..54d6721 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -351,7 +351,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY 1
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index ad7cf76..205f5cc 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -155,7 +155,7 @@
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index ec4ed1e..c476333 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -158,7 +158,7 @@
* CFI FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 7d6aaa1..237f361 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -164,7 +164,7 @@
* CFI FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 6ec92c3..efa2802 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -160,7 +160,7 @@
* Flash configuration
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_BASE 0xffe00000
#define CFG_FLASH_SIZE 0x00200000
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index b7c43fe..6b73abe 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -181,7 +181,7 @@
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index 05dc841..d4e4871 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -210,7 +210,7 @@
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index c985927..af88a3f 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -191,7 +191,7 @@
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index f07e470..5dcca75 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -54,7 +54,6 @@
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#undef CONFIG_SHOW_BOOT_PROGRESS
/*-----------------------------------------------------------------------
@@ -208,7 +207,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 7dcce83..e775e60 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -153,7 +153,7 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#ifndef __ASSEMBLY__
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 9c1a3a4..a475f97 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -131,7 +131,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -233,39 +233,124 @@
#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MCOPT1 0x04322000
+#define CFG_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
+ SDRAM_MCOPT1_8_BANKS | \
+ SDRAM_MCOPT1_DDR2_TYPE | \
+ SDRAM_MCOPT1_QDEP | \
+ SDRAM_MCOPT1_DCOO_DISABLED)
#define CFG_SDRAM0_MCOPT2 0x00000000
-#define CFG_SDRAM0_MODT0 0x01800000
+#define CFG_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
+ SDRAM_MODT_EB0R_ENABLE)
#define CFG_SDRAM0_MODT1 0x00000000
-#define CFG_SDRAM0_CODT 0x0080f837
-#define CFG_SDRAM0_RTR 0x06180000
-#define CFG_SDRAM0_INITPLR0 0xa8380000
-#define CFG_SDRAM0_INITPLR1 0x81900400
-#define CFG_SDRAM0_INITPLR2 0x81020000
-#define CFG_SDRAM0_INITPLR3 0x81030000
-#define CFG_SDRAM0_INITPLR4 0x81010404
-#define CFG_SDRAM0_INITPLR5 0x81000542
-#define CFG_SDRAM0_INITPLR6 0x81900400
-#define CFG_SDRAM0_INITPLR7 0x8D080000
-#define CFG_SDRAM0_INITPLR8 0x8D080000
-#define CFG_SDRAM0_INITPLR9 0x8D080000
-#define CFG_SDRAM0_INITPLR10 0x8D080000
-#define CFG_SDRAM0_INITPLR11 0x81000442
-#define CFG_SDRAM0_INITPLR12 0x81010780
-#define CFG_SDRAM0_INITPLR13 0x81010400
-#define CFG_SDRAM0_INITPLR14 0x00000000
-#define CFG_SDRAM0_INITPLR15 0x00000000
-#define CFG_SDRAM0_RQDC 0x80000038
-#define CFG_SDRAM0_RFDC 0x00000209
-#define CFG_SDRAM0_RDCC 0x40000000
-#define CFG_SDRAM0_DLCR 0x030000a5
-#define CFG_SDRAM0_CLKTR 0x80000000
+#define CFG_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
+ SDRAM_CODT_CKLZ_36OHM | \
+ SDRAM_CODT_DQS_1_8_V_DDR2 | \
+ SDRAM_CODT_IO_NMODE)
+#define CFG_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
+#define CFG_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(80) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CFG_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CFG_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CFG_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
+ SDRAM_INITPLR_IMA_ENCODE(0))
+#define CFG_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_75OHM))
+#define CFG_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+ JEDEC_MA_MR_BLEN_4 | \
+ JEDEC_MA_MR_DLL_RESET))
+#define CFG_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(0x0) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CFG_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+ JEDEC_MA_MR_BLEN_4))
+#define CFG_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CFG_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CFG_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
+#define CFG_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
+#define CFG_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
+ SDRAM_RQDC_RQFD_ENCODE(56))
+#define CFG_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
+#define CFG_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
+#define CFG_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
+ SDRAM_DLCR_DLCS_CONT_DONE | \
+ SDRAM_DLCR_DLCV_ENCODE(165))
+#define CFG_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
#define CFG_SDRAM0_WRDTR 0x00000000
-#define CFG_SDRAM0_SDTR1 0x80201000
-#define CFG_SDRAM0_SDTR2 0x32204232
-#define CFG_SDRAM0_SDTR3 0x080b0d1a
-#define CFG_SDRAM0_MMODE 0x00000442
-#define CFG_SDRAM0_MEMODE 0x00000404
+#define CFG_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
+ SDRAM_SDTR1_RTW_2_CLK | \
+ SDRAM_SDTR1_RTRO_1_CLK)
+#define CFG_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
+ SDRAM_SDTR2_WTR_2_CLK | \
+ SDRAM_SDTR2_XSNR_32_CLK | \
+ SDRAM_SDTR2_WPC_4_CLK | \
+ SDRAM_SDTR2_RPC_2_CLK | \
+ SDRAM_SDTR2_RP_3_CLK | \
+ SDRAM_SDTR2_RRD_2_CLK)
+#define CFG_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
+ SDRAM_SDTR3_RC_ENCODE(11) | \
+ SDRAM_SDTR3_XCS | \
+ SDRAM_SDTR3_RFC_ENCODE(26))
+#define CFG_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
+ SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
+ SDRAM_MMODE_BLEN_4)
+#define CFG_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
+ SDRAM_MEMODE_RTT_75OHM)
/*-----------------------------------------------------------------------
* I2C
@@ -290,6 +375,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 4ca4ed0..a887446 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -110,7 +110,7 @@
* FLASH related
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index 569800a..819e456 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -142,7 +142,7 @@
#define CFG_BOOTMAPSZ (8 << 20)
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_PROTECTION
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index bc64294..e5a0fb9 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -434,7 +434,7 @@
* FLASH organization
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#undef CFG_FLASH_PROTECTION
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 2f3a066..3d135c4 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -124,7 +124,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH0 0xFC000000
#define CFG_FLASH1 0xF8000000
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index e4be1ed..bc94cf4 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -57,7 +57,7 @@
* Hardware drivers
*/
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_PROTECTION /*for Intel P30 Flash*/
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 65b240e..cfc6fdc 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -125,7 +125,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -223,6 +223,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index e4c3f72..f512847 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -211,7 +211,7 @@
#define CFG_FLASH_SIZE 0x04000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h
index 4e9645e..6adba96 100644
--- a/include/configs/mcu25.h
+++ b/include/configs/mcu25.h
@@ -105,7 +105,7 @@
/* Use common CFI driver */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY 1
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 8dfb9aa..75040fe 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -203,7 +203,7 @@
#define CONFIG_ENV_OVERWRITE 1
#endif
-#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#if 0
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 59ff96b..5fe3075 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -153,7 +153,7 @@
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_SIZE 32
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h
index 9cbc9cc..6f1c640 100644
--- a/include/configs/mgsuvd.h
+++ b/include/configs/mgsuvd.h
@@ -189,7 +189,7 @@
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_SIZE 32
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 7e0df87..36a42ba 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -154,7 +154,7 @@
#define CFG_FLASH_BASE XILINX_FLASH_START
#define CFG_FLASH_SIZE XILINX_FLASH_SIZE
#define CFG_FLASH_CFI 1
- #define CFG_FLASH_CFI_DRIVER 1
+ #define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
diff --git a/include/configs/ml507.h b/include/configs/ml507.h
new file mode 100644
index 0000000..c653a51
--- /dev/null
+++ b/include/configs/ml507.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/*
+#define DEBUG
+#define ET_DEBUG
+*/
+ /*CPU*/
+#define CONFIG_XILINX_ML507 1
+#define CONFIG_XILINX_440 1
+#define CONFIG_440 1
+#define CONFIG_4xx 1
+#include "../board/xilinx/ml507/xparameters.h"
+
+/*Mem Map*/
+#define CFG_SDRAM_BASE 0x0
+#define CFG_SDRAM_SIZE_MB 256
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN ( 192 * 1024 )
+#define CFG_MALLOC_LEN ( CFG_ENV_SIZE + 128 * 1024 )
+
+/*Uart*/
+#define CONFIG_XILINX_UARTLITE
+#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
+#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE }
+#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
+
+/*Cmd*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMLS
+
+/*Env*/
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SIZE 0x20000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_OFFSET 0x340000
+#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
+
+/*Misc*/
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
+#define CFG_LOAD_ADDR 0x00400000 /* default load address */
+#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_LOOPW /* enable loopw command */
+#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CFG_HUSH_PARSER /* Use the HUSH parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
+#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */
+#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
+
+/*Stack*/
+#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+/*Speed*/
+#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
+
+/*Flash*/
+#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
+#define CFG_FLASH_SIZE (32*1024*1024)
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_EMPTY_INFO 1
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 259
+#define CFG_FLASH_PROTECTION
+#define MTDIDS_DEFAULT "nor0=ml507-flash"
+#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 3d1eafe..f2a35ee 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -263,7 +263,7 @@
* Flash configuration
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_BASE 0xff000000
#define CFG_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 2f24967..d379b1f 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -374,7 +374,7 @@
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_WRITE_SWAPPED_DATA
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 0fc0b97..3df6e39 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -67,7 +67,7 @@
/* Flash */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_BASE 0xA0000000
#define CFG_MAX_FLASH_SECT 256
@@ -86,7 +86,7 @@
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
/* UART */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#endif /* __MPR2_H */
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 5e79a27..1c3d277 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -63,7 +63,7 @@
#define CFG_BAUDRATE_TABLE { 115200 }
/* SCIF */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE
@@ -82,7 +82,7 @@
/* FLASH */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 7298e55..3809e71 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -62,7 +62,7 @@
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
/* SCIF */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */
#undef CFG_CONSOLE_OVERWRITE_ROUTINE
@@ -90,7 +90,7 @@
/* FLASH */
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 3000c77..4356a67 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -42,7 +42,7 @@
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ENV
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_SCIF1 1
#define BOARD_LATE_INIT 1
@@ -86,7 +86,7 @@
#define CFG_RX_ETH_BUFFER (8)
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_CFI_BROKEN_TABLE
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
diff --git a/include/configs/munices.h b/include/configs/munices.h
index e0046ec..cea2834 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -133,7 +133,7 @@
*/
#define CFG_FLASH_BASE 0xFF000000
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x01000000 /* 16 MByte */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 37ba872..9ede764 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -185,7 +185,7 @@
* CFI FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index f30cb46..746a56e 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -56,7 +56,7 @@
/*
* Hardware drivers
*/
-#define CFG_NS9750_UART 1 /* use on-chip UART */
+#define CONFIG_NS9750_UART 1 /* use on-chip UART */
#define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */
/*
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
index 0be46ea..46b30e0 100644
--- a/include/configs/omap1510inn.h
+++ b/include/configs/omap1510inn.h
@@ -179,7 +179,7 @@
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 88a3f6e..afdcba4 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -151,7 +151,7 @@
/*
* Board NAND Info.
*/
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
@@ -283,7 +283,7 @@
* CFI FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index e3bde4f..1c44ce0 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -174,7 +174,7 @@
* FLASH driver setup
*/
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 0913b14..33a94bc 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -128,7 +128,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 82f2391..ac0d83a 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -279,7 +279,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index aca70dc..889207a 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -218,7 +218,7 @@
*/
#if defined(CONFIG_SCPU)
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
#endif
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index dee6643..6f1195b 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -452,7 +452,7 @@
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index a2f3650..179ff7a 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -333,7 +333,7 @@
* FLASH and environment organization
*/
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_MONITOR_BASE 0
#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 3dfd218..19e627b 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -146,7 +146,7 @@
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 128
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_ENV_IS_IN_FLASH 1
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 622a5d4..d464734 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -182,7 +182,7 @@
* FLASH organization
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
index cc261c3..34a1ea6 100644
--- a/include/configs/quantum.h
+++ b/include/configs/quantum.h
@@ -170,13 +170,13 @@
#define CFG_FLASH_BASE 0xFF000000
#if 1
- #define CFG_FLASH_CFI_DRIVER
+ #define CONFIG_FLASH_CFI_DRIVER
#else
- #undef CFG_FLASH_CFI_DRIVER
+ #undef CONFIG_FLASH_CFI_DRIVER
#endif
-#ifdef CFG_FLASH_CFI_DRIVER
+#ifdef CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI 1
#undef CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index e269336..06ede3e 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -26,7 +26,7 @@
#define CONFIG_DOS_PARTITION
/* SCIF */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF1 1
#define BOARD_LATE_INIT 1
@@ -65,7 +65,7 @@
* NOR Flash ( Spantion S29GL256P )
*/
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_BASE (0xA0000000)
#define CFG_MAX_FLASH_BANKS (1)
#define CFG_MAX_FLASH_SECT 256
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 4c82c5a..77881e7 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -49,7 +49,7 @@
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF0 1
@@ -106,7 +106,7 @@
#define CFG_RX_ETH_BUFFER (8)
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_CFI_BROKEN_TABLE
#undef CFG_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
new file mode 100644
index 0000000..32ed574
--- /dev/null
+++ b/include/configs/redwood.h
@@ -0,0 +1,186 @@
+/*
+ * Configuration for AMCC 460SX Ref (redwood)
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1 /* ... PPC460 family */
+#define CONFIG_460SX 1 /* ... PPC460 family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+/*-----------------------------------------------------------------------
+ * Include common defines/options for all AMCC boards
+ *----------------------------------------------------------------------*/
+#define CONFIG_HOSTNAME redwood
+
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
+#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
+
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
+#define CFG_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
+#define CFG_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x01000000
+
+#define CFG_PCIE0_XCFGBASE 0xb0000000
+#define CFG_PCIE1_XCFGBASE 0xb2000000
+#define CFG_PCIE2_XCFGBASE 0xb4000000
+#define CFG_PCIE0_CFGBASE 0xb6000000
+#define CFG_PCIE1_CFGBASE 0xb8000000
+#define CFG_PCIE2_CFGBASE 0xba000000
+
+/* PCIe mapped UTL registers */
+#define CFG_PCIE0_REGBASE 0xd0000000
+#define CFG_PCIE1_REGBASE 0xd0010000
+#define CFG_PCIE2_REGBASE 0xd0020000
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+
+#define CFG_FPGA_BASE 0xe2000000 /* epld */
+#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define CONFIG_DDR_ECC 1 /* with ECC support */
+
+#define CFG_SPD_MAX_DIMMS 2
+
+/* SPD i2c spd addresses */
+#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
+#define IIC0_DIMM0_ADDR 0x53
+#define IIC0_DIMM1_ADDR 0x52
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_SPEED 400000 /* I2C speed */
+
+#define IIC0_BOOTPROM_ADDR 0x50
+#define IIC0_ALT_BOOTPROM_ADDR 0x54
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
+
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+/*----------------------------------------------------------------------------+
+| Commands in addition to amcc-common.h
++----------------------------------------------------------------------------*/
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_M88E1141_PHY 1 /* Enable phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
+
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR 0xfffa0000
+#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*---------------------------------------------------------------------------*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 7481556..261229c 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -133,7 +133,7 @@
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
#define CFG_FLASH_SIZE 8 /* flash size in MB */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 358fc02..b4238e5 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -178,7 +178,7 @@
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 6345cce..b244eef 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -290,7 +290,7 @@
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION /* use hardware protection */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index ebfcb46..efc787e 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -223,7 +223,7 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_WRITE_SWAPPED_DATA
#define CFG_FLASH_EMPTY_INFO
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 87311ea..659f74e 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -397,7 +397,7 @@ extern unsigned long offsetOfEnvironment;
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 0e830b8..e29655e 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -178,7 +178,7 @@
#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
#define CFG_SATA_MAX_DEVICE (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
-#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
+#define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */
/************************************************************
* DISK Partition support
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 730037e..18675c2 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -123,7 +123,7 @@
* FLASH related
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 5a65663..1306702 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -52,7 +52,7 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF2 1
@@ -89,7 +89,7 @@
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/* Timeout for Flash erase operations (in ms) */
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index 3e47eb8..1d202d4 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -196,7 +196,7 @@
/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 1627413..8a64942 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -139,7 +139,7 @@
#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 18f5533..f4e4608 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -189,7 +189,7 @@
#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
CFG_FLASH_BASE+0x04000000 } /* two banks */
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index f46c464..daaa23f 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -180,7 +180,7 @@
*/
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 69d2d67..93798a4 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -287,7 +287,7 @@
/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index a1e9789..4f1c156 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -98,7 +98,7 @@
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index fcafba5..37a52cf 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -213,7 +213,7 @@
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@@ -449,7 +449,7 @@
/****************************************************************/
/* NAND */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 70336b5..bbbfa15 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -151,7 +151,7 @@
#define CONFIG_CMD_DATE
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index ba42192..81133bb 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -89,7 +89,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index f77dd14..6367f87 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -293,7 +293,7 @@
*/
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_MONITOR_BASE 0
#define CFG_MONITOR_LEN 0x40000
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index e74b1bb..106e6f2 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -230,7 +230,7 @@
* FLASH organization
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index 042750e..a186188 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -168,7 +168,7 @@
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index c203522..3574548 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -201,7 +201,7 @@
* Flash configuration - use CFI driver
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_CFI_AMD_RESET 1
#define CFG_FLASH_BASE 0xFF000000
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index f104886..1a125f1 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -202,7 +202,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 8c827af..20917ee 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -60,7 +60,7 @@
* FLASH organization
*/
#define CFG_FLASH_CFI /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_BASE PHYS_FLASH_1
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 891b515..cb2042c 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -105,7 +105,7 @@
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index cd120df..b50cba5 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -210,7 +210,7 @@
* FLASH organization
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h
index d9eb911..e7aa26d 100644
--- a/include/linux/mtd/nand_ids.h
+++ b/include/linux/mtd/nand_ids.h
@@ -28,7 +28,7 @@
#ifndef __LINUX_MTD_NAND_IDS_H
#define __LINUX_MTD_NAND_IDS_H
-#ifndef CFG_NAND_LEGACY
+#ifndef CONFIG_NAND_LEGACY
#error This module is for the legacy NAND support
#endif
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
index bb66e45..99eafbb 100644
--- a/include/linux/mtd/nand_legacy.h
+++ b/include/linux/mtd/nand_legacy.h
@@ -36,7 +36,7 @@
#ifndef __LINUX_MTD_NAND_LEGACY_H
#define __LINUX_MTD_NAND_LEGACY_H
-#ifndef CFG_NAND_LEGACY
+#ifndef CONFIG_NAND_LEGACY
#error This module is for the legacy NAND support
#endif
diff --git a/include/nand.h b/include/nand.h
index 764e9f9..4c2b76d 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -26,7 +26,7 @@
extern void nand_init(void);
-#ifndef CFG_NAND_LEGACY
+#ifndef CONFIG_NAND_LEGACY
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@@ -128,5 +128,5 @@ void board_nand_select_device(struct nand_chip *nand, int chip);
__attribute__((noreturn)) void nand_boot(void);
-#endif /* !CFG_NAND_LEGACY */
+#endif /* !CONFIG_NAND_LEGACY */
#endif
diff --git a/include/ppc405.h b/include/ppc405.h
index 2231a5f..f19b67f 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -119,367 +119,6 @@
#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
-/******************************************************************************
- * Universal interrupt controller
- ******************************************************************************/
-#define UIC_SR 0x0 /* UIC status */
-#define UIC_ER 0x2 /* UIC enable */
-#define UIC_CR 0x3 /* UIC critical */
-#define UIC_PR 0x4 /* UIC polarity */
-#define UIC_TR 0x5 /* UIC triggering */
-#define UIC_MSR 0x6 /* UIC masked status */
-#define UIC_VR 0x7 /* UIC vector */
-#define UIC_VCR 0x8 /* UIC vector configuration */
-
-#define UIC_DCR_BASE 0xc0
-#define UIC0_DCR_BASE UIC_DCR_BASE
-#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
-#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
-#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
-#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
-#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
-#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
-#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
-#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
-#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
-
-#if defined(CONFIG_405EX)
-#define uic0sr uicsr /* UIC status */
-#define uic0srs uicsrs /* UIC status set */
-#define uic0er uicer /* UIC enable */
-#define uic0cr uiccr /* UIC critical */
-#define uic0pr uicpr /* UIC polarity */
-#define uic0tr uictr /* UIC triggering */
-#define uic0msr uicmsr /* UIC masked status */
-#define uic0vr uicvr /* UIC vector */
-#define uic0vcr uicvcr /* UIC vector configuration*/
-
-#define UIC_DCR_BASE1 0xd0
-#define UIC1_DCR_BASE 0xd0
-#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
-#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
-#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
-#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
-#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
-#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
-#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
-#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
-#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
-
-#define UIC_DCR_BASE2 0xe0
-#define UIC2_DCR_BASE 0xe0
-#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
-#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
-#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
-#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
-#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
-#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
-#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
-#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
-#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
-#endif
-
-/*-----------------------------------------------------------------------------+
-| Universal interrupt controller interrupts
-+-----------------------------------------------------------------------------*/
-#if defined(CONFIG_405EZ)
-#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
-#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
-#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
-#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
-#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
-#define UIC_UART0 0x04000000 /* UART 0 */
-#define UIC_UART1 0x02000000 /* UART 1 */
-#define UIC_CAN0 0x01000000 /* CAN 0 */
-#define UIC_CAN1 0x00800000 /* CAN 1 */
-#define UIC_SPI 0x00400000 /* SPI */
-#define UIC_IIC 0x00200000 /* IIC */
-#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
-#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
-#define UIC_USBH1 0x00040000 /* USB Host 1 */
-#define UIC_USBH2 0x00020000 /* USB Host 2 */
-#define UIC_USBDEV 0x00010000 /* USB Device */
-#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
-#define UIC_ENET1 0x00008000 /* dummy define */
-#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
-
-#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
-#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
-#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
-#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
-
-#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
-#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
-#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
-#define UIC_NAND 0x00000200 /* NAND Flash controller */
-#define UIC_ADC 0x00000100 /* ADC */
-#define UIC_DAC 0x00000080 /* DAC */
-#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
-#define UIC_RESERVED0 0x00000020 /* Reserved */
-#define UIC_EXT0 0x00000010 /* External interrupt 0 */
-#define UIC_EXT1 0x00000008 /* External interrupt 1 */
-#define UIC_EXT2 0x00000004 /* External interrupt 2 */
-#define UIC_EXT3 0x00000002 /* External interrupt 3 */
-#define UIC_EXT4 0x00000001 /* External interrupt 4 */
-
-#elif defined(CONFIG_405EX)
-
-/* UIC 0 */
-#define UIC_U0 0x80000000 /* */
-#define UIC_U1 0x40000000 /* */
-#define UIC_IIC0 0x20000000 /* */
-#define UIC_PKA 0x10000000 /* */
-#define UIC_TRNG 0x08000000 /* */
-#define UIC_EBM 0x04000000 /* */
-#define UIC_BGI 0x02000000 /* */
-#define UIC_IIC1 0x01000000 /* */
-#define UIC_SPI 0x00800000 /* */
-#define UIC_EIRQ0 0x00400000 /**/
-#define UIC_MTE 0x00200000 /*MAL Tx EOB */
-#define UIC_MRE 0x00100000 /*MAL Rx EOB */
-#define UIC_DMA0 0x00080000 /* */
-#define UIC_DMA1 0x00040000 /* */
-#define UIC_DMA2 0x00020000 /* */
-#define UIC_DMA3 0x00010000 /* */
-#define UIC_PCIE0AL 0x00008000 /* */
-#define UIC_PCIE0VPD 0x00004000 /* */
-#define UIC_RPCIE0HRST 0x00002000 /* */
-#define UIC_FPCIE0HRST 0x00001000 /* */
-#define UIC_PCIE0TCR 0x00000800 /* */
-#define UIC_PCIEMSI0 0x00000400 /* */
-#define UIC_PCIEMSI1 0x00000200 /* */
-#define UIC_SECURITY 0x00000100 /* */
-#define UIC_ENET 0x00000080 /* */
-#define UIC_ENET1 0x00000040 /* */
-#define UIC_PCIEMSI2 0x00000020 /* */
-#define UIC_EIRQ4 0x00000010 /**/
-#define UICB0_UIC2NCI 0x00000008 /* */
-#define UICB0_UIC2CI 0x00000004 /* */
-#define UICB0_UIC1NCI 0x00000002 /* */
-#define UICB0_UIC1CI 0x00000001 /* */
-
-#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
- UICB0_UIC1CI | UICB0_UIC2NCI)
-
-#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
-#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
-/* UIC 1 */
-#define UIC_MS 0x80000000 /* MAL SERR */
-#define UIC_MTDE 0x40000000 /* MAL TXDE */
-#define UIC_MRDE 0x20000000 /* MAL RXDE */
-#define UIC_PCIE0BMVC0 0x10000000 /* */
-#define UIC_PCIE0DCRERR 0x08000000 /* */
-#define UIC_EBC 0x04000000 /* */
-#define UIC_NDFC 0x02000000 /* */
-#define UIC_PCEI1DCRERR 0x01000000 /* */
-#define UIC_GPTCMPT8 0x00800000 /* */
-#define UIC_GPTCMPT9 0x00400000 /* */
-#define UIC_PCIE1AL 0x00200000 /* */
-#define UIC_PCIE1VPD 0x00100000 /* */
-#define UIC_RPCE1HRST 0x00080000 /* */
-#define UIC_FPCE1HRST 0x00040000 /* */
-#define UIC_PCIE1TCR 0x00020000 /* */
-#define UIC_PCIE1VC0 0x00010000 /* */
-#define UIC_GPTCMPT3 0x00008000 /* */
-#define UIC_GPTCMPT4 0x00004000 /* */
-#define UIC_EIRQ7 0x00002000 /* */
-#define UIC_EIRQ8 0x00001000 /* */
-#define UIC_EIRQ9 0x00000800 /* */
-#define UIC_GPTCMP5 0x00000400 /* */
-#define UIC_GPTCMP6 0x00000200 /* */
-#define UIC_GPTCMP7 0x00000100 /* */
-#define UIC_SROM 0x00000080 /* SERIAL ROM*/
-#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
-#define UIC_EIRQ2 0x00000020 /* */
-#define UIC_EIRQ5 0x00000010 /* */
-#define UIC_EIRQ6 0x00000008 /* */
-#define UIC_EMAC0WAKE 0x00000004 /* */
-#define UIC_EIRQ1 0x00000002 /* */
-#define UIC_EMAC1WAKE 0x00000001 /* */
-#define UIC_MAL_SERR UIC_MS /* MAL SERR */
-#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
-#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
-/* UIC 2 */
-#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
-#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
-#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
-#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
-#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
-#define UIC_DDRMCUE 0x04000000 /* */
-#define UIC_DDRMCCE 0x02000000 /* */
-#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
-#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
-#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
-#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
-#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
-#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
-#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
-#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
-#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
-#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
-#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
-#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
-#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
-#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
-#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
-#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
-#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
-#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
-#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
-#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
-#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
-#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
-#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
-#define UIC_USBWAKE 0x00000002 /* USB wakup*/
-#define UIC_USBOTG 0x00000001 /* USB OTG*/
-#define UIC_ETH0 UIC_ENET
-#define UIC_ETH1 UIC_ENET1
-
-#else /* !defined(CONFIG_405EZ) */
-
-#define UIC_UART0 0x80000000 /* UART 0 */
-#define UIC_UART1 0x40000000 /* UART 1 */
-#define UIC_IIC 0x20000000 /* IIC */
-#define UIC_EXT_MAST 0x10000000 /* External Master */
-#define UIC_PCI 0x08000000 /* PCI write to command reg */
-#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
-#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
-#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
-#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
-#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
-#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
-#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
-#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
-#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
-#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
-#define UIC_ENET 0x00010000 /* Ethernet0 */
-#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
-#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
-#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
-#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
-#define UIC_EXT0 0x00000040 /* External interrupt 0 */
-#define UIC_EXT1 0x00000020 /* External interrupt 1 */
-#define UIC_EXT2 0x00000010 /* External interrupt 2 */
-#define UIC_EXT3 0x00000008 /* External interrupt 3 */
-#define UIC_EXT4 0x00000004 /* External interrupt 4 */
-#define UIC_EXT5 0x00000002 /* External interrupt 5 */
-#define UIC_EXT6 0x00000001 /* External interrupt 6 */
-#endif /* defined(CONFIG_405EZ) */
-
-/******************************************************************************
- * External Bus Controller (EBC)
- *****************************************************************************/
-
-/* Bank Configuration Register */
-#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
-#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \
- EBC_BXCR_BAS_MASK) << 0)
-#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
-#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
-#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
-#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
-#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
-#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
-#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
-#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
-#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
-#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
-#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
-#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
-#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
-#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
-#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
-#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
-
-/* Bank Access Parameter Register */
-#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
-#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
-#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \
- (static_cast(unsigned long, n)) \
- & 0xFF)
-#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \
- (static_cast(unsigned long, n)) \
- & 0x1F)
-#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \
- (static_cast(unsigned long, n)) \
- & 0x7)
-#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
-#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
-#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
-#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
-#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
-#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \
- (static_cast(unsigned long, n)) \
- & 0x3)
-#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \
- (static_cast(unsigned long, n)) \
- & 0x3)
-#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \
- (static_cast(unsigned long, n)) \
- & 0x3)
-#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \
- (static_cast(unsigned long, n)) \
- & 0x3)
-#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \
- (static_cast(unsigned long, n)) \
- & 0x7)
-#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
-#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
-#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
-#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
-#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
-#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
-#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
-#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
-
-/* Configuration Register */
-#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
-#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
-#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
-#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
-#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
-#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
-#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
-#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
-#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
-#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
-#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
-#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
-#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0)
-#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
-#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
-#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
-#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \
- (static_cast(unsigned long, n)) \
- & 0x1F)
-#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
-#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
-#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
-#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
-#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
-
#ifndef CONFIG_405EP
/******************************************************************************
* Decompression Controller
@@ -1254,6 +893,42 @@
#if defined(CONFIG_405EX)
#define SDR0_SRST 0x0200
+/*
+ * Software Reset Register
+ */
+#define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
+#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
+#define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
+#define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
+#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
+#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
+#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
+#define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
+#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
+#define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
+#define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
+#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
+#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
+#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
+#define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
+#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
+#define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
+#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
+#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
+#define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
+#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
+#define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
+#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
+#define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
+#define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
+#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
+#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
+#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
+#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
+#define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
+#define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
+#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
+
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
diff --git a/include/ppc440.h b/include/ppc440.h
index c581f1b..92db15f 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -77,7 +77,6 @@
#define tbl 0x11c /* time base lower (supervisor)*/
#define tbu 0x11d /* time base upper (supervisor)*/
#define pir 0x11e /* processor id register */
-/*#define pvr 0x11f processor version register */
#define dbsr 0x130 /* debug status register */
#define dbcr0 0x134 /* debug control register 0 */
#define dbcr1 0x135 /* debug control register 1 */
@@ -268,86 +267,6 @@
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
-/******************************************************************************
- * PCI express defines
- ******************************************************************************/
-#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
-#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
-#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
-#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
-#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
-#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
-#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
-#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
-#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
-#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
-#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
-#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
-#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
-#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
-#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
-#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
-#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
-#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
-#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
-#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
-#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
-#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
-#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
-#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
-#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
-#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
-#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
-#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
-#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
-#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
-#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
-#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
-#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
-
-#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
-#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
-#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
-#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
-#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
-#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
-#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
-#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
-#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
-#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
-#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
-#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
-#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
-#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
-#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
-#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
-#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
-#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
-#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
-#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
-#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
-#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
-#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
-#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
-#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
-#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
-#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
-#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
-#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
-#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
-#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
-#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
-#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
-#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
-#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
-#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
-#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
-#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
-#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
-#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
-#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
-#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
-#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
#endif /* CONFIG_440SPE */
/*-----------------------------------------------------------------------------
@@ -749,7 +668,8 @@
+----------------------------------------------------------------------------*/
#if defined (CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
@@ -837,7 +757,8 @@
/*-----------------------------------------------------------------------------
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
#define CNTRL_DCR_BASE 0x160
#else
#define CNTRL_DCR_BASE 0x0b0
@@ -863,193 +784,6 @@
#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
/*-----------------------------------------------------------------------------
- | Universal interrupt controller
- +----------------------------------------------------------------------------*/
-#define UIC_SR 0x0 /* UIC status */
-#define UIC_ER 0x2 /* UIC enable */
-#define UIC_CR 0x3 /* UIC critical */
-#define UIC_PR 0x4 /* UIC polarity */
-#define UIC_TR 0x5 /* UIC triggering */
-#define UIC_MSR 0x6 /* UIC masked status */
-#define UIC_VR 0x7 /* UIC vector */
-#define UIC_VCR 0x8 /* UIC vector configuration */
-
-#define UIC0_DCR_BASE 0xc0
-#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
-#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
-#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
-#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
-#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
-#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
-#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
-#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
-
-#define UIC1_DCR_BASE 0xd0
-#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
-#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
-#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
-#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
-#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
-#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
-#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
-#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
-
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UIC2_DCR_BASE 0xe0
-#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
-#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
-#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
-#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
-#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
-#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
-#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
-#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
-#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
-
-#define UIC3_DCR_BASE 0xf0
-#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
-#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
-#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
-#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
-#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
-#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
-#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
-#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
-#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_440GX)
-#define UIC2_DCR_BASE 0x210
-#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
-#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
-#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
-#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
-#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
-#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
-#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
-#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
-
-
-#define UIC_DCR_BASE 0x200
-#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
-#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
-#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
-#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
-#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
-#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
-#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
-#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
-#endif /* CONFIG_440GX */
-
-/* The following is for compatibility with 405 code */
-#define uicsr uic0sr
-#define uicer uic0er
-#define uiccr uic0cr
-#define uicpr uic0pr
-#define uictr uic0tr
-#define uicmsr uic0msr
-#define uicvr uic0vr
-#define uicvcr uic0vcr
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
-/*----------------------------------------------------------------------------+
-| Clock / Power-on-reset DCR's.
-+----------------------------------------------------------------------------*/
-#define CPR0_CLKUPD 0x20
-#define CPR0_CLKUPD_BSY_MASK 0x80000000
-#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
-#define CPR0_CLKUPD_BSY_BUSY 0x80000000
-#define CPR0_CLKUPD_CUI_MASK 0x80000000
-#define CPR0_CLKUPD_CUI_DISABLE 0x00000000
-#define CPR0_CLKUPD_CUI_ENABLE 0x80000000
-#define CPR0_CLKUPD_CUD_MASK 0x40000000
-#define CPR0_CLKUPD_CUD_DISABLE 0x00000000
-#define CPR0_CLKUPD_CUD_ENABLE 0x40000000
-
-#define CPR0_PLLC 0x40
-#define CPR0_PLLC_RST_MASK 0x80000000
-#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
-#define CPR0_PLLC_RST_PLLRESET 0x80000000
-#define CPR0_PLLC_ENG_MASK 0x40000000
-#define CPR0_PLLC_ENG_DISABLE 0x00000000
-#define CPR0_PLLC_ENG_ENABLE 0x40000000
-#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
-#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
-#define CPR0_PLLC_SRC_MASK 0x20000000
-#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
-#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
-#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
-#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
-#define CPR0_PLLC_SEL_MASK 0x07000000
-#define CPR0_PLLC_SEL_PLLOUT 0x00000000
-#define CPR0_PLLC_SEL_CPU 0x01000000
-#define CPR0_PLLC_SEL_EBC 0x05000000
-#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
-#define CPR0_PLLC_TUNE_MASK 0x000003FF
-#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-
-#define CPR0_PLLD 0x60
-#define CPR0_PLLD_FBDV_MASK 0x1F000000
-#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
-#define CPR0_PLLD_FWDVA_MASK 0x000F0000
-#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
-#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
-#define CPR0_PLLD_FWDVB_MASK 0x00000700
-#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
-#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
-#define CPR0_PLLD_LFBDV_MASK 0x0000003F
-#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
-#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
-
-#define CPR0_PRIMAD 0x80
-#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
-#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
-
-#define CPR0_PRIMBD 0xA0
-#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
-#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
-
-#define CPR0_OPBD 0xC0
-#define CPR0_OPBD_OPBDV0_MASK 0x03000000
-#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
-
-#define CPR0_PERD 0xE0
-#if !defined(CONFIG_440EPX)
-#define CPR0_PERD_PERDV0_MASK 0x03000000
-#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
-#endif
-
-#define CPR0_MALD 0x100
-#define CPR0_MALD_MALDV0_MASK 0x03000000
-#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
-
-#define CPR0_ICFG 0x140
-#define CPR0_ICFG_RLI_MASK 0x80000000
-#define CPR0_ICFG_RLI_RESETCPR 0x00000000
-#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
-#define CPR0_ICFG_ICS_MASK 0x00000007
-#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
-#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
-
-/************************/
-/* IIC defines */
-/************************/
-#define IIC0_MMIO_BASE 0xA0000400
-#define IIC1_MMIO_BASE 0xA0000500
-
-#endif /* CONFIG_440SP */
-
-/*-----------------------------------------------------------------------------
| DMA
+----------------------------------------------------------------------------*/
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
@@ -1136,708 +870,6 @@
#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
#endif /* CONFIG_440GX */
-
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller 0 interrupts (UIC0)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440SP)
-#define UIC_U0 0x80000000 /* UART 0 */
-#define UIC_U1 0x40000000 /* UART 1 */
-#define UIC_IIC0 0x20000000 /* IIC */
-#define UIC_IIC1 0x10000000 /* IIC */
-#define UIC_PIM 0x08000000 /* PCI0 inbound message */
-#define UIC_PCRW 0x04000000 /* PCI0 command write register */
-#define UIC_PPM 0x02000000 /* PCI0 power management */
-#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
-#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
-#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
-#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
-#define UIC_P1PM 0x00100000 /* PCI1 power management */
-#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
-#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
-#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
-#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
-#define UIC_P2PM 0x00008000 /* PCI2 power management */
-#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
-#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
-#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
-#define UIC_D0CSF 0x00000800 /* DMA0 command status */
-#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
-#define UIC_D1CSF 0x00000200 /* DMA1 command status */
-#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
-#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
-#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
-#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
-#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
-#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
-#define UIC_GPTCT 0x00000004 /* GPT count timer */
-#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
-#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
-#define UIC_U0 0x80000000 /* UART 0 */
-#define UIC_U1 0x40000000 /* UART 1 */
-#define UIC_IIC0 0x20000000 /* IIC */
-#define UIC_IIC1 0x10000000 /* IIC */
-#define UIC_PIM 0x08000000 /* PCI inbound message */
-#define UIC_PCRW 0x04000000 /* PCI command register write */
-#define UIC_PPM 0x02000000 /* PCI power management */
-#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
-#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
-#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
-#define UIC_MTE 0x00200000 /* MAL TXEOB */
-#define UIC_MRE 0x00100000 /* MAL RXEOB */
-#define UIC_D0 0x00080000 /* DMA channel 0 */
-#define UIC_D1 0x00040000 /* DMA channel 1 */
-#define UIC_D2 0x00020000 /* DMA channel 2 */
-#define UIC_D3 0x00010000 /* DMA channel 3 */
-#define UIC_RSVD0 0x00008000 /* Reserved */
-#define UIC_RSVD1 0x00004000 /* Reserved */
-#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
-#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
-#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
-#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
-#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
-#define UIC_EIR0 0x00000100 /* External interrupt 0 */
-#define UIC_EIR1 0x00000080 /* External interrupt 1 */
-#define UIC_EIR2 0x00000040 /* External interrupt 2 */
-#define UIC_EIR3 0x00000020 /* External interrupt 3 */
-#define UIC_EIR4 0x00000010 /* External interrupt 4 */
-#define UIC_EIR5 0x00000008 /* External interrupt 5 */
-#define UIC_EIR6 0x00000004 /* External interrupt 6 */
-#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
-#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define UIC_U0 0x80000000 /* UART 0 */
-#define UIC_U1 0x40000000 /* UART 1 */
-#define UIC_IIC0 0x20000000 /* IIC */
-#define UIC_KRD 0x10000000 /* Kasumi Ready for data */
-#define UIC_KDA 0x08000000 /* Kasumi Data Available */
-#define UIC_PCRW 0x04000000 /* PCI command register write */
-#define UIC_PPM 0x02000000 /* PCI power management */
-#define UIC_IIC1 0x01000000 /* IIC */
-#define UIC_SPI 0x00800000 /* SPI */
-#define UIC_EPCISER 0x00400000 /* External PCI SERR */
-#define UIC_MTE 0x00200000 /* MAL TXEOB */
-#define UIC_MRE 0x00100000 /* MAL RXEOB */
-#define UIC_D0 0x00080000 /* DMA channel 0 */
-#define UIC_D1 0x00040000 /* DMA channel 1 */
-#define UIC_D2 0x00020000 /* DMA channel 2 */
-#define UIC_D3 0x00010000 /* DMA channel 3 */
-#define UIC_UD0 0x00008000 /* UDMA irq 0 */
-#define UIC_UD1 0x00004000 /* UDMA irq 1 */
-#define UIC_UD2 0x00002000 /* UDMA irq 2 */
-#define UIC_UD3 0x00001000 /* UDMA irq 3 */
-#define UIC_HSB2D 0x00000800 /* USB2.0 Device */
-#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
-#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
-#define UIC_EIP94 0x00000100 /* Security EIP94 */
-#define UIC_ETH0 0x00000080 /* Emac 0 */
-#define UIC_ETH1 0x00000040 /* Emac 1 */
-#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
-#define UIC_EIR4 0x00000010 /* External interrupt 4 */
-#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
-#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
-#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
-#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_TXEOB UIC_MTE
-#define UIC_MAL_RXEOB UIC_MRE
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UIC_RSVD0 0x80000000 /* N/A - unused */
-#define UIC_U1 0x40000000 /* UART 1 */
-#define UIC_IIC0 0x20000000 /* IIC */
-#define UIC_IIC1 0x10000000 /* IIC */
-#define UIC_PIM 0x08000000 /* PCI inbound message */
-#define UIC_PCRW 0x04000000 /* PCI command register write */
-#define UIC_PPM 0x02000000 /* PCI power management */
-#define UIC_PCIVPD 0x01000000 /* PCI VPD */
-#define UIC_MSI0 0x00800000 /* PCI MSI level 0 */
-#define UIC_EIR0 0x00400000 /* External interrupt 0 */
-#define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */
-#define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */
-#define UIC_D0 0x00080000 /* DMA channel 0 */
-#define UIC_D1 0x00040000 /* DMA channel 1 */
-#define UIC_D2 0x00020000 /* DMA channel 2 */
-#define UIC_D3 0x00010000 /* DMA channel 3 */
-#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */
-#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */
-#define UIC_EIR1 0x00002000 /* External interrupt 1 */
-#define UIC_TRNGDA 0x00001000 /* TRNG data available */
-#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */
-#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
-#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
-#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
-#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
-#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
-#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
-#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
-#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
-#define UIC_EIP94 0x00000004 /* Security EIP94 */
-#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
-#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-
-#elif !defined(CONFIG_440SPE)
-#define UIC_U0 0x80000000 /* UART 0 */
-#define UIC_U1 0x40000000 /* UART 1 */
-#define UIC_IIC0 0x20000000 /* IIC */
-#define UIC_IIC1 0x10000000 /* IIC */
-#define UIC_PIM 0x08000000 /* PCI inbound message */
-#define UIC_PCRW 0x04000000 /* PCI command register write */
-#define UIC_PPM 0x02000000 /* PCI power management */
-#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
-#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
-#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
-#define UIC_MTE 0x00200000 /* MAL TXEOB */
-#define UIC_MRE 0x00100000 /* MAL RXEOB */
-#define UIC_D0 0x00080000 /* DMA channel 0 */
-#define UIC_D1 0x00040000 /* DMA channel 1 */
-#define UIC_D2 0x00020000 /* DMA channel 2 */
-#define UIC_D3 0x00010000 /* DMA channel 3 */
-#define UIC_RSVD0 0x00008000 /* Reserved */
-#define UIC_RSVD1 0x00004000 /* Reserved */
-#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
-#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
-#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
-#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
-#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
-#define UIC_EIR0 0x00000100 /* External interrupt 0 */
-#define UIC_EIR1 0x00000080 /* External interrupt 1 */
-#define UIC_EIR2 0x00000040 /* External interrupt 2 */
-#define UIC_EIR3 0x00000020 /* External interrupt 3 */
-#define UIC_EIR4 0x00000010 /* External interrupt 4 */
-#define UIC_EIR5 0x00000008 /* External interrupt 5 */
-#define UIC_EIR6 0x00000004 /* External interrupt 6 */
-#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
-#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-#endif /* CONFIG_440GX */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_TXEOB UIC_MTE
-#define UIC_MAL_RXEOB UIC_MRE
-
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller 1 interrupts (UIC1)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440SP)
-#define UIC_EIR0 0x80000000 /* External interrupt 0 */
-#define UIC_MS 0x40000000 /* MAL SERR */
-#define UIC_MTDE 0x20000000 /* MAL TXDE */
-#define UIC_MRDE 0x10000000 /* MAL RXDE */
-#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
-#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
-#define UIC_MTE 0x02000000 /* MAL TXEOB */
-#define UIC_MRE 0x01000000 /* MAL RXEOB */
-#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
-#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
-#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
-#define UIC_L2C 0x00100000 /* L2 cache */
-#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
-#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
-#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
-#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
-#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
-#define UIC_EIR1 0x00004000 /* External interrupt 1 */
-#define UIC_EIR2 0x00002000 /* External interrupt 2 */
-#define UIC_EIR3 0x00001000 /* External interrupt 3 */
-#define UIC_EIR4 0x00000800 /* External interrupt 4 */
-#define UIC_EIR5 0x00000400 /* External interrupt 5 */
-#define UIC_DMAE 0x00000200 /* DMA error */
-#define UIC_I2OE 0x00000100 /* I2O error */
-#define UIC_SRE 0x00000080 /* Serial ROM error */
-#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
-#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
-#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
-#define UIC_ETH0 0x00000008 /* Ethernet 0 */
-#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
-#define UIC_ETH1 0x00000002 /* Reserved */
-#define UIC_XOR 0x00000001 /* XOR */
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
-#define UIC_MS 0x80000000 /* MAL SERR */
-#define UIC_MTDE 0x40000000 /* MAL TXDE */
-#define UIC_MRDE 0x20000000 /* MAL RXDE */
-#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
-#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
-#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
-#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
-#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
-#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
-#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
-#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
-#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
-#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
-#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
-#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
-#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
-#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
-#define UIC_PPMI 0x00004000 /* PPM interrupt status */
-#define UIC_EIR7 0x00002000 /* External interrupt 7 */
-#define UIC_EIR8 0x00001000 /* External interrupt 8 */
-#define UIC_EIR9 0x00000800 /* External interrupt 9 */
-#define UIC_EIR10 0x00000400 /* External interrupt 10 */
-#define UIC_EIR11 0x00000200 /* External interrupt 11 */
-#define UIC_EIR12 0x00000100 /* External interrupt 12 */
-#define UIC_SRE 0x00000080 /* Serial ROM error */
-#define UIC_RSVD2 0x00000040 /* Reserved */
-#define UIC_RSVD3 0x00000020 /* Reserved */
-#define UIC_PAE 0x00000010 /* PCI asynchronous error */
-#define UIC_ETH0 0x00000008 /* Ethernet 0 */
-#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
-#define UIC_ETH1 0x00000002 /* Ethernet 1 */
-#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UIC_EIR2 0x80000000 /* External interrupt 2 */
-#define UIC_U0 0x40000000 /* UART 0 */
-#define UIC_SPI 0x20000000 /* SPI */
-#define UIC_TRNGAL 0x10000000 /* TRNG alarm */
-#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
-#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
-#define UIC_NDFC 0x02000000 /* NDFC */
-#define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */
-#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
-#define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */
-#define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */
-#define UIC_L2C 0x00100000 /* L2 cache */
-#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
-#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
-#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
-#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
-#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
-#define UIC_CT5 0x00004000 /* GPT compare timer 5 */
-#define UIC_CT6 0x00002000 /* GPT compare timer 6 */
-#define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */
-#define UIC_EIR3 0x00000800 /* External interrupt 3 */
-#define UIC_EIR4 0x00000400 /* External interrupt 4 */
-#define UIC_DMAE 0x00000200 /* DMA error */
-#define UIC_I2OE 0x00000100 /* I2O error */
-#define UIC_SRE 0x00000080 /* Serial ROM error */
-#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
-#define UIC_EIR5 0x00000020 /* External interrupt 5 */
-#define UIC_EIR6 0x00000010 /* External interrupt 6 */
-#define UIC_U2 0x00000008 /* UART 2 */
-#define UIC_U3 0x00000004 /* UART 3 */
-#define UIC_EIR7 0x00000002 /* External interrupt 7 */
-#define UIC_EIR8 0x00000001 /* External interrupt 8 */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define UIC_MS 0x80000000 /* MAL SERR */
-#define UIC_MTDE 0x40000000 /* MAL TXDE */
-#define UIC_MRDE 0x20000000 /* MAL RXDE */
-#define UIC_U2 0x10000000 /* UART 2 */
-#define UIC_U3 0x08000000 /* UART 3 */
-#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
-#define UIC_NDFC 0x02000000 /* NDFC */
-#define UIC_KSLE 0x01000000 /* KASUMI slave error */
-#define UIC_CT5 0x00800000 /* GPT compare timer 5 */
-#define UIC_CT6 0x00400000 /* GPT compare timer 6 */
-#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
-#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
-#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
-#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
-#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
-#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
-#define UIC_CT0 0x00008000 /* GPT compare timer 0 */
-#define UIC_CT1 0x00004000 /* GPT compare timer 1 */
-#define UIC_EIR7 0x00002000 /* External interrupt 7 */
-#define UIC_EIR8 0x00001000 /* External interrupt 8 */
-#define UIC_EIR9 0x00000800 /* External interrupt 9 */
-#define UIC_CT2 0x00000400 /* GPT compare timer 2 */
-#define UIC_CT3 0x00000200 /* GPT compare timer 3 */
-#define UIC_CT4 0x00000100 /* GPT compare timer 4 */
-#define UIC_SRE 0x00000080 /* Serial ROM error */
-#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
-#define UIC_RSVD0 0x00000020 /* Reserved */
-#define UIC_EPCIPER 0x00000010 /* External PCI PERR */
-#define UIC_EIR0 0x00000008 /* External interrupt 0 */
-#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
-#define UIC_EIR1 0x00000002 /* External interrupt 1 */
-#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_SERR UIC_MS
-#define UIC_MAL_TXDE UIC_MTDE
-#define UIC_MAL_RXDE UIC_MRDE
-#define UIC_ENET UIC_ETH0
-
-#elif !defined(CONFIG_440SPE)
-#define UIC_MS 0x80000000 /* MAL SERR */
-#define UIC_MTDE 0x40000000 /* MAL TXDE */
-#define UIC_MRDE 0x20000000 /* MAL RXDE */
-#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
-#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
-#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
-#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
-#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
-#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
-#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
-#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
-#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
-#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
-#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
-#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
-#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
-#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
-#define UIC_PPMI 0x00004000 /* PPM interrupt status */
-#define UIC_EIR7 0x00002000 /* External interrupt 7 */
-#define UIC_EIR8 0x00001000 /* External interrupt 8 */
-#define UIC_EIR9 0x00000800 /* External interrupt 9 */
-#define UIC_EIR10 0x00000400 /* External interrupt 10 */
-#define UIC_EIR11 0x00000200 /* External interrupt 11 */
-#define UIC_EIR12 0x00000100 /* External interrupt 12 */
-#define UIC_SRE 0x00000080 /* Serial ROM error */
-#define UIC_RSVD2 0x00000040 /* Reserved */
-#define UIC_RSVD3 0x00000020 /* Reserved */
-#define UIC_PAE 0x00000010 /* PCI asynchronous error */
-#define UIC_ETH0 0x00000008 /* Ethernet 0 */
-#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
-#define UIC_ETH1 0x00000002 /* Ethernet 1 */
-#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
-#endif /* CONFIG_440SP */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_SERR UIC_MS
-#define UIC_MAL_TXDE UIC_MTDE
-#define UIC_MAL_RXDE UIC_MRDE
-#define UIC_ENET UIC_ETH0
-
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller 2 interrupts (UIC2)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
-#define UIC_ETH2 0x80000000 /* Ethernet 2 */
-#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
-#define UIC_ETH3 0x20000000 /* Ethernet 3 */
-#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
-#define UIC_TAH0 0x08000000 /* TAH 0 */
-#define UIC_TAH1 0x04000000 /* TAH 1 */
-#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
-#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
-#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
-#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
-#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
-#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
-#define UIC_IMUTO 0x00080000 /* IMU timeout */
-#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
-#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
-#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
-#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
-#define UIC_EIR13 0x00004000 /* External interrupt 13 */
-#define UIC_EIR14 0x00002000 /* External interrupt 14 */
-#define UIC_EIR15 0x00001000 /* External interrupt 15 */
-#define UIC_EIR16 0x00000800 /* External interrupt 16 */
-#define UIC_EIR17 0x00000400 /* External interrupt 17 */
-#define UIC_PCIVPD 0x00000200 /* PCI VPD */
-#define UIC_L2C 0x00000100 /* L2 Cache */
-#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
-#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
-#define UIC_RSVD26 0x00000020 /* Reserved */
-#define UIC_RSVD27 0x00000010 /* Reserved */
-#define UIC_RSVD28 0x00000008 /* Reserved */
-#define UIC_RSVD29 0x00000004 /* Reserved */
-#define UIC_RSVD30 0x00000002 /* Reserved */
-#define UIC_RSVD31 0x00000001 /* Reserved */
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UIC_TAH0 0x80000000 /* TAHOE 0 */
-#define UIC_TAH1 0x40000000 /* TAHOE 1 */
-#define UIC_EIR9 0x20000000 /* External interrupt 9 */
-#define UIC_MS 0x10000000 /* MAL SERR */
-#define UIC_MTDE 0x08000000 /* MAL TXDE */
-#define UIC_MRDE 0x04000000 /* MAL RXDE */
-#define UIC_MTE 0x02000000 /* MAL TXEOB */
-#define UIC_MRE 0x01000000 /* MAL RXEOB */
-#define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */
-#define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */
-#define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */
-#define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */
-#define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */
-#define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */
-#define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */
-#define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */
-#define UIC_ETH0 0x00008000 /* Ethernet 0 */
-#define UIC_ETH1 0x00004000 /* Ethernet 1 */
-#define UIC_ETH2 0x00002000 /* Ethernet 2 */
-#define UIC_ETH3 0x00001000 /* Ethernet 3 */
-#define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */
-#define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */
-#define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */
-#define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */
-#define UIC_EIR10 0x00000080 /* External interrupt 10 */
-#define UIC_EIR11 0x00000040 /* External interrupt 11 */
-#define UIC_RSVD2 0x00000020 /* Reserved */
-#define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */
-#define UIC_OTG 0x00000008 /* USB2.0 OTG */
-#define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */
-#define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */
-#define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
-
-#define UIC_EIR5 0x80000000 /* External interrupt 5 */
-#define UIC_EIR6 0x40000000 /* External interrupt 6 */
-#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
-#define UIC_EIR2 0x10000000 /* External interrupt 2 */
-#define UIC_EIR3 0x08000000 /* External interrupt 3 */
-#define UIC_DDR2 0x04000000 /* DDR2 sdram */
-#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
-#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
-#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
-#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
-
-#endif /* CONFIG_440GX */
-
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller Base 0 interrupts (UICB0)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
-#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
-#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
-#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
-#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
-#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
-#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
-
-#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
- UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
-#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
-#define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */
-#define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */
-#define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */
-#define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */
-
-#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
- UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
-#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
-#define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */
-#define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */
-
-#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
- UICB0_UIC1CI | UICB0_UIC2NCI)
-
-#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
-
-#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
-#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
-
-#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI)
-
-#endif /* CONFIG_440GX */
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller interrupts
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440SPE)
-/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
-/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
-#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
-#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
-#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
-#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
-#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
-#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
-
-#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
- UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller 0 interrupts (UIC0)
-+---------------------------------------------------------------------------*/
-#define UIC_U0 0x80000000 /* UART 0 */
-#define UIC_U1 0x40000000 /* UART 1 */
-#define UIC_IIC0 0x20000000 /* IIC */
-#define UIC_IIC1 0x10000000 /* IIC */
-#define UIC_PIM 0x08000000 /* PCI inbound message */
-#define UIC_PCRW 0x04000000 /* PCI command register write */
-#define UIC_PPM 0x02000000 /* PCI power management */
-#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
-#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
-#define UIC_EIR15 0x00400000 /* External intp 15 */
-#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
-#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
-#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
-#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
-#define UIC_EIR14 0x00002000 /* External interrupt 14 */
-#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
-#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
-#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
-#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
-#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
-#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
-#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
-#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
-#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
-#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
-#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller 1 interrupts (UIC1)
-+---------------------------------------------------------------------------*/
-#define UIC_EIR13 0x80000000 /* externei intp 13 */
-#define UIC_MS 0x40000000 /* MAL SERR */
-#define UIC_MTDE 0x20000000 /* MAL TXDE */
-#define UIC_MRDE 0x10000000 /* MAL RXDE */
-#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
-#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
-#define UIC_MTE 0x02000000 /* MAL TXEOB */
-#define UIC_MRE 0x01000000 /* MAL RXEOB */
-#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
-#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
-#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
-#define UIC_L2C 0x00100000 /* L2 cache */
-#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
-#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
-#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
-#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
-#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
-#define UIC_EIR12 0x00004000 /* External interrupt 12 */
-#define UIC_EIR11 0x00002000 /* External interrupt 11 */
-#define UIC_EIR10 0x00001000 /* External interrupt 10 */
-#define UIC_EIR9 0x00000800 /* External interrupt 9 */
-#define UIC_EIR8 0x00000400 /* External interrupt 8 */
-#define UIC_DMAE 0x00000200 /* dma error */
-#define UIC_I2OE 0x00000100 /* i2o error */
-#define UIC_SRE 0x00000080 /* Serial ROM error */
-#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
-#define UIC_EIR7 0x00000020 /* External interrupt 7 */
-#define UIC_EIR6 0x00000010 /* External interrupt 6 */
-#define UIC_ETH0 0x00000008 /* Ethernet 0 */
-#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
-#define UIC_ETH1 0x00000002 /* reserved */
-#define UIC_XOR 0x00000001 /* xor */
-
-/*---------------------------------------------------------------------------+
-| Universal interrupt controller 2 interrupts (UIC2)
-+---------------------------------------------------------------------------*/
-#define UIC_PEOAL 0x80000000 /* PE0 AL */
-#define UIC_PEOVA 0x40000000 /* PE0 VPD access */
-#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
-#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
-#define UIC_PE0TCR 0x08000000 /* PE0 TCR */
-#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
-#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
-#define UIC_PE1AL 0x00800000 /* PE1 AL */
-#define UIC_PE1VA 0x00400000 /* PE1 VPD access */
-#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
-#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
-#define UIC_PE1TCR 0x00080000 /* PE1 TCR */
-#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
-#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
-#define UIC_PE2AL 0x00008000 /* PE2 AL */
-#define UIC_PE2VA 0x00004000 /* PE2 VPD access */
-#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
-#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
-#define UIC_PE2TCR 0x00000800 /* PE2 TCR */
-#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
-#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
-#define UIC_EIR5 0x00000080 /* External interrupt 5 */
-#define UIC_EIR4 0x00000040 /* External interrupt 4 */
-#define UIC_EIR3 0x00000020 /* External interrupt 3 */
-#define UIC_EIR2 0x00000010 /* External interrupt 2 */
-#define UIC_EIR1 0x00000008 /* External interrupt 1 */
-#define UIC_EIR0 0x00000004 /* External interrupt 0 */
-#endif /* CONFIG_440SPE */
-
-/*-----------------------------------------------------------------------------+
-| External Bus Controller Bit Settings
-+-----------------------------------------------------------------------------*/
-#define EBC_CFGADDR_MASK 0x0000003F
-
-#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
-#define EBC_BXCR_BS_MASK 0x000E0000
-#define EBC_BXCR_BS_1MB 0x00000000
-#define EBC_BXCR_BS_2MB 0x00020000
-#define EBC_BXCR_BS_4MB 0x00040000
-#define EBC_BXCR_BS_8MB 0x00060000
-#define EBC_BXCR_BS_16MB 0x00080000
-#define EBC_BXCR_BS_32MB 0x000A0000
-#define EBC_BXCR_BS_64MB 0x000C0000
-#define EBC_BXCR_BS_128MB 0x000E0000
-#define EBC_BXCR_BU_MASK 0x00018000
-#define EBC_BXCR_BU_R 0x00008000
-#define EBC_BXCR_BU_W 0x00010000
-#define EBC_BXCR_BU_RW 0x00018000
-#define EBC_BXCR_BW_MASK 0x00006000
-#define EBC_BXCR_BW_8BIT 0x00000000
-#define EBC_BXCR_BW_16BIT 0x00002000
-#define EBC_BXCR_BW_32BIT 0x00006000
-#define EBC_BXAP_BME_ENABLED 0x80000000
-#define EBC_BXAP_BME_DISABLED 0x00000000
-#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
-#define EBC_BXAP_BCE_DISABLE 0x00000000
-#define EBC_BXAP_BCE_ENABLE 0x00400000
-#define EBC_BXAP_BCT_MASK 0x00300000
-#define EBC_BXAP_BCT_2TRANS 0x00000000
-#define EBC_BXAP_BCT_4TRANS 0x00100000
-#define EBC_BXAP_BCT_8TRANS 0x00200000
-#define EBC_BXAP_BCT_16TRANS 0x00300000
-#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
-#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
-#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
-#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
-#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
-#define EBC_BXAP_RE_ENABLED 0x00000100
-#define EBC_BXAP_RE_DISABLED 0x00000000
-#define EBC_BXAP_SOR_DELAYED 0x00000000
-#define EBC_BXAP_SOR_NONDELAYED 0x00000080
-#define EBC_BXAP_BEM_WRITEONLY 0x00000000
-#define EBC_BXAP_BEM_RW 0x00000040
-#define EBC_BXAP_PEN_DISABLED 0x00000000
-
-#define EBC_CFG_LE_MASK 0x80000000
-#define EBC_CFG_LE_UNLOCK 0x00000000
-#define EBC_CFG_LE_LOCK 0x80000000
-#define EBC_CFG_PTD_MASK 0x40000000
-#define EBC_CFG_PTD_ENABLE 0x00000000
-#define EBC_CFG_PTD_DISABLE 0x40000000
-#define EBC_CFG_RTC_MASK 0x38000000
-#define EBC_CFG_RTC_16PERCLK 0x00000000
-#define EBC_CFG_RTC_32PERCLK 0x08000000
-#define EBC_CFG_RTC_64PERCLK 0x10000000
-#define EBC_CFG_RTC_128PERCLK 0x18000000
-#define EBC_CFG_RTC_256PERCLK 0x20000000
-#define EBC_CFG_RTC_512PERCLK 0x28000000
-#define EBC_CFG_RTC_1024PERCLK 0x30000000
-#define EBC_CFG_RTC_2048PERCLK 0x38000000
-#define EBC_CFG_ATC_MASK 0x04000000
-#define EBC_CFG_ATC_HI 0x00000000
-#define EBC_CFG_ATC_PREVIOUS 0x04000000
-#define EBC_CFG_DTC_MASK 0x02000000
-#define EBC_CFG_DTC_HI 0x00000000
-#define EBC_CFG_DTC_PREVIOUS 0x02000000
-#define EBC_CFG_CTC_MASK 0x01000000
-#define EBC_CFG_CTC_HI 0x00000000
-#define EBC_CFG_CTC_PREVIOUS 0x01000000
-#define EBC_CFG_OEO_MASK 0x00800000
-#define EBC_CFG_OEO_HI 0x00000000
-#define EBC_CFG_OEO_PREVIOUS 0x00800000
-#define EBC_CFG_EMC_MASK 0x00400000
-#define EBC_CFG_EMC_NONDEFAULT 0x00000000
-#define EBC_CFG_EMC_DEFAULT 0x00400000
-#define EBC_CFG_PME_MASK 0x00200000
-#define EBC_CFG_PME_DISABLE 0x00000000
-#define EBC_CFG_PME_ENABLE 0x00200000
-#define EBC_CFG_PMT_MASK 0x001F0000
-#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-#define EBC_CFG_PR_MASK 0x0000C000
-#define EBC_CFG_PR_16 0x00000000
-#define EBC_CFG_PR_32 0x00004000
-#define EBC_CFG_PR_64 0x00008000
-#define EBC_CFG_PR_128 0x0000C000
-
/*-----------------------------------------------------------------------------+
| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
@@ -1855,7 +887,7 @@
#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
#endif
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
#define SDR0_CP440 0x0180
#define SDR0_CP440_ERPN_MASK 0x30000000
#define SDR0_CP440_ERPN_MASK_HI 0x3000
@@ -2793,7 +1825,8 @@
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
@@ -2873,118 +1906,10 @@
#endif /* CONFIG_440GX */
#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
-/*--------------------------------------*/
-#define CPR0_PLLC 0x40
-#define CPR0_PLLC_RST_MASK 0x80000000
-#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
-#define CPR0_PLLC_RST_PLLRESET 0x80000000
-#define CPR0_PLLC_ENG_MASK 0x40000000
-#define CPR0_PLLC_ENG_DISABLE 0x00000000
-#define CPR0_PLLC_ENG_ENABLE 0x40000000
-#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
-#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
-#define CPR0_PLLC_SRC_MASK 0x20000000
-#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
-#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
-#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
-#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
-#define CPR0_PLLC_SEL_MASK 0x07000000
-#define CPR0_PLLC_SEL_PLL 0x00000000
-#define CPR0_PLLC_SEL_CPU 0x01000000
-#define CPR0_PLLC_SEL_PER 0x05000000
-#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
-#define CPR0_PLLC_TUNE_MASK 0x000003FF
-#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-/*--------------------------------------*/
-#define CPR0_PLLD 0x60
-#define CPR0_PLLD_FBDV_MASK 0x1F000000
-#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
-#define CPR0_PLLD_FWDVA_MASK 0x000F0000
-#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
-#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
-#define CPR0_PLLD_FWDVB_MASK 0x00000700
-#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
-#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
-#define CPR0_PLLD_LFBDV_MASK 0x0000003F
-#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
-#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
-/*--------------------------------------*/
-#define CPR0_PRIMAD 0x80
-#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
-#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
-/*--------------------------------------*/
-#define CPR0_PRIMBD 0xA0
-#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
-#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
-/*--------------------------------------*/
-#if 0
-#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
-#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
-#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
-#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
-#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
-#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
-#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
-#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
-#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
-#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
-#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
-#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
-#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
-#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
-#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
-#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
-#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
-#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
-#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
-#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
-#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
-#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
-#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
-#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
-#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
-#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
-#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
-#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
-#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
-#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
-#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
-#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
-#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
-#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
+#define CPR0_ICFG_RLI_MASK 0x80000000
+#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
+#define CPR0_PERD_PERDV0_MASK 0x07000000
#endif
-/*--------------------------------------*/
-#define CPR0_OPBD 0xC0
-#define CPR0_OPBD_OPBDV0_MASK 0x03000000
-#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
-/*--------------------------------------*/
-#define CPR0_PERD 0xE0
-#define CPR0_PERD_PERDV0_MASK 0x07000000
-#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
-#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
-/*--------------------------------------*/
-#define CPR0_MALD 0x100
-#define CPR0_MALD_MALDV0_MASK 0x03000000
-#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
-/*--------------------------------------*/
-#define CPR0_SPCID 0x120
-#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
-#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
-#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
-/*--------------------------------------*/
-#define CPR0_ICFG 0x140
-#define CPR0_ICFG_RLI_MASK 0x80000000
-#define CPR0_ICFG_RLI_RESETCPR 0x00000000
-#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
-#define CPR0_ICFG_ICS_MASK 0x00000007
-#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
@@ -3006,20 +1931,6 @@
#define IICDIRECTCNTL 0x10
/*-----------------------------------------------------------------------------
-| UART Register Offsets
-'----------------------------------------------------------------------------*/
-#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
-#define INT_ENABLE 0x01
-#define FIFO_CONTROL 0x02
-#define LINE_CONTROL 0x03
-#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
-#define MODEM_STATUS 0x06
-#define SCRATCH 0x07
-
-/*-----------------------------------------------------------------------------
| PCI Internal Registers et. al. (accessed via plb)
+----------------------------------------------------------------------------*/
#define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
@@ -3145,7 +2056,8 @@
* GPIO macro register defines
******************************************************************************/
#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460SX)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
#define GPIO0_OR (GPIO0_BASE+0x0)
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 1d06da8..c71da60 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -41,7 +41,8 @@
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
#endif
@@ -58,6 +59,10 @@
#endif
#include <asm/ppc4xx-sdram.h>
+#include <asm/ppc4xx-ebc.h>
+#if !defined(CONFIG_XILINX_440)
+#include <asm/ppc4xx-uic.h>
+#endif
/*
* Macro for generating register field mnemonics
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 4c97b36..b74c6fc 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -153,6 +153,20 @@ typedef struct emac_4xx_hw_st {
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
+/*
+ * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
+ * not have a pin function control (PFC) register to otherwise determine
+ * the bridge configuration.
+ */
+#define EMAC_PHY_MODE_NONE 0
+#define EMAC_PHY_MODE_NONE_RGMII 1
+#define EMAC_PHY_MODE_RGMII_NONE 2
+#define EMAC_PHY_MODE_RGMII_RGMII 3
+#define EMAC_PHY_MODE_NONE_GMII 4
+#define EMAC_PHY_MODE_GMII_NONE 5
+#define EMAC_PHY_MODE_NONE_MII 6
+#define EMAC_PHY_MODE_MII_NONE 7
+
/* ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -218,12 +232,12 @@ typedef struct emac_4xx_hw_st {
#endif
/* RGMII Function Enable (FER) Register Bit Definitions */
-/* Note: for EMAC 2 and 3 only, 440GX only */
#define RGMII_FER_DIS (0x00)
#define RGMII_FER_RTBI (0x04)
#define RGMII_FER_RGMII (0x05)
#define RGMII_FER_TBI (0x06)
#define RGMII_FER_GMII (0x07)
+#define RGMII_FER_MII (RGMII_FER_GMII)
#define RGMII_FER_V(__x) ((__x - 2) * 4)
diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 83d1d1d..b6a7a91 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -174,7 +174,7 @@ uint32_t ZEXPORT crc32 (uint32_t crc, const Bytef *buf, uInt len)
#if defined(CONFIG_CMD_JFFS2) || \
(defined(CONFIG_CMD_NAND) \
- && !defined(CFG_NAND_LEGACY))
+ && !defined(CONFIG_NAND_LEGACY))
/* No ones complement version. JFFS2 (and other things ?)
* don't use ones compliment in their CRC calculations.