summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--.travis.yml115
-rw-r--r--Kconfig18
-rw-r--r--README72
-rw-r--r--arch/arc/include/asm/linkage.h12
-rw-r--r--arch/arm/Kconfig19
-rw-r--r--arch/arm/cpu/arm1136/mx31/Makefile4
-rw-r--r--arch/arm/cpu/arm1136/mx31/relocate.S23
-rw-r--r--arch/arm/cpu/arm1136/mx35/Makefile4
-rw-r--r--arch/arm/cpu/arm1136/mx35/relocate.S23
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c13
-rw-r--r--arch/arm/cpu/armv7/lowlevel_init.S22
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c29
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c6
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig5
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c21
-rw-r--r--arch/arm/cpu/pxa/cpuinfo.c17
-rw-r--r--arch/arm/imx-common/Makefile1
-rw-r--r--arch/arm/imx-common/cmd_dek.c91
-rw-r--r--arch/arm/imx-common/cpu.c10
-rw-r--r--arch/arm/imx-common/timer.c17
-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-mx5/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h4
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h10
-rw-r--r--arch/arm/include/asm/spl.h2
-rw-r--r--arch/arm/lib/crt0.S13
-rw-r--r--arch/arm/lib/spl.c4
-rw-r--r--arch/arm/mach-tegra/Kconfig3
-rw-r--r--arch/m68k/Kconfig4
-rw-r--r--arch/m68k/config.mk3
-rw-r--r--arch/m68k/cpu/mcf530x/Makefile9
-rw-r--r--arch/m68k/cpu/mcf530x/config.mk12
-rw-r--r--arch/m68k/cpu/mcf530x/cpu.c36
-rw-r--r--arch/m68k/cpu/mcf530x/cpu_init.c160
-rw-r--r--arch/m68k/cpu/mcf530x/interrupts.c29
-rw-r--r--arch/m68k/cpu/mcf530x/speed.c23
-rw-r--r--arch/m68k/cpu/mcf530x/start.S257
-rw-r--r--arch/m68k/include/asm/cache.h3
-rw-r--r--arch/m68k/include/asm/config.h3
-rw-r--r--arch/m68k/include/asm/immap.h24
-rw-r--r--arch/m68k/include/asm/immap_5307.h118
-rw-r--r--arch/m68k/include/asm/m5307.h70
-rw-r--r--arch/m68k/include/asm/timer.h3
-rw-r--r--arch/m68k/include/asm/u-boot.h8
-rw-r--r--arch/m68k/lib/Makefile4
-rw-r--r--board/BuR/common/bur_common.h4
-rw-r--r--board/BuR/common/common.c442
-rw-r--r--board/BuR/kwb/board.c152
-rw-r--r--board/BuR/kwb/mux.c51
-rw-r--r--board/BuR/tseries/board.c58
-rw-r--r--board/BuR/tseries/mux.c23
-rw-r--r--board/armltd/vexpress64/vexpress64.c3
-rw-r--r--board/birdland/bav335x/Kconfig33
-rw-r--r--board/birdland/bav335x/MAINTAINERS13
-rw-r--r--board/birdland/bav335x/Makefile11
-rw-r--r--board/birdland/bav335x/README31
-rw-r--r--board/birdland/bav335x/board.c430
-rw-r--r--board/birdland/bav335x/board.h59
-rw-r--r--board/birdland/bav335x/mux.c190
-rw-r--r--board/birdland/bav335x/u-boot.lds116
-rw-r--r--board/boundary/nitrogen6x/nitrogen6x.c1
-rw-r--r--board/freescale/common/pfuze.c38
-rw-r--r--board/freescale/common/pfuze.h1
-rw-r--r--board/freescale/mx25pdk/mx25pdk.c4
-rw-r--r--board/freescale/mx53loco/mx53loco.c16
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c6
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c6
-rw-r--r--board/freescale/mx6slevk/mx6slevk.c49
-rw-r--r--board/freescale/mx6sxsabresd/mx6sxsabresd.c6
-rw-r--r--board/nvidia/seaboard/seaboard.c4
-rw-r--r--board/quipos/cairo/Kconfig12
-rw-r--r--board/quipos/cairo/Makefile8
-rw-r--r--board/quipos/cairo/cairo.c110
-rw-r--r--board/quipos/cairo/cairo.h319
-rw-r--r--board/samsung/common/board.c10
-rw-r--r--board/samsung/odroid/odroid.c4
-rw-r--r--board/sysam/amcore/Kconfig22
-rw-r--r--board/sysam/amcore/MAINTAINERS6
-rw-r--r--board/sysam/amcore/Makefile7
-rw-r--r--board/sysam/amcore/amcore.c101
-rw-r--r--board/sysam/amcore/config.mk7
-rw-r--r--board/sysam/amcore/u-boot.lds87
-rw-r--r--board/tbs/tbs2910/tbs2910.c28
-rw-r--r--board/warp/Kconfig12
-rw-r--r--board/warp/MAINTAINERS6
-rw-r--r--board/warp/Makefile8
-rw-r--r--board/warp/warp.c119
-rw-r--r--common/Kconfig2
-rw-r--r--common/board_f.c32
-rw-r--r--common/board_r.c25
-rw-r--r--common/cmd_bootm.c3
-rw-r--r--common/cmd_eeprom.c6
-rw-r--r--common/cmd_gpt.c52
-rw-r--r--common/cmd_usb_mass_storage.c2
-rw-r--r--common/cmd_yaffs2.c26
-rw-r--r--common/lcd_console.c39
-rw-r--r--common/spl/spl.c35
-rw-r--r--configs/am335x_boneblack_defconfig2
-rw-r--r--configs/am335x_boneblack_vboot_defconfig2
-rw-r--r--configs/am335x_evm_defconfig2
-rw-r--r--configs/am335x_evm_nor_defconfig2
-rw-r--r--configs/am335x_evm_spiboot_defconfig2
-rw-r--r--configs/am335x_evm_usbspl_defconfig2
-rw-r--r--configs/am335x_igep0033_defconfig2
-rw-r--r--configs/amcore_defconfig2
-rw-r--r--configs/birdland_bav335a_defconfig5
-rw-r--r--configs/birdland_bav335b_defconfig5
-rw-r--r--configs/cairo_defconfig4
-rw-r--r--configs/warp_defconfig3
-rw-r--r--doc/README.fsl-esdhc1
-rw-r--r--doc/README.gpt8
-rw-r--r--doc/README.mxc_hab48
-rw-r--r--drivers/crypto/fsl/Makefile2
-rw-r--r--drivers/crypto/fsl/desc.h15
-rw-r--r--drivers/crypto/fsl/fsl_blob.c52
-rw-r--r--drivers/crypto/fsl/jobdesc.c149
-rw-r--r--drivers/crypto/fsl/jobdesc.h14
-rw-r--r--drivers/crypto/fsl/jr.c31
-rw-r--r--drivers/gpio/Makefile4
-rw-r--r--drivers/gpio/tegra_gpio.c27
-rw-r--r--drivers/mmc/fsl_esdhc.c33
-rw-r--r--drivers/mtd/nand/omap_gpmc.c28
-rw-r--r--drivers/net/designware.c9
-rw-r--r--drivers/net/designware.h4
-rw-r--r--drivers/video/am335x-fb.c13
-rw-r--r--drivers/video/am335x-fb.h9
-rw-r--r--fs/ext4/ext4_write.c3
-rw-r--r--include/_exports.h2
-rw-r--r--include/asm-generic/u-boot.h9
-rw-r--r--include/configs/M54451EVB.h2
-rw-r--r--include/configs/M54455EVB.h2
-rw-r--r--include/configs/M5475EVB.h4
-rw-r--r--include/configs/M5485EVB.h4
-rw-r--r--include/configs/am3517_crane.h1
-rw-r--r--include/configs/am3517_evm.h1
-rw-r--r--include/configs/amcore.h140
-rw-r--r--include/configs/bav335x.h633
-rw-r--r--include/configs/bur_am335x_common.h34
-rw-r--r--include/configs/cm_t35.h1
-rw-r--r--include/configs/devkit8000.h2
-rw-r--r--include/configs/flea3.h1
-rw-r--r--include/configs/ipam390.h1
-rw-r--r--include/configs/kwb.h99
-rw-r--r--include/configs/mx35pdk.h1
-rw-r--r--include/configs/mx53loco.h2
-rw-r--r--include/configs/mx6sabre_common.h16
-rw-r--r--include/configs/mx6slevk.h12
-rw-r--r--include/configs/odroid.h5
-rw-r--r--include/configs/odroid_xu3.h10
-rw-r--r--include/configs/omap3_cairo.h286
-rw-r--r--include/configs/omap3_evm_common.h1
-rw-r--r--include/configs/ot1200.h10
-rw-r--r--include/configs/siemens-am33x-common.h1
-rw-r--r--include/configs/spear-common.h2
-rw-r--r--include/configs/tam3517-common.h1
-rw-r--r--include/configs/tao3530.h1
-rw-r--r--include/configs/tbs2910.h13
-rw-r--r--include/configs/tegra-common.h6
-rw-r--r--include/configs/ti814x_evm.h1
-rw-r--r--include/configs/ti816x_evm.h1
-rw-r--r--include/configs/ti_armv7_common.h5
-rw-r--r--include/configs/tricorder.h1
-rw-r--r--include/configs/tseries.h123
-rw-r--r--include/configs/vexpress_aemv8a.h46
-rw-r--r--include/configs/warp.h228
-rw-r--r--include/configs/woodburn_common.h1
-rw-r--r--include/configs/x600.h1
-rw-r--r--include/exports.h2
-rw-r--r--include/fsl_esdhc.h2
-rw-r--r--include/fsl_sec.h78
-rw-r--r--include/linux/linkage.h13
-rw-r--r--include/mc34704.h1
-rw-r--r--include/mmc.h1
-rw-r--r--include/power/pfuze100_pmic.h2
-rw-r--r--include/power/tps65217.h1
-rw-r--r--include/stdio_dev.h2
-rw-r--r--lib/asm-offsets.c4
-rw-r--r--scripts/basic/fixdep.c6
-rwxr-xr-xscripts/checkstack.pl27
180 files changed, 6054 insertions, 442 deletions
diff --git a/.travis.yml b/.travis.yml
index 923c9dd..1d5c18a 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -10,7 +10,7 @@ cache:
install:
# install U-Boot build dependencies
- - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev gcc-arm-linux-gnueabi gcc-arm-linux-gnueabihf
+ - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev build-essential
# install latest device tree compiler
- git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- make -j4 -C /tmp/dtc
@@ -18,11 +18,17 @@ install:
- export BUILDMAN_ROOT="root:"
- export BUILDMAN_MIPS="mips:"
- export BUILDMAN_PPC="ppc:"
- - echo -e "[toolchain]\\n${BUILDMAN_ROOT} /\n" > ~/.buildman
- - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/" >> ~/.buildman
- - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/" >> ~/.buildman
+ - export BUILDMAN_ARM="arm:"
+ - export BUILDMAN_SANDBOX="sandbox:"
+ - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
- export BUILDMAN_ALIAS="x86:"
- - echo -e "[toolchain-alias]\\n${BUILDMAN_ALIAS} i386" >> ~/.buildman
+ - export BUILDMAN_ALIAS_ARM="arm:"
+ - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
- cat ~/.buildman
env:
@@ -40,6 +46,10 @@ before_script:
- if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then ls -al /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
script:
# the execution sequence for each test
@@ -54,19 +64,24 @@ matrix:
# each env setting here is a dedicated build
- env:
- TEST_CMD="./MAKEALL -a arm -v atmel"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v denx"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v freescale"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v siemens"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CMD="./MAKEALL -a arm -v ti"
- CROSS_COMPILE="arm-linux-gnueabi-"
+ INSTALL_TOOLCHAIN="arm"
+ CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-"
- env:
- TEST_CONFIG_CMD="make sandbox_defconfig"
TEST_CMD="make -j4"
@@ -82,45 +97,93 @@ matrix:
INSTALL_TOOLCHAIN="mips"
CROSS_COMPILE="/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/mips-linux-"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards atmel"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards atmel -x avr32"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards denx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards denx"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards freescale arm"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards freescale -x powerpc,m68k,aarch64"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards siemens"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards freescale -x arm,m68k,aarch64"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards siemens"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards ti"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm1136"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm1176"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards ti"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm720t"
+ INSTALL_TOOLCHAIN="arm"
- env:
- - TEST_CMD="tools/buildman/buildman mips"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards arm920t"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards davinci"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards kirkwood"
+ INSTALL_TOOLCHAIN="arm"
+ - env:
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mips"
INSTALL_TOOLCHAIN="mips"
- env:
- - TEST_CMD="tools/buildman/buildman mpc5xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc5xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc8xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc8xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc5xxx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc5xxx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc512x"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc512x"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc8260"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc8260"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc83xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc83xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc85xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc85xx"
INSTALL_TOOLCHAIN="ppc"
- env:
- - TEST_CMD="tools/buildman/buildman mpc86xx"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman mpc86xx"
INSTALL_TOOLCHAIN="ppc"
-
- env:
- - TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86"
+ - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains"
+ TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86"
+ INSTALL_TOOLCHAIN="i386"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
diff --git a/Kconfig b/Kconfig
index 91a0618..b879461 100644
--- a/Kconfig
+++ b/Kconfig
@@ -96,6 +96,24 @@ config SPL
help
If you want to build SPL as well as the normal image, say Y.
+config SPL_STACK_R
+ depends on SPL
+ bool "Enable SDRAM location for SPL stack"
+ help
+ SPL starts off execution in SRAM and thus typically has only a small
+ stack available. Since SPL sets up DRAM while in its board_init_f()
+ function, it is possible for the stack to move there before
+ board_init_r() is reached. This option enables a special SDRAM
+ location for the SPL stack. U-Boot SPL switches to this after
+ board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+ depends on SPL_STACK_R
+ hex "SDRAM location for SPL stack"
+ help
+ Specify the address in SDRAM for the SPL stack. This will be set up
+ before board_init_r() is called.
+
config TPL
bool
depends on SPL && SUPPORT_TPL
diff --git a/README b/README
index febefb5..676f41e 100644
--- a/README
+++ b/README
@@ -273,6 +273,75 @@ run some of U-Boot's tests.
See board/sandbox/README.sandbox for more details.
+Board Initialisation Flow:
+--------------------------
+
+This is the intended start-up flow for boards. This should apply for both
+SPL and U-Boot proper (i.e. they both follow the same rules). At present SPL
+mostly uses a separate code path, but the funtion names and roles of each
+function are the same. Some boards or architectures may not conform to this.
+At least most ARM boards which use CONFIG_SPL_FRAMEWORK conform to this.
+
+Execution starts with start.S with three functions called during init after
+that. The purpose and limitations of each is described below.
+
+lowlevel_init():
+ - purpose: essential init to permit execution to reach board_init_f()
+ - no global_data or BSS
+ - there is no stack (ARMv7 may have one but it will soon be removed)
+ - must not set up SDRAM or use console
+ - must only do the bare minimum to allow execution to continue to
+ board_init_f()
+ - this is almost never needed
+ - return normally from this function
+
+board_init_f():
+ - purpose: set up the machine ready for running board_init_r():
+ i.e. SDRAM and serial UART
+ - global_data is available
+ - stack is in SRAM
+ - BSS is not available, so you cannot use global/static variables,
+ only stack variables and global_data
+
+ Non-SPL-specific notes:
+ - dram_init() is called to set up DRAM. If already done in SPL this
+ can do nothing
+
+ SPL-specific notes:
+ - you can override the entire board_init_f() function with your own
+ version as needed.
+ - preloader_console_init() can be called here in extremis
+ - should set up SDRAM, and anything needed to make the UART work
+ - these is no need to clear BSS, it will be done by crt0.S
+ - must return normally from this function (don't call board_init_r()
+ directly)
+
+Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
+this point the stack and global_data are relocated to below
+CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
+memory.
+
+board_init_r():
+ - purpose: main execution, common code
+ - global_data is available
+ - SDRAM is available
+ - BSS is available, all static/global variables can be used
+ - execution eventually continues to main_loop()
+
+ Non-SPL-specific notes:
+ - U-Boot is relocated to the top of memory and is now running from
+ there.
+
+ SPL-specific notes:
+ - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
+ CONFIG_SPL_STACK_R_ADDR points into SDRAM
+ - preloader_console_init() can be called here - typically this is
+ done by defining CONFIG_SPL_BOARD_INIT and then supplying a
+ spl_board_init() function containing this call
+ - loads U-Boot or (in falcon mode) Linux
+
+
+
Configuration Options:
----------------------
@@ -4353,6 +4422,9 @@ to save the current settings.
If defined, specified the chip address of the EEPROM device.
The default address is zero.
+ - CONFIG_SYS_I2C_EEPROM_BUS:
+ If defined, specified the i2c bus of the EEPROM device.
+
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
If defined, the number of bits used to address bytes in a
single page in the EEPROM device. A 64 byte page, for example
diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h
new file mode 100644
index 0000000..2d1a603
--- /dev/null
+++ b/arch/arc/include/asm/linkage.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_LINKAGE_H
+#define __ASM_ARC_LINKAGE_H
+
+#define ASM_NL ` /* use '`' to mark new line in macro */
+
+#endif /* __ASM_ARC_LINKAGE_H */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bc55e5b..27bcc2d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -381,6 +381,19 @@ config TARGET_AM43XX_EVM
select CPU_V7
select SUPPORT_SPL
+config TARGET_BAV335X
+ bool "Support bav335x"
+ select CPU_V7
+ select SUPPORT_SPL
+ help
+ The BAV335x OEM Network Processor integrates all the functions of an
+ embedded network computer in a small, easy to use SODIMM module which
+ incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+ processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+ ethernet with simple connection to external connectors.
+
+ For more information, visit: http://birdland.com/oem
+
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
select CPU_V7
@@ -465,6 +478,10 @@ config TARGET_WANDBOARD
bool "Support wandboard"
select CPU_V7
+config TARGET_WARP
+ bool "Support WaRP"
+ select CPU_V7
+
config TARGET_TITANIUM
bool "Support titanium"
select CPU_V7
@@ -832,6 +849,7 @@ source "board/syteco/zmx25/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
+source "board/birdland/bav335x/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
@@ -842,6 +860,7 @@ source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
source "board/wandboard/Kconfig"
+source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/xaeniax/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
index 9670ed9..dcbd570 100644
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
@@ -8,3 +8,7 @@
obj-y += generic.o
obj-y += timer.o
obj-y += devices.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm1136/mx31/relocate.S b/arch/arm/cpu/arm1136/mx31/relocate.S
new file mode 100644
index 0000000..1c556df
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx31/relocate.S
@@ -0,0 +1,23 @@
+/*
+ * relocate - i.MX31-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX31 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index c533215..796db9c 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -10,3 +10,7 @@
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm1136/mx35/relocate.S b/arch/arm/cpu/arm1136/mx35/relocate.S
new file mode 100644
index 0000000..43003f8
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx35/relocate.S
@@ -0,0 +1,23 @@
+/*
+ * relocate - i.MX35-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX35 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 81477aa..67bef23 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -275,6 +275,14 @@ static void watchdog_disable(void)
;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ board_early_init_f();
+ sdram_init();
+}
+#endif
+
void s_init(void)
{
/*
@@ -290,6 +298,7 @@ void s_init(void)
setup_clocks_for_console();
uart_soft_reset();
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
+ /* TODO: This does not work, gd is not available yet */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
@@ -298,9 +307,5 @@ void s_init(void)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
-#ifdef CONFIG_SPL_BUILD
- board_early_init_f();
- sdram_init();
-#endif
}
#endif
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index f1aea05..427b0b1 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -17,10 +17,17 @@
ENTRY(lowlevel_init)
/*
- * Setup a temporary stack
+ * Setup a temporary stack. Global data is not available yet.
*/
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#ifdef CONFIG_DM
+ mov r9, #0
+#else
+ /*
+ * Set up global data for boards that still need it. This will be
+ * removed soon.
+ */
#ifdef CONFIG_SPL_BUILD
ldr r9, =gdata
#else
@@ -28,13 +35,24 @@ ENTRY(lowlevel_init)
bic sp, sp, #7
mov r9, sp
#endif
+#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
*/
push {ip, lr}
/*
- * go setup pll, mux, memory
+ * Call the very early init function. This should do only the
+ * absolute bare minimum to get started. It should not:
+ *
+ * - set up DRAM
+ * - use global_data
+ * - clear BSS
+ * - try to start a console
+ *
+ * For boards with SPL this should be empty since SPL can do all of
+ * this init in the SPL board_init_f() function which is called
+ * immediately after this.
*/
bl s_init
pop {ip, pc}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index e599a12..ef02972 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -230,6 +230,11 @@ static void imx_set_wdog_powerdown(bool enable)
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+#ifdef CONFIG_MX6SX
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+ writew(enable, &wdog3->wmcr);
+#endif
+
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
@@ -255,6 +260,23 @@ static void clear_mmdc_ch_mask(void)
writel(0, &mxc_ccm->ccdr);
}
+static void init_bandgap(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ /*
+ * Ensure the bandgap has stabilized.
+ */
+ while (!(readl(&anatop->ana_misc0) & 0x80))
+ ;
+ /*
+ * For best noise performance of the analog blocks using the
+ * outputs of the bandgap, the reftop_selfbiasoff bit should
+ * be set.
+ */
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+}
+
+
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
@@ -275,6 +297,13 @@ int arch_cpu_init(void)
clear_mmdc_ch_mask();
/*
+ * Disable self-bias circuit in the analog bandap.
+ * The self-bias circuit is used by the bandgap during startup.
+ * This bit should be set after the bandgap has initialized.
+ */
+ init_bandgap();
+
+ /*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
* scenario.
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index cb35c19..6c8f3bc 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -128,14 +128,18 @@ void s_init(void)
do_io_settings();
#endif
prcm_init();
+}
+
#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
#ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f();
#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
-#endif
}
+#endif
/*
* Routine: wait_for_command_complete
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 4a0ac2c..65da6e2 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -91,6 +91,10 @@ config TARGET_TWISTER
bool "Twister"
select SUPPORT_SPL
+config TARGET_OMAP3_CAIRO
+ bool "QUIPOS CAIRO"
+ select SUPPORT_SPL
+
endchoice
config DM
@@ -133,5 +137,6 @@ source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
+source "board/quipos/cairo/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 90d6ae7..dd53b20 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -240,8 +240,6 @@ void try_unlock_memory(void)
*****************************************************************************/
void s_init(void)
{
- int in_sdram = is_running_in_sdram();
-
watchdog_init();
try_unlock_memory();
@@ -264,10 +262,14 @@ void s_init(void)
#ifdef CONFIG_USB_EHCI_OMAP
ehci_clocks_enable();
#endif
+}
- if (!in_sdram)
- mem_init();
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ mem_init();
}
+#endif
/*
* Routine: misc_init_r
@@ -345,7 +347,16 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg
goto usage;
}
} else if (strncmp(argv[1], "sw", 2) == 0) {
- omap_nand_switch_ecc(0, 0);
+ if (argc == 2) {
+ omap_nand_switch_ecc(0, 1);
+ } else {
+ if (strncmp(argv[2], "hamming", 7) == 0)
+ omap_nand_switch_ecc(0, 1);
+ else if (strncmp(argv[2], "bch8", 4) == 0)
+ omap_nand_switch_ecc(0, 8);
+ else
+ goto usage;
+ }
} else {
goto usage;
}
diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c
index 17d8be5..25de9e5 100644
--- a/arch/arm/cpu/pxa/cpuinfo.c
+++ b/arch/arm/cpu/pxa/cpuinfo.c
@@ -46,6 +46,13 @@ int cpu_is_pxa27x(void)
return id == CPU_VALUE_PXA27X;
}
+int cpu_is_pxa27xm(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
+ ((id & CPU_MASK_PXA_REVID) == 8);
+}
+
uint32_t pxa_get_cpu_revision(void)
{
return pxa_get_cpuid() & CPU_MASK_PRODREV;
@@ -91,13 +98,17 @@ static const char *pxa27x_get_revision(void)
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
- if ((id == 5) || (id == 6) || (id > 7))
+ if ((id == 5) || (id == 6) || (id > 8))
return unknown;
/* Cap the special PXA270 C5 case. */
if (id == 7)
id = 5;
+ /* Cap the special PXA270M A1 case. */
+ if (id == 8)
+ id = 1;
+
return rev[id];
}
@@ -107,7 +118,9 @@ static int print_cpuinfo_pxa2xx(void)
puts("Marvell PXA25x rev. ");
puts(pxa25x_get_revision());
} else if (cpu_is_pxa27x()) {
- puts("Marvell PXA27x rev. ");
+ puts("Marvell PXA27x");
+ if (cpu_is_pxa27xm()) puts("M");
+ puts(" rev. ");
puts(pxa27x_get_revision());
} else
return -EINVAL;
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 25a9d4c..606482f 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
quiet_cmd_cpp_cfg = CFGS $@
cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c
new file mode 100644
index 0000000..d93d5fb
--- /dev/null
+++ b/arch/arm/imx-common/cmd_dek.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Command for encapsulating DEK blob
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <linux/compiler.h>
+#include <fsl_sec.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
+* @src: - Address of data to be encapsulated
+* @dst: - Desination address of encapsulated data
+* @len: - Size of data to be encapsulated
+*
+* Returns zero on success,and negative on error.
+*/
+static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
+{
+ int ret = 0;
+ u32 jr_size = 4;
+
+ u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+ if (out_jr_size != jr_size) {
+ hab_caam_clock_enable(1);
+ sec_init();
+ }
+
+ if (!((len == 128) | (len == 192) | (len == 256))) {
+ debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+ return -1;
+ }
+
+ len /= 8;
+ ret = blob_dek(src, dst, len);
+
+ return ret;
+}
+
+/**
+ * do_dek_blob() - Handle the "dek_blob" command-line command
+ * @cmdtp: Command data struct pointer
+ * @flag: Command flag
+ * @argc: Command-line argument count
+ * @argv: Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ uint32_t src_addr, dst_addr, len;
+ uint8_t *src_ptr, *dst_ptr;
+ int ret = 0;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ src_addr = simple_strtoul(argv[1], NULL, 16);
+ dst_addr = simple_strtoul(argv[2], NULL, 16);
+ len = simple_strtoul(argv[3], NULL, 10);
+
+ src_ptr = map_sysmem(src_addr, len/8);
+ dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8));
+
+ ret = blob_encap_dek(src_ptr, dst_ptr, len);
+
+ return ret;
+}
+
+/***************************************************/
+static char dek_blob_help_text[] =
+ "src dst len - Encapsulate and create blob of data\n"
+ " $len bits long at address $src and\n"
+ " store the result at address $dst.\n";
+
+U_BOOT_CMD(
+ dek_blob, 4, 1, do_dek_blob,
+ "Data Encryption Key blob encapsulation",
+ dek_blob_help_text
+);
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 28ccd29..067d08f 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -24,13 +24,16 @@
#include <fsl_esdhc.h>
#endif
-char *get_reset_cause(void)
+static u32 reset_cause = -1;
+
+static char *get_reset_cause(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
+ reset_cause = cause;
switch (cause) {
case 0x00001:
@@ -53,6 +56,11 @@ char *get_reset_cause(void)
}
}
+u32 get_imx_reset_cause(void)
+{
+ return reset_cause;
+}
+
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 65ef60b..e522990 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -176,3 +176,20 @@ ulong get_tbclk(void)
{
return gpt_get_clk();
}
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+ return ticks;
+}
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 254136e..4715f4e 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -17,3 +17,5 @@
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
+
+u32 get_imx_reset_cause(void);
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index ac7705b..b06c77f 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -24,6 +24,5 @@ void set_chipselect_size(int const);
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
-char *get_reset_cause(void);
#endif
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 39f3c07..0592ce0 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1063,4 +1063,6 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index ae88b6e..9a4ad8b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -215,6 +215,10 @@
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
+
+#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
+
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 9ded3d8..6ba1034 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -31,7 +31,12 @@ enum {
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
+ MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
+ MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
+ MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
@@ -58,5 +63,10 @@ enum {
MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+ MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+ MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 17b6f54..6db405d 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -37,6 +37,8 @@ void spl_board_load_image(void);
/* Linker symbols. */
extern char __bss_start[], __bss_end[];
+#ifndef CONFIG_DM
extern gd_t gdata;
+#endif
#endif
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 22df3e5..7939ced 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -113,7 +113,14 @@ here:
/* Set up final (full) environment */
bl c_runtime_cpu_setup /* we still call old routine here */
-
+#endif
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
+# ifdef CONFIG_SPL_BUILD
+ /* Use a DRAM stack for the rest of SPL, if requested */
+ bl spl_relocate_stack_gd
+ cmp r0, #0
+ movne sp, r0
+# endif
ldr r0, =__bss_start /* this is auto-relocated! */
ldr r1, =__bss_end /* this is auto-relocated! */
@@ -124,9 +131,10 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */
addlo r0, r0, #4 /* move to next */
blo clbss_l
+#if ! defined(CONFIG_SPL_BUILD)
bl coloured_LED_init
bl red_led_on
-
+#endif
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov r0, r9 /* gd_t */
ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */
@@ -134,7 +142,6 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */
ldr pc, =board_init_r /* this is auto-relocated! */
/* we should not return here. */
-
#endif
ENDPROC(_main)
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index c41850a..bd8c7d2 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -13,6 +13,7 @@
#include <image.h>
#include <linux/compiler.h>
+#ifndef CONFIG_DM
/* Pointer to as well as the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
@@ -21,6 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
* pafches that rely on it. The global_data area is set up in crt0.S.
*/
gd_t gdata __attribute__ ((section(".data")));
+#endif
/*
* In the context of SPL, board_init_f must ensure that any clocks/etc for
@@ -33,8 +35,10 @@ void __weak board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
+#ifndef CONFIG_DM
/* TODO: Remove settings of the global data pointer here */
gd = &gdata;
+#endif
board_init_r(NULL, 0);
}
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 8615248..fccfd79 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -29,6 +29,9 @@ config USE_PRIVATE_LIBGCC
config DM
default y
+config SPL_DM
+ default y
+
config DM_SERIAL
default y
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 78c98ed..53c4aab 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -67,6 +67,9 @@ config TARGET_M5475EVB
config TARGET_M5485EVB
bool "Support M5485EVB"
+config TARGET_AMCORE
+ bool "Support AMCORE"
+
endchoice
source "board/BuS/eb_cpu5282/Kconfig"
@@ -89,5 +92,6 @@ source "board/freescale/m54451evb/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
source "board/freescale/m548xevb/Kconfig"
+source "board/sysam/amcore/Kconfig"
endmenu
diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk
index 3b3a7e8..a629b68 100644
--- a/arch/m68k/config.mk
+++ b/arch/m68k/config.mk
@@ -11,6 +11,9 @@ endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
+# Support generic board on m68k
+__HAVE_ARCH_GENERIC_BOARD := y
+
PLATFORM_CPPFLAGS += -D__M68K__
PLATFORM_LDFLAGS += -n
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile
new file mode 100644
index 0000000..9492bde
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y = start.o
+obj-y = interrupts.o cpu.o speed.o cpu_init.o
+
diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk
new file mode 100644
index 0000000..aef72d7
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/config.mk
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
+is5307:=$(shell grep CONFIG_M5307 $(cfg))
+
+ifneq (,$(findstring CONFIG_M5307,$(is5307)))
+PLATFORM_CPPFLAGS += -mcpu=5307
+endif
diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
new file mode 100644
index 0000000..78f4385
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/cpu.c
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ /* enable watchdog/reset, set timeout to 0 and wait */
+ out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI);
+
+ /* wait for watchdog reset */
+ for (;;)
+ ;
+
+ /* we don't return! */
+ return 0;
+}
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
+ strmhz(buf, CONFIG_SYS_CPU_CLK));
+ return 0;
+}
+#endif
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
new file mode 100644
index 0000000..80dc239
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_M5307)
+/*
+ * Simple mcf5307 chip select module init.
+ *
+ * Note: this chip has an issue reported in the device "errata":
+ * MCF5307ER Rev 4.2 reports @ section 35:
+ * Corrupted Return PC in Exception Stack Frame
+ * When processing an autovectored interrupt an error can occur that
+ * causes 0xFFFFFFFF to be written as the return PC value in the
+ * exception stack frame. The problem is caused by a conflict between
+ * an internal autovector access and a chip select mapped to the IACK
+ * address space (0xFFFFXXXX).
+ * Workaround:
+ * Set the C/I bit in the chip select mask register (CSMR) for the
+ * chip select that is mapped to 0xFFFFXXXX.
+ * This will prevent the chip select from asserting for IACK accesses.
+ */
+
+#define MCF5307_SP_ERR_FIX(cs_base, mask) \
+ do { \
+ if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
+ 0xffff0000) \
+ setbits_be32(&mask, CSMR_CI); \
+ } while (0)
+
+void init_csm(void)
+{
+ csm_t *csm = (csm_t *)(MMAP_CSM);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
+ defined(CONFIG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
+ defined(CONFIG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
+ defined(CONFIG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
+ defined(CONFIG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
+ defined(CONFIG_SYS_CS4_CTRL))
+ out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
+ out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
+ defined(CONFIG_SYS_CS5_CTRL))
+ out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
+ out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
+ defined(CONFIG_SYS_CS6_CTRL))
+ out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
+ out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
+ out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
+ defined(CONFIG_SYS_CS7_CTRL))
+ out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
+ out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
+ out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
+ MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
+#endif
+}
+
+/*
+ * Set up the memory map and initialize registers
+ */
+void cpu_init_f(void)
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_8(&sim->sypcr, 0x00);
+ out_8(&sim->swivr, 0x0f);
+ out_8(&sim->swsr, 0x00);
+ out_8(&sim->mpark, 0x00);
+
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* timer 2 not masked */
+ out_be32(&icr->imr, 0xfffffbff);
+
+ out_8(&icr->icr0, 0x00); /* sw watchdog */
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x88); /* timer 2 */
+ out_8(&icr->icr3, 0x00); /* i2c */
+ out_8(&icr->icr4, 0x00); /* uart 0 */
+ out_8(&icr->icr5, 0x00); /* uart 1 */
+ out_8(&icr->icr6, 0x00); /* dma 0 */
+ out_8(&icr->icr7, 0x00); /* dma 1 */
+ out_8(&icr->icr8, 0x00); /* dma 2 */
+ out_8(&icr->icr9, 0x00); /* dma 3 */
+
+ /* Chipselect Init */
+ init_csm();
+
+ /* enable data/instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return 0;
+}
+
+void uart_port_conf(void)
+{
+}
+
+void arch_preboot_os(void)
+{
+ /*
+ * OS can change interrupt offsets and are about to boot the OS so
+ * we need to make sure we disable all async interrupts.
+ */
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ out_8(&icr->icr1, 0x00); /* timer 1 */
+ out_8(&icr->icr2, 0x00); /* timer 2 */
+}
+#endif
diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c
new file mode 100644
index 0000000..bf4038d
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/interrupts.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int interrupt_init(void)
+{
+ enable_interrupts();
+
+ return 0;
+}
+
+void dtimer_intr_setup(void)
+{
+ intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+ /* clearing TIMER2 mask, so enabling the related interrupt */
+ out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
+ /* set TIMER2 interrupt priority */
+ out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif
diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
new file mode 100644
index 0000000..3cf1986
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/speed.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#if defined(CONFIG_M5307)
+ gd->bus_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+#endif
+
+ return 0;
+}
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
new file mode 100644
index 0000000..097958a
--- /dev/null
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define _START _start
+#define _FAULT _fault
+
+
+.macro SAVE_ALL
+ move.w #0x2700,%sr; /* disable intrs */
+ subl #60,%sp; /* space for 15 regs */
+ moveml %d0-%d7/%a0-%a6,%sp@
+.endm
+
+.macro RESTORE_ALL
+ moveml %sp@,%d0-%d7/%a0-%a6;
+ addl #60,%sp; /* space for 15 regs */
+ rte
+.endm
+
+/* If we come from a pre-loader we don't need an initial exception
+ * table.
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+/* Flash offset is 0 until we setup CS0 */
+.long 0x00000000
+#if defined(CONFIG_M5307) && \
+ (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long _start - CONFIG_SYS_TEXT_BASE
+#else
+.long _START
+#endif
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#endif
+
+ .text
+ .globl _start
+_start:
+ nop
+ nop
+ move.w #0x2700,%sr
+
+ /* set MBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.c %d0, %MBAR
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.c %d0, %RAMBAR
+
+ /* DS 4.8.2 (Cache Organization) invalidate and disable cache */
+ move.l #CF_CACR_CINVA, %d0
+ movec %d0, %CACR
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
+ /*
+ * if we come from a pre-loader we have no exception table and
+ * therefore no VBR to set
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
+ movec %d0, %VBR
+#endif
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
+ /*
+ * set stackpointer to internal sram end - 80
+ * (global data struct size + some bytes)
+ * get some stackspace for the first c-code,
+ */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* run low-level CPU init code (from flash) */
+ bsr cpu_init_f
+
+ /* run low-level board init code (from flash) */
+ bsr board_init_f
+
+ /* board_init_f() does not return */
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+ .globl relocate_code
+relocate_code:
+ link.w %a6,#0
+ move.l 8(%a6), %sp /* set new stack pointer */
+ move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
+ move.l 16(%a6), %a0 /* Save copy of Destination Address */
+
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
+ move.l #__init_end, %a2
+ move.l %a0, %a3
+ /* copy the code to RAM */
+1:
+ move.l (%a1)+, (%a3)+
+ cmp.l %a1,%a2
+ bgt.s 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ move.l %a0, %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+ jmp (%a1)
+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ move.l %a0, %a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1
+ move.l %a0, %d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE), %d1
+6:
+ clr.l (%a1)+
+ cmp.l %a1,%d1
+ bgt.s 6b
+
+ /*
+ * fix got table in RAM
+ */
+ move.l %a0, %a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1
+ /* * fix got pointer register a5 */
+ move.l %a1,%a5
+
+ move.l %a0, %a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE), %a2
+
+7:
+ move.l (%a1),%d1
+ sub.l #_start, %d1
+ add.l %a0,%d1
+ move.l %d1,(%a1)+
+ cmp.l %a2, %a1
+ bne 7b
+
+ /* calculate relative jump to board_init_r in ram */
+ move.l %a0, %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+ /* set parameters for board_init_r */
+ move.l %a0,-(%sp) /* dest_addr */
+ move.l %d0,-(%sp) /* gd */
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+ halt
+#endif
+ jsr (%a1)
+
+/*--------------------------------------------------------------------------*/
+/* exception code */
+ .globl _fault
+_fault:
+ bra _fault
+
+ .globl _exc_handler
+_exc_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr exc_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+ .globl _int_handler
+_int_handler:
+ SAVE_ALL
+ movel %sp,%sp@-
+ bsr int_handler
+ addql #4,%sp
+ RESTORE_ALL
+
+/*--------------------------------------------------------------------------*/
+
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 59fa33b..812f25c 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -15,7 +15,8 @@
#define CONFIG_CF_V2
#endif
-#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
+ defined(CONFIG_MCF5301x)
#define CONFIG_CF_V3
#endif
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index 9c4d3fb..7590842 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -7,6 +7,9 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_LMB
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index f0a76f4..aca5f3a 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -240,6 +240,30 @@
#endif
#endif /* CONFIG_M5282 */
+#ifdef CONFIG_M5307
+#include <asm/immap_5307.h>
+#include <asm/m5307.h>
+
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+ (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
+ (CONFIG_SYS_INTR_BASE))->ipr)
+#define CONFIG_SYS_TMRINTR_NO (31)
+#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
+ MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5307 */
+
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
new file mode 100644
index 0000000..c839f46
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __IMMAP_5307__
+#define __IMMAP_5307__
+
+#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
+
+typedef struct sim {
+ u8 rsr;
+ u8 sypcr;
+ u8 swivr;
+ u8 swsr;
+ u16 par;
+ u8 irqpar;
+ u8 res1;
+ u8 pllcr;
+ u8 res2;
+ u16 res3;
+ u8 mpark;
+ u8 res4;
+ u16 res5;
+ u32 res6;
+} sim_t;
+
+typedef struct intctrl {
+ u32 ipr;
+ u32 imr;
+ u16 res7;
+ u8 res8;
+ u8 avr;
+ u8 icr0;
+ u8 icr1;
+ u8 icr2;
+ u8 icr3;
+ u8 icr4;
+ u8 icr5;
+ u8 icr6;
+ u8 icr7;
+ u8 icr8;
+ u8 icr9;
+ u16 res9;
+} intctrl_t;
+
+typedef struct csm {
+ u16 csar0; /* Chip-select Address */
+ u16 res1;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res2;
+ u16 cscr0; /* Chip-select Control */
+ u16 csar1;
+ u16 res3;
+ u32 csmr1;
+ u16 res4;
+ u16 cscr1;
+ u16 csar2;
+ u16 res5;
+ u32 csmr2;
+ u16 res6;
+ u16 cscr2;
+ u16 csar3;
+ u16 res7;
+ u32 csmr3;
+ u16 res8;
+ u16 cscr3;
+ u16 csar4;
+ u16 res9;
+ u32 csmr4;
+ u16 res10;
+ u16 cscr4;
+ u16 csar5;
+ u16 res11;
+ u32 csmr5;
+ u16 res12;
+ u16 cscr5;
+ u16 csar6;
+ u16 res13;
+ u32 csmr6;
+ u16 res14;
+ u16 cscr6;
+ u16 csar7;
+ u16 res15;
+ u32 csmr7;
+ u16 res16;
+ u16 cscr7;
+} csm_t;
+
+typedef struct sdramctrl {
+ u16 dcr;
+ u16 res1;
+ u32 res2;
+ u32 dacr0;
+ u32 dmr0;
+ u32 dacr1;
+ u32 dmr1;
+} sdramctrl_t;
+
+typedef struct gpio {
+ u16 paddr;
+ u16 res1;
+ u16 padat;
+ u16 res2;
+} gpio_t;
+
+#endif /* __IMMAP_5307__ */
+
diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h
new file mode 100644
index 0000000..8192c46
--- /dev/null
+++ b/arch/m68k/include/asm/m5307.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef mcf5307_h
+#define mcf5307_h
+
+/*
+ * Size of internal RAM (RAMBAR)
+ */
+#define INT_RAM_SIZE 4096
+
+/* Bit definitions and macros for SYPCR */
+#define SYPCR_SWTAVAL 0x02
+#define SYPCR_SWTA 0x04
+#define SYPCR_SWT(x) ((x&0x3)<<3)
+#define SYPCR_SWP 0x20
+#define SYPCR_SWRI 0x40
+#define SYPCR_SWE 0x80
+
+/* Bit definitions and macros for CSMR */
+#define CSMR_V 0x01
+#define CSMR_UD 0x02
+#define CSMR_UC 0x04
+#define CSMR_SD 0x08
+#define CSMR_SC 0x10
+#define CSMR_CI 0x20
+#define CSMR_AM 0x40
+#define CSMR_WP 0x100
+
+/* Bit definitions and macros for DACR (SDRAM) */
+#define DACR_PM_CONTINUOUS 0x04
+#define DACR_IP_PRECHG_ALL 0x08
+#define DACR_PORT_SZ_32 0
+#define DACR_PORT_SZ_8 (1<<4)
+#define DACR_PORT_SZ_16 (2<<4)
+#define DACR_IMRS_INIT_CMD (1<<6)
+#define DACR_CMD_PIN(x) ((x&7)<<8)
+#define DACR_CASL(x) ((x&3)<<12)
+#define DACR_RE (1<<15)
+
+/* Bit definitions and macros for CSCR */
+#define CSCR_BSTW 0x08
+#define CSCR_BSTR 0x10
+#define CSCR_BEM 0x20
+#define CSCR_PS(x) ((x&0x3)<<6)
+#define CSCR_AA 0x100
+#define CSCR_WS ((x&0xf)<<10)
+
+/* Bit definitions for the ICR family of registers */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+#endif /* mcf5307_h */
+
diff --git a/arch/m68k/include/asm/timer.h b/arch/m68k/include/asm/timer.h
index 2bdaddc..8fb3216 100644
--- a/arch/m68k/include/asm/timer.h
+++ b/arch/m68k/include/asm/timer.h
@@ -17,7 +17,8 @@
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+ defined(CONFIG_M5272) || defined(CONFIG_M5307)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 983cb2d..911c0d3 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -20,6 +20,11 @@
* include/asm-ppc/u-boot.h
*/
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
#ifndef __ASSEMBLY__
typedef struct bd_info {
@@ -48,6 +53,9 @@ typedef struct bd_info {
#endif /* __ASSEMBLY__ */
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_M68K
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index 65867d6..d0e1a84 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -5,7 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o
+ifndef CONFIG_SYS_GENERIC_BOARD
+obj-y += board.o
+endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
index 15225b0..39afbba 100644
--- a/board/BuR/common/bur_common.h
+++ b/board/BuR/common/bur_common.h
@@ -12,6 +12,10 @@
#ifndef _BUR_COMMON_H_
#define _BUR_COMMON_H_
+#include <../../../drivers/video/am335x-fb.h>
+
+int load_lcdtiming(struct am335x_lcdpanel *panel);
+void br_summaryscreen(void);
void blink(u32 blinks, u32 intervall, u32 pin);
void pmicsetup(u32 mpupll);
void enable_uart0_pin_mux(void);
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 25cbe62..18e1520 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -9,7 +9,7 @@
* SPDX-License-Identifier: GPL-2.0+
*
*/
-
+#include <version.h>
#include <common.h>
#include <errno.h>
#include <spl.h>
@@ -26,10 +26,421 @@
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
+#include <lcd.h>
+#include <fs.h>
+#ifdef CONFIG_USE_FDT
+ #include <fdt_support.h>
+#endif
#include "bur_common.h"
+#include "../../../drivers/video/am335x-fb.h"
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USE_FDT
+ #define FDTPROP(a, b, c) fdt_getprop_u32_default((void *)a, b, c, ~0UL)
+ #define PATHTIM "/panel/display-timings/default"
+ #define PATHINF "/panel/panel-info"
+#endif
/* --------------------------------------------------------------------------*/
+#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \
+ !defined(CONFIG_SPL_BUILD)
+int load_lcdtiming(struct am335x_lcdpanel *panel)
+{
+ struct am335x_lcdpanel pnltmp;
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ u32 dtbprop;
+
+ if (dtbaddr == ~0UL) {
+ puts("load_lcdtiming: failed to get 'dtbaddr' from env!\n");
+ return -1;
+ }
+ memcpy(&pnltmp, (void *)panel, sizeof(struct am335x_lcdpanel));
+
+ pnltmp.hactive = FDTPROP(dtbaddr, PATHTIM, "hactive");
+ pnltmp.vactive = FDTPROP(dtbaddr, PATHTIM, "vactive");
+ pnltmp.bpp = FDTPROP(dtbaddr, PATHINF, "bpp");
+ pnltmp.hfp = FDTPROP(dtbaddr, PATHTIM, "hfront-porch");
+ pnltmp.hbp = FDTPROP(dtbaddr, PATHTIM, "hback-porch");
+ pnltmp.hsw = FDTPROP(dtbaddr, PATHTIM, "hsync-len");
+ pnltmp.vfp = FDTPROP(dtbaddr, PATHTIM, "vfront-porch");
+ pnltmp.vbp = FDTPROP(dtbaddr, PATHTIM, "vback-porch");
+ pnltmp.vsw = FDTPROP(dtbaddr, PATHTIM, "vsync-len");
+ pnltmp.pup_delay = FDTPROP(dtbaddr, PATHTIM, "pupdelay");
+ pnltmp.pon_delay = FDTPROP(dtbaddr, PATHTIM, "pondelay");
+
+ /* calc. proper clk-divisor */
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "clock-frequency");
+ if (dtbprop != ~0UL)
+ pnltmp.pxl_clk_div = 192000000 / dtbprop;
+ else
+ pnltmp.pxl_clk_div = ~0UL;
+
+ /* check polarity of control-signals */
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "hsync-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= HSYNC_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "vsync-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= VSYNC_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-ctrl");
+ if (dtbprop == 1)
+ pnltmp.pol |= HSVS_CONTROL;
+ dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-edge");
+ if (dtbprop == 1)
+ pnltmp.pol |= HSVS_RISEFALL;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "pixelclk-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= PXCLK_INVERT;
+ dtbprop = FDTPROP(dtbaddr, PATHTIM, "de-active");
+ if (dtbprop == 0)
+ pnltmp.pol |= DE_INVERT;
+#else
+ pnltmp.hactive = getenv_ulong("ds1_hactive", 10, ~0UL);
+ pnltmp.vactive = getenv_ulong("ds1_vactive", 10, ~0UL);
+ pnltmp.bpp = getenv_ulong("ds1_bpp", 10, ~0UL);
+ pnltmp.hfp = getenv_ulong("ds1_hfp", 10, ~0UL);
+ pnltmp.hbp = getenv_ulong("ds1_hbp", 10, ~0UL);
+ pnltmp.hsw = getenv_ulong("ds1_hsw", 10, ~0UL);
+ pnltmp.vfp = getenv_ulong("ds1_vfp", 10, ~0UL);
+ pnltmp.vbp = getenv_ulong("ds1_vbp", 10, ~0UL);
+ pnltmp.vsw = getenv_ulong("ds1_vsw", 10, ~0UL);
+ pnltmp.pxl_clk_div = getenv_ulong("ds1_pxlclkdiv", 10, ~0UL);
+ pnltmp.pol = getenv_ulong("ds1_pol", 16, ~0UL);
+ pnltmp.pup_delay = getenv_ulong("ds1_pupdelay", 10, ~0UL);
+ pnltmp.pon_delay = getenv_ulong("ds1_tondelay", 10, ~0UL);
+#endif
+ if (
+ ~0UL == (pnltmp.hactive) ||
+ ~0UL == (pnltmp.vactive) ||
+ ~0UL == (pnltmp.bpp) ||
+ ~0UL == (pnltmp.hfp) ||
+ ~0UL == (pnltmp.hbp) ||
+ ~0UL == (pnltmp.hsw) ||
+ ~0UL == (pnltmp.vfp) ||
+ ~0UL == (pnltmp.vbp) ||
+ ~0UL == (pnltmp.vsw) ||
+ ~0UL == (pnltmp.pxl_clk_div) ||
+ ~0UL == (pnltmp.pol) ||
+ ~0UL == (pnltmp.pup_delay) ||
+ ~0UL == (pnltmp.pon_delay)
+ ) {
+ puts("lcd-settings in env/dtb incomplete!\n");
+ printf("display-timings:\n"
+ "================\n"
+ "hactive: %d\n"
+ "vactive: %d\n"
+ "bpp : %d\n"
+ "hfp : %d\n"
+ "hbp : %d\n"
+ "hsw : %d\n"
+ "vfp : %d\n"
+ "vbp : %d\n"
+ "vsw : %d\n"
+ "pxlclk : %d\n"
+ "pol : 0x%08x\n"
+ "pondly : %d\n",
+ pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
+ pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
+ pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
+ pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay);
+
+ return -1;
+ }
+ debug("lcd-settings in env complete, taking over.\n");
+ memcpy((void *)panel,
+ (void *)&pnltmp,
+ sizeof(struct am335x_lcdpanel));
+
+ return 0;
+}
+
+#ifdef CONFIG_USE_FDT
+static int load_devicetree(void)
+{
+ char *dtbname = getenv("dtb");
+ char *dtbdev = getenv("dtbdev");
+ char *dtppart = getenv("dtbpart");
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ loff_t dtbsize;
+
+ if (!dtbdev || !dtbdev) {
+ puts("load_devicetree: <dtbdev>/<dtbpart> missing.\n");
+ return -1;
+ }
+
+ if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) {
+ puts("load_devicetree: set_blk_dev failed.\n");
+ return -1;
+ }
+ if (dtbname && dtbaddr != ~0UL) {
+ if (fs_read(dtbname, dtbaddr, 0, 0, &dtbsize) == 0) {
+ gd->fdt_blob = (void *)dtbaddr;
+ gd->fdt_size = dtbsize;
+ debug("loaded %d bytes of dtb onto 0x%08x\n",
+ (u32)dtbsize, dtbaddr);
+ return dtbsize;
+ }
+ puts("load_devicetree: load dtb failed,file does not exist!\n");
+ }
+
+ puts("load_devicetree: <dtb>/<dtbaddr> missing!\n");
+ return -1;
+}
+
+static const char *dtbmacaddr(u32 ifno)
+{
+ int node, len;
+ char enet[16];
+ const char *mac;
+ const char *path;
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("dtbmacaddr: failed to get 'dtbaddr' from env!\n");
+ return NULL;
+ }
+
+ node = fdt_path_offset((void *)dtbaddr, "/aliases");
+ if (node < 0)
+ return NULL;
+
+ sprintf(enet, "ethernet%d", ifno);
+ path = fdt_getprop((void *)dtbaddr, node, enet, NULL);
+ if (!path) {
+ printf("no alias for %s\n", enet);
+ return NULL;
+ }
+
+ node = fdt_path_offset((void *)dtbaddr, path);
+ mac = fdt_getprop((void *)dtbaddr, node, "mac-address", &len);
+ if (mac && is_valid_ether_addr((u8 *)mac))
+ return mac;
+
+ return NULL;
+}
+
+static void br_summaryscreen_printdtb(char *prefix,
+ char *name,
+ char *suffix)
+{
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+ char buf[32] = { 0 };
+ const char *nodep = buf;
+ char *mac = 0;
+ int nodeoffset;
+ int len;
+
+ if (dtbaddr == ~0UL) {
+ puts("br_summaryscreen: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+
+ if (strcmp(name, "brmac1") == 0) {
+ mac = (char *)dtbmacaddr(0);
+ if (mac)
+ sprintf(buf, "%pM", mac);
+ } else if (strcmp(name, "brmac2") == 0) {
+ mac = (char *)dtbmacaddr(1);
+ if (mac)
+ sprintf(buf, "%pM", mac);
+ } else {
+ nodeoffset = fdt_path_offset((void *)dtbaddr,
+ "/factory-settings");
+ if (nodeoffset < 0) {
+ puts("no 'factory-settings' in dtb!\n");
+ return;
+ }
+ nodep = fdt_getprop((void *)dtbaddr, nodeoffset, name, &len);
+ }
+ if (nodep && strlen(nodep) > 1)
+ lcd_printf("%s %s %s", prefix, nodep, suffix);
+ else
+ lcd_printf("\n");
+}
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(blob, "/factory-settings");
+ if (nodeoffset < 0) {
+ puts("set bootloader version 'factory-settings' not in dtb!\n");
+ return -1;
+ }
+ if (fdt_setprop(blob, nodeoffset, "bl-version",
+ PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) {
+ puts("set bootloader version 'bl-version' prop. not in dtb!\n");
+ return -1;
+ }
+ return 0;
+}
+#else
+
+static void br_summaryscreen_printenv(char *prefix,
+ char *name, char *altname,
+ char *suffix)
+{
+ char *envval = getenv(name);
+ if (0 != envval) {
+ lcd_printf("%s %s %s", prefix, envval, suffix);
+ } else if (0 != altname) {
+ envval = getenv(altname);
+ if (0 != envval)
+ lcd_printf("%s %s %s", prefix, envval, suffix);
+ } else {
+ lcd_printf("\n");
+ }
+}
+#endif
+void br_summaryscreen(void)
+{
+#ifdef CONFIG_USE_FDT
+ br_summaryscreen_printdtb(" - B&R -", "order-no", "-\n");
+ br_summaryscreen_printdtb(" Serial/Rev :", "serial-no", " /");
+ br_summaryscreen_printdtb(" ", "hw-revision", "\n");
+ br_summaryscreen_printdtb(" MAC (IF1) :", "brmac1", "\n");
+ br_summaryscreen_printdtb(" MAC (IF2) :", "brmac2", "\n");
+ lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+ lcd_puts("\n");
+#else
+ br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n");
+ br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n");
+ br_summaryscreen_printenv(" MAC (IF1) :", "br_mac1", "ethaddr", "\n");
+ br_summaryscreen_printenv(" MAC (IF2) :", "br_mac2", 0, "\n");
+ lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+ lcd_puts("\n");
+#endif
+}
+
+void lcdpower(int on)
+{
+ u32 pin, swval, i;
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("lcdpower: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+ pin = FDTPROP(dtbaddr, PATHINF, "pwrpin");
+#else
+ pin = getenv_ulong("ds1_pwr", 16, ~0UL);
+#endif
+ if (pin == ~0UL) {
+ puts("no pwrpin in dtb/env, cannot powerup display!\n");
+ return;
+ }
+
+ for (i = 0; i < 3; i++) {
+ if (pin != 0) {
+ swval = pin & 0x80 ? 0 : 1;
+ if (on)
+ gpio_direction_output(pin & 0x7F, swval);
+ else
+ gpio_direction_output(pin & 0x7F, !swval);
+
+ debug("switched pin %d to %d\n", pin & 0x7F, swval);
+ }
+ pin >>= 8;
+ }
+}
+
+vidinfo_t panel_info = {
+ .vl_col = 1366, /*
+ * give full resolution for allocating enough
+ * memory
+ */
+ .vl_row = 768,
+ .vl_bpix = 5,
+ .priv = 0
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct am335x_lcdpanel lcd_panel;
+#ifdef CONFIG_USE_FDT
+ /* TODO: is there a better place to load the dtb ? */
+ load_devicetree();
+#endif
+ memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel));
+ if (load_lcdtiming(&lcd_panel) != 0)
+ return;
+
+ lcd_panel.panel_power_ctrl = &lcdpower;
+
+ if (0 != am335xfb_init(&lcd_panel))
+ printf("ERROR: failed to initialize video!");
+ /*
+ * modifiy panel info to 'real' resolution, to operate correct with
+ * lcd-framework.
+ */
+ panel_info.vl_col = lcd_panel.hactive;
+ panel_info.vl_row = lcd_panel.vactive;
+
+ lcd_set_flush_dcache(1);
+}
+
+void lcd_enable(void)
+{
+#ifdef CONFIG_USE_FDT
+ u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL);
+
+ if (dtbaddr == ~0UL) {
+ puts("lcdpower: failed to get 'dtbaddr' from env!\n");
+ return;
+ }
+ unsigned int driver = FDTPROP(dtbaddr, PATHINF, "brightdrv");
+ unsigned int bright = FDTPROP(dtbaddr, PATHINF, "brightdef");
+ unsigned int pwmfrq = FDTPROP(dtbaddr, PATHINF, "brightfdim");
+#else
+ unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL);
+ unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50);
+ unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL);
+#endif
+ unsigned int tmp;
+ struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+
+ bright = bright != ~0UL ? bright : 50;
+
+ switch (driver) {
+ case 0: /* PMIC LED-Driver */
+ /* brightness level */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, bright, 0xFF);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x0A, 0xFF);
+ break;
+ case 1: /* PWM using timer6 */
+ if (pwmfrq != ~0UL) {
+ timerhw->tiocp_cfg = TCFG_RESET;
+ udelay(10);
+ while (timerhw->tiocp_cfg & TCFG_RESET)
+ ;
+ tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */
+ timerhw->tldr = tmp;
+ timerhw->tcrr = tmp;
+ tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright;
+ timerhw->tmar = tmp;
+ timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) |
+ TCLR_CE | TCLR_AR | TCLR_ST);
+ } else {
+ puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n");
+ }
+ break;
+ default:
+ puts("no suitable backlightdriver in env/dtb!\n");
+ break;
+ }
+ br_summaryscreen();
+}
+#elif CONFIG_SPL_BUILD
+#else
+#error "LCD-support with a suitable FB-Driver is mandatory !"
+#endif /* CONFIG_LCD */
+
void blink(u32 blinks, u32 intervall, u32 pin)
{
gpio_direction_output(pin, 0);
@@ -43,6 +454,7 @@ void blink(u32 blinks, u32 intervall, u32 pin)
gpio_set_value(pin, 0);
}
+
#ifdef CONFIG_SPL_BUILD
void pmicsetup(u32 mpupll)
{
@@ -115,6 +527,9 @@ void pmicsetup(u32 mpupll)
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+ /* Set PWR_EN bit in Status Register */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF);
}
void set_uart_mux_conf(void)
@@ -176,9 +591,9 @@ static struct cpsw_platform_data cpsw_data = {
int board_eth_init(bd_t *bis)
{
int rv = 0;
- uint8_t mac_addr[6];
+ char mac_addr[6];
+ const char *mac = 0;
uint32_t mac_hi, mac_lo;
-
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
@@ -192,14 +607,19 @@ int board_eth_init(bd_t *bis)
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
-
- if (is_valid_ether_addr(mac_addr)) {
- printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
- mac_addr[0], mac_addr[1], mac_addr[2],
- mac_addr[3], mac_addr[4], mac_addr[5]
- );
- eth_setenv_enetaddr("ethaddr", mac_addr);
+ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT)
+ printf("<ethaddr> not set. trying DTB ... ");
+ mac = dtbmacaddr(0);
+ #endif
+ if (!mac) {
+ printf("<ethaddr> not set. validating E-fuse MAC ... ");
+ if (is_valid_ether_addr((const u8 *)mac_addr))
+ mac = (const char *)mac_addr;
+ }
+
+ if (mac) {
+ printf("using: %pM on ", mac);
+ eth_setenv_enetaddr("ethaddr", (const u8 *)mac);
}
}
writel(MII_MODE_ENABLE, &cdev->miisel);
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
index 804765a..892311e 100644
--- a/board/BuR/kwb/board.c
+++ b/board/BuR/kwb/board.c
@@ -26,14 +26,13 @@
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
+#include <lcd.h>
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
-#define KEY (0+4)
-#define LCD_PWR (0+5)
-#define PUSH_KEY (0+31)
-#define USB2SD_NRST (32+29)
-#define USB2SD_PWR (96+13)
+#define ESC_KEY (0+19)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
/* -------------------------------------------------------------------------*/
/* -- PSOC Resetcontroller Register defines -- */
@@ -46,6 +45,13 @@
/* -- defines for RSTCTRL_CTRLREG -- */
#define RSTCTRL_FORCE_PWR_NEN 0x0404
+#define RSTCTRL_CAN_STB 0x4040
+
+#define VXWORKS_BOOTLINE 0x80001100
+#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks"
+#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget"
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
@@ -107,10 +113,13 @@ void am33xx_spl_board_init(void)
&cmper->epwmss0clkctrl,
&cmper->epwmss1clkctrl,
&cmper->epwmss2clkctrl,
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
-
+ /* setup LCD-Pixel Clock */
+ writel(0x2, CM_DPLL + 0x34);
/* power-OFF LCD-Display */
gpio_direction_output(LCD_PWR, 0);
@@ -121,7 +130,7 @@ void am33xx_spl_board_init(void)
/* power-ON 3V3 via Resetcontroller */
oldspeed = i2c_get_bus_speed();
if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
- buf = RSTCTRL_FORCE_PWR_NEN;
+ buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
(uint8_t *)&buf, sizeof(buf));
i2c_set_bus_speed(oldspeed);
@@ -129,15 +138,6 @@ void am33xx_spl_board_init(void)
puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
}
-#if defined(CONFIG_AM335X_USB0)
- /* power on USB2SD Controller */
- gpio_direction_output(USB2SD_PWR, 1);
- mdelay(1);
- /* give a reset Pulse to USB2SD Controller */
- gpio_direction_output(USB2SD_NRST, 0);
- mdelay(1);
- gpio_set_value(USB2SD_NRST, 1);
-#endif
pmicsetup(0);
}
@@ -166,59 +166,111 @@ int board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- const unsigned int ton = 250;
const unsigned int toff = 1000;
unsigned int cnt = 3;
unsigned short buf = 0xAAAA;
+ unsigned char scratchreg = 0;
unsigned int oldspeed;
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+ /* try to read out some boot-instruction from resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+ i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ &scratchreg, sizeof(scratchreg));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
- if (gpio_get_value(KEY)) {
+ if (gpio_get_value(ESC_KEY)) {
do {
- /* turn on light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x09, 0xFF);
- mdelay(ton);
- /* turn off light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ lcd_position_cursor(1, 8);
+ switch (cnt) {
+ case 3:
+ lcd_puts(
+ "release ESC-KEY to enter SERVICE-mode.");
+ break;
+ case 2:
+ lcd_puts(
+ "release ESC-KEY to enter DIAGNOSE-mode.");
+ break;
+ case 1:
+ lcd_puts(
+ "release ESC-KEY to enter BOOT-mode. ");
+ break;
+ }
mdelay(toff);
cnt--;
- if (!gpio_get_value(KEY) &&
+ if (!gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && 2 == cnt) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "switching to network-console ... ");
+ setenv("bootcmd", "run netconsole");
+ cnt = 4;
+ break;
+ } else if (!gpio_get_value(ESC_KEY) &&
gpio_get_value(PUSH_KEY) && 1 == cnt) {
- puts("updating from USB ...\n");
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "updating U-BOOT from USB ... ");
setenv("bootcmd", "run usbupdate");
+ cnt = 4;
+ break;
+ } else if ((!gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && cnt == 0) ||
+ (gpio_get_value(ESC_KEY) &&
+ gpio_get_value(PUSH_KEY) && cnt == 0)) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting script from network ... ");
+ setenv("bootcmd", "run netscript");
+ cnt = 4;
break;
- } else if (!gpio_get_value(KEY)) {
+ } else if (!gpio_get_value(ESC_KEY)) {
break;
}
} while (cnt);
+ } else if (scratchreg == 0xCC) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting vxworks from network ... ");
+ setenv("bootcmd", "run netboot");
+ cnt = 4;
+ } else if (scratchreg == 0xCD) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting script from network ... ");
+ setenv("bootcmd", "run netscript");
+ cnt = 4;
+ } else if (scratchreg == 0xCE) {
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "starting AR from eMMC ... ");
+ setenv("bootcmd", "run mmcboot");
+ cnt = 4;
}
+ lcd_position_cursor(1, 8);
switch (cnt) {
case 0:
- puts("3 blinks ... entering BOOT mode.\n");
+ lcd_puts("entering BOOT-mode. ");
+ setenv("bootcmd", "run defaultAR");
buf = 0x0000;
break;
case 1:
- puts("2 blinks ... entering DIAGNOSE mode.\n");
+ lcd_puts("entering DIAGNOSE-mode. ");
buf = 0x0F0F;
break;
case 2:
- puts("1 blinks ... entering SERVICE mode.\n");
+ lcd_puts("entering SERVICE mode. ");
buf = 0xB4B4;
break;
case 3:
- puts("0 blinks ... entering RUN mode.\n");
+ lcd_puts("loading OS... ");
buf = 0x0404;
break;
}
- mdelay(ton);
- /* turn on light */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_WLEDCTRL1, 0x09, 0xFF);
/* write bootinfo into scratchregister of resetcontroller */
oldspeed = i2c_get_bus_speed();
if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
@@ -228,6 +280,30 @@ int board_late_init(void)
} else {
puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
}
+ /* setup vxworks bootline */
+ char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
+
+ /* setup default IP, in case if there is nothing in environment */
+ if (!getenv("ipaddr")) {
+ setenv("ipaddr", "192.168.60.1");
+ setenv("netmask", "255.255.255.0");
+ setenv("serverip", "192.168.60.254");
+ setenv("gatewayip", "192.168.60.254");
+ puts("net: had no IP! made default setup.\n");
+ }
+
+ sprintf(vxworksbootline,
+ "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
+ DEFAULT_BOOTLINE,
+ getenv("serverip"),
+ getenv("ipaddr"), getenv("netmask"),
+ getenv("gatewayip"),
+ VXWORKS_USER,
+ (unsigned int) gd->fb_base-0x20,
+ (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
+ (u32)getenv_ulong("vx_romfsbase", 16, 0),
+ (u32)getenv_ulong("vx_romfssize", 16, 0));
+
/*
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
* expect that vectors are there, original u-boot moves them to _start
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
index ecb2e7a..9f89b5e 100644
--- a/board/BuR/kwb/mux.c
+++ b/board/BuR/kwb/mux.c
@@ -16,23 +16,17 @@
#include <asm/io.h>
#include <i2c.h>
-static struct module_pin_mux usb0_pin_mux[] = {
- {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
- /* USB0 DrvBus Receiver disable (from romcode 0x20) */
- {OFFSET(usb0_drvvbus), (MODE(0))},
- /* USB1 DrvBus as GPIO due to HW-Workaround */
- {OFFSET(usb1_drvvbus), (MODE(7))},
- {-1},
-};
-static struct module_pin_mux spi1_pin_mux[] = {
+static struct module_pin_mux spi0_pin_mux[] = {
/* SPI1_SCLK */
- {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
- {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
- {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
- {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ /* SPI1_CS1 */
+ {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
@@ -53,30 +47,34 @@ static struct module_pin_mux dcan1_pin_mux[] = {
};
static struct module_pin_mux gpios[] = {
- /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
- {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
- /* GPIO0_4 (SPI D1) - TA602 */
- {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
- /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
- {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
/* GPIO0_7 (PWW0 OUT) - CAN TERM */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
- /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
- {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
- /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
- {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_19 (DMA_INTR0) - TA602 */
+ {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
/* GPIO0_30 (GPMC_WAIT0) - TA601 */
{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO1_29 (gpmc_csn0) - MMC nRST */
+ {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
/* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
/* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_4 (GPMC_nWE) - TST_BAST */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
+ {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
+ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
@@ -126,6 +124,10 @@ static struct module_pin_mux mii1_pin_mux[] = {
};
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
@@ -187,8 +189,7 @@ void enable_board_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(usb0_pin_mux);
- configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
index c0178e7..9402aa4 100644
--- a/board/BuR/tseries/board.c
+++ b/board/BuR/tseries/board.c
@@ -27,15 +27,15 @@
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
+#include <lcd.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------------------*/
/* -- defines for GPIO -- */
-#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
#define REPSWITCH (0+20) /* GPIO0_20 */
-
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
static const struct ddr_data ddr3_data = {
@@ -82,7 +82,6 @@ static const struct ctrl_ioregs ddr3_ioregs = {
int spl_start_uboot(void)
{
if (0 == gpio_get_value(REPSWITCH)) {
- blink(5, 125, ETHLED_ORANGE);
mdelay(1000);
printf("SPL: entering u-boot instead kernel image.\n");
return 1;
@@ -96,7 +95,35 @@ static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
- pmicsetup(1000);
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+ /*
+ * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
+ * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
+ * the source of timer6 clk to CLK_M_OSC
+ */
+ writel(0x01, &cmdpll->clktimer6clk);
+
+ /* enable additional clocks of modules which are accessed later */
+ u32 *const clk_domains[] = {
+ &cmper->lcdcclkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_tsspecific[] = {
+ &cmper->lcdclkctrl,
+ &cmper->timer5clkctrl,
+ &cmper->timer6clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
+
+ /* setup LCD-Pixel Clock */
+ writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
+
+ pmicsetup(0);
}
const struct dpll_params *get_dpll_ddr_params(void)
@@ -116,6 +143,9 @@ void sdram_init(void)
/* Basic board specific setup. Pinmux has been handled already. */
int board_init(void)
{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND
gpmc_init();
@@ -126,24 +156,12 @@ int board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- gpio_direction_output(ETHLED_ORANGE, 0);
-
if (0 == gpio_get_value(REPSWITCH)) {
- printf("\n\n\n"
- "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
- "!!!!!!! recovery switch activated !!!!!!!\n"
- "!!!!!!! running usbupdate !!!!!!!\n"
- "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
- setenv("bootcmd", "sleep 2; run netupdate;");
+ lcd_position_cursor(1, 8);
+ lcd_puts(
+ "switching to network-console ... ");
+ setenv("bootcmd", "run netconsole");
}
-
- printf("turning on display power+backlight ... ");
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
- 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
- tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
- 0x62, TPS65217_MASK_ALL_BITS); /* 100% */
- printf("ok.\n");
-
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index 0ba25ee..2c87a63 100644
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -25,6 +25,13 @@ static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
+static struct module_pin_mux uart1_pin_mux[] = {
+ /* UART0_RXD */
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
@@ -131,9 +138,9 @@ static struct module_pin_mux gpIOs[] = {
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
- /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
- {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
+ /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
+ {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
@@ -168,7 +175,14 @@ static struct module_pin_mux gpIOs[] = {
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
-
+#ifndef CONFIG_NAND
+ /* GPIO2_3 - NAND_OE */
+ {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+ /* GPIO2_4 - NAND_WEN */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+ /* GPIO2_5 - NAND_BE_CLE */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+#endif
{-1},
};
@@ -229,5 +243,6 @@ void enable_board_pin_mux(void)
#endif
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(uart1_pin_mux);
configure_module_pin_mux(gpIOs);
}
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 5897318..20db812 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -143,5 +143,8 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
return rc;
}
diff --git a/board/birdland/bav335x/Kconfig b/board/birdland/bav335x/Kconfig
new file mode 100644
index 0000000..3380ed3
--- /dev/null
+++ b/board/birdland/bav335x/Kconfig
@@ -0,0 +1,33 @@
+if TARGET_BAV335X
+
+config SYS_BOARD
+ default "bav335x"
+
+config SYS_VENDOR
+ default "birdland"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "bav335x"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. Depending on your specific
+ board you may want something other than UART0 as for example the IDK
+ uses UART3 so enter 4 here.
+
+config BAV_VERSION
+ int "BAV335x Version (1=A, 2=B)"
+ range 1 2
+ help
+ The BAV335x has various version of the board. Rev.A (mostly obsolete)
+ used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY.
+ Overwrite this if you have an older Rev.A and want ethernet support.
+
+endif
diff --git a/board/birdland/bav335x/MAINTAINERS b/board/birdland/bav335x/MAINTAINERS
new file mode 100644
index 0000000..45dcfcb
--- /dev/null
+++ b/board/birdland/bav335x/MAINTAINERS
@@ -0,0 +1,13 @@
+BAV335x BOARD
+M: Gilles Gameiro <gilles@gigadevices.com>
+S: Maintained
+F: include/configs/bav335x.h
+F: board/birdland/bav335x/Kconfig
+F: board/birdland/bav335x/Makefile
+F: board/birdland/bav335x/README
+F: board/birdland/bav335x/board.c
+F: board/birdland/bav335x/board.h
+F: board/birdland/bav335x/mux.c
+F: board/birdland/bav335x/u-boot.lds
+F: configs/birdland_bav335a_defconfig
+F: configs/birdland_bav335b_defconfig
diff --git a/board/birdland/bav335x/Makefile b/board/birdland/bav335x/Makefile
new file mode 100644
index 0000000..2fc5614
--- /dev/null
+++ b/board/birdland/bav335x/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile
+#
+# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
diff --git a/board/birdland/bav335x/README b/board/birdland/bav335x/README
new file mode 100644
index 0000000..08c73ee
--- /dev/null
+++ b/board/birdland/bav335x/README
@@ -0,0 +1,31 @@
+Summary
+=======
+
+This document covers various features of the 'BAV335x' board build.
+For more information about this board, visit http://birdland.com/oem
+
+
+Hardware
+========
+
+The binary produced supports the bav335x Rev.A with 10/100 MB PHY
+and Rev.B (default) with GB ethernet PHY.
+If the BAV335x EEPROM is populated and programmed, the board will
+automatically detect the version and extract proper serial# and
+mac address from the EE.
+
+
+Customization
+=============
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+ errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings). Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c
new file mode 100644
index 0000000..d1e1c8c
--- /dev/null
+++ b/board/birdland/bav335x/board.c
@@ -0,0 +1,430 @@
+/*
+ * board.c
+ *
+ * Board functions for Birdland Audio BAV335x Network Processor
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN 7
+
+static __maybe_unused struct ctrl_dev *cdev =
+ (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct board_eeconfig *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
+ return -ENODEV;
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct board_eeconfig)))
+ return -EIO;
+
+ if (header->magic != BOARD_MAGIC) {
+ /* read the i2c eeprom again using only a 1 byte address */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct board_eeconfig)))
+ return -EIO;
+
+ if (header->magic != BOARD_MAGIC)
+ return -EINVAL;
+ }
+ return 0;
+}
+
+
+
+
+enum board_type get_board_type(bool debug)
+{
+ int ecode;
+ struct board_eeconfig header;
+
+ ecode = read_eeprom(&header);
+ if (ecode == 0) {
+ if (header.version[1] == 'A') {
+ if (debug)
+ puts("=== Detected Board model BAV335x Rev.A");
+ return BAV335A;
+ } else if (header.version[1] == 'B') {
+ if (debug)
+ puts("=== Detected Board model BAV335x Rev.B");
+ return BAV335B;
+ } else if (debug) {
+ puts("### Un-known board model in serial-EE\n");
+ }
+ } else if (debug) {
+ switch (ecode) {
+ case -ENODEV:
+ puts("### Board doesn't have a serial-EE\n");
+ break;
+ case -EINVAL:
+ puts("### Board serial-EE signature is incorrect.\n");
+ break;
+ default:
+ puts("### IO Error reading serial-EE.\n");
+ break;
+ }
+ }
+
+#if (CONFIG_BAV_VERSION == 1)
+ if (debug)
+ puts("### Selecting BAV335A as per config\n");
+ return BAV335A;
+#elif (CONFIG_BAV_VERSION == 2)
+ if (debug)
+ puts("### Selecting BAV335B as per config\n");
+ return BAV335B;
+#endif
+#if (NOT_DEFINED == 2)
+#error "SHOULD NEVER DISPLAY THIS"
+#endif
+
+ if (debug)
+ puts("### Defaulting to model BAV335x Rev.B\n");
+ return BAV335B;
+}
+
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr3_bav335x_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+
+static struct emif_regs ddr3_bav335x_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ /* debug print detect status */
+ (void)get_board_type(true);
+
+ /* Get the frequency */
+ /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /* Set the USB Current Limit */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+ TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("! tps65217_reg_write: could not set USB limit\n");
+
+ /* Set the Core Voltage (DCDC3) to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("! tps65217_reg_write: could not set Core Voltage\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set the MPU Voltage (DCDC2) */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2,
+ TPS65217_DCDC_VOLT_SEL_1325MV)) {
+ puts("! tps65217_reg_write: could not set MPU Voltage\n");
+ return;
+ }
+
+ /*
+ * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+ * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+ */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
+ puts("! tps65217_reg_write: could not set LDO3\n");
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
+ puts("! tps65217_reg_write: could not set LDO4\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ return &dpll_ddr_bone_black;
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+ enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+ enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+ enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+ enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+ enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+ enum board_type board;
+
+ board = get_board_type(false);
+ enable_board_pin_mux(board);
+}
+
+const struct ctrl_ioregs ioregs_bonelt = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+ config_ddr(400, &ioregs_bonelt,
+ &ddr3_bav335x_data,
+ &ddr3_bav335x_cmd_ctrl_data,
+ &ddr3_bav335x_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+ gpmc_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "BAV335xB");
+ setenv("board_rev", "B"); /* Fix me, but why bother.. */
+#endif
+ return 0;
+}
+#endif
+
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+
+/*
+ * This function will:
+ * Perform fixups to the PHY present on certain boards. We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int ecode, rv, n;
+ uint8_t mac_addr[6];
+ struct board_eeconfig header;
+ __maybe_unused enum board_type board;
+
+ /* Default manufacturing address; used when no EE or invalid */
+ n = 0;
+ mac_addr[0] = 0;
+ mac_addr[1] = 0x20;
+ mac_addr[2] = 0x18;
+ mac_addr[3] = 0x1C;
+ mac_addr[4] = 0x00;
+ mac_addr[5] = 0x01;
+
+ ecode = read_eeprom(&header);
+ /* if we have a valid EE, get mac address from there */
+ if ((ecode == 0) &&
+ is_valid_ether_addr((const u8 *)&header.mac_addr[0][0])) {
+ memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
+ }
+
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+ board = get_board_type(false);
+
+ /* Rev.A uses 10/100 PHY in mii mode */
+ if (board == BAV335A) {
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+ }
+ /* Rev.B (default) uses GB PHY in rmii mode */
+ else {
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
+ = PHY_INTERFACE_MODE_RGMII;
+ }
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+#endif
+
+ return n;
+}
+#endif
diff --git a/board/birdland/bav335x/board.h b/board/birdland/bav335x/board.h
new file mode 100644
index 0000000..b598ce1
--- /dev/null
+++ b/board/birdland/bav335x/board.h
@@ -0,0 +1,59 @@
+/*
+ * board.c
+ *
+ * Board functions for Birdland Audio BAV335x Network Processor
+ *
+ * Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Serial MagicE: AA 55 BA BE */
+#define BOARD_MAGIC 0xBEBA55AA
+enum board_type {UNKNOWN, BAV335A, BAV335B};
+
+
+/*
+ * The BAV335x may use a built-in read-only serial EEProm.
+ * The Evaluation board, disables the write-protect so the Serial-EE
+ * Can be programmed during manufacturing to store fields such as
+ * a board serial number, ethernet mac address and other user fields.
+ * Additionally, the Serial-EE can store the specific version of the
+ * board it runs on, and overwrite the defaults in _defconfig
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct board_eeconfig {
+ unsigned int magic;
+ char name[HDR_NAME_LEN]; /* BAV3354 */
+ char version[4]; /* 0B20 - Rev.B2 */
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+enum board_type get_board_type(bool verbose_debug_output);
+
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(enum board_type board);
+
+#endif
diff --git a/board/birdland/bav335x/mux.c b/board/birdland/bav335x/mux.c
new file mode 100644
index 0000000..f18bfa4
--- /dev/null
+++ b/board/birdland/bav335x/mux.c
@@ -0,0 +1,190 @@
+/*
+ * mux.c
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR 0x35
+#define CFG_REG 0x10
+
+
+void enable_board_pin_mux(enum board_type board)
+{
+ configure_module_pin_mux(i2c1_pin_mux);
+ if (board == BAV335A)
+ configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
+ else
+ configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
+
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+}
diff --git a/board/birdland/bav335x/u-boot.lds b/board/birdland/bav335x/u-boot.lds
new file mode 100644
index 0000000..fc80f21
--- /dev/null
+++ b/board/birdland/bav335x/u-boot.lds
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ board/birdland/bav335x/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index e8ea256..d46b8db 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -1018,5 +1018,6 @@ int misc_init_r(void)
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+ setenv_hex("reset_cause", get_imx_reset_cause());
return 0;
}
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 2cd1794..4980bf7 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -5,9 +5,47 @@
*/
#include <common.h>
+#include <errno.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
+int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id, ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+ id = id & 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf("Not supported, id=%d\n", id);
+ return -EINVAL;
+ }
+
+ ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+ if (ret < 0) {
+ printf("Set SW1AB mode error!\n");
+ return ret;
+ }
+
+ for (i = 0; i < switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+ if (ret < 0) {
+ printf("Set switch 0x%x mode error!\n",
+ offset + i * SWITCH_SIZE);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
struct pmic *pfuze_common_init(unsigned char i2cbus)
{
struct pmic *p;
diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h
index 7a4126c..53cfc99 100644
--- a/board/freescale/common/pfuze.h
+++ b/board/freescale/common/pfuze.h
@@ -8,5 +8,6 @@
#define __PFUZE_BOARD_HELPER__
struct pmic *pfuze_common_init(unsigned char i2cbus);
+int pfuze_mode_init(struct pmic *p, u32 mode);
#endif
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 71a395c..01dac72 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -146,8 +146,8 @@ int board_late_init(void)
if (!p)
return -ENODEV;
- /* Turn on Ethernet PHY supply */
- pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+ /* Turn on Ethernet PHY and LCD supplies */
+ pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
return 0;
}
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index efcf4b3..9ece6ec 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -366,22 +366,6 @@ int board_early_init_f(void)
return 0;
}
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 cpurev;
-
- cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
- (cpurev & 0xFF000) >> 12,
- (cpurev & 0x000F0) >> 4,
- (cpurev & 0x0000F) >> 0,
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- printf("Reset cause: %s\n", get_reset_cause());
- return 0;
-}
-#endif
-
/*
* Do not overwrite the console
* Use always serial for U-Boot console
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index a90360f..b76e4eb 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -29,6 +29,7 @@
#include <asm/arch/crm_regs.h>
#include <pca953x.h>
#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -494,11 +495,16 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
int power_init_board(void)
{
struct pmic *p;
+ unsigned int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
return 0;
}
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2f7198d..bb2dd96 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -631,12 +631,16 @@ int board_init(void)
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg;
+ unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
reg &= ~LDO_VOL_MASK;
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 838ea6c..7c18c90 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,13 +13,18 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
+#include <i2c.h>
#include <mmc.h>
#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
@@ -40,6 +45,16 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
+ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_FAST)
+
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
int dram_init(void)
@@ -221,6 +236,34 @@ int board_mmc_init(bd_t *bis)
return 0;
}
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+};
+
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ return pfuze_mode_init(p, APS_PFM);
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
@@ -247,7 +290,7 @@ static int setup_fec(void)
static iomux_v3_cfg_t const usb_otg_pads[] = {
/* OTG1 */
MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
/* OTG2 */
MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};
@@ -297,6 +340,10 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index a2c9aae..2ff960e 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -199,12 +199,16 @@ static struct i2c_pads_info i2c_pad_info1 = {
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg;
+ unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg &= ~LDO_VOL_MASK;
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 11472eb..25480e4 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,10 +20,8 @@
void gpio_early_init_uart(void)
{
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-#ifndef CONFIG_SPL_BUILD
gpio_request(GPIO_PI3, NULL);
-#endif
- tegra_spl_gpio_direction_output(GPIO_PI3, 0);
+ gpio_direction_output(GPIO_PI3, 0);
}
#endif
diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig
new file mode 100644
index 0000000..8df9421
--- /dev/null
+++ b/board/quipos/cairo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_CAIRO
+
+config SYS_BOARD
+ default "cairo"
+
+config SYS_VENDOR
+ default "quipos"
+
+config SYS_CONFIG_NAME
+ default "omap3_cairo"
+
+endif
diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile
new file mode 100644
index 0000000..445088f
--- /dev/null
+++ b/board/quipos/cairo/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 DENX Software Engineering
+# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cairo.o
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
new file mode 100644
index 0000000..b97a09a
--- /dev/null
+++ b/board/quipos/cairo/cairo.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014 DENX
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from code written by Robert Aigner (ra@spiid.net)
+ *
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <netdev.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include <asm/omap_mmc.h>
+#include "cairo.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+ u8 retval = 0;
+
+ /* TODO: verify if cairo handheld platform needs extvbus programming */
+
+ return retval;
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_CAIRO();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory.
+ *
+ * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->sharing = SAMSUNG_SHARING;
+ timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
+ timings->ctrla = SAMSUNG_V_ACTIMA_165;
+ timings->ctrlb = SAMSUNG_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mr = SAMSUNG_V_MR_165;
+}
+#endif
+
+static const struct ns16550_platdata cairo_serial = {
+ OMAP34XX_UART2,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(cairo_uart) = {
+ "serial_omap",
+ &cairo_serial
+};
+
+/* force SPL booting into U-Boot, not Linux */
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 1;
+}
+#endif
diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h
new file mode 100644
index 0000000..50734d0
--- /dev/null
+++ b/board/quipos/cairo/cairo.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) DENX
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Original code (C) Copyright 2010
+ * Robert Aigner (ra@spiid.net)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 Cairo board",
+ "NAND",
+};
+
+/*
+ * OMAP3 Cairo handheld hardware revision
+ */
+enum {
+ OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */
+ OMAP3_CAIRO_BOARD_GEN_2,
+};
+
+#define MUX_CAIRO() \
+MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
+MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
+ (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
+
+#endif
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 6c7f59b..2e17da8 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -82,13 +82,19 @@ int board_init(void)
}
boot_temp_check();
#endif
+#ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE
+ /* The last few MB of memory can be reserved for secure firmware */
+ ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE;
+ gd->ram_size -= size;
+ gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
+#endif
return exynos_init();
}
int dram_init(void)
{
- int i;
+ unsigned int i;
u32 addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
@@ -100,7 +106,7 @@ int dram_init(void)
void dram_init_banksize(void)
{
- int i;
+ unsigned int i;
u32 addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 6f4b8ca..ae41c29 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -427,10 +427,6 @@ int exynos_early_init_f(void)
int exynos_init(void)
{
- /* The last MB of memory is reserved for secure firmware */
- gd->ram_size -= SZ_1M;
- gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
-
board_gpio_init();
return 0;
diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig
new file mode 100644
index 0000000..dd9816e
--- /dev/null
+++ b/board/sysam/amcore/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_AMCORE
+
+config SYS_CPU
+ string
+ default "mcf530x"
+
+config SYS_BOARD
+ string
+ default "amcore"
+
+config SYS_VENDOR
+ string
+ default "sysam"
+
+config SYS_CONFIG_NAME
+ string
+ default "amcore"
+
+endif
+
+
+
diff --git a/board/sysam/amcore/MAINTAINERS b/board/sysam/amcore/MAINTAINERS
new file mode 100644
index 0000000..fe5dd9b
--- /dev/null
+++ b/board/sysam/amcore/MAINTAINERS
@@ -0,0 +1,6 @@
+AMCORE BOARD
+M: Angelo Dureghello <angelo@sysam.it>
+S: Maintained
+F: board/sysam/amcore/
+F: include/configs/amcore.h
+F: configs/amcore_defconfig
diff --git a/board/sysam/amcore/Makefile b/board/sysam/amcore/Makefile
new file mode 100644
index 0000000..051186f
--- /dev/null
+++ b/board/sysam/amcore/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = amcore.o
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
new file mode 100644
index 0000000..42b7c23
--- /dev/null
+++ b/board/sysam/amcore/amcore.c
@@ -0,0 +1,101 @@
+/*
+ * Board functions for Sysam AMCORE (MCF5307 based) board
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file copies memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+void init_lcd(void)
+{
+ /* setup for possible K0108 lcd connected on the parallel port */
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+
+ out_be16(&sim->par, 0x300);
+
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+ out_be16(&gpio->paddr, 0xfcff);
+ out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("AMCORE v.001(alpha)\n");
+
+ init_lcd();
+
+ return 0;
+}
+
+/*
+ * in initdram we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+ while (usec--)
+ asm volatile ("nop");
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize, RC;
+
+ sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
+
+ /*
+ * SDRAM MT48LC4M32B2 details
+ * Memory block 0: 16 MB of SDRAM at address $00000000
+ * Port size: 32-bit port
+ *
+ * Memory block 0 wired as follows:
+ * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+ * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
+ *
+ * Ensure that there is a delay of at least 100 microseconds from
+ * processor reset to the following code so that the SDRAM is ready
+ * for commands.
+ */
+ fudelay(100);
+
+ /*
+ * DCR
+ * set proper RC as per specification
+ */
+ RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* 0x8000 is the faster option */
+ out_be16(&dc->dcr, 0x8200 | RC);
+
+ /*
+ * DACR0, page mode continuous, CMD on A20 0x0300
+ */
+ out_be32(&dc->dacr0, 0x00003304);
+
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+ out_be32(&dc->dmr0, dramsize|1);
+
+ /* issue a PRECHARGE ALL */
+ out_be32(&dc->dacr0, 0x0000330c);
+ out_be32((u32 *)0x00000004, 0xbeaddeed);
+ /* issue AUTOREFRESH */
+ out_be32(&dc->dacr0, 0x0000b304);
+ /* let refresh occour */
+ fudelay(1);
+
+ out_be32(&dc->dacr0, 0x0000b344);
+ out_be32((u32 *)0x00000c00, 0xbeaddeed);
+
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+}
diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk
new file mode 100644
index 0000000..d01a8bb
--- /dev/null
+++ b/board/sysam/amcore/config.mk
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
diff --git a/board/sysam/amcore/u-boot.lds b/board/sysam/amcore/u-boot.lds
new file mode 100644
index 0000000..2f7a241
--- /dev/null
+++ b/board/sysam/amcore/u-boot.lds
@@ -0,0 +1,87 @@
+/*
+ * Linker script for Sysam AMCORE board
+ *
+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf530x/start.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.sdata)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index dfa430e..42b166d 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -326,21 +326,25 @@ static void setup_display(void)
reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
writel(reg, &ccm->analog_pll_video);
- /* select video pll for ldb_di0_clk */
- reg = readl(&ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
- writel(reg, &ccm->cs2cdr);
+ /* gate ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);
- /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
- reg = readl(&ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &ccm->cscmr2);
-
- /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
+ /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
reg = readl(&ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+ MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+ (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+ (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &ccm->chsccdr);
+
+ /* enable ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);
}
#endif /* CONFIG_VIDEO_IPUV3 */
diff --git a/board/warp/Kconfig b/board/warp/Kconfig
new file mode 100644
index 0000000..7b569cc
--- /dev/null
+++ b/board/warp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WARP
+
+config SYS_BOARD
+ default "warp"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "warp"
+
+endif
diff --git a/board/warp/MAINTAINERS b/board/warp/MAINTAINERS
new file mode 100644
index 0000000..ee2114d
--- /dev/null
+++ b/board/warp/MAINTAINERS
@@ -0,0 +1,6 @@
+WaRP BOARD
+M: Otavio Salvador <otavio@ossystems.com.br>
+S: Maintained
+F: board/warp/
+F: include/configs/warp.h
+F: configs/warp_defconfig
diff --git a/board/warp/Makefile b/board/warp/Makefile
new file mode 100644
index 0000000..c555f87
--- /dev/null
+++ b/board/warp/Makefile
@@ -0,0 +1,8 @@
+# Copyright (C) 2014 O.S. Systems Software LTDA.
+# Copyright (C) 2014 Kynetics LLC.
+# Copyright (C) 2014 Revolution Robotics, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := warp.o
diff --git a/board/warp/warp.c b/board/warp/warp.c
new file mode 100644
index 0000000..21ac5e7
--- /dev/null
+++ b/board/warp/warp.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2014, 2015 O.S. Systems Software LTDA.
+ * Copyright (C) 2014 Kynetics LLC.
+ * Copyright (C) 2014 Revolution Robotics, Inc.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <watchdog.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS | \
+ PAD_CTL_LVE)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS | \
+ PAD_CTL_LVE)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* Assume boot SD always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_usb_phy_mode(int port)
+{
+ return USB_INIT_DEVICE;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: WaRP Board\n");
+
+ return 0;
+}
diff --git a/common/Kconfig b/common/Kconfig
index f82bc88..e662774 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -133,7 +133,7 @@ config LOOPW
Infinite write loop on address range
config CMD_MEMTEST
- bool "crc32"
+ bool "memtest"
help
Simple RAM read/write test.
diff --git a/common/board_f.c b/common/board_f.c
index 4d8b8a6..fc3e7dd 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -174,7 +174,7 @@ static int announce_dram_init(void)
return 0;
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int init_func_ram(void)
{
#ifdef CONFIG_BOARD_TYPES
@@ -598,7 +598,7 @@ static int display_new_sp(void)
return 0;
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int setup_board_part1(void)
{
bd_t *bd = gd->bd;
@@ -619,7 +619,7 @@ static int setup_board_part1(void)
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
@@ -648,6 +648,14 @@ static int setup_board_part2(void)
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
+#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
+ bd->bi_pcifreq = gd->pci_clk;
+#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
+ bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
+ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
+#endif
return 0;
}
@@ -709,6 +717,13 @@ static int setup_reloc(void)
{
#ifdef CONFIG_SYS_TEXT_BASE
gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
+#ifdef CONFIG_M68K
+ /*
+ * On all ColdFire arch cpu, monitor code starts always
+ * just after the default vector table location, so at 0x400
+ */
+ gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
+#endif
#endif
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
@@ -834,6 +849,9 @@ static init_fnc_t init_sequence_f[] = {
#ifdef CONFIG_FSL_ESDHC
get_clocks,
#endif
+#ifdef CONFIG_M68K
+ get_clocks,
+#endif
env_init, /* initialize environment */
#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
/* get CPU and bus clocks according to the environment variable */
@@ -860,7 +878,7 @@ static init_fnc_t init_sequence_f[] = {
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
checkcpu,
#endif
print_cpuinfo, /* display cpu info (and speed) */
@@ -886,7 +904,7 @@ static init_fnc_t init_sequence_f[] = {
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
dram_init, /* configure available RAM banks */
#endif
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
init_func_ram,
#endif
#ifdef CONFIG_POST
@@ -954,7 +972,7 @@ static init_fnc_t init_sequence_f[] = {
reserve_stacks,
setup_dram_config,
show_dram_config,
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
setup_board_part1,
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
@@ -1044,7 +1062,7 @@ void board_init_f_r(void)
* Transfer execution from Flash to RAM by calculating the address
* of the in-RAM copy of board_init_r() and calling it
*/
- (board_init_r + gd->reloc_off)(gd, gd->relocaddr);
+ (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
/* NOTREACHED - board_init_r() does not return */
hang();
diff --git a/common/board_r.c b/common/board_r.c
index 4fcd4f6..38be09b 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -167,14 +167,17 @@ static int initr_serial(void)
return 0;
}
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int initr_trap(void)
{
/*
* Setup trap handlers
*/
+#if defined(CONFIG_PPC)
trap_init(gd->relocaddr);
-
+#else
+ trap_init(CONFIG_SYS_SDRAM_BASE);
+#endif
return 0;
}
#endif
@@ -268,14 +271,6 @@ static int initr_malloc(void)
return 0;
}
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-static int initr_noncached(void)
-{
- noncached_init();
- return 0;
-}
-#endif
-
#ifdef CONFIG_DM
static int initr_dm(void)
{
@@ -703,9 +698,6 @@ init_fnc_t init_sequence_r[] = {
#endif
initr_barrier,
initr_malloc,
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
- initr_noncached,
-#endif
bootstage_relocate,
#ifdef CONFIG_DM
initr_dm,
@@ -729,7 +721,7 @@ init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
initr_trap,
#endif
#ifdef CONFIG_ADDR_MAP
@@ -767,7 +759,7 @@ init_fnc_t init_sequence_r[] = {
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
@@ -831,7 +823,8 @@ init_fnc_t init_sequence_r[] = {
#if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
initr_enable_interrupts,
#endif
-#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
+#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) \
+ || defined(CONFIG_M68K)
timer_init, /* initialize timer */
#endif
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 48199bf..4f77f22 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -78,7 +78,8 @@ static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc,
return CMD_RET_USAGE;
}
- if (state != BOOTM_STATE_START && images.state >= state) {
+ if (((state & BOOTM_STATE_START) != BOOTM_STATE_START) &&
+ images.state >= state) {
printf("Trying to execute a command out of order\n");
return CMD_RET_USAGE;
}
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index 29f0f1f..e9904cd 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -161,6 +161,9 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_read (addr, alen, buffer, len);
#else
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
if (i2c_read(addr[0], offset, alen - 1, buffer, len))
rcode = 1;
#endif
@@ -339,6 +342,9 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
/* Write is enabled ... now write eeprom value.
*/
#endif
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
if (i2c_write(addr[0], offset, alen - 1, buffer, len))
rcode = 1;
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
index e38422d..c56fe15 100644
--- a/common/cmd_gpt.c
+++ b/common/cmd_gpt.c
@@ -154,17 +154,24 @@ static int set_gpt_info(block_dev_desc_t *dev_desc,
/* extract disk guid */
s = str;
- tok = strsep(&s, ";");
- val = extract_val(tok, "uuid_disk");
+ val = extract_val(str, "uuid_disk");
if (!val) {
+#ifdef CONFIG_RANDOM_UUID
+ *str_disk_guid = malloc(UUID_STR_LEN + 1);
+ gen_rand_uuid_str(*str_disk_guid, UUID_STR_FORMAT_STD);
+#else
free(str);
return -2;
+#endif
+ } else {
+ val = strsep(&val, ";");
+ if (extract_env(val, &p))
+ p = val;
+ *str_disk_guid = strdup(p);
+ free(val);
+ /* Move s to first partition */
+ strsep(&s, ";");
}
- if (extract_env(val, &p))
- p = val;
- *str_disk_guid = strdup(p);
- free(val);
-
if (strlen(s) == 0)
return -3;
@@ -192,20 +199,25 @@ static int set_gpt_info(block_dev_desc_t *dev_desc,
/* uuid */
val = extract_val(tok, "uuid");
- if (!val) { /* 'uuid' is mandatory */
- errno = -4;
- goto err;
- }
- if (extract_env(val, &p))
- p = val;
- if (strlen(p) >= sizeof(parts[i].uuid)) {
- printf("Wrong uuid format for partition %d\n", i);
+ if (!val) {
+ /* 'uuid' is optional if random uuid's are enabled */
+#ifdef CONFIG_RANDOM_UUID
+ gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_STD);
+#else
errno = -4;
goto err;
+#endif
+ } else {
+ if (extract_env(val, &p))
+ p = val;
+ if (strlen(p) >= sizeof(parts[i].uuid)) {
+ printf("Wrong uuid format for partition %d\n", i);
+ errno = -4;
+ goto err;
+ }
+ strcpy((char *)parts[i].uuid, p);
+ free(val);
}
- strcpy((char *)parts[i].uuid, p);
- free(val);
-
/* name */
val = extract_val(tok, "name");
if (!val) { /* name is mandatory */
@@ -281,11 +293,11 @@ static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part)
}
/* save partitions layout to disk */
- gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
+ ret = gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
free(str_disk_guid);
free(partitions);
- return 0;
+ return ret;
}
/**
diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
index 2c879ea..51c3fff 100644
--- a/common/cmd_usb_mass_storage.c
+++ b/common/cmd_usb_mass_storage.c
@@ -159,6 +159,6 @@ exit:
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
"Use the UMS [User Mass Storage]",
- "ums <USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
+ "<USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
" devtype defaults to mmc"
);
diff --git a/common/cmd_yaffs2.c b/common/cmd_yaffs2.c
index d43a9d4..9244606 100644
--- a/common/cmd_yaffs2.c
+++ b/common/cmd_yaffs2.c
@@ -281,46 +281,46 @@ int do_ymv(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
U_BOOT_CMD(ytrace, 2, 0, do_ytrace,
"show/set yaffs trace mask",
- "ytrace [new_mask] show/set yaffs trace mask");
+ "[new_mask] show/set yaffs trace mask");
U_BOOT_CMD(ydevls, 1, 0, do_ydevls,
"list yaffs mount points", "list yaffs mount points");
U_BOOT_CMD(ydevconfig, 5, 0, do_ydevconfig,
"configure yaffs mount point",
- "ydevconfig mtpoint mtd_id start_block end_block configures a yaffs2 mount point");
+ "mtpoint mtd_id start_block end_block configures a yaffs2 mount point");
U_BOOT_CMD(ymount, 2, 0, do_ymount,
- "mount yaffs", "ymount mtpoint mounts a yaffs2 mount point");
+ "mount yaffs", "mtpoint mounts a yaffs2 mount point");
U_BOOT_CMD(yumount, 2, 0, do_yumount,
- "unmount yaffs", "yunmount mtpoint unmounts a yaffs2 mount point");
+ "unmount yaffs", "mtpoint unmounts a yaffs2 mount point");
-U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "yls [-l] dirname");
+U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "[-l] dirname");
U_BOOT_CMD(yrd, 2, 0, do_yrd,
- "read file from yaffs", "yrd path read file from yaffs");
+ "read file from yaffs", "path read file from yaffs");
U_BOOT_CMD(ywr, 4, 0, do_ywr,
"write file to yaffs",
- "ywr filename value num_vlues write values to yaffs file");
+ "filename value num_vlues write values to yaffs file");
U_BOOT_CMD(yrdm, 3, 0, do_yrdm,
"read file to memory from yaffs",
- "yrdm filename offset reads yaffs file into memory");
+ "filename offset reads yaffs file into memory");
U_BOOT_CMD(ywrm, 4, 0, do_ywrm,
"write file from memory to yaffs",
- "ywrm filename offset size writes memory to yaffs file");
+ "filename offset size writes memory to yaffs file");
U_BOOT_CMD(ymkdir, 2, 0, do_ymkdir,
- "YAFFS mkdir", "ymkdir dir create a yaffs directory");
+ "YAFFS mkdir", "dir create a yaffs directory");
U_BOOT_CMD(yrmdir, 2, 0, do_yrmdir,
- "YAFFS rmdir", "yrmdir dirname removes a yaffs directory");
+ "YAFFS rmdir", "dirname removes a yaffs directory");
-U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "yrm path removes a yaffs file");
+U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "path removes a yaffs file");
U_BOOT_CMD(ymv, 4, 0, do_ymv,
"YAFFS mv",
- "ymv old_path new_path moves/rename files within a yaffs mount point");
+ "old_path new_path moves/rename files within a yaffs mount point");
diff --git a/common/lcd_console.c b/common/lcd_console.c
index 74c388a..8bf83b9 100644
--- a/common/lcd_console.c
+++ b/common/lcd_console.c
@@ -209,3 +209,42 @@ void lcd_printf(const char *fmt, ...)
lcd_puts(buf);
}
+
+static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned int col, row;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ col = simple_strtoul(argv[1], NULL, 10);
+ row = simple_strtoul(argv[2], NULL, 10);
+ lcd_position_cursor(col, row);
+
+ return 0;
+}
+
+static int do_lcd_puts(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setcurs, 3, 1, do_lcd_setcursor,
+ "set cursor position within screen",
+ " <col> <row> in character"
+);
+
+U_BOOT_CMD(
+ lcdputs, 2, 1, do_lcd_puts,
+ "print string on lcd-framebuffer",
+ " <string>"
+);
+
diff --git a/common/spl/spl.c b/common/spl/spl.c
index ded0f30..cd75bbc 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -281,3 +281,38 @@ void preloader_console_init(void)
spl_display_print();
#endif
}
+
+/**
+ * spl_relocate_stack_gd() - Relocate stack ready for board_init_r() execution
+ *
+ * Sometimes board_init_f() runs with a stack in SRAM but we want to use SDRAM
+ * for the main board_init_r() execution. This is typically because we need
+ * more stack space for things like the MMC sub-system.
+ *
+ * This function calculates the stack position, copies the global_data into
+ * place and returns the new stack position. The caller is responsible for
+ * setting up the sp register.
+ *
+ * @return new stack location, or 0 to use the same stack
+ */
+ulong spl_relocate_stack_gd(void)
+{
+#ifdef CONFIG_SPL_STACK_R
+ gd_t *new_gd;
+ ulong ptr;
+
+ /* Get stack position: use 8-byte alignment for ABI compliance */
+ ptr = CONFIG_SPL_STACK_R - sizeof(gd_t);
+ ptr &= ~7;
+ new_gd = (gd_t *)ptr;
+ memcpy(new_gd, (void *)gd, sizeof(gd_t));
+ gd = new_gd;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ return ptr;
+#else
+ return 0;
+#endif
+}
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index b631c41..f5b807b 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 51bf370..db27c3e 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 2e5aeaa..b2f332e 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index be90163..ed72af6 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index a6188ea..097dd47 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 352c1fb..773042a 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index f3544b5..7634d03 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -1,4 +1,6 @@
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_IGEP0033=y
CONFIG_SYS_MALLOC_F=y
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
new file mode 100644
index 0000000..705c400
--- /dev/null
+++ b/configs/amcore_defconfig
@@ -0,0 +1,2 @@
+CONFIG_M68K=y
+CONFIG_TARGET_AMCORE=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
new file mode 100644
index 0000000..8546fd8
--- /dev/null
+++ b/configs/birdland_bav335a_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_BAV335X=y
++S:CONFIG_BAV_VERSION=1
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
new file mode 100644
index 0000000..c3f2ecc
--- /dev/null
+++ b/configs/birdland_bav335b_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_BAV335X=y
++S:CONFIG_BAV_VERSION=2
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
new file mode 100644
index 0000000..ae1dda2
--- /dev/null
+++ b/configs/cairo_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
++S:CONFIG_TARGET_OMAP3_CAIRO=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
new file mode 100644
index 0000000..624a8af
--- /dev/null
+++ b/configs/warp_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_ARM=y
+CONFIG_TARGET_WARP=y
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index b70f271..619c6b2 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -1,5 +1,6 @@
CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
+CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
Accessing ESDHC registers can be determined by ESDHC IP's endian
mode or processor's endian mode.
diff --git a/doc/README.gpt b/doc/README.gpt
index ec0156d..59fdeeb 100644
--- a/doc/README.gpt
+++ b/doc/README.gpt
@@ -157,11 +157,13 @@ To restore GUID partition table one needs to:
"partitions=uuid_disk=${uuid_gpt_disk};name=${uboot_name},
size=${uboot_size},uuid=${uboot_uuid};"
- Fields 'name', 'size' and 'uuid' are mandatory for every partition.
+ The fields 'name' and 'size' are mandatory for every partition.
The field 'start' is optional.
- option: CONFIG_RANDOM_UUID
- If any partition "UUID" no exists then it is randomly generated.
+ The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
+ enabled. A random uuid will be used if omitted or they point to an empty/
+ non-existent environment variable. The environment variable will be set to
+ the generated UUID.
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab
index 43e64a2..e9340dd 100644
--- a/doc/README.mxc_hab
+++ b/doc/README.mxc_hab
@@ -46,3 +46,51 @@ cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
NOTE: U-Boot_CSF.bin needs to be padded to the value specified in
the imximage.cfg file.
+
+Setup U-Boot Image for Encrypted Boot
+-------------------------------------
+An authenticated U-Boot image is used as starting point for
+Encrypted Boot. The image is encrypted by Freescale's Code
+Signing Tool (CST). The CST replaces only the image data of
+u-boot.imx with the encrypted data. The Initial Vector Table,
+DCD, and Boot data, remains in plaintext.
+
+The image data is encrypted with a Encryption Key (DEK).
+Therefore, this key is needed to decrypt the data during the
+booting process. The DEK is protected by wrapping it in a Blob,
+which needs to be appended to the U-Boot image and specified in
+the CSF file.
+
+The DEK blob is generated by an authenticated U-Boot image with
+the dek_blob cmd enabled. The image used for DEK blob generation
+needs to have the following configurations enabled:
+
+CONFIG_SECURE_BOOT
+CONFIG_SYS_FSL_SEC_COMPAT 4 /* HAB version */
+CONFIG_FSL_CAAM
+CONFIG_CMD_DEKBLOB
+
+Note: The encrypted boot feature is only supported by HABv4 or
+greater.
+
+The dek_blob command then can be used to generate the DEK blob of
+a DEK previously loaded in memory. The command is used as follows:
+
+dek_blob <DEK address> <Output Address> <Key Size in Bits>
+example: dek_blob 0x10800000 0x10801000 192
+
+The resulting DEK blob then is used to construct the encrypted
+U-Boot image. Note that the blob needs to be transferred back
+to the host.Then the following commands are used to construct
+the final image.
+
+objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \
+ U-Boot_CSF.bin U-Boot_CSF_pad.bin
+cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
+objcopy -I binary -O binary --pad-to <blob_dst> --gap-fill=0x00 \
+ u-boot-signed.imx u-boot-signed-pad.bin
+cat u-boot-signed-pad.imx DEK_blob.bin > u-boot-encrypted.imx
+
+ NOTE: u-boot-signed.bin needs to be padded to the value
+ equivalent to the address in which the DEK blob is specified
+ in the CSF.
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index c0cf642..4aa91e4 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -8,5 +8,5 @@
obj-y += sec.o
obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
-obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
+obj-$(CONFIG_CMD_BLOB)$(CONFIG_CMD_DEKBLOB) += fsl_blob.o
obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 504f2b0..18e2ec8 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -12,11 +12,18 @@
#ifndef DESC_H
#define DESC_H
+#define KEY_BLOB_SIZE 32
+#define MAC_SIZE 16
+
/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
#define MAX_CAAM_DESCSIZE 64
+/* Size of DEK Blob descriptor, inclusive of header */
+#define DEK_BLOB_DESCSIZE 9
+
/* Block size of any entity covered/uncovered with a KEK/TKEK */
#define KEK_BLOCKSIZE 16
+
/*
* Supported descriptor command types as they show up
* inside a descriptor command word.
@@ -273,6 +280,13 @@
#define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT)
/*
+ * AAD Definitions
+ */
+#define AES_KEY_SHIFT 8
+#define LD_CCM_MODE 0x66
+#define KEY_AES_SRC (0x55 << AES_KEY_SHIFT)
+
+/*
* FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE
* Command Constructs
*/
@@ -418,6 +432,7 @@
#define OP_PCLID_MASK (0xff << 16)
/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
+#define OP_PCLID_SECMEM 0x08
#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT)
#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT)
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index 9923bcb..8b25921 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -7,6 +7,8 @@
#include <common.h>
#include <malloc.h>
+#include <fsl_sec.h>
+#include <asm-generic/errno.h>
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
@@ -59,3 +61,53 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
free(desc);
return ret;
}
+
+#ifdef CONFIG_CMD_DEKBLOB
+int blob_dek(const u8 *src, u8 *dst, u8 len)
+{
+ int ret, size, i = 0;
+ u32 *desc;
+
+ int out_sz = WRP_HDR_SIZE + len + KEY_BLOB_SIZE + MAC_SIZE;
+
+ puts("\nEncapsulating provided DEK to form blob\n");
+ desc = memalign(ARCH_DMA_MINALIGN,
+ sizeof(uint32_t) * DEK_BLOB_DESCSIZE);
+ if (!desc) {
+ debug("Not enough memory for descriptor allocation\n");
+ return -ENOMEM;
+ }
+
+ ret = inline_cnstr_jobdesc_blob_dek(desc, src, dst, len);
+ if (ret) {
+ debug("Error in Job Descriptor Construction: %d\n", ret);
+ } else {
+ size = roundup(sizeof(uint32_t) * DEK_BLOB_DESCSIZE,
+ ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)desc,
+ (unsigned long)desc + size);
+ size = roundup(sizeof(uint8_t) * out_sz, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)dst,
+ (unsigned long)dst + size);
+
+ ret = run_descriptor_jr(desc);
+ }
+
+ if (ret) {
+ debug("Error in Encapsulation %d\n", ret);
+ goto err;
+ }
+
+ size = roundup(out_sz, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range((unsigned long)dst, (unsigned long)dst+size);
+
+ puts("DEK Blob\n");
+ for (i = 0; i < out_sz; i++)
+ printf("%02X", ((uint8_t *)dst)[i]);
+ printf("\n");
+
+err:
+ free(desc);
+ return ret;
+}
+#endif
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index cc0dced..5695bef 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -9,12 +9,157 @@
*/
#include <common.h>
+#include <fsl_sec.h>
#include "desc_constr.h"
#include "jobdesc.h"
#include "rsa_caam.h"
-#define KEY_BLOB_SIZE 32
-#define MAC_SIZE 16
+#ifdef CONFIG_MX6
+/*!
+ * Secure memory run command
+ *
+ * @param sec_mem_cmd Secure memory command register
+ * @return cmd_status Secure memory command status register
+ */
+uint32_t secmem_set_cmd(uint32_t sec_mem_cmd)
+{
+ uint32_t temp_reg;
+
+ sec_out32(CAAM_SMCJR0, sec_mem_cmd);
+
+ do {
+ temp_reg = sec_in32(CAAM_SMCSJR0);
+ } while (temp_reg & CMD_COMPLETE);
+
+ return temp_reg;
+}
+
+/*!
+ * CAAM page allocation:
+ * Allocates a partition from secure memory, with the id
+ * equal to partion_num. This will de-allocate the page
+ * if it is already allocated. The partition will have
+ * full access permissions. The permissions are set before,
+ * running a job descriptor. A memory page of secure RAM
+ * is allocated for the partition.
+ *
+ * @param page Number of the page to allocate.
+ * @param partition Number of the partition to allocate.
+ * @return 0 on success, ERROR_IN_PAGE_ALLOC otherwise
+ */
+int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
+{
+ uint32_t temp_reg;
+
+ /*
+ * De-Allocate partition_num if already allocated to ARM core
+ */
+ if (sec_in32(CAAM_SMPO_0) & PARTITION_OWNER(partition_num)) {
+ temp_reg = secmem_set_cmd(PARTITION(partition_num) |
+ CMD_PART_DEALLOC);
+ if (temp_reg & SMCSJR_AERR) {
+ printf("Error: De-allocation status 0x%X\n", temp_reg);
+ return ERROR_IN_PAGE_ALLOC;
+ }
+ }
+
+ /* set the access rights to allow full access */
+ sec_out32(CAAM_SMAG1JR0(partition_num), 0xF);
+ sec_out32(CAAM_SMAG2JR0(partition_num), 0xF);
+ sec_out32(CAAM_SMAPJR0(partition_num), 0xFF);
+
+ /* Now need to allocate partition_num of secure RAM. */
+ /* De-Allocate page_num by starting with a page inquiry command */
+ temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY);
+
+ /* if the page is owned, de-allocate it */
+ if ((temp_reg & SMCSJR_PO) == PAGE_OWNED) {
+ temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_PAGE_DEALLOC);
+ if (temp_reg & SMCSJR_AERR) {
+ printf("Error: Allocation status 0x%X\n", temp_reg);
+ return ERROR_IN_PAGE_ALLOC;
+ }
+ }
+
+ /* Allocate page_num to partition_num */
+ temp_reg = secmem_set_cmd(PAGE(page_num) | PARTITION(partition_num)
+ | CMD_PAGE_ALLOC);
+ if (temp_reg & SMCSJR_AERR) {
+ printf("Error: Allocation status 0x%X\n", temp_reg);
+ return ERROR_IN_PAGE_ALLOC;
+ }
+ /* page inquiry command to ensure that the page was allocated */
+ temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY);
+
+ /* if the page is not owned => problem */
+ if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) {
+ printf("Allocation of page %d in partition %d failed 0x%X\n",
+ temp_reg, page_num, partition_num);
+
+ return ERROR_IN_PAGE_ALLOC;
+ }
+
+ return 0;
+}
+
+int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
+ uint8_t *dek_blob, uint32_t in_sz)
+{
+ uint32_t ret = 0;
+ u32 aad_w1, aad_w2;
+ /* output blob will have 32 bytes key blob in beginning and
+ * 16 byte HMAC identifier at end of data blob */
+ uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+ /* Setting HDR for blob */
+ uint8_t wrapped_key_hdr[8] = {HDR_TAG, 0x00, WRP_HDR_SIZE + out_sz,
+ HDR_PAR, HAB_MOD, HAB_ALG, in_sz, HAB_FLG};
+
+ /* initialize the blob array */
+ memset(dek_blob, 0, out_sz + 8);
+ /* Copy the header into the DEK blob buffer */
+ memcpy(dek_blob, wrapped_key_hdr, sizeof(wrapped_key_hdr));
+
+ /* allocating secure memory */
+ ret = caam_page_alloc(PAGE_1, PARTITION_1);
+ if (ret)
+ return ret;
+
+ /* Write DEK to secure memory */
+ memcpy((uint32_t *)SEC_MEM_PAGE1, (uint32_t *)plain_txt, in_sz);
+
+ unsigned long start = (unsigned long)SEC_MEM_PAGE1 &
+ ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
+
+ /* Now configure the access rights of the partition */
+ sec_out32(CAAM_SMAG1JR0(PARTITION_1), KS_G1); /* set group 1 */
+ sec_out32(CAAM_SMAG2JR0(PARTITION_1), 0); /* clear group 2 */
+ sec_out32(CAAM_SMAPJR0(PARTITION_1), PERM); /* set perm & locks */
+
+ /* construct aad for AES */
+ aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE;
+ aad_w2 = 0x0;
+
+ init_job_desc(desc, 0);
+
+ append_cmd(desc, CMD_LOAD | CLASS_2 | KEY_IMM | KEY_ENC |
+ (0x0c << LDST_OFFSET_SHIFT) | 0x08);
+
+ append_u32(desc, aad_w1);
+
+ append_u32(desc, aad_w2);
+
+ append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
+
+ append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR);
+
+ append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
+ OP_PCLID_SECMEM);
+
+ return ret;
+}
+#endif
void inline_cnstr_jobdesc_hash(uint32_t *desc,
const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h
index 84b3edd..112404c 100644
--- a/drivers/crypto/fsl/jobdesc.h
+++ b/drivers/crypto/fsl/jobdesc.h
@@ -14,6 +14,20 @@
#define KEY_IDNFR_SZ_BYTES 16
+#ifdef CONFIG_CMD_DEKBLOB
+/* inline_cnstr_jobdesc_blob_dek:
+ * Intializes and constructs the job descriptor for DEK encapsulation
+ * using the given parameters.
+ * @desc: reference to the job descriptor
+ * @plain_txt: reference to the DEK
+ * @enc_blob: reference where to store the blob
+ * @in_sz: size in bytes of the DEK
+ * @return: 0 on success, ECONSTRJDESC otherwise
+ */
+int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
+ uint8_t *enc_blob, uint32_t in_sz);
+#endif
+
void inline_cnstr_jobdesc_hash(uint32_t *desc,
const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
u32 alg_type, uint32_t alg_size, int sg_tbl);
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index f9d4938..f99d594 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -90,11 +90,13 @@ static int jr_init(void)
jr.liodn = DEFAULT_JR_LIODN;
#endif
jr.size = JR_SIZE;
- jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t));
+ jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+ JR_SIZE * sizeof(dma_addr_t));
if (!jr.input_ring)
return -1;
jr.output_ring =
- (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring));
+ (struct op_ring *)memalign(ARCH_DMA_MINALIGN,
+ JR_SIZE * sizeof(struct op_ring));
if (!jr.output_ring)
return -1;
@@ -163,13 +165,23 @@ static int jr_enqueue(uint32_t *desc_addr,
CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
return -1;
- jr.input_ring[head] = desc_phys_addr;
jr.info[head].desc_phys_addr = desc_phys_addr;
jr.info[head].desc_addr = (uint32_t)desc_addr;
jr.info[head].callback = (void *)callback;
jr.info[head].arg = arg;
jr.info[head].op_done = 0;
+ unsigned long start = (unsigned long)&jr.info[head] &
+ ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + sizeof(struct jr_info),
+ ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
+
+ jr.input_ring[head] = desc_phys_addr;
+ start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
+
jr.head = (head + 1) & (jr.size - 1);
sec_out32(&regs->irja, 1);
@@ -187,6 +199,13 @@ static int jr_dequeue(void)
void *arg = NULL;
while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+ unsigned long start = (unsigned long)jr.output_ring &
+ ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start +
+ sizeof(struct op_ring)*JR_SIZE,
+ ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(start, end);
+
found = 0;
dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
@@ -333,13 +352,17 @@ static int instantiate_rng(void)
memset(&op, 0, sizeof(struct result));
- desc = malloc(sizeof(int) * 6);
+ desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
if (!desc) {
printf("cannot allocate RNG init descriptor memory\n");
return -1;
}
inline_cnstr_jobdesc_rng_instantiation(desc);
+ int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
+ flush_dcache_range((unsigned long)desc,
+ (unsigned long)desc + size);
+
ret = run_descriptor_jr(desc);
if (ret)
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15..fe9a3b2 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -8,6 +8,10 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
endif
+/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */
+ifdef CONFIG_TEGRA_GPIO
+obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+endif
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 43928b8..f870cdb 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -132,21 +132,6 @@ static void set_level(unsigned gpio, int high)
writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
}
-/* set GPIO pin 'gpio' as an output, with polarity 'value' */
-int tegra_spl_gpio_direction_output(int gpio, int value)
-{
- /* Configure as a GPIO */
- set_config(gpio, 1);
-
- /* Configure GPIO output value. */
- set_level(gpio, value);
-
- /* Configure GPIO direction as output. */
- set_direction(gpio, 1);
-
- return 0;
-}
-
/*
* Generic_GPIO primitives.
*/
@@ -338,12 +323,19 @@ static int gpio_tegra_bind(struct udevice *parent)
int bank_count;
int bank;
int ret;
- int len;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
+ /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
+#ifdef CONFIG_SPL_BUILD
+ ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+ bank_count = TEGRA_GPIO_BANKS;
+#else
+ {
+ int len;
+
/*
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
@@ -353,6 +345,8 @@ static int gpio_tegra_bind(struct udevice *parent)
bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
parent->of_offset, "reg");
+ }
+#endif
for (bank = 0; bank < bank_count; bank++) {
int port;
@@ -388,4 +382,5 @@ U_BOOT_DRIVER(gpio_tegra) = {
.probe = gpio_tegra_probe,
.priv_auto_alloc_size = sizeof(struct tegra_port_info),
.ops = &gpio_tegra_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f5d2ccb..c5e270d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -54,19 +54,21 @@ struct fsl_esdhc {
uint fevt; /* Force event register */
uint admaes; /* ADMA error status register */
uint adsaddr; /* ADMA system address register */
- char reserved2[160]; /* reserved */
+ char reserved2[100]; /* reserved */
+ uint vendorspec; /* Vendor Specific register */
+ char reserved3[59]; /* reserved */
uint hostver; /* Host controller version register */
- char reserved3[4]; /* reserved */
- uint dmaerraddr; /* DMA error address register */
char reserved4[4]; /* reserved */
- uint dmaerrattr; /* DMA error attribute register */
+ uint dmaerraddr; /* DMA error address register */
char reserved5[4]; /* reserved */
+ uint dmaerrattr; /* DMA error attribute register */
+ char reserved6[4]; /* reserved */
uint hostcapblt2; /* Host controller capabilities register 2 */
- char reserved6[8]; /* reserved */
+ char reserved7[8]; /* reserved */
uint tcr; /* Tuning control register */
- char reserved7[28]; /* reserved */
+ char reserved8[28]; /* reserved */
uint sddirctl; /* SD direction control register */
- char reserved8[712]; /* reserved */
+ char reserved9[712]; /* reserved */
uint scr; /* eSDHC control register */
};
@@ -342,6 +344,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
goto out;
}
+ /* Switch voltage to 1.8V if CMD11 succeeded */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
+ esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+ printf("Run CMD11 1.8V switch\n");
+ /* Sleep for 5 ms - max time for card to switch to 1.8V */
+ udelay(5000);
+ }
+
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
int timeout = 2500;
@@ -414,6 +425,10 @@ out:
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
;
}
+
+ /* If this was CMD11, then notify that power cycle is needed */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
+ printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
}
esdhc_write32(&regs->irqstat, -1);
@@ -509,6 +524,10 @@ static int esdhc_init(struct mmc *mmc)
/* Set timout to the maximum value */
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
+#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+ esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+#endif
+
return 0;
}
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 24123fc..610f969 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -30,13 +30,22 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
static uint8_t cs_next;
static __maybe_unused struct nand_ecclayout omap_ecclayout;
+#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
+ { CONFIG_NAND_OMAP_GPMC_WSCFG };
+#else
+/* wscfg is preset to zero since its a static variable */
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
/*
* Driver configurations
*/
struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
- int cs;
+ uint8_t cs;
+ uint8_t ws; /* wait status pin (0,1) */
};
/* We are wasting a bit of memory but al least we are safe */
@@ -76,7 +85,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
/* Check wait pin as dev ready indicator */
static int omap_dev_ready(struct mtd_info *mtd)
{
- return gpmc_cfg->status & (1 << 8);
+ register struct nand_chip *this = mtd->priv;
+ struct omap_nand_info *info = this->priv;
+ return gpmc_cfg->status & (1 << (8 + info->ws));
}
/*
@@ -901,8 +912,18 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
return -EINVAL;
}
} else {
- err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ if (eccstrength == 1) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_HAM1_CODE_SW,
mtd->writesize, mtd->oobsize);
+ } else if (eccstrength == 8) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+ mtd->writesize, mtd->oobsize);
+ } else {
+ printf("nand: error: unsupported ECC scheme\n");
+ return -EINVAL;
+ }
}
/* Update NAND handling after ECC mode switch */
@@ -962,6 +983,7 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;
omap_nand_info[cs].cs = cs;
+ omap_nand_info[cs].ws = wscfg[cs];
nand->priv = &omap_nand_info[cs];
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index c03e935..cc01604 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -253,11 +253,20 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
+#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
&dma_p->opmode);
+#else
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
+ &dma_p->opmode);
+#endif
writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
+#ifdef CONFIG_DW_AXI_BURST_LEN
+ writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
+#endif
+
/* Start up the PHY */
if (phy_startup(priv->phydev)) {
printf("Could not initialize PHY %s\n",
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ce51102..49d900c 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -68,7 +68,9 @@ struct eth_dma_regs {
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
- u8 reserved[40];
+ u32 reserved1[2];
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index ab98941..6f95649 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -127,6 +127,12 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
memset((void *)gd->fb_base, 0, 0x20);
*(unsigned int *)gd->fb_base = 0x4000;
+ /* turn ON display through powercontrol function if accessible */
+ if (0 != panel->panel_power_ctrl)
+ panel->panel_power_ctrl(1);
+
+ debug("am335x-fb: wait for stable power ...\n");
+ mdelay(panel->pup_delay);
lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
lcdhw->raster_ctrl = 0;
lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
@@ -159,11 +165,8 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
gd->fb_base += 0x20; /* point fb behind palette */
- /* turn ON display through powercontrol function if accessible */
- if (0 != panel->panel_power_ctrl) {
- mdelay(panel->pon_delay);
- panel->panel_power_ctrl(1);
- }
+ debug("am335x-fb: waiting picture to be stable.\n.");
+ mdelay(panel->pon_delay);
return 0;
}
diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h
index 8a0b131..7f799d1 100644
--- a/drivers/video/am335x-fb.h
+++ b/drivers/video/am335x-fb.h
@@ -55,9 +55,14 @@ struct am335x_lcdpanel {
unsigned int vsw; /* Vertical Sync Pulse Width */
unsigned int pxl_clk_div; /* Pixel clock divider*/
unsigned int pol; /* polarity of sync, clock signals */
+ unsigned int pup_delay; /*
+ * time in ms after power on to
+ * initialization of lcd-controller
+ * (VCC ramp up time)
+ */
unsigned int pon_delay; /*
- * time in ms for turning on lcd after
- * initializing lcd-controller
+ * time in ms after initialization of
+ * lcd-controller (pic stabilization)
*/
void (*panel_power_ctrl)(int); /* fp for power on/off display */
};
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index f7c52cc..fbc4c4b 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -1000,10 +1000,13 @@ int ext4_write_file(const char *filename, void *buf, loff_t offset,
}
ext4fs_close();
+ *actwrite = len;
+
return 0;
fail:
ext4fs_close();
+ *actwrite = 0;
return -1;
}
diff --git a/include/_exports.h b/include/_exports.h
index 5944703..279017e 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -23,7 +23,9 @@
EXPORT_FUNC(dummy, void, free_hdlr, void)
#endif
EXPORT_FUNC(malloc, void *, malloc, size_t)
+#ifndef CONFIG_SYS_MALLOC_SIMPLE
EXPORT_FUNC(free, void, free, void *)
+#endif
EXPORT_FUNC(udelay, void, udelay, unsigned long)
EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long)
EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list)
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index a63a87a..c918049 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -45,7 +45,7 @@ typedef struct bd_info {
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
@@ -66,10 +66,15 @@ typedef struct bd_info {
#if defined(CONFIG_MPC512X)
unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 0f4b726..734a77f 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -22,6 +22,8 @@
#define CONFIG_M54451 /* define processor type */
#define CONFIG_M54451EVB /* M54451EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7a55d3c..2faf581 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -22,6 +22,8 @@
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index e88a6bd..2f4549f 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -22,11 +22,13 @@
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index e412806..9aa02f7 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -22,11 +22,13 @@
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 09ee10c..290a6a3 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -297,7 +297,6 @@
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 190ef0e..3de5079 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -306,7 +306,6 @@
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
new file mode 100644
index 0000000..2a785b3
--- /dev/null
+++ b/include/configs/amcore.h
@@ -0,0 +1,140 @@
+/*
+ * Sysam AMCORE board configuration
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AMCORE_CONFIG_H
+#define __AMCORE_CONFIG_H
+
+#define CONFIG_AMCORE
+#define CONFIG_HOSTNAME AMCORE
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_MCF530x
+#define CONFIG_M5307
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND "bootm ffc20000"
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AES
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_DIAG
+
+#define CONFIG_SYS_PROMPT "amcore $ "
+/* undef to save memory */
+#undef CONFIG_SYS_LONGHELP
+
+#if defined(CONFIG_CMD_KGDB)
+/* Console I/O buff. size */
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0x0
+#define CONFIG_SYS_MEMTEST_END 0x1000000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_CLK 45000000
+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+/* Register Base Addrs */
+#define CONFIG_SYS_MBAR 0x10000000
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+/* size of internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+
+/* memory map space for linux boot data */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+ CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+ CF_CACR_EC)
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1 C/I BIT for errata */
+#define CONFIG_SYS_CS0_MASK 0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define CONFIG_SYS_CS0_CTRL 0x1980
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE 0x3000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x0100
+
+#endif /* __AMCORE_CONFIG_H */
+
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
new file mode 100644
index 0000000..490c53e
--- /dev/null
+++ b/include/configs/bav335x.h
@@ -0,0 +1,633 @@
+/*
+ * bav335x.h
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BAV335X_H
+#define __CONFIG_BAV335X_H
+
+#include <configs/ti_am335x_common.h>
+#define CONFIG_ENV_IS_NOWHERE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_FIT
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+# ifdef CONFIG_ENABLE_VBOOT
+# define CONFIG_FIT_SIGNATURE
+# define CONFIG_RSA
+# endif
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* Custom script for NOR */
+#define CONFIG_SYS_LDSCRIPT "board/birdland/bav335x/u-boot.lds"
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdtaddr} u-boot-spl-os; " \
+ "nand read ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+DEFAULT_LINUX_BOOT_ENV \
+"boot_fdt=try\0" \
+"bootpart=0:2\0" \
+"bootdir=\0" \
+"fdtdir=/dtbs\0" \
+"bootfile=zImage\0" \
+"fdtfile=undefined\0" \
+"console=ttyO0,115200n8\0" \
+"loadaddr=0x82000000\0" \
+"fdtaddr=0x88000000\0" \
+"rdaddr=0x88080000\0" \
+"initrd_high=0xffffffff\0" \
+"fdt_high=0xffffffff\0" \
+"partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+"optargs=\0" \
+"cmdline=\0" \
+"mmcdev=0\0" \
+"mmcpart=1\0" \
+"mmcroot=/dev/mmcblk0p2 ro\0" \
+"mmcrootfstype=ext4 rootwait fixrtc\0" \
+"rootpath=/export/rootfs\0" \
+"nfsopts=nolock\0" \
+"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+"ramroot=/dev/ram0 rw\0" \
+"ramrootfstype=ext2\0" \
+"mmcargs=setenv bootargs console=${console} ${optargs} " \
+ "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
+"server_ip=192.168.1.100\0" \
+"gw_ip=192.168.1.1\0" \
+"netmask=255.255.255.0\0" \
+"hostname=\0" \
+"device=eth0\0" \
+"autoconf=off\0" \
+"root_dir=/home/userid/targetNFS\0" \
+"nfs_options=,vers=3\0" \
+"nfsrootfstype=ext4 rootwait fixrtc\0" \
+"nfsargs=setenv bootargs console=${console} ${optargs} " \
+ "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
+ "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
+"bootenv=uEnv.txt\0" \
+"script=boot.scr\0" \
+"scriptfile=${script}\0" \
+"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
+"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
+ "source ${loadaddr}\0" \
+ "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
+"importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t -r $loadaddr $filesize\0" \
+"ramargs=setenv bootargs console=${console} " \
+ "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
+"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadrd=load mmc ${bootpart} ${rdaddr} " \
+ "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
+"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
+ "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
+"mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "gpio set 54;" \
+ "setenv bootpart ${mmcdev}:1; " \
+ "if test -e mmc ${bootpart} /etc/fstab; then " \
+ "setenv mmcpart 1;" \
+ "fi; " \
+ "echo Checking for: /uEnv.txt ...;" \
+ "if test -e mmc ${bootpart} /uEnv.txt; then " \
+ "if run loadbootenv; then " \
+ "gpio set 55;" \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "echo Checking if uenvcmd is set ...;" \
+ "if test -n ${uenvcmd}; then " \
+ "gpio set 56; " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "echo Checking if client_ip is set ...;" \
+ "if test -n ${client_ip}; then " \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo using ${fdtfile} ...;" \
+ "fi;" \
+ "gpio set 56; " \
+ "if test -n ${uname_r}; then " \
+ "echo Running nfsboot_uname_r ...;" \
+ "run nfsboot_uname_r;" \
+ "fi;" \
+ "echo Running nfsboot ...;" \
+ "run nfsboot;" \
+ "fi;" \
+ "fi; " \
+ "echo Checking for: /${script} ...;" \
+ "if test -e mmc ${bootpart} /${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile ${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/${script} ...;" \
+ "if test -e mmc ${bootpart} /boot/${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile /boot/${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/uEnv.txt ...;" \
+ "for i in 1 2 3 4 5 6 7 ; do " \
+ "setenv mmcpart ${i};" \
+ "setenv bootpart ${mmcdev}:${mmcpart};" \
+ "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
+ "gpio set 55;" \
+ "load mmc ${bootpart} ${loadaddr} " \
+ "/boot/uEnv.txt;" \
+ "env import -t ${loadaddr} ${filesize};" \
+ "echo Loaded environment from /boot/uEnv.txt;" \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo Using: dtb=${fdtfile} ...;" \
+ "fi;" \
+ "echo Checking if uname_r is set in " \
+ "/boot/uEnv.txt...;" \
+ "if test -n ${uname_r}; then " \
+ "gpio set 56; " \
+ "echo Running uname_boot ...;" \
+ "setenv mmcroot /dev/mmcblk${mmcdev}" \
+ "p${mmcpart} ro;" \
+ "run uname_boot;" \
+ "fi;" \
+ "fi;" \
+ "done;" \
+ "fi;\0" \
+"netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} dtbs/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} vmlinuz-${uname_r}; " \
+ "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+"findfdt="\
+ "if test $board_rev = B; then " \
+ "setenv fdtfile birdland_bav335b.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $board_rev = A; then " \
+ "setenv fdtfile birdland_bav335a.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
+"uname_boot="\
+ "setenv bootdir /boot; " \
+ "setenv bootfile vmlinuz-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+ "echo loading ${bootdir}/${bootfile} ...; "\
+ "run loadimage;" \
+ "setenv fdtdir /boot/dtbs/${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/" \
+ "${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtb-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtbs; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "echo; echo unable to find " \
+ "[${fdtfile}] " \
+ "did you name it correctly?" \
+ "echo booting fallback " \
+ "[/boot/dtbs/" \
+ "${uname_r}" \
+ "/${fdtbase}.dtb]...;" \
+ "setenv fdtdir /boot/dtbs/" \
+ "${uname_r}; " \
+ "setenv fdtfile " \
+ "${fdtbase}.dtb; " \
+ "run loadfdt;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi; " \
+ "setenv rdfile initrd.img-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
+ "echo loading ${bootdir}/${rdfile} ...; "\
+ "run loadrd;" \
+ "if test -n ${uuid}; then " \
+ "setenv mmcroot UUID=${uuid} ro;" \
+ "fi;" \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
+ "${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
+ "else " \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi;" \
+"fi;\0" \
+ NANDARGS \
+ DFUARGS
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "gpio set 53; " \
+ "i2c mw 0x24 1 0x3e; " \
+ "run findfdt; " \
+ "setenv mmcdev 0; " \
+ "setenv bootpart 0:1; " \
+ "run mmcboot;" \
+ "gpio clear 56; " \
+ "gpio clear 55; " \
+ "gpio clear 54; " \
+ "setenv mmcdev 1; " \
+ "setenv bootpart 1:1; " \
+ "run mmcboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#endif
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=nand.0:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+#endif /* !CONFIG_NAND */
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+#endif
+
+/*
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#endif /* CONFIG_MUSB_GADGET */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "BAV335x U-Boot SPL"
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+ "dfu_alt_info_nand=" \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0xD80000;" \
+ "fdt ram 0x80F80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+ "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
+#define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
+ "512k(u-boot),128k(u-boot-env1)," \
+ "128k(u-boot-env2),3464k(kernel)," \
+ "-(rootfs)"
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x0
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI flash. */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "512k(u-boot)," \
+ "128k(u-boot-env1)," \
+ "128k(u-boot-env2)," \
+ "4m(kernel),-(rootfs)"
+#endif
+#endif /* NOR support */
+
+#endif /* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index e9d5d01..a558e42 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -12,6 +12,31 @@
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
+#define BUR_COMMON_ENV \
+"defaultip=192.168.60.253\0" \
+"defaultsip=192.168.60.254\0" \
+"netconsole=echo switching to network console ...; " \
+"if dhcp; then " \
+"setenv ncip ${serverip}; else " \
+"setenv ncip 192.168.60.254; " \
+"setenv serverip 192.168.60.254; " \
+"setenv gatewayip 192.168.60.254; " \
+"setenv ipaddr 192.168.60.1; " \
+"fi;" \
+"setenv netdisplay0 '" \
+"setcurs 1 9; puts myip; setcurs 10 9; puts ${ipaddr};" \
+"setcurs 1 10;puts serverip; setcurs 10 10; puts ${serverip}\;'" \
+"run netdisplay0; " \
+"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+
+#define CONFIG_CMD_TIME
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4)
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_24BMP
+#define CONFIG_BMP_32BPP
+
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_AM33XX
@@ -47,7 +72,7 @@
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT 4
+#define CONFIG_NET_RETRY_COUNT 2
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
@@ -57,7 +82,9 @@
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-
+/* Network console */
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
@@ -110,7 +137,7 @@
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_MALLOC_LEN (5120 << 10)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
@@ -175,7 +202,6 @@
*
* ----------------------------------------------------------------------------
*/
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index b2a9f35..9feca1b 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -365,7 +365,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 1c69551..84b047e 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -213,8 +213,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
-#undef CONFIG_SPL_STACK
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index edff0f5..854ae90 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -22,6 +22,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 310d5e2..664a2b2 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -18,6 +18,7 @@
/*
* Board
*/
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_BARIX_IPAM390
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 29b263f..dd30df2 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -14,6 +14,11 @@
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -38,57 +43,71 @@
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SPL_MMC_SUPPORT
-#undef CONFIG_SPL_OS_BOOT
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-
-#endif /* CONFIG_SPL_OS_BOOT */
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80100000\0" \
- "bootfile=arimg\0" \
- "usbboot=echo Booting from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 ${loadaddr} ${bootfile}; " \
- "usb stop; " \
- "go ${loadaddr};\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload 0; " \
- "dhcp; " \
- "tftp ${loadaddr} arimg; " \
- "go ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0"
+BUR_COMMON_ENV \
+"vx_romfsbase=0x800E0000\0" \
+"vx_romfssize=0x20000\0" \
+"vx_memtop=0x8FBEF000\0" \
+"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
+"autoload=0\0" \
+"loadaddr=0x80100000\0" \
+"logoaddr=0x82000000\0" \
+"defaultARlen=0x8000\0" \
+"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
+"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \
+"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"mmcboot=echo booting AR from eMMC-flash ...; "\
+ "run logo0 || run logo1; " \
+ "run loadromfs; " \
+ "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \
+ "run defaultAR;\0" \
+"netboot=echo booting AR from network ...; " \
+ "run loadromfs; " \
+ "tftp ${loadaddr} arimg && go ${loadaddr}; " \
+ "puts 'networkboot failed!';\0" \
+"usbupdate=echo updating u-boot from usb ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img && source; " \
+ "puts 'usbupdate failed!'\0" \
+"netscript=echo running script from network (tftp) ...; " \
+ "tftp 0x80000000 netscript.img && source; " \
+ "puts 'netscript load failed!'\0" \
+"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \
+"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \
+ "if tftp 0x80100000 arimg.bin; " \
+ "then mmc write 0x80100000 800 ${defaultARlen}; " \
+ "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \
+"netupdateROMFS=echo updating romfs from network (tftp) ...; " \
+ "if tftp 0x80100000 romfs.bin; " \
+ "then mmc write 0x80100000 700 100; " \
+ "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0"
+
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
"run usbupdate;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+#define CONFIG_BOOTDELAY 0
/* undefine command which we not need here */
-#undef CONFIG_BOOTM_LINUX
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
/* USB configuration */
#define CONFIG_USB_MUSB_DSPS
@@ -100,6 +119,8 @@
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 603d17c..857dd07 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -19,6 +19,7 @@
#define CONFIG_MX35
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA0000000
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 42bc3c8..8d8b93c 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -24,6 +24,8 @@
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 4aa8101..f0e37f0 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -53,6 +53,8 @@
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
@@ -276,4 +278,18 @@
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "FSL"
+
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index c567d9d..1221418 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -48,6 +48,18 @@
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 8b47537..5ee0abe 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -29,6 +29,9 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+/* Reserve the last 1 MiB for the secure firmware */
+#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL)
+#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
@@ -56,8 +59,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MEM_TOP_HIDE (SZ_1M) /* ram console */
-
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 9fa8660..c395020 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -25,13 +25,11 @@
#define CONFIG_CMD_MMC
-/*
- * FIXME: The number of bank is actually 8. But there is no way to reserve the
- * last 16 Mib in the last bank now. So I just excluded the last bank
- * temporally.
- */
-#define CONFIG_NR_DRAM_BANKS 7
+#define CONFIG_NR_DRAM_BANKS 8
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+/* Reserve the last 22 MiB for the secure firmware */
+#define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL)
+#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE
#define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
new file mode 100644
index 0000000..3030054
--- /dev/null
+++ b/include/configs/omap3_cairo.h
@@ -0,0 +1,286 @@
+/*
+ * Configuration settings for the QUIPOS Cairo board.
+ *
+ * Copyright (C) DENX GmbH
+ *
+ * Author :
+ * Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from EVM code by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Also derived from include/configs/omap3_beagle.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OMAP3_CAIRO_CONFIG_H
+#define __OMAP3_CAIRO_CONFIG_H
+
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs. We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+#define CONFIG_NAND
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_ENV_OVERWRITE
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* Probe all devices */
+#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
+
+#define CONFIG_NAND
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+
+/* Disable some commands */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_LED 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+/* override default CONFIG_BOOTDELAY */
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "machid=ffffffff\0" \
+ "fdt_high=0x87000000\0" \
+ "baudrate=115200\0" \
+ "ethaddr=00:50:C2:7E:90:F0\0" \
+ "fec_addr=00:50:C2:7E:90:F0\0" \
+ "netmask=255.255.255.0\0" \
+ "ipaddr=192.168.2.9\0" \
+ "gateway=192.168.2.1\0" \
+ "serverip=192.168.2.10\0" \
+ "nfshost=192.168.2.10\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "bootargs_mmc_ramdisk=mem=128M " \
+ "console=ttyO1,115200n8 " \
+ "root=/dev/ram0 rw " \
+ "initrd=0x81600000,16M " \
+ "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
+ "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "mmcboot=mmc init; " \
+ "fatload mmc 0 0x80000000 uImage; " \
+ "fatload mmc 0 0x81600000 ramdisk.gz; " \
+ "setenv bootargs ${bootargs_mmc_ramdisk}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
+ "root=/dev/nfs " \
+ "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
+ "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
+ "omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
+ "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
+ "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
+ "omapfb.rotate_type=1\0" \
+ "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
+ "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
+ "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
+ "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
+ "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
+ "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
+ "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
+ "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
+ "nand erase 0 20000; " \
+ "fatload mmc 0 0x81600000 MLO; " \
+ "nandecc hw; " \
+ "nand write.i 0x81600000 0 20000;\0" \
+ "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
+ "nand erase 80000 40000; " \
+ "fatload mmc 0 0x81600000 u-boot.bin; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 80000 40000;\0" \
+ "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
+ "nand erase 280000 300000; " \
+ "fatload mmc 0 0x81600000 uImage; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 280000 300000;\0" \
+ "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
+ "nandecc sw; " \
+ "nand write.jffs2 0x680000 0xFF ${filesize}; " \
+ "nand erase 680000 ${filesize}; " \
+ "nand write.jffs2 81600000 680000 ${filesize};\0" \
+ "flash_scrub=nand scrub; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs;\0" \
+ "flash_all=run ledred; " \
+ "nand erase.chip; " \
+ "run ledorange; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs; " \
+ "run ledgreen; " \
+ "run boot_nand; \0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
+ "else run boot_nand; fi"
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#define CONFIG_OMAP3_SPI
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* Defines for SPL */
+#define CONFIG_SPL_OMAP3_ID_NAND
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+
+/* env defaults */
+#define CONFIG_BOOTFILE "uImage"
+
+/* Override OMAP3 common serial console configuration from UART3
+ * to UART2.
+ *
+ * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
+ * are needed and peripheral clocks for UART2 must be enabled in
+ * function per_clocks_enable().
+ */
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX 2
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NS16550_COM3
+#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
+#undef CONFIG_SERIAL3
+#define CONFIG_SERIAL2
+#endif
+
+/* Keep old prompt in case some existing script depends on it */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "Cairo # "
+
+/* Provide MACH_TYPE for compatibility with non-DT kernels */
+#define MACH_TYPE_OMAP3_CAIRO 3063
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
+ /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#endif /* __OMAP3_CAIRO_CONFIG_H */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 8885e17..e7df154 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -259,7 +259,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index c061e93..3c60b4f 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -131,6 +131,16 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+#ifndef CONFIG_SPL
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_BUS 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#endif
+
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 21e13e5..c7affd6 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -142,7 +142,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index a11f4ed..16281f5 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -11,6 +11,8 @@
* Common configurations used for both spear3xx as well as spear6xx
*/
+#define CONFIG_SYS_GENERIC_BOARD
+
/* U-boot Load Address */
#define CONFIG_SYS_TEXT_BASE 0x00700000
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 9fbe68a..38288f6 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -237,7 +237,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 7d2c0d2..dd69d4e 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -346,7 +346,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index c097b98..7089378 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -165,6 +165,19 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+#ifdef CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "TBS"
+#endif /* CONFIG_CMD_USB_MASS_STORAGE */
#define CONFIG_USB_KEYBOARD
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 005fc6a..fa6ccc1 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -43,13 +43,7 @@
/*
* NS16550 Configuration
*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#else
#define CONFIG_TEGRA_SERIAL
-#endif
#define CONFIG_SYS_NS16550
/*
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index deb6bb2..dcc2bdc 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -171,7 +171,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index f69a559..27a3dd1 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -136,7 +136,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40400000
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 2bd1164..c0c1060 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -213,10 +213,9 @@
* SPLs). We have our BSS be placed 2MiB after this, to allow for the
* default Linux kernel address of 0x80008000 to work with most sized
* kernels, in the Falcon Mode case. We have the SPL malloc pool at the
- * end of the BSS area. We place our stack at 32MiB after the start of
- * DRAM to allow room for all of the above.
+ * end of the BSS area. We suggest that the stack be placed at 32MiB after
+ * the start of DRAM to allow room for all of the above (handled in Kconfig).
*/
-#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20))
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#endif
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 36621a5..10ac4a4 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -354,7 +354,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 9a62070..a6c7d5f 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -14,6 +14,19 @@
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -22,6 +35,8 @@
/* Support both device trees and ATAGs. */
#define CONFIG_OF_LIBFDT
+#define CONFIG_USE_FDT /* use fdt within board code */
+#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -79,8 +94,8 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif /* CONFIG_NAND */
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifdef CONFIG_NAND
#define NANDARGS \
@@ -103,47 +118,83 @@
#ifdef CONFIG_MMC
#define MMCARGS \
- "silent=1\0"
+"dtbdev=mmc\0" \
+"dtbpart=0:1\0" \
+"logo0=ext4load mmc 0:3 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"logo1=ext4load mmc 0:1 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"mmcroot0=setenv bootargs ${optargs} console=${console}\0" \
+"mmcroot1=setenv bootargs ${optargs} console=${console} root=/dev/mmcblk0p2 " \
+ "rootfstype=ext4\0" \
+"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
+ "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
+ "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
+"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
+ "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
+"defboot=run logo0 || run logo1; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
+ "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
+ "run ramboot; run usbupdate;\0" \
+"bootlimit=1\0" \
+"altbootcmd=run logo0 || run logo1; " \
+ "run mmcboot0;\0" \
+"upduboot=dhcp; " \
+ "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
#else
#define MMCARGS ""
#endif /* CONFIG_MMC */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80200000\0" \
- "bootfile=zImage\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "rootpath=/tftpboot/tseries/rootfs-small\0" \
- "nfsopts=nolock\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "run netargs; " \
- "bootm ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0" \
- NANDARGS \
- MMCARGS
+BUR_COMMON_ENV \
+"verify=no\0" \
+"autoload=0\0" \
+"dtb=bur-ppt-ts30.dtb\0" \
+"dtbaddr=0x80100000\0" \
+"loadaddr=0x80200000\0" \
+"ramaddr=0x80A00000\0" \
+"kernel=zImage\0" \
+"ramdisk=rootfs.cpio.uboot\0" \
+"console=ttyO0,115200n8\0" \
+"optargs=consoleblank=0 quiet lpj=1191936 panic=2\0" \
+"nfsroot=/tftpboot/tseries/rootfs-small\0" \
+"nfsopts=nolock\0" \
+"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
+ "ip=dhcp\0" \
+"netboot=echo Booting from network ...; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${dtbaddr} ${dtb}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${dtbaddr}\0" \
+"ramboot=echo Booting from network into RAM ...; "\
+ "if dhcp; then; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${ramaddr} ${ramdisk}; " \
+ "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
+ "then; else tftp ${dtbaddr} ${dtb}; fi;" \
+ "run mmcroot0; " \
+ "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
+"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start && fatload usb 0 0x80000000 updateubootusb.img && source\0" \
+"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
+NANDARGS \
+MMCARGS
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
- "run mmcboot1;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+ "run defboot;"
+#define CONFIG_BOOTDELAY 0
#ifdef CONFIG_NAND
/*
@@ -260,6 +311,10 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FS_GENERIC
#endif /* CONFIG_MMC, ... */
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 7fb28a5..e6cd881 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -29,8 +29,6 @@
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
-#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_SUPPORT_RAW_INITRD
/* Cache Definitions */
@@ -56,7 +54,6 @@
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
/* SMP Spin Table Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
@@ -79,13 +76,6 @@
#define V2M_BASE 0x80000000
-/*
- * Physical addresses, offset from V2M_PA_CS0-3
- */
-#define V2M_NOR0 (V2M_PA_CS0)
-#define V2M_NOR1 (V2M_PA_CS4)
-#define V2M_SRAM (V2M_PA_CS1)
-
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
@@ -146,9 +136,17 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-/* SMSC91C111 Ethernet Configuration */
+/* Ethernet Configuration */
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+/* The real hardware Versatile express uses SMSC9118 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE (0x018000000)
+#else
+/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE (0x01A000000)
+#endif
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
@@ -175,7 +173,6 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
@@ -237,7 +234,7 @@
"fdt_addr_r=0x83000000\0" \
"fdt_high=0xa0000000\0"
-#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0"
#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
"$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY -1
@@ -258,4 +255,27 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
+/* Flash memory is available on the Juno board only */
+#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif
+
#endif /* __VEXPRESS_AEMV8A_H */
diff --git a/include/configs/warp.h b/include/configs/warp.h
new file mode 100644
index 0000000..bcdd112
--- /dev/null
+++ b/include/configs/warp.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ * Copyright (C) 2014 Kynetics LLC.
+ * Copyright (C) 2014 Revolution Robotics, Inc.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * Configuration settings for the WaRP Board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Command definition */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x82000000
+#define CONFIG_SYS_TEXT_BASE 0x87800000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OFFSET (6 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* VDD voltage 1.65 - 1.95 */
+#define CONFIG_SYS_SD_VOLTAGE 0x00000080
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */
+#endif
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "FSL"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sl-warp.dtb\0" \
+ "fdt_addr=0x88000000\0" \
+ "initrd_addr=0x83800000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 8e1c7a4..48b8692 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -21,6 +21,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 04187c0..241bf65 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -16,6 +16,7 @@
*/
#define CONFIG_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
+#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/hardware.h>
diff --git a/include/exports.h b/include/exports.h
index 205affe..1a01e43 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -15,7 +15,9 @@ int printf(const char* fmt, ...);
void install_hdlr(int, interrupt_handler_t, void*);
void free_hdlr(int);
void *malloc(size_t);
+#ifndef CONFIG_SYS_MALLOC_SIMPLE
void free(void*);
+#endif
void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
int vprintf(const char *, va_list);
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 313fa1e..57295b4 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -155,6 +155,8 @@
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 sdhc_clk;
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index b6e6f04..ebb1ac6 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -135,7 +135,7 @@ typedef struct ccsr_sec {
#define CONFIG_JRSTARTR_JR0 0x00000001
struct jr_regs {
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
u32 irba_l;
u32 irba_h;
#else
@@ -148,7 +148,7 @@ struct jr_regs {
u32 irsa;
u32 rsvd3;
u32 irja;
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
u32 orba_l;
u32 orba_h;
#else
@@ -180,7 +180,7 @@ struct jr_regs {
* related information
*/
struct sg_entry {
-#ifdef CONFIG_SYS_FSL_SEC_LE
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
uint32_t addr_lo; /* Memory Address - lo */
uint16_t addr_hi; /* Memory Address of start of buffer - hi */
uint16_t reserved_zero;
@@ -201,7 +201,79 @@ struct sg_entry {
#define SG_ENTRY_OFFSET_SHIFT 0
};
+#ifdef CONFIG_MX6
+/* CAAM Job Ring 0 Registers */
+/* Secure Memory Partition Owner register */
+#define SMCSJR_PO (3 << 6)
+/* JR Allocation Error */
+#define SMCSJR_AERR (3 << 12)
+/* Secure memory partition 0 page 0 owner register */
+#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
+/* Secure memory command register */
+#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
+/* Secure memory command status register */
+#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
+/* Secure memory access permissions register */
+#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
+/* Secure memory access group 2 register */
+#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
+/* Secure memory access group 1 register */
+#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
+
+/* Commands and macros for secure memory */
+#define CMD_PAGE_ALLOC 0x1
+#define CMD_PAGE_DEALLOC 0x2
+#define CMD_PART_DEALLOC 0x3
+#define CMD_INQUIRY 0x5
+#define CMD_COMPLETE (3 << 14)
+#define PAGE_AVAILABLE 0
+#define PAGE_OWNED (3 << 6)
+#define PAGE(x) (x << 16)
+#define PARTITION(x) (x << 8)
+#define PARTITION_OWNER(x) (0x3 << (x*2))
+
+/* Address of secure 4kbyte pages */
+#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
+#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
+#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
+#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
+
+#define JR_MID 2 /* Matches ROM configuration */
+#define KS_G1 (1 << JR_MID) /* CAAM only */
+#define PERM 0x0000B008 /* Clear on release, lock SMAP
+ * lock SMAG group 1 Blob */
+
+#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
+
+/* HAB WRAPPED KEY header */
+#define WRP_HDR_SIZE 0x08
+#define HDR_TAG 0x81
+#define HDR_PAR 0x41
+/* HAB WRAPPED KEY Data */
+#define HAB_MOD 0x66
+#define HAB_ALG 0x55
+#define HAB_FLG 0x00
+
+/* Partition and Page IDs */
+#define PARTITION_1 1
+#define PAGE_1 1
+
+#define ERROR_IN_PAGE_ALLOC 1
+#define ECONSTRJDESC -1
+
+#endif
+
int sec_init(void);
+
+/* blob_dek:
+ * Encapsulates the src in a secure blob and stores it dst
+ * @src: reference to the plaintext
+ * @dst: reference to the output adrress
+ * @len: size in bytes of src
+ * @return: 0 on success, error otherwise
+ */
+int blob_dek(const u8 *src, u8 *dst, u8 len);
+
#endif
#endif /* __FSL_SEC_H */
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 5797498..efb04ee 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -11,6 +11,11 @@
#include <asm/linkage.h>
+/* Some toolchains use other characters (e.g. '`') to mark new line in macro */
+#ifndef ASM_NL
+#define ASM_NL ;
+#endif
+
#ifdef __cplusplus
#define CPP_ASMLINKAGE extern "C"
#else
@@ -43,15 +48,15 @@
#define ALIGN_STR __ALIGN_STR
#define LENTRY(name) \
- ALIGN; \
+ ALIGN ASM_NL \
SYMBOL_NAME_LABEL(name)
#define ENTRY(name) \
- .globl SYMBOL_NAME(name); \
+ .globl SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define WEAK(name) \
- .weak SYMBOL_NAME(name); \
+ .weak SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#ifndef END
@@ -61,7 +66,7 @@
#ifndef ENDPROC
#define ENDPROC(name) \
- .type name STT_FUNC; \
+ .type name STT_FUNC ASM_NL \
END(name)
#endif
diff --git a/include/mc34704.h b/include/mc34704.h
index 53716e0..482d51a 100644
--- a/include/mc34704.h
+++ b/include/mc34704.h
@@ -40,6 +40,7 @@ enum {
/* GENERAL2 register fields */
#define ONOFFE (1 << 0)
#define ONOFFD (1 << 1)
+#define ONOFFA (1 << 3)
#define ALLOFF (1 << 4)
#endif /* __MC34704_H__ */
diff --git a/include/mmc.h b/include/mmc.h
index 7d6feca..2ad0f19 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -106,6 +106,7 @@
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
#define SD_CMD_SEND_IF_COND 8
+#define SD_CMD_SWITCH_UHS18V 11
#define SD_CMD_APP_SET_BUS_WIDTH 6
#define SD_CMD_ERASE_WR_BLK_START 32
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index d304658..07199b4 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -232,5 +232,7 @@ enum {
#define APS_PFM 0xc
#define PWM_PFM 0xd
+#define SWITCH_SIZE 0x7
+
int power_pfuze100_init(unsigned char bus);
#endif
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 297c4cb..93cbe36 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -73,6 +73,7 @@ enum {
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
+#define TPS65217_PWR_OFF 0x80
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 24da23f..95d6246 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -23,7 +23,7 @@
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
- char name[16]; /* Device name */
+ char name[32]; /* Device name */
/* GENERAL functions */
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 129bc3e..221ebbf 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -32,15 +32,11 @@ int main(void)
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
-#if defined(CONFIG_ARM)
-
DEFINE(GD_RELOCADDR, offsetof(struct global_data, relocaddr));
DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off));
DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp));
-#endif
-
return 0;
}
diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index 1a41723..b304068 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -221,11 +221,7 @@ static void use_config(const char *m, int slen)
define_config(m, slen, hash);
- /* printf(" $(wildcard include/config/"); */
- /* modified for U-Boot */
- printf(" $(wildcard %sinclude/config/",
- strncmp(depfile, "spl/", 4) ?
- (strncmp(depfile, "tpl/", 4) ? "" : "tpl/") : "spl/");
+ printf(" $(wildcard include/config/");
for (i = 0; i < slen; i++) {
c = m[i];
if (c == '_')
diff --git a/scripts/checkstack.pl b/scripts/checkstack.pl
index c1cdc0a..dd83978 100755
--- a/scripts/checkstack.pl
+++ b/scripts/checkstack.pl
@@ -13,7 +13,7 @@
# Random bits by Matt Mackall <mpm@selenic.com>
# M68k port by Geert Uytterhoeven and Andreas Schwab
# AVR32 port by Haavard Skinnemoen (Atmel)
-# PARISC port by Kyle McMartin <kyle@parisc-linux.org>
+# AArch64, PARISC ports by Kyle McMartin
# sparc port by Martin Habets <errandir_news@mph.eclipse.co.uk>
#
# Usage:
@@ -34,7 +34,7 @@ use strict;
# $1 (first bracket) matches the dynamic amount of the stack growth
#
# use anything else and feel the pain ;)
-my (@stack, $re, $dre, $x, $xs);
+my (@stack, $re, $dre, $x, $xs, $funcre);
{
my $arch = shift;
if ($arch eq "") {
@@ -44,21 +44,23 @@ my (@stack, $re, $dre, $x, $xs);
$x = "[0-9a-f]"; # hex character
$xs = "[0-9a-f ]"; # hex character or space
- if ($arch eq 'arm') {
+ $funcre = qr/^$x* <(.*)>:$/;
+ if ($arch eq 'aarch64') {
+ #ffffffc0006325cc: a9bb7bfd stp x29, x30, [sp,#-80]!
+ $re = qr/^.*stp.*sp,\#-([0-9]{1,8})\]\!/o;
+ } elsif ($arch eq 'arm') {
#c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
$re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
} elsif ($arch eq 'avr32') {
#8000008a: 20 1d sub sp,4
#80000ca8: fa cd 05 b0 sub sp,sp,1456
$re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
- } elsif ($arch =~ /^i[3456]86$/) {
+ } elsif ($arch =~ /^x86(_64)?$/ || $arch =~ /^i[3456]86$/) {
#c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
- $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%esp$/o;
- $dre = qr/^.*[as][du][db] (%.*),\%esp$/o;
- } elsif ($arch eq 'x86_64') {
- # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
- $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%rsp$/o;
- $dre = qr/^.*[as][du][db] (\%.*),\%rsp$/o;
+ # or
+ # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
+ $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%(e|r)sp$/o;
+ $dre = qr/^.*[as][du][db] (%.*),\%(e|r)sp$/o;
} elsif ($arch eq 'ia64') {
#e0000000044011fc: 01 0f fc 8c adds r12=-384,r12
$re = qr/.*adds.*r12=-(([0-9]{2}|[3-9])[0-9]{2}),r12/o;
@@ -66,6 +68,10 @@ my (@stack, $re, $dre, $x, $xs);
# 2b6c: 4e56 fb70 linkw %fp,#-1168
# 1df770: defc ffe4 addaw #-28,%sp
$re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o;
+ } elsif ($arch eq 'metag') {
+ #400026fc: 40 00 00 82 ADD A0StP,A0StP,#0x8
+ $re = qr/.*ADD.*A0StP,A0StP,\#(0x$x{1,8})/o;
+ $funcre = qr/^$x* <[^\$](.*)>:$/;
} elsif ($arch eq 'mips64') {
#8800402c: 67bdfff0 daddiu sp,sp,-16
$re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
@@ -109,7 +115,6 @@ my (@stack, $re, $dre, $x, $xs);
#
# main()
#
-my $funcre = qr/^$x* <(.*)>:$/;
my ($func, $file, $lastslash);
while (my $line = <STDIN>) {