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-rw-r--r--arch/arm/cpu/armv7/keystone/psc.c42
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h1
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h3
3 files changed, 22 insertions, 24 deletions
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc8..fa5422f 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASE K2HK_PSC_BASE
-#endif
-
int psc_delay(void)
{
udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
retry = 0;
do {
- ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+ ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
/* Get the power domain associated with the module number */
- domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
- v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
- pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
- ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
/* Set the reset isolation bit */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
- v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
@@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
u32 pdctl;
u32 ptcmd;
- pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+ pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
- ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 50ce649..2cac633 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -16,7 +16,6 @@
#define KS2_RSTCTRL_MASK 0xffff0000
#define KS2_RSTCTRL_SWRST 0xfffe0000
-#define K2HK_PSC_BASE 0x02350000
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index ffdecbf..4e49143 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -119,6 +119,9 @@ struct ddr3_emif_config {
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
+/* PSC */
+#define KS2_PSC_BASE 0x02350000
+
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
generated by cgit v1.1 at 2024-11-30 10:59:26 +0000