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-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/Makefile10
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg107
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c394
-rw-r--r--board/freescale/mx7d_12x12_ddr3_arm2/plugin.S176
-rw-r--r--boards.cfg1
-rw-r--r--include/configs/mx7d_12x12_ddr3_arm2.h56
6 files changed, 744 insertions, 0 deletions
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/Makefile b/board/freescale/mx7d_12x12_ddr3_arm2/Makefile
new file mode 100644
index 0000000..f88af50
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/Makefile
@@ -0,0 +1,10 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx7d_12x12_ddr3_arm2.o
+
+extra-$(CONFIG_USE_PLUGIN) := plugin.bin
+$(obj)/plugin.bin: $(obj)/plugin.o
+ $(OBJCOPY) -O binary --gap-fill 0xff $< $@
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
new file mode 100644
index 0000000..619944c
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd/onenand, nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_EIMNOR
+BOOT_FROM nor
+#else
+BOOT_FROM sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF 0x2000
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x0040005e
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020001
+DATA 4 0x307a00d4 0x00010000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00090004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0908120a
+DATA 4 0x307a0104 0x0002020e
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020204
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x03030803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x00040404
+DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0244 0x00001323
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c b/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
new file mode 100644
index 0000000..c7a9efe
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
@@ -0,0 +1,394 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#ifdef CONFIG_SYS_I2C_MXC
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+#endif
+#include <asm/arch/crm_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
+ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+#define USDHC_PAD_VSELECT (PAD_CTL_DSE_3P3V_32OHM | \
+ PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
+ .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
+ .gp = IMX_GPIO_NR(1, 4),
+ },
+ .sda = {
+ .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
+ .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
+ .gp = IMX_GPIO_NR(1, 5),
+ },
+};
+
+/* I2C2 */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL | PC,
+ .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | PC,
+ .gp = IMX_GPIO_NR(1, 6),
+ },
+ .sda = {
+ .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA | PC,
+ .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 | PC,
+ .gp = IMX_GPIO_NR(1, 7),
+ },
+};
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
+ MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_ECSPI1_MISO__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_ECSPI1_SS0__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(5, 11)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR, 0, 4},
+};
+
+int mmc_get_env_devno(void)
+{
+ u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x58);
+ u32 dev_no;
+ u32 bootsel;
+
+ bootsel = (soc_sbmr & 0x0000F000) >> 12;
+
+ /* If not boot from sd/mmc, use default value */
+ if ((bootsel != BOOT_TYPE_SD) && (bootsel != BOOT_TYPE_MMC))
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ /* BOOT_CFG2[2] and BOOT_CFG2[3] */
+ dev_no = (soc_sbmr & 0x00000C00) >> 10;
+
+ return dev_no - 1;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no + 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = 1; /* uSDHC2 emmc always present */
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC2 (eMMC)
+ * mmc1 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return 0;
+ }
+
+ if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ }
+
+ return 0;
+}
+
+int check_mmc_autodetect(void)
+{
+ char *autodetect_str = getenv("mmcautodetect");
+
+ if ((autodetect_str != NULL) &&
+ (strcmp(autodetect_str, "yes") == 0)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+void board_late_mmc_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_devno();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ setenv_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+ mmc_map_to_kernel_blk(dev_no));
+ setenv("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
+
+#endif
+
+#ifdef CONFIG_SYS_USE_SPINOR
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ /* Chip selects CS0:CS3 */
+ MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+ gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_USE_SPINOR
+ setup_spinor();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+#ifdef CONFIG_PFUZE3000_PMIC_I2C
+#define PFUZE_DEVICEID 0x0
+#define PFUZE_REVID 0x3
+#define PFUZE_FABID 0x4
+
+#define PFUZE_LDOGCTL 0x69
+
+static int setup_pmic_voltages(void)
+{
+ unsigned char value, rev_id = 0;
+
+ i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE);
+ if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
+ if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_DEVICEID, 1, &value, 1)) {
+ printf("Read device ID error!\n");
+ return -1;
+ }
+ if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_REVID, 1, &rev_id, 1)) {
+ printf("Read Rev ID error!\n");
+ return -1;
+ }
+ printf("Found PFUZE300! deviceid 0x%x, revid 0x%x\n", value, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_LDOGCTL, 1, &value, 1)) {
+ printf("Read LDOCTL error!\n");
+ return -1;
+ }
+ value |= 0x1;
+ if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE_LDOGCTL, 1, &value, 1)) {
+ printf("Set LDOCTL error!\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_PFUZE3000_PMIC_I2C
+ int ret = 0;
+
+ ret = setup_pmic_voltages();
+ if (ret)
+ return ret;
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_init();
+#endif
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+ puts("Board: MX7D 12x12 DDR3 ARM2\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+ MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+ MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ ARRAY_SIZE(usb_otg1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ ARRAY_SIZE(usb_otg2_pads));
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return 1;
+ }
+ return 0;
+}
+#endif
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
new file mode 100644
index 0000000..28dbd5c
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_12x12_ddr3_arm2_ddr_setting
+ /* Configure ocram_epdc */
+ ldr r0, =IOMUXC_GPR_BASE_ADDR
+ ldr r1, =0x4f400005
+ str r1, [r0, #0x4]
+
+ ldr r0, =SRC_BASE_ADDR
+ ldr r1, =0x2
+ ldr r2, =0x1000
+ str r1, [r0, r2]
+
+ ldr r0, =DDRC_IPS_BASE_ADDR
+ ldr r1, =0x03040001
+ str r1, [r0]
+ ldr r1, =0x80400003
+ str r1, [r0, #0x1a0]
+ ldr r1, =0x00100020
+ str r1, [r0, #0x1a4]
+ ldr r1, =0x80100004
+ str r1, [r0, #0x1a8]
+ ldr r1, =0x0040005e
+ str r1, [r0, #0x64]
+ ldr r1, =0x1
+ str r1, [r0, #0x490]
+ ldr r1, =0x00020001
+ str r1, [r0, #0xd0]
+ ldr r1, =0x00010000
+ str r1, [r0, #0xd4]
+ ldr r1, =0x09300004
+ str r1, [r0, #0xdc]
+ ldr r1, =0x04080000
+ str r1, [r0, #0xe0]
+ ldr r1, =0x00090004
+ str r1, [r0, #0xe4]
+ ldr r1, =0x33f
+ str r1, [r0, #0xf4]
+ ldr r1, =0x0908120a
+ str r1, [r0, #0x100]
+ ldr r1, =0x0002020e
+ str r1, [r0, #0x104]
+ ldr r1, =0x03040407
+ str r1, [r0, #0x108]
+ ldr r1, =0x00002006
+ str r1, [r0, #0x10c]
+ ldr r1, =0x04020204
+ str r1, [r0, #0x110]
+ ldr r1, =0x03030202
+ str r1, [r0, #0x114]
+ ldr r1, =0x03030803
+ str r1, [r0, #0x120]
+ ldr r1, =0x00800020
+ str r1, [r0, #0x180]
+ ldr r1, =0x02098204
+ str r1, [r0, #0x190]
+ ldr r1, =0x00030303
+ str r1, [r0, #0x194]
+
+ ldr r1, =0x00000016
+ str r1, [r0, #0x200]
+ ldr r1, =0x00171717
+ str r1, [r0, #0x204]
+ ldr r1, =0x04040404
+ str r1, [r0, #0x214]
+ ldr r1, =0x00040404
+ str r1, [r0, #0x218]
+
+ ldr r1, =0x06000601
+ str r1, [r0, #0x240]
+ ldr r1, =0x00001323
+ str r1, [r0, #0x244]
+
+ ldr r0, =SRC_BASE_ADDR
+ mov r1, #0x0
+ ldr r2, =0x1000
+ str r1, [r0, r2]
+
+ ldr r0, =DDRPHY_IPS_BASE_ADDR
+ ldr r1, =0x17420f40
+ str r1, [r0]
+ ldr r1, =0x10210100
+ str r1, [r0, #0x4]
+ ldr r1, =0x00060807
+ str r1, [r0, #0x10]
+ ldr r1, =0x00000d6e
+ str r1, [r0, #0x9c]
+ ldr r1, =0x08080808
+ str r1, [r0, #0x20]
+ ldr r1, =0x08080808
+ str r1, [r0, #0x30]
+ ldr r1, =0x01000010
+ str r1, [r0, #0x50]
+
+ ldr r1, =0x0e407304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e447304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e447306
+ str r1, [r0, #0xc0]
+
+wait_zq:
+ ldr r1, [r0, #0xc4]
+ tst r1, #0x1
+ beq wait_zq
+
+ ldr r1, =0x0e447304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e407304
+ str r1, [r0, #0xc0]
+
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x0
+ ldr r2, =0x4130
+ str r1, [r0, r2]
+ ldr r0, =IOMUXC_GPR_BASE_ADDR
+ mov r1, #0x178
+ str r1, [r0, #0x20]
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x2
+ ldr r2, =0x4130
+ str r1, [r0, r2]
+ ldr r0, =DDRPHY_IPS_BASE_ADDR
+ ldr r1, =0x0000000f
+ str r1, [r0, #0x18]
+
+ ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+ ldr r1, [r0, #0x4]
+ tst r1, #0x1
+ beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+.endm
+
+.macro imx7_qos_setting
+ ldr r0, =QOSC_IPS_BASE_ADDR
+ ldr r1, =0x0
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x060]
+ str r1, [r0, #0x3400]
+ str r1, [r0, #0x2c00]
+ str r1, [r0, #0x3c00]
+
+ ldr r1, =0x0f020722
+ str r1, [r0, #0x34d0]
+ str r1, [r0, #0x34e0]
+
+ ldr r1, =0x1
+ str r1, [r0, #0x2c00]
+ str r1, [r0, #0x3c00]
+
+ ldr r1, =0x0f020222
+ str r1, [r0, #0x2c50]
+ str r1, [r0, #0x3c50]
+ str r1, [r0, #0x2c60]
+ str r1, [r0, #0x3c60]
+ ldr r1, =0x0f020422
+ str r1, [r0, #0x2c70]
+ str r1, [r0, #0x3c70]
+.endm
+
+.macro imx7_ddr_setting
+ imx7d_12x12_ddr3_arm2_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
diff --git a/boards.cfg b/boards.cfg
index 1e153ae..7e7fd81 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -387,6 +387,7 @@ Active arm armv7 mx6 freescale mx6sxsabreauto
Active arm armv7 mx7 freescale mx7d_12x12_lpddr3_arm2 mx7d_12x12_lpddr3_arm2 mx7d_12x12_lpddr3_arm2:IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg,MX7D,DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx7 freescale mx7d_12x12_lpddr3_arm2 mx7d_12x12_lpddr3_arm2_qspi1 mx7d_12x12_lpddr3_arm2:IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg,MX7D,SYS_BOOT_QSPI,DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx7 freescale mx7d_12x12_lpddr3_arm2 mx7d_12x12_lpddr3_arm2_spinor mx7d_12x12_lpddr3_arm2:IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg,MX7D,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx7 freescale mx7d_12x12_ddr3_arm2 mx7d_12x12_ddr3_arm2 mx7d_12x12_ddr3_arm2:IMX_CONFIG=board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg,MX7D,DEFAULT_FDT_FILE="imx7d-12x12-ddr3-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx7 freescale mx7d_19x19_ddr3_arm2 mx7d_19x19_ddr3_arm2 mx7d_19x19_ddr3_arm2:IMX_CONFIG=board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg,MX7D,DEFAULT_FDT_FILE="imx7d-19x19-ddr3-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx7 freescale mx7dsabresd mx7dsabresd mx7dsabresd:IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx7 freescale mx7dsabresd mx7dsabresd_qspi1 mx7dsabresd:IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D,SYS_BOOT_QSPI Fabio Estevam <fabio.estevam@freescale.com>
diff --git a/include/configs/mx7d_12x12_ddr3_arm2.h b/include/configs/mx7d_12x12_ddr3_arm2.h
new file mode 100644
index 0000000..b6c07db
--- /dev/null
+++ b/include/configs/mx7d_12x12_ddr3_arm2.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX7D_12X12_DDR3_ARM2_CONFIG_H
+#define __MX7D_12X12_DDR3_ARM2_CONFIG_H
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */
+
+#define PHYS_SDRAM_SIZE SZ_1G
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#ifdef CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_SYS_USE_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#else
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+/* PMIC */
+#define CONFIG_PFUZE3000_PMIC_I2C
+#ifdef CONFIG_PFUZE3000_PMIC_I2C
+#define CONFIG_PMIC_I2C_BUS 0
+#define CONFIG_PMIC_I2C_SLAVE 0x8
+#endif
+#endif
+
+#ifdef CONFIG_SYS_USE_SPINOR
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 3
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(5, 3)<<8))
+#endif
+
+#include "mx7d_arm2.h"
+
+#endif
generated by cgit v1.1 at 2024-11-21 16:24:54 +0000