diff options
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 4 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 17 | ||||
| -rw-r--r-- | cpu/mpc85xx/fdt.c | 2 |
3 files changed, 22 insertions, 1 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4..25c0416 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a8d83b1..5336934 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) * initialize a bunch of registers */ +#ifdef CONFIG_FSL_CORENET +static void corenet_tb_init(void) +{ + volatile ccsr_rcpm_t *rcpm = + (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + volatile ccsr_pic_t *pic = + (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + u32 whoami = in_be32(&pic->whoami); + + /* Enable the timebase register for this core */ + out_be32(&rcpm->ctbenrl, (1 << whoami)); +} +#endif + void cpu_init_f (void) { volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -229,6 +243,9 @@ void cpu_init_f (void) #if defined(CONFIG_FSL_DMA) dma_init(); #endif +#ifdef CONFIG_FSL_CORENET + corenet_tb_init(); +#endif } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 61e0fb0..efb6518 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_add_enet_stashing(blob); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 8, 1); + "timebase-frequency", get_tbclk(), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo); |