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-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c3
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c38
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h2
-rw-r--r--arch/arm/include/asm/emif.h8
4 files changed, 31 insertions, 20 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 1104655..ec542fd 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -27,6 +27,7 @@
#include <asm/arch/common_def.h>
#include <asm/io.h>
#include <asm/omap_common.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -107,7 +108,7 @@ void s_init(void)
preloader_console_init();
- config_ddr();
+ config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
#endif
/* Enable MMC0 */
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 26c6a66..9b1a80c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -22,6 +22,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +30,6 @@ struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -143,33 +143,37 @@ static void config_emif_ddr2(void)
printf("Couldn't configure SDRAM\n");
}
-void config_ddr(void)
+void config_ddr(short ddr_type)
{
struct ddr_ioctrl ioctrl;
enable_emif_clocks();
- config_vtp();
+ if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+ config_vtp();
- config_cmd_ctrl(&ddr2_cmd_ctrl_data);
+ config_cmd_ctrl(&ddr2_cmd_ctrl_data);
- config_ddr_data(0, &ddr2_data);
- config_ddr_data(1, &ddr2_data);
+ config_ddr_data(0, &ddr2_data);
+ config_ddr_data(1, &ddr2_data);
- writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
- writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+ writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+ writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
- ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data2ctl = DDR_IOCTRL_VALUE;
- config_io_ctrl(&ioctrl);
+ config_io_ctrl(&ioctrl);
- writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
- writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
+ writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
+ &ddrctrl->ddrioctrl);
+ writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
+ &ddrctrl->ddrckectrl);
- config_emif_ddr2();
+ config_emif_ddr2();
+ }
}
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 087082f..842e45f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -232,6 +232,6 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
-void config_ddr(void);
+void config_ddr(short ddr_type);
#endif /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 674c3de..ed251ec 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -19,7 +19,7 @@
#define EMIF1_BASE 0x4c000000
#define EMIF2_BASE 0x4d000000
-/* Registers shifts and masks */
+/* Registers shifts, masks and values */
/* EMIF_MOD_ID_REV */
#define EMIF_REG_SCHEME_SHIFT 30
@@ -46,6 +46,12 @@
/* SDRAM_CONFIG */
#define EMIF_REG_SDRAM_TYPE_SHIFT 29
#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1 0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1 1
+#define EMIF_REG_SDRAM_TYPE_DDR2 2
+#define EMIF_REG_SDRAM_TYPE_DDR3 3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5
#define EMIF_REG_IBANK_POS_SHIFT 27
#define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
#define EMIF_REG_DDR_TERM_SHIFT 24