diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 7 | ||||
| -rw-r--r-- | board/freescale/corenet_ds/law.c | 3 |
3 files changed, 19 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b3da970..f1f80f7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -222,6 +222,10 @@ static void corenet_tb_init(void) void cpu_init_f (void) { extern void m8560_cpm_reset (void); +#ifdef CONFIG_SYS_DCSRBAR_PHYS + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -262,6 +266,13 @@ void cpu_init_f (void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); + + #ifdef CONFIG_SYS_DCSRBAR_PHYS + /* set DCSRCR so that DCSR space is 1G */ + setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); + in_be32(&gur->dcsrcr); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 267a940..6aaade0 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,8 @@ typedef struct ccsr_gur { u32 cgencrl; /* Core general control */ u8 res31[184]; u32 sriopstecr; /* SRIO prescaler timer enable control */ - u8 res32[1788]; + u32 dcsrcr; /* DCSR Control register */ + u8 res32[1784]; u32 pmuxcr; /* Pin multiplexing control */ u8 res33[60]; u32 iovselsr; /* I/O voltage selection status */ @@ -1772,6 +1773,10 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +#define FSL_CORENET_DCSR_SZ_MASK 0x00000003 +#define FSL_CORENET_DCSR_SZ_4M 0x0 +#define FSL_CORENET_DCSR_SZ_1G 0x3 + /* * On p4080 we have an LIODN for msg unit (rmu) but not maintenance * everything after has RMan thus msg unit LIODN is used for maintenance diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c index dd6f6f7..58f23c5 100644 --- a/board/freescale/corenet_ds/law.c +++ b/board/freescale/corenet_ds/law.c @@ -37,7 +37,8 @@ struct law_entry law_table[] = { #endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), |