diff options
| -rw-r--r-- | board/freescale/p2041rdb/cpld.c | 16 | ||||
| -rw-r--r-- | board/freescale/p2041rdb/cpld.h | 2 |
2 files changed, 11 insertions, 7 deletions
diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index 8e1f46e..37b0ed5 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -53,7 +53,11 @@ void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); */ void __cpld_set_altbank(void) { + u8 reg5 = CPLD_READ(sw_ctl_on); + + CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); CPLD_WRITE(fbank_sel, 1); + CPLD_WRITE(system_rst, 1); } void cpld_set_altbank(void) __attribute__((weak, alias("__cpld_set_altbank"))); @@ -61,12 +65,12 @@ void cpld_set_altbank(void) /** * Set the boot bank to the default bank */ -void __cpld_clear_altbank(void) +void __cpld_set_defbank(void) { - CPLD_WRITE(fbank_sel, 0); + CPLD_WRITE(system_rst_default, 1); } -void cpld_clear_altbank(void) - __attribute__((weak, alias("__cpld_clear_altbank"))); +void cpld_set_defbank(void) + __attribute__((weak, alias("__cpld_set_defbank"))); #ifdef DEBUG static void cpld_dump_regs(void) @@ -101,9 +105,7 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strcmp(argv[2], "altbank") == 0) cpld_set_altbank(); else - cpld_clear_altbank(); - - cpld_reset(); + cpld_set_defbank(); } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[8] = {"1ms", "10ms", "30ms", "disable", "100ms", "1s", "10s", "60s"}; diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h index 3b24cb0..dcdb410 100644 --- a/board/freescale/p2041rdb/cpld.h +++ b/board/freescale/p2041rdb/cpld.h @@ -29,6 +29,7 @@ typedef struct cpld_data { u8 fbank_sel; /* 0xb - Flash bank selection */ u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ u8 sw[1]; /* 0xd - SW2 Status */ + u8 system_rst_default; /* 0xe - system reset to default register */ } __attribute__ ((packed)) cpld_data_t; #define SERDES_MUX_LANE_6_MASK 0x2 @@ -39,6 +40,7 @@ typedef struct cpld_data { #define SERDES_MUX_LANE_C_SHIFT 2 #define SERDES_MUX_LANE_D_MASK 0x8 #define SERDES_MUX_LANE_D_SHIFT 3 +#define CPLD_SWITCH_BANK_ENABLE 0x40 /* Pointer to the CPLD register set */ #define cpld ((cpld_data_t *)CPLD_BASE) |