diff options
| -rw-r--r-- | include/configs/MPC837XEMDS.h | 283 |
1 files changed, 166 insertions, 117 deletions
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 03aedec..76e598d 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -88,17 +88,17 @@ /* Arbiter Configuration Register */ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ /* System Priority Control Register */ -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ /* * IP blocks clock configuration */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ +#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ /* * System IO Config @@ -146,46 +146,47 @@ */ #define CONFIG_SYS_DDR_SIZE 512 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | 0x00010000 /* ODT_WR to CSn */ \ - | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) + | CSCONFIG_ROW_BIT_14 \ + | CSCONFIG_COL_BIT_10) /* 0x80010202 */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ - | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ - | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ - | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ - | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ - | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ - | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ - | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) /* 0x00620802 */ -#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ - | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ - | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ - | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ - | (13 << TIMING_CFG1_REFREC_SHIFT ) \ - | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ - | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ - | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (13 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) /* 0x3935d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ - | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ - | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ - | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ - | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ - | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ - | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (6 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) /* 0x131088c8 */ -#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ - | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) +#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x03E00100 */ #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ - | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x1432 << SDRAM_MODE_SD_SHIFT)) /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 +#define CONFIG_SYS_DDR_MODE2 0x00000000 #endif /* @@ -207,8 +208,8 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -216,7 +217,8 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Local Bus Configuration & Clock Setup @@ -229,19 +231,20 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ + /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ -#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ - | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ - | BR_V ) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | (2 << BR_PS_SHIFT) /* 16 bit port */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -249,7 +252,7 @@ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ | OR_GPCM_EHTR \ - | OR_GPCM_EAD ) + | OR_GPCM_EAD) /* 0xFE000FF7 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ @@ -263,11 +266,13 @@ * BCSR on the Local Bus */ #define CONFIG_SYS_BCSR 0xF8000000 -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ + /* Access window base at BCSR base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + /* Port size=8bit, MSEL=GPCM */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) +#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ /* * NAND Flash on the Local Bus @@ -275,22 +280,22 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ -#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V ) /* valid */ -#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \ | OR_FCM_BCTLD \ | OR_FCM_CST \ | OR_FCM_CHT \ | OR_FCM_SCY_1 \ | OR_FCM_RST \ | OR_FCM_TRLX \ - | OR_FCM_EHTR ) + | OR_FCM_EHTR) /* 0xFFFF919E */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE @@ -306,7 +311,7 @@ #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) @@ -326,11 +331,11 @@ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* * Config on-board RTC @@ -342,9 +347,9 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ @@ -397,9 +402,9 @@ extern int board_pci_host_broken(void); */ #define CONFIG_TSEC_ENET /* TSEC ethernet support */ #define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) #define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) /* * TSEC ethernet configuration @@ -435,12 +440,12 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA #define CONFIG_SATA2 #define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #ifdef CONFIG_FSL_SATA #define CONFIG_LBA48 @@ -454,11 +459,12 @@ extern int board_pci_host_broken(void); */ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 #else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ + #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 @@ -526,17 +532,19 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + /* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup @@ -555,53 +563,93 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ + | BATU_BL_8M \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ + | BATU_BL_128K \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ + | BATU_BL_32M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ + | BATU_BL_128K \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #else @@ -639,30 +687,31 @@ extern int board_pci_host_broken(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8379_mds.dtb\0" \ - "" + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc8379_mds.dtb\0" \ + "" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |