summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/include/asm/arch-mx31/imx-regs.h7
-rw-r--r--arch/arm/include/asm/arch-mx35/imx-regs.h2
-rw-r--r--arch/nios2/lib/board.c12
-rw-r--r--board/freescale/mx28evk/iomux.c3
-rw-r--r--board/freescale/mx6qsabrelite/mx6qsabrelite.c11
-rw-r--r--drivers/i2c/mxc_i2c.c31
-rw-r--r--drivers/i2c/mxs_i2c.c2
-rw-r--r--drivers/mmc/fsl_esdhc.c20
-rw-r--r--drivers/mmc/mmc.c23
-rw-r--r--drivers/net/sh_eth.h7
-rw-r--r--include/configs/flea3.h2
-rw-r--r--include/configs/imx31_phycore.h3
-rw-r--r--include/configs/mx28evk.h8
-rw-r--r--include/configs/mx35pdk.h2
-rw-r--r--include/configs/mx53ard.h2
-rw-r--r--include/configs/mx53evk.h2
-rw-r--r--include/configs/mx53loco.h2
-rw-r--r--include/configs/mx53smd.h2
-rw-r--r--include/configs/mx6qsabrelite.h8
-rw-r--r--include/configs/nios2-generic.h12
-rw-r--r--net/arp.c2
21 files changed, 99 insertions, 64 deletions
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6454acb..7ddbbd6 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -606,6 +606,13 @@ struct esdc_regs {
#define UART4_BASE 0x43FB0000
#define UART5_BASE 0x43FB4000
+#define I2C1_BASE_ADDR 0x43f80000
+#define I2C1_CLK_OFFSET 26
+#define I2C2_BASE_ADDR 0x43F98000
+#define I2C2_CLK_OFFSET 28
+#define I2C3_BASE_ADDR 0x43f84000
+#define I2C3_CLK_OFFSET 30
+
#define ESDCTL_SDE (1 << 31)
#define ESDCTL_CMD_RW (0 << 28)
#define ESDCTL_CMD_PRECHARGE (1 << 28)
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index e570ad1..3146006 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -39,7 +39,7 @@
#define MAX_BASE_ADDR 0x43F04000
#define EVTMON_BASE_ADDR 0x43F08000
#define CLKCTL_BASE_ADDR 0x43F0C000
-#define I2C_BASE_ADDR 0x43F80000
+#define I2C1_BASE_ADDR 0x43F80000
#define I2C3_BASE_ADDR 0x43F84000
#define ATA_BASE_ADDR 0x43F8C000
#define UART1_BASE 0x43F90000
diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
index ca8a3e5..1e495d4 100644
--- a/arch/nios2/lib/board.c
+++ b/arch/nios2/lib/board.c
@@ -87,17 +87,15 @@ void board_init (void)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
+ static gd_t gd_data;
+ static bd_t bd_data;
- /* Pointer is writable since we allocated a register for it.
- * Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address.
- */
- gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET;
+ /* Pointer is writable since we allocated a register for it. */
+ gd = &gd_data;
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
- memset( gd, 0, GENERATED_GBL_DATA_SIZE );
-
- gd->bd = (bd_t *)(gd+1); /* At end of global data */
+ gd->bd = &bd_data;
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 00cc0cc..40d8cf6 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -159,6 +159,9 @@ const iomux_cfg_t iomux_setup[] = {
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
};
#define HW_DRAM_CTL29 (0x74 >> 2)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 29cbfed..0eae96d 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -55,6 +55,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -72,6 +77,11 @@ iomux_v3_cfg_t uart2_pads[] = {
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+iomux_v3_cfg_t i2c3_pads[] = {
+ MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
iomux_v3_cfg_t usdhc3_pads[] = {
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -336,6 +346,7 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
#ifdef CONFIG_CMD_SATA
setup_sata();
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c88ac7c..fc68062 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -59,27 +59,10 @@ struct mxc_i2c_regs {
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
-#define I2C_BASE 0x43f80000
-#define I2C_CLK_OFFSET 26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE 0x43f98000
-#define I2C_CLK_OFFSET 28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE 0x43f84000
-#define I2C_CLK_OFFSET 30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE I2C3_BASE_ADDR
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE CONFIG_SYS_I2C_BASE
#else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif
#define I2C_MAX_TIMEOUT 10000
@@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
(struct clock_control_regs *)CCM_BASE;
/* start the required I2C clock */
- writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+ writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
&sc_regs->cgr0);
#endif
@@ -248,12 +231,6 @@ int i2c_imx_start(void)
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
int result;
- int speed = i2c_get_bus_speed();
- u8 clk_idx = i2c_imx_get_clk(speed);
- u8 idx = i2c_clk_div[clk_idx][1];
-
- /* Store divider value */
- writeb(idx, &i2c_regs->ifdr);
/* Enable I2C controller */
writeb(0, &i2c_regs->i2sr);
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index c8fea32..48aaaa6 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -97,7 +97,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen,
for (i = 0; i < alen; i++) {
data >>= 8;
- data |= ((char *)&addr)[i] << 24;
+ data |= ((char *)&addr)[alen - i - 1] << 24;
if ((i & 3) == 2)
writel(data, &i2c_regs->hw_i2c_data);
}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 07370b5..b6c969d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(&regs->dsaddr, (u32)data->dest);
} else {
+ flush_dcache_range((ulong)data->src,
+ (ulong)data->src+data->blocks
+ *data->blocksize);
+
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
@@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
return 0;
}
-
+static void check_and_invalidate_dcache_range
+ (struct mmc_cmd *cmd,
+ struct mmc_data *data) {
+ unsigned start = (unsigned)data->dest ;
+ unsigned size = roundup(ARCH_DMA_MINALIGN,
+ data->blocks*data->blocksize);
+ unsigned end = start+size ;
+ invalidate_dcache_range(start, end);
+}
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
@@ -315,6 +327,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
;
+ if (data && (data->flags & MMC_DATA_READ))
+ check_and_invalidate_dcache_range(cmd, data);
+
irqstat = esdhc_read32(&regs->irqstat);
esdhc_write32(&regs->irqstat, irqstat);
@@ -528,6 +543,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
/* First reset the eSDHC controller */
esdhc_reset(regs);
+ esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
+ | SYSCTL_IPGEN | SYSCTL_CKEN);
+
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index aebe578..c1c2862 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -333,6 +333,7 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
int err = 0;
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
+ int timeout = 1000;
if (!mmc)
return -1;
@@ -352,6 +353,10 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
break;
blk += blk_r;
+
+ /* Waiting for the ready status */
+ if (mmc_send_status(mmc, timeout))
+ return 0;
}
return blk;
@@ -1195,9 +1200,9 @@ int mmc_startup(struct mmc *mmc)
}
if (mmc->card_caps & MMC_MODE_HS)
- mmc_set_clock(mmc, 50000000);
+ mmc->tran_speed = 50000000;
else
- mmc_set_clock(mmc, 25000000);
+ mmc->tran_speed = 25000000;
} else {
width = ((mmc->host_caps & MMC_MODE_MASK_WIDTH_BITS) >>
MMC_MODE_WIDTH_BITS_SHIFT);
@@ -1234,13 +1239,14 @@ int mmc_startup(struct mmc *mmc)
if (mmc->card_caps & MMC_MODE_HS) {
if (mmc->card_caps & MMC_MODE_HS_52MHz)
- mmc_set_clock(mmc, 52000000);
+ mmc->tran_speed = 52000000;
else
- mmc_set_clock(mmc, 26000000);
- } else
- mmc_set_clock(mmc, 20000000);
+ mmc->tran_speed = 26000000;
+ }
}
+ mmc_set_clock(mmc, mmc->tran_speed);
+
/* fill in device description */
mmc->block_dev.lun = 0;
mmc->block_dev.type = 0;
@@ -1305,8 +1311,11 @@ int mmc_register(struct mmc *mmc)
block_dev_desc_t *mmc_get_dev(int dev)
{
struct mmc *mmc = find_mmc_device(dev);
+ if (!mmc)
+ return NULL;
- return mmc ? &mmc->block_dev : NULL;
+ mmc_init(mmc);
+ return &mmc->block_dev;
}
#endif
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index a1ba68b..50f4b69 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -452,17 +452,16 @@ enum ECSR_STATUS_BIT {
/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
-#if defined(CONFIG_CPU_SH7724)
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+ ECSIPR_BRCRXIP = 0x20,
ECSIPR_PSRTOIP = 0x10,
- ECSIPR_LCHNGIP = 0x04,
- ECSIPR_ICDIP = 0x01,
#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
ECSIPR_PSRTOIP = 0x10,
ECSIPR_PHYIP = 0x08,
+#endif
ECSIPR_LCHNGIP = 0x04,
ECSIPR_MPDIP = 0x02,
ECSIPR_ICDIP = 0x01,
-#endif
};
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 6c5fcac..e8e3c6a 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -66,7 +66,7 @@
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_SPI
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index acbd670..a412cf6 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -54,7 +54,8 @@
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_UART
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 8f60496..54d21e6 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -68,6 +68,7 @@
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_I2C
/*
* Memory configurations
@@ -188,6 +189,13 @@
#define CONFIG_USB_STORAGE
#endif
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
/*
* SPI
*/
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index ebbd371..f930ed0 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -57,7 +57,7 @@
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index ffc799c..0a928af 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -50,7 +50,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 8f2c03f..67def93 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -53,7 +53,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2 1
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Configs */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index f936785..0a25c7d 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -89,7 +89,7 @@
/* I2C Configs */
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Controller */
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 1df20fa..760014f 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -50,7 +50,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index fd25faf..fbd10d6 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -58,6 +58,14 @@
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#endif
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
index a383fa4..69ff3ef 100644
--- a/include/configs/nios2-generic.h
+++ b/include/configs/nios2-generic.h
@@ -117,10 +117,9 @@
/*
* MEMORY ORGANIZATION
- * -Monitor at top of sdram.
- * -The heap is placed below the monitor
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
*/
#define CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
@@ -130,10 +129,7 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000)
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \
CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - \
- GENERATED_GBL_DATA_SIZE - \
- GENERATED_BD_INFO_SIZE)
-#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP CONFIG_SYS_MALLOC_BASE
/*
* MISC
diff --git a/net/arp.c b/net/arp.c
index bac4cab..8e1d2ed 100644
--- a/net/arp.c
+++ b/net/arp.c
@@ -194,7 +194,7 @@ void ArpReceive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len)
#ifdef CONFIG_KEEP_SERVERADDR
if (NetServerIP == NetArpWaitPacketIP) {
char buf[20];
- sprintf(buf, "%pM", arp->ar_sha);
+ sprintf(buf, "%pM", &arp->ar_sha);
setenv("serveraddr", buf);
}
#endif
generated by cgit v1.1 at 2024-11-10 01:18:03 +0000