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-rw-r--r--Makefile12
-rw-r--r--board/freescale/common/cadmus.c (renamed from board/cds/common/cadmus.c)0
-rw-r--r--board/freescale/common/cadmus.h (renamed from board/cds/common/cadmus.h)0
-rw-r--r--board/freescale/common/eeprom.c (renamed from board/cds/common/eeprom.c)0
-rw-r--r--board/freescale/common/eeprom.h (renamed from board/cds/common/eeprom.h)0
-rw-r--r--board/freescale/common/ft_board.c (renamed from board/cds/common/ft_board.c)50
-rw-r--r--board/freescale/common/via.c (renamed from board/cds/common/via.c)0
-rw-r--r--board/freescale/common/via.h (renamed from board/cds/common/via.h)0
-rw-r--r--board/freescale/mpc8540ads/Makefile (renamed from board/mpc8540ads/Makefile)0
-rw-r--r--board/freescale/mpc8540ads/config.mk (renamed from board/mpc8540ads/config.mk)0
-rw-r--r--board/freescale/mpc8540ads/init.S (renamed from board/mpc8540ads/init.S)0
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c (renamed from board/mpc8540ads/mpc8540ads.c)44
-rw-r--r--board/freescale/mpc8540ads/u-boot.lds (renamed from board/mpc8540ads/u-boot.lds)4
-rw-r--r--board/freescale/mpc8541cds/Makefile (renamed from board/cds/mpc8541cds/Makefile)0
-rw-r--r--board/freescale/mpc8541cds/config.mk (renamed from board/cds/mpc8541cds/config.mk)0
-rw-r--r--board/freescale/mpc8541cds/init.S (renamed from board/cds/mpc8541cds/init.S)0
-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c (renamed from board/cds/mpc8541cds/mpc8541cds.c)44
-rw-r--r--board/freescale/mpc8541cds/u-boot.lds (renamed from board/cds/mpc8555cds/u-boot.lds)4
-rw-r--r--board/freescale/mpc8544ds/init.S25
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c81
-rw-r--r--board/freescale/mpc8548cds/Makefile (renamed from board/cds/mpc8548cds/Makefile)0
-rw-r--r--board/freescale/mpc8548cds/config.mk (renamed from board/cds/mpc8548cds/config.mk)0
-rw-r--r--board/freescale/mpc8548cds/init.S (renamed from board/cds/mpc8548cds/init.S)25
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c (renamed from board/cds/mpc8548cds/mpc8548cds.c)58
-rw-r--r--board/freescale/mpc8548cds/u-boot.lds (renamed from board/cds/mpc8548cds/u-boot.lds)4
-rw-r--r--board/freescale/mpc8555cds/Makefile (renamed from board/cds/mpc8555cds/Makefile)0
-rw-r--r--board/freescale/mpc8555cds/config.mk (renamed from board/cds/mpc8555cds/config.mk)0
-rw-r--r--board/freescale/mpc8555cds/init.S (renamed from board/cds/mpc8555cds/init.S)0
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c (renamed from board/cds/mpc8555cds/mpc8555cds.c)44
-rw-r--r--board/freescale/mpc8555cds/u-boot.lds (renamed from board/cds/mpc8541cds/u-boot.lds)4
-rw-r--r--board/freescale/mpc8560ads/Makefile (renamed from board/mpc8560ads/Makefile)0
-rw-r--r--board/freescale/mpc8560ads/config.mk (renamed from board/mpc8560ads/config.mk)0
-rw-r--r--board/freescale/mpc8560ads/init.S (renamed from board/mpc8560ads/init.S)0
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c (renamed from board/mpc8560ads/mpc8560ads.c)62
-rw-r--r--board/freescale/mpc8560ads/u-boot.lds (renamed from board/mpc8560ads/u-boot.lds)4
-rw-r--r--board/freescale/mpc8568mds/Makefile (renamed from board/mpc8568mds/Makefile)4
-rw-r--r--board/freescale/mpc8568mds/bcsr.c (renamed from board/mpc8568mds/bcsr.c)0
-rw-r--r--board/freescale/mpc8568mds/bcsr.h (renamed from board/mpc8568mds/bcsr.h)0
-rw-r--r--board/freescale/mpc8568mds/config.mk (renamed from board/mpc8568mds/config.mk)0
-rw-r--r--board/freescale/mpc8568mds/init.S (renamed from board/mpc8568mds/init.S)10
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c (renamed from board/mpc8568mds/mpc8568mds.c)182
-rw-r--r--board/freescale/mpc8568mds/u-boot.lds (renamed from board/mpc8568mds/u-boot.lds)4
-rw-r--r--board/mpc8540eval/mpc8540eval.c14
-rw-r--r--board/mpc8568mds/ft_board.c45
-rw-r--r--board/pm854/pm854.c14
-rw-r--r--board/pm856/pm856.c11
-rw-r--r--board/sbc8560/sbc8560.c14
-rw-r--r--board/stxgp3/stxgp3.c6
-rw-r--r--board/stxssa/stxssa.c6
-rw-r--r--board/tqm85xx/sdram.c6
-rw-r--r--board/tqm85xx/tqm85xx.c8
-rw-r--r--cpu/mpc85xx/Makefile4
-rw-r--r--cpu/mpc85xx/commproc.c28
-rw-r--r--cpu/mpc85xx/cpu.c124
-rw-r--r--cpu/mpc85xx/cpu_init.c16
-rw-r--r--cpu/mpc85xx/ether_fcc.c54
-rw-r--r--cpu/mpc85xx/fdt.c64
-rw-r--r--cpu/mpc85xx/interrupts.c10
-rw-r--r--cpu/mpc85xx/pci.c34
-rw-r--r--cpu/mpc85xx/qe_io.c4
-rw-r--r--cpu/mpc85xx/serial_scc.c35
-rw-r--r--cpu/mpc85xx/spd_sdram.c17
-rw-r--r--cpu/mpc85xx/speed.c34
-rw-r--r--cpu/mpc85xx/traps.c4
-rw-r--r--drivers/pci/fsl_pci_init.c23
-rw-r--r--include/asm-ppc/immap_85xx.h45
-rw-r--r--include/asm-ppc/immap_fsl_pci.h4
-rw-r--r--include/asm-ppc/iopin_85xx.h40
-rw-r--r--include/asm-ppc/mmu.h4
-rw-r--r--include/common.h1
-rw-r--r--include/configs/MPC8540ADS.h12
-rw-r--r--include/configs/MPC8541CDS.h13
-rw-r--r--include/configs/MPC8544DS.h119
-rw-r--r--include/configs/MPC8548CDS.h103
-rw-r--r--include/configs/MPC8555CDS.h13
-rw-r--r--include/configs/MPC8560ADS.h14
-rw-r--r--include/configs/MPC8568MDS.h39
-rw-r--r--include/e500.h1
-rw-r--r--include/ioports.h2
79 files changed, 773 insertions, 877 deletions
diff --git a/Makefile b/Makefile
index 1ff80b5..bde38ca 100644
--- a/Makefile
+++ b/Makefile
@@ -1911,7 +1911,7 @@ TQM834x_config: unconfig
#########################################################################
MPC8540ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
MPC8540EVAL_config \
MPC8540EVAL_33_config \
@@ -1935,7 +1935,7 @@ MPC8540EVAL_66_slave_config: unconfig
@$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
MPC8560ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale
MPC8541CDS_legacy_config \
MPC8541CDS_config: unconfig
@@ -1945,7 +1945,7 @@ MPC8541CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
echo "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
+ @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale
MPC8544DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
@@ -1958,7 +1958,7 @@ MPC8548CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
echo "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
+ @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale
MPC8555CDS_legacy_config \
MPC8555CDS_config: unconfig
@@ -1968,10 +1968,10 @@ MPC8555CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
echo "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
+ @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale
MPC8568MDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
diff --git a/board/cds/common/cadmus.c b/board/freescale/common/cadmus.c
index 5f86de5..5f86de5 100644
--- a/board/cds/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
diff --git a/board/cds/common/cadmus.h b/board/freescale/common/cadmus.h
index 217ea64..217ea64 100644
--- a/board/cds/common/cadmus.h
+++ b/board/freescale/common/cadmus.h
diff --git a/board/cds/common/eeprom.c b/board/freescale/common/eeprom.c
index 5034e0c..5034e0c 100644
--- a/board/cds/common/eeprom.c
+++ b/board/freescale/common/eeprom.c
diff --git a/board/cds/common/eeprom.h b/board/freescale/common/eeprom.h
index 12a0789..12a0789 100644
--- a/board/cds/common/eeprom.h
+++ b/board/freescale/common/eeprom.h
diff --git a/board/cds/common/ft_board.c b/board/freescale/common/ft_board.c
index 3eda100..6f221af 100644
--- a/board/cds/common/ft_board.c
+++ b/board/freescale/common/ft_board.c
@@ -21,24 +21,29 @@
*/
#include <common.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "cadmus.h"
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
+#if defined(CONFIG_OF_BOARD_SETUP)
static void cds_pci_fixup(void *blob)
{
- int len;
- u32 *map;
- int slot;
- int i;
+ int node, tmp[2];
+ const char *path;
+ int len, slot, i;
+ u32 *map = NULL;
- map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
-
- if (!map)
- map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ node = fdt_path_offset(blob, path);
+ if (node >= 0) {
+ map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+ }
+ }
+ }
if (map) {
len /= sizeof(u32);
@@ -50,33 +55,18 @@ static void cds_pci_fixup(void *blob)
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
-
map+=7;
}
- } else {
- printf("*** Warning - No PCI node found\n");
}
}
-#endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
-
+ ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-
cds_pci_fixup(blob);
+#endif
}
#endif
diff --git a/board/cds/common/via.c b/board/freescale/common/via.c
index 4a63d77..4a63d77 100644
--- a/board/cds/common/via.c
+++ b/board/freescale/common/via.c
diff --git a/board/cds/common/via.h b/board/freescale/common/via.h
index 77cfacc..77cfacc 100644
--- a/board/cds/common/via.h
+++ b/board/freescale/common/via.h
diff --git a/board/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
index 2913650..2913650 100644
--- a/board/mpc8540ads/Makefile
+++ b/board/freescale/mpc8540ads/Makefile
diff --git a/board/mpc8540ads/config.mk b/board/freescale/mpc8540ads/config.mk
index 92f8931..92f8931 100644
--- a/board/mpc8540ads/config.mk
+++ b/board/freescale/mpc8540ads/config.mk
diff --git a/board/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S
index 544fde9..544fde9 100644
--- a/board/mpc8540ads/init.S
+++ b/board/freescale/mpc8540ads/init.S
diff --git a/board/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 914e51a..35f5eea 100644
--- a/board/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -30,11 +30,8 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
+#include <libfdt.h>
+#include <fdt_support.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@@ -77,13 +74,12 @@ initdram(int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/*
@@ -125,9 +121,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -186,8 +181,7 @@ local_bus_init(void)
void
sdram_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@@ -282,8 +276,7 @@ int testdram (void)
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
@@ -331,22 +324,25 @@ pci_init_board(void)
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
+ int node, tmp[2];
+ const char *path;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
}
}
#endif
diff --git a/board/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
index e7a88cf..a7c68b3 100644
--- a/board/mpc8540ads/u-boot.lds
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/mpc8540ads/init.o (.bootpg)
+ board/freescale/mpc8540ads/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/mpc8540ads/init.o (.text)
+ board/freescale/mpc8540ads/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/cds/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
index 7f53098..7f53098 100644
--- a/board/cds/mpc8541cds/Makefile
+++ b/board/freescale/mpc8541cds/Makefile
diff --git a/board/cds/mpc8541cds/config.mk b/board/freescale/mpc8541cds/config.mk
index 17cc8bc..17cc8bc 100644
--- a/board/cds/mpc8541cds/config.mk
+++ b/board/freescale/mpc8541cds/config.mk
diff --git a/board/cds/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S
index 978bda5..978bda5 100644
--- a/board/cds/mpc8541cds/init.S
+++ b/board/freescale/mpc8541cds/init.S
diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 558ba99..9ab98d4 100644
--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -28,6 +28,8 @@
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
@@ -203,8 +205,7 @@ int board_early_init_f (void)
int checkboard (void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -250,7 +251,6 @@ long int
initdram(int board_type)
{
long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
@@ -263,7 +263,7 @@ initdram(int board_type)
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -293,9 +293,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -344,8 +343,7 @@ sdram_init(void)
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -506,3 +504,31 @@ pci_init_board(void)
pci_mpc85xx_init(hose);
#endif
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
index de0923a..4360d67 100644
--- a/board/cds/mpc8555cds/u-boot.lds
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/cds/mpc8555cds/init.o (.bootpg)
+ board/freescale/mpc8541cds/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/cds/mpc8555cds/init.o (.text)
+ board/freescale/mpc8541cds/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 68ccba7..084d4b8 100644
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -27,13 +27,6 @@
#include <config.h>
#include <mpc85xx.h>
-#define LAWAR_TRGT_PCI1 0x00000000
-#define LAWAR_TRGT_PCIE1 0x00200000
-#define LAWAR_TRGT_PCIE2 0x00100000
-#define LAWAR_TRGT_PCIE3 0x00300000
-#define LAWAR_TRGT_LBC 0x00400000
-#define LAWAR_TRGT_DDR 0x00f00000
-
/*
* TLB0 and TLB1 Entries
*
@@ -212,31 +205,31 @@ law_entry:
.long (4f-3f)/8
3:
.long 0
- .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+ .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
/* contains both PCIE3 MEM & IO space */
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
4:
entry_end
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index b6c9e93..66cb536 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -29,14 +29,11 @@
#include <asm/io.h>
#include <spd.h>
#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/pixis.h"
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
-
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
@@ -52,10 +49,9 @@ int board_early_init_f (void)
int checkboard (void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %x\n",&gur->porpllsr);
@@ -149,8 +145,7 @@ int first_free_busno=0;
void
pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy)
return val;
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
+
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
+ int node, tmp[2];
+ const char *path;
ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
#ifdef CONFIG_PCI1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
-#endif
-#ifdef CONFIG_PCIE1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCIE2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci2", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCIE3
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
- debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci3", NULL);
+ if (path) {
+ tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
+ }
}
#endif
diff --git a/board/cds/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
index 7f53098..7f53098 100644
--- a/board/cds/mpc8548cds/Makefile
+++ b/board/freescale/mpc8548cds/Makefile
diff --git a/board/cds/mpc8548cds/config.mk b/board/freescale/mpc8548cds/config.mk
index b23bc87..b23bc87 100644
--- a/board/cds/mpc8548cds/config.mk
+++ b/board/freescale/mpc8548cds/config.mk
diff --git a/board/cds/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
index 72940b0..a83a095 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/freescale/mpc8548cds/init.S
@@ -28,13 +28,6 @@
#include <config.h>
#include <mpc85xx.h>
-#define LAWAR_TRGT_PCI1 0x00000000
-#define LAWAR_TRGT_PCI2 0x00100000
-#define LAWAR_TRGT_PCIE 0x00200000
-#define LAWAR_TRGT_RIO 0x00c00000
-#define LAWAR_TRGT_LBC 0x00400000
-#define LAWAR_TRGT_DDR 0x00f00000
-
/*
* TLB0 and TLB1 Entries
*
@@ -232,39 +225,39 @@ law_entry:
.long (4f-3f)/8
3:
.long 0
- .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+ .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
#ifdef CFG_PCI1_MEM_PHYS
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
#endif
#ifdef CFG_PCI2_MEM_PHYS
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
#endif
#ifdef CFG_PCIE1_MEM_PHYS
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
#endif
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
#ifdef CFG_RIO_MEM_PHYS
.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
#endif
4:
entry_end
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 36d7e1e..47e2dd8 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -29,14 +29,13 @@
#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
#include "../common/via.h"
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
@@ -55,9 +54,8 @@ int board_early_init_f (void)
int checkboard (void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -96,7 +94,6 @@ long int
initdram(int board_type)
{
long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
@@ -109,7 +106,7 @@ initdram(int board_type)
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -139,9 +136,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -177,8 +173,7 @@ sdram_init(void)
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -330,8 +325,7 @@ int first_free_busno=0;
void
pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -524,30 +518,30 @@ int last_stage_init(void)
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_pci_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
-
+ int node, tmp[2];
+ const char *path;
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
#ifdef CONFIG_PCI1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
-
#ifdef CONFIG_PCIE1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
+ }
}
#endif
diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
index b19c481..ee772d3 100644
--- a/board/cds/mpc8548cds/u-boot.lds
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/cds/mpc8548cds/init.o (.bootpg)
+ board/freescale/mpc8548cds/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/cds/mpc8548cds/init.o (.text)
+ board/freescale/mpc8548cds/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/cds/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
index 7f53098..7f53098 100644
--- a/board/cds/mpc8555cds/Makefile
+++ b/board/freescale/mpc8555cds/Makefile
diff --git a/board/cds/mpc8555cds/config.mk b/board/freescale/mpc8555cds/config.mk
index 5dcaa77..5dcaa77 100644
--- a/board/cds/mpc8555cds/config.mk
+++ b/board/freescale/mpc8555cds/config.mk
diff --git a/board/cds/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S
index 978bda5..978bda5 100644
--- a/board/cds/mpc8555cds/init.S
+++ b/board/freescale/mpc8555cds/init.S
diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 8f16421..74c220d 100644
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -26,6 +26,8 @@
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
@@ -201,8 +203,7 @@ int board_early_init_f (void)
int checkboard (void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -248,7 +249,6 @@ long int
initdram(int board_type)
{
long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
@@ -261,7 +261,7 @@ initdram(int board_type)
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -291,9 +291,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -342,8 +341,7 @@ sdram_init(void)
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -506,3 +504,31 @@ pci_init_board(void)
pci_mpc85xx_init(hose);
#endif
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
index 7a5daef..df21ea8 100644
--- a/board/cds/mpc8541cds/u-boot.lds
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/cds/mpc8541cds/init.o (.bootpg)
+ board/freescale/mpc8555cds/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/cds/mpc8541cds/init.o (.text)
+ board/freescale/mpc8555cds/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
index 2913650..2913650 100644
--- a/board/mpc8560ads/Makefile
+++ b/board/freescale/mpc8560ads/Makefile
diff --git a/board/mpc8560ads/config.mk b/board/freescale/mpc8560ads/config.mk
index 9aef2bb..9aef2bb 100644
--- a/board/mpc8560ads/config.mk
+++ b/board/freescale/mpc8560ads/config.mk
diff --git a/board/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S
index 544fde9..544fde9 100644
--- a/board/mpc8560ads/init.S
+++ b/board/freescale/mpc8560ads/init.S
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index eef524b..bb7f11b 100644
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -32,10 +32,8 @@
#include <ioports.h>
#include <spd.h>
#include <miiphy.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
+#include <fdt_support.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@@ -278,13 +276,12 @@ initdram(int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/*
@@ -326,9 +323,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -387,8 +383,7 @@ local_bus_init(void)
void
sdram_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@@ -483,8 +478,7 @@ int testdram (void)
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
@@ -548,35 +542,25 @@ pci_init_board(void)
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_soc_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
-
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_brgfreq);
-
- p = ft_get_prop(blob,
- "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
- &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_baudrate);
-
- p = ft_get_prop(blob,
- "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
- &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_baudrate);
-}
-
+#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
+ int node, tmp[2];
+ const char *path;
+
ft_cpu_setup(blob, bd);
- ft_soc_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
}
#endif
diff --git a/board/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
index 726a153..c2cba61 100644
--- a/board/mpc8560ads/u-boot.lds
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/mpc8560ads/init.o (.bootpg)
+ board/freescale/mpc8560ads/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/mpc8560ads/init.o (.text)
+ board/freescale/mpc8560ads/init.o (.text)
cpu/mpc85xx/commproc.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
diff --git a/board/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
index a799aa4..643fbc0 100644
--- a/board/mpc8568mds/Makefile
+++ b/board/freescale/mpc8568mds/Makefile
@@ -29,9 +29,7 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o \
- bcsr.o \
- ft_board.o
+COBJS := $(BOARD).o bcsr.o
SOBJS := init.o
diff --git a/board/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
index aae0f98..aae0f98 100644
--- a/board/mpc8568mds/bcsr.c
+++ b/board/freescale/mpc8568mds/bcsr.c
diff --git a/board/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
index aefd9bf..aefd9bf 100644
--- a/board/mpc8568mds/bcsr.h
+++ b/board/freescale/mpc8568mds/bcsr.h
diff --git a/board/mpc8568mds/config.mk b/board/freescale/mpc8568mds/config.mk
index 021522c..021522c 100644
--- a/board/mpc8568mds/config.mk
+++ b/board/freescale/mpc8568mds/config.mk
diff --git a/board/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
index 972a7d4..e36036d 100644
--- a/board/mpc8568mds/init.S
+++ b/board/freescale/mpc8568mds/init.S
@@ -28,7 +28,6 @@
#include <config.h>
#include <mpc85xx.h>
-
/*
* TLB0 and TLB1 Entries
*
@@ -216,15 +215,14 @@ tlb1_entry:
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
+#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
diff --git a/board/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 818ff13..460cb1b 100644
--- a/board/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -26,9 +26,12 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <i2c.h>
#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "bcsr.h"
@@ -133,7 +136,6 @@ long int
initdram(int board_type)
{
long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
@@ -146,7 +148,7 @@ initdram(int board_type)
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@ -176,9 +178,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -211,8 +212,7 @@ sdram_init(void)
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
uint lsdmr_common;
@@ -337,16 +337,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
};
#endif
-static struct pci_controller hose[] = {
- {
+static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc8568mds_config_table,
#endif
- }
};
-
#endif /* CONFIG_PCI */
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno = 0;
+
/*
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
*/
@@ -389,11 +392,164 @@ pib_init(void)
asm("eieio");
}
+#ifdef CONFIG_PCI
void
pci_init_board(void)
{
-#ifdef CONFIG_PCI
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCI1
+{
pib_init();
- pci_mpc85xx_init(hose);
+
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+
+ uint pci_32 = 1; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = 66666000;
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno = hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
index 71099f6..4682041 100644
--- a/board/mpc8568mds/u-boot.lds
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -37,7 +37,7 @@ SECTIONS
.bootpg 0xFFFFF000:
{
cpu/mpc85xx/start.o (.bootpg)
- board/mpc8568mds/init.o (.bootpg)
+ board/freescale/mpc8568mds/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -67,7 +67,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/mpc8568mds/init.o (.text)
+ board/freescale/mpc8568mds/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 3b3c8ed..64dfe09 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -35,8 +35,7 @@ long int fixed_sdram (void);
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
@@ -68,14 +67,13 @@ long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
@@ -138,8 +136,7 @@ long int initdram (int board_type)
* enable errors */
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -222,8 +219,7 @@ int testdram (void)
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
diff --git a/board/mpc8568mds/ft_board.c b/board/mpc8568mds/ft_board.c
deleted file mode 100644
index 36815cc..0000000
--- a/board/mpc8568mds/ft_board.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <ft_build.h>
-
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-}
-#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */
diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 6ead1d0..999d8b5 100644
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -45,8 +45,7 @@ long int fixed_sdram(void);
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
@@ -79,13 +78,12 @@ initdram(int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
@@ -133,9 +131,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -229,8 +226,7 @@ int testdram (void)
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index a100754..bfde695 100644
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -232,13 +232,12 @@ initdram(int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
@@ -287,9 +286,8 @@ initdram(int board_type)
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
@@ -382,8 +380,7 @@ int testdram (void)
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index e8b9929..47df884 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
@@ -264,16 +263,15 @@ long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#endif /* 0 */
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
@@ -336,8 +334,7 @@ long int initdram (int board_type)
* enable errors */
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -424,8 +421,7 @@ long int fixed_sdram (void)
#define CFG_DDR_CONTROL 0xc2000000
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = 0x00000007;
ddr->cs1_bnds = 0x0010001f;
diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c
index a58c043..3649acf 100644
--- a/board/stxgp3/stxgp3.c
+++ b/board/stxgp3/stxgp3.c
@@ -203,8 +203,7 @@ int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
@@ -283,11 +282,10 @@ initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 9bacb98..e2b38a6 100644
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -252,8 +252,7 @@ int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
@@ -302,8 +301,7 @@ initdram (int board_type)
#if defined(CONFIG_DDR_DLL)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c
index 9c1f087..2053ade 100644
--- a/board/tqm85xx/sdram.c
+++ b/board/tqm85xx/sdram.c
@@ -57,8 +57,7 @@ int cas_latency(void);
long int sdram_setup(int casl)
{
int i;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
@@ -150,8 +149,7 @@ long int initdram (int board_type)
* This DLL-Override only used on TQM8540 and TQM8560
*/
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
index 256c076..5d5cb1b 100644
--- a/board/tqm85xx/tqm85xx.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -262,8 +262,7 @@ int checkboard (void)
int misc_init_r (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
@@ -324,9 +323,8 @@ int misc_init_r (void)
*/
void local_bus_init (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 32091fa..d179d70 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -29,8 +29,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o resetvec.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
+ $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c
index 3504d50..b0ecd25 100644
--- a/cpu/mpc85xx/commproc.c
+++ b/cpu/mpc85xx/commproc.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
void
m8560_cpm_reset(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile ulong count;
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
@@ -50,11 +50,11 @@ m8560_cpm_reset(void)
/*
* Reset CPM
*/
- immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
+ cpm->im_cpm_cp.cpcr = CPM_CR_RST;
count = 0;
do { /* Spin until command processed */
__asm__ __volatile__ ("eieio");
- } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
+ } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
}
/* Allocate some memory from the dual ported ram.
@@ -64,7 +64,7 @@ m8560_cpm_reset(void)
uint
m8560_cpm_dpalloc(uint size, uint align)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint retloc;
uint align_mask, off;
uint savebase;
@@ -86,7 +86,7 @@ m8560_cpm_dpalloc(uint size, uint align)
retloc = gd->dp_alloc_base;
gd->dp_alloc_base += size;
- memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
+ memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
return(retloc);
}
@@ -120,16 +120,16 @@ m8560_cpm_hostalloc(uint size, uint align)
void
m8560_cpm_setbrg(uint brg, uint rate)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
@@ -142,16 +142,16 @@ m8560_cpm_setbrg(uint brg, uint rate)
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
@@ -167,14 +167,14 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16)
void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bbc5444..ac8b018 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -30,11 +30,6 @@
#include <command.h>
#include <asm/cache.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
-
int checkcpu (void)
{
sys_info_t sysinfo;
@@ -44,6 +39,8 @@ int checkcpu (void)
uint fam;
uint ver;
uint major, minor;
+ u32 ddr_ratio;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
svr = get_svr();
ver = SVR_VER(svr);
@@ -107,14 +104,25 @@ int checkcpu (void)
puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
- printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+ ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ switch (ddr_ratio) {
+ case 0x0:
+ printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
+ break;
+ case 0x7:
+ printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
+ break;
+ default:
+ printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
+ break;
+ }
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
lcrr = lbc->lcrr;
}
@@ -214,8 +222,7 @@ reset_85xx_watchdog(void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
@@ -225,8 +232,7 @@ void dma_init(void) {
}
uint dma_check(void) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
volatile uint status = dma->sr0;
/* While the channel is busy, spin */
@@ -245,8 +251,7 @@ uint dma_check(void) {
}
int dma_xfer(void *dest, uint count, void *src) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
dma->dar0 = (uint) dest;
dma->sar0 = (uint) src;
@@ -258,94 +263,3 @@ int dma_xfer(void *dest, uint count, void *src) {
return dma_check();
}
#endif
-
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_cpu_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- ulong clock;
- int len;
-
- clock = bd->bi_busfreq;
- p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
-#if defined(CONFIG_HAS_ETH0)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enetaddr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enetaddr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH1)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet1addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet1addr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH2)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
-#ifdef CONFIG_UEC_ETH
- p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
- p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
-#endif
-#endif
-
-#if defined(CONFIG_HAS_ETH3)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
-#ifdef CONFIG_UEC_ETH
- p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
- p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
-#endif
-#endif
-
-}
-#endif
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 79ad20c..fdb9ecb 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -59,7 +59,7 @@ static void config_qe_ioports(void)
#endif
#ifdef CONFIG_CPM2
-static void config_8560_ioports (volatile immap_t * immr)
+void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
int portnum;
@@ -99,7 +99,7 @@ static void config_8560_ioports (volatile immap_t * immr)
}
if (pmsk != 0) {
- volatile ioport_t *iop = ioport_addr (immr, portnum);
+ volatile ioport_t *iop = ioport_addr (cpm, portnum);
uint tpmsk = ~pmsk;
/*
@@ -131,8 +131,7 @@ static void config_8560_ioports (volatile immap_t * immr)
void cpu_init_f (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
@@ -143,7 +142,7 @@ void cpu_init_f (void)
#ifdef CONFIG_CPM2
- config_8560_ioports(immap);
+ config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
@@ -222,18 +221,15 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
-#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-#endif
#ifdef CONFIG_CLEAR_LAW0
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+ volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index 5b23a80..bd62aab 100644
--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -230,8 +230,8 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
{
struct ether_fcc_info_s * info = dev->priv;
int i;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
@@ -242,35 +242,35 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (1-2): ioports have been set up already */
/* 28.9 - (3): connect FCC's tx and rx clocks */
- immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
- immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
+ cpm->im_cpm_mux.cmxuar = 0; /* ATM */
+ cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
}
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 1){
- immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 2){
- immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
}
/* 28.9 - (6): FDSR: Ethernet Syn */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
+ cpm->im_cpm_fcc1.fdsr = 0xD555;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
+ cpm->im_cpm_fcc2.fdsr = 0xD555;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
+ cpm->im_cpm_fcc3.fdsr = 0xD555;
}
/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
@@ -296,7 +296,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* 28.9 - (7): initialize parameter ram */
- pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
+ pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
/* clear whole structure to make sure all reserved fields are zero */
memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
@@ -385,14 +385,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (8)(9): clear out events in FCCE */
/* 28.9 - (9): FCCM: mask all events */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc1.fccm = 0;
+ cpm->im_cpm_fcc1.fcce = ~0x0;
+ cpm->im_cpm_fcc1.fccm = 0;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc2.fccm = 0;
+ cpm->im_cpm_fcc2.fcce = ~0x0;
+ cpm->im_cpm_fcc2.fccm = 0;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc3.fccm = 0;
+ cpm->im_cpm_fcc3.fcce = ~0x0;
+ cpm->im_cpm_fcc3.fccm = 0;
}
/* 28.9 - (10-12): we don't use ethernet interrupts */
@@ -413,11 +413,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (14): enable tx/rx in gfmr */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
}
return 1;
@@ -426,15 +426,15 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
/* write GFMR: disable tx/rx */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
}
}
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
new file mode 100644
index 0000000..737a6c4
--- /dev/null
+++ b/cpu/mpc85xx/fdt.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+ fdt_fixup_ethernet(blob, bd);
+#endif
+
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "timebase-frequency", bd->bi_busfreq / 8, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+#ifdef CONFIG_QE
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CFG_NS16550
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CONFIG_CPM2
+ do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
+ "current-speed", bd->bi_baudrate, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
+ "clock-frequency", bd->bi_brgfreq, 1);
+#endif
+
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index bf737d6..18e5377 100644
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -80,19 +80,17 @@ int disable_interrupts (void)
int interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
- immr->im_pic.gcr = MPC85xx_PICGCR_RST;
- while (immr->im_pic.gcr & MPC85xx_PICGCR_RST);
- immr->im_pic.gcr = MPC85xx_PICGCR_M;
+ pic->gcr = MPC85xx_PICGCR_RST;
+ while (pic->gcr & MPC85xx_PICGCR_RST);
+ pic->gcr = MPC85xx_PICGCR_M;
decrementer_count = get_tbclk() / CFG_HZ;
mtspr(SPRN_TCR, TCR_PIE);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
- volatile ccsr_pic_t *pic = &immr->im_pic;
-
pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index db09e45..a5060cd 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -29,10 +29,6 @@
#include <asm/cpm_85xx.h>
#include <pci.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
#if defined(CONFIG_PCI)
static struct pci_controller *pci_hose;
@@ -43,12 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
u16 reg16;
u32 dev;
- volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
- volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+ volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
- volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
+ volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR);
#endif
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
struct pci_controller * hose;
pci_hose = board_hose;
@@ -216,27 +211,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
hose->last_busno = pci_hose_scan(hose);
#endif
}
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[0].first_busno;
- p[1] = pci_hose[0].last_busno;
- }
-
-#ifdef CONFIG_MPC85XX_PCI2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[1].first_busno;
- p[1] = pci_hose[1].last_busno;
- }
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c
index 8878bc5..98075bb 100644
--- a/cpu/mpc85xx/qe_io.c
+++ b/cpu/mpc85xx/qe_io.c
@@ -34,9 +34,9 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
- &(im->im_gur.qe_par_io);
+ &(gur->qe_par_io);
/* Caculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c
index 4e925f8..7ee3cc8 100644
--- a/cpu/mpc85xx/serial_scc.c
+++ b/cpu/mpc85xx/serial_scc.c
@@ -88,17 +88,17 @@ DECLARE_GLOBAL_DATA_PTR;
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
- volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
+ volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
uint dpaddr;
/* initialize pointers to SCC */
- sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+ sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
/* Disable transmitter/receiver.
*/
@@ -107,8 +107,8 @@ int serial_init (void)
/* put the SCC channel into NMSI (non multiplexd serial interface)
* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
*/
- im->im_cpm.im_cpm_mux.cmxscr = \
- (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
+ cpm->im_cpm_mux.cmxscr = \
+ (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
/* Set up the baud rate generator.
*/
@@ -123,7 +123,7 @@ int serial_init (void)
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
tbdf = rbdf + 1;
@@ -201,14 +201,13 @@ serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
if (c == '\n')
serial_putc ('\r');
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
/* Wait for last character to go.
*/
@@ -235,12 +234,11 @@ serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
/* Wait for character to show up.
*/
@@ -260,11 +258,10 @@ serial_tstc()
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 5dc223a..553f736 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -53,8 +53,8 @@ picos_to_clk(int picos)
{
int clks;
- clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
- if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
+ if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
clks++;
}
@@ -171,8 +171,7 @@ unsigned int determine_refresh_rate(unsigned int spd_refresh)
long int
spd_sdram(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
spd_eeprom_t spd;
unsigned int n_ranks;
unsigned int rank_density;
@@ -309,7 +308,7 @@ spd_sdram(void)
if ((SVR_VER(get_svr()) == SVR_8548_E) &&
(SVR_MJREV(get_svr()) == 1) &&
(spd.mem_type == SPD_MEMTYPE_DDR2)) {
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrioovcr = (0x80000000 /* Enable */
| 0x10000000);/* VSEL to 1.8V */
}
@@ -422,7 +421,7 @@ spd_sdram(void)
* Adjust the CAS Latency to allow for bus speeds that
* are slower than the DDR module.
*/
- busfreq = get_bus_freq(0) / 1000000; /* MHz */
+ busfreq = get_ddr_freq(0) / 1000000; /* MHz */
effective_data_rate = max_data_rate;
if (busfreq < 90) {
@@ -1023,8 +1022,7 @@ spd_sdram(void)
static unsigned int
setup_laws_and_tlbs(unsigned int memsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
unsigned int tlb_size;
unsigned int law_size;
unsigned int ram_tlb_index;
@@ -1130,8 +1128,7 @@ ddr_enable_ecc(unsigned int dram_size)
{
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 12359a2..27de37a 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -35,8 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -49,6 +48,15 @@ void get_sys_info (sys_info_t * sysInfo)
* overflow for processor speeds above 2GHz */
half_freqSystemBus = sysInfo->freqSystemBus/2;
sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+
+#ifdef CONFIG_DDR_CLK_FREQ
+ {
+ u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ if (ddr_ratio != 0x7)
+ sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ }
+#endif
}
@@ -56,12 +64,12 @@ int get_clocks (void)
{
sys_info_t sys_info;
#if defined(CONFIG_CPM2)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
- immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
- sccr = immap->im_cpm.im_cpm_intctl.sccr;
+ cpm->im_cpm_intctl.sccr &= 0xfffffffc;
+ sccr = cpm->im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
@@ -94,3 +102,19 @@ ulong get_bus_freq (ulong dummy)
return val;
}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq (ulong dummy)
+{
+ ulong val;
+
+ sys_info_t sys_info;
+
+ get_sys_info (&sys_info);
+ val = sys_info.freqDDRBus;
+
+ return val;
+}
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index efc80c7..2381fb0 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -288,8 +288,8 @@ UnknownException(struct pt_regs *regs)
void
ExtIntException(struct pt_regs *regs)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_pic_t *pic = &immap->im_pic;
+ volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+
uint vect;
#if defined(CONFIG_CMD_KGDB)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 1e77884..68e45e1 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -112,6 +112,29 @@ fsl_pci_init(struct pci_controller *hose)
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
enabled = ltssm >= PCI_LTSSM_L0;
+#ifdef CONFIG_FSL_PCIE_RESET
+ if (ltssm == 1) {
+ int i;
+ debug("....PCIe link error. "
+ "LTSSM=0x%02x.", ltssm);
+ pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
+ temp32 = pci->pdb_stat;
+ udelay(100);
+ debug(" Asserting PCIe reset @%x = %x\n",
+ &pci->pdb_stat, pci->pdb_stat);
+ pci->pdb_stat &= ~0x08000000; /* clear reset */
+ asm("sync;isync");
+ for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ &ltssm);
+ udelay(1000);
+ debug("....PCIe link error. "
+ "LTSSM=0x%02x.\n", ltssm);
+ }
+ enabled = ltssm >= PCI_LTSSM_L0;
+ }
+#endif
+
if (!enabled) {
debug("....PCIE link error. Skipping scan."
"LTSSM=0x%02x\n", ltssm);
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 496fc72..d769d70 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -720,11 +720,10 @@ typedef struct ccsr_tsec {
} ccsr_tsec_t;
/*
- * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ * PIC Registers(0x4_0000-0x8_0000)
*/
typedef struct ccsr_pic {
- char res0[106496]; /* 0x26000-0x40000 */
- char res1[64];
+ char res1[64]; /* 0x40000 */
uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
char res2[12];
uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
@@ -1619,25 +1618,25 @@ typedef struct ccsr_gur {
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
-typedef struct immap {
- ccsr_local_ecm_t im_local_ecm;
- ccsr_ddr_t im_ddr;
- ccsr_i2c_t im_i2c;
- ccsr_duart_t im_duart;
- ccsr_lbc_t im_lbc;
- ccsr_pcix_t im_pcix;
- ccsr_pcix_t im_pcix2;
- char reserved[90112];
- ccsr_l2cache_t im_l2cache;
- ccsr_dma_t im_dma;
- ccsr_tsec_t im_tsec1;
- ccsr_tsec_t im_tsec2;
- ccsr_pic_t im_pic;
- ccsr_cpm_t im_cpm;
- ccsr_rio_t im_rio;
- ccsr_gur_t im_gur;
-} immap_t;
-
-extern immap_t *immr;
+#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
+#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
+#define CFG_MPC85xx_ECM_OFFSET (0x0000)
+#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
+#define CFG_MPC85xx_DDR_OFFSET (0x2000)
+#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_LBC_OFFSET (0x5000)
+#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
+#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
+#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
+#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
+#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_L2_OFFSET (0x20000)
+#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
+#define CFG_MPC85xx_DMA_OFFSET (0x21000)
+#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_PIC_OFFSET (0x40000)
+#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
+#define CFG_MPC85xx_CPM_OFFSET (0x80000)
+#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
#endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h
index bd732b6..6715064 100644
--- a/include/asm-ppc/immap_fsl_pci.h
+++ b/include/asm-ppc/immap_fsl_pci.h
@@ -144,7 +144,9 @@ typedef struct ccsr_pci {
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
- char res23[456]; /* (- #x1000 #xe38) 456 */
+ char res23[200];
+ u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
+ char res24[252];
} ccsr_fsl_pci_t;
#endif /*__IMMAP_fsl_pci__*/
diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h
index f854df6..daddb55 100644
--- a/include/asm-ppc/iopin_85xx.h
+++ b/include/asm-ppc/iopin_85xx.h
@@ -23,121 +23,121 @@ typedef struct {
extern __inline__ void iopin_set_high (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_low (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_high (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_low (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_out (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_in (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_out (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_in (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_odr (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_act (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_odr (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_act (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_ded (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_gen (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_ded (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_gen (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index b3cfa9b..3d40332 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
-#define LAWAR_TRGT_IF_PEX 0x00200000
+#define LAWAR_TRGT_IF_PCIE1 0x00200000
+#define LAWAR_TRGT_IF_PCIE2 0x00100000
+#define LAWAR_TRGT_IF_PCIE3 0x00300000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
diff --git a/include/common.h b/include/common.h
index 63ac8b0..01957e3 100644
--- a/include/common.h
+++ b/include/common.h
@@ -497,6 +497,7 @@ ulong get_bus_freq (ulong);
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
+ulong get_ddr_freq (ulong);
#endif
#if defined(CONFIG_MPC86xx)
typedef MPC86xx_SYS_INFO sys_info_t;
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index be603ac..35e1d63 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -298,13 +298,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8540@0"
-#define OF_SOC "soc8540@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
@@ -424,6 +420,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -441,6 +438,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 8dda665..d2e7237 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8541@0"
-#define OF_SOC "soc8541@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
-#define OF_PCI "pci@e0008000"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -422,6 +417,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -434,6 +430,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 13e2a2c..545a76c 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -40,6 +40,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -251,13 +252,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8544@0"
-#define OF_SOC "soc8544@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
@@ -410,6 +407,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -426,6 +424,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
@@ -475,10 +474,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.251
@@ -488,8 +483,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_BOOTFILE 8544ds/uImage.uboot
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
-#define CONFIG_SERVERIP 192.168.0.1
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
@@ -499,65 +494,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
- "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcieerr=md ${a}020 1; md ${a}e00 e;" \
- "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1;" \
- "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \
- "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
- "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
- "pci w $b.0 130 ffffffff\0" \
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcie3regs=setenv a e000b; run pciereg\0" \
- "pcie1cfg=setenv b 3; run pciecfg\0" \
- "pcie2cfg=setenv b 5; run pciecfg\0" \
- "pcie3cfg=setenv b 0; run pciecfg\0" \
- "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
- "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
- "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
- "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
- "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
-#else
-#define PCIE_ENV ""
-#endif
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
- "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
-#else
-#define PCI_ENV ""
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-#define ENET_ENV \
- "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
- "md ${a}098 2\0" \
- "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
- "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
- "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
- "echo mib;md ${a}680 31\0" \
- "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
- "enet1regs=setenv a e0024; run enetreg\0" \
- "enet3regs=setenv a e0026; run enetreg\0"
-#else
-#define ENET_ENV ""
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
@@ -570,29 +506,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8544ds/ramdisk.uboot\0" \
- "dtbaddr=c00000\0" \
- "dtbfile=8544ds/mpc8544ds.dtb\0" \
- "bdev=sda3\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
- "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
- PCIE_ENV \
- PCI_ENV \
- ENET_ENV
-
+ "fdtaddr=c00000\0" \
+ "fdtfile=8544ds/mpc8544ds.dtb\0" \
+ "bdev=sda3\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -600,23 +516,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
-
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr $ramdiskaddr $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4edc7fd..3f382e5 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -42,6 +42,7 @@
#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -333,14 +334,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8548@0"
-#define OF_SOC "soc8548@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
-#define OF_PCI "pci@e0008000"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -483,6 +479,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -495,6 +492,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
@@ -568,72 +566,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_PCIE1)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
- "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
- "pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
- "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie1cfg=setenv b 3; run pciecfg\0" \
- "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
- "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
-#else
-#define PCIE_ENV ""
-#endif
-
-#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
-#else
-#define PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV1 \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
- "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
-#else
-#define PCI_ENV1 ""
-#endif
-
-#if defined(CONFIG_PCI2)
-#define PCI_ENV2 \
- "pci2regs=setenv a e0009; run pcireg\0" \
- "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
- "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
-#else
-#define PCI_ENV2 ""
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-#define ENET_ENV \
- "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
- "md ${a}098 2\0" \
- "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
- "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
- "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
- "echo mib;md ${a}680 31\0" \
- "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
- "enet1regs=setenv a e0024; run enetreg\0" \
- "enet2regs=setenv a e0025; run enetreg\0" \
- "enet3regs=setenv a e0026; run enetreg\0" \
- "enet4regs=setenv a e0027; run enetreg\0"
-#else
-#define ENET_ENV ""
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
@@ -647,28 +579,7 @@ extern unsigned long get_clock_freq(void);
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
- "fdtfile=mpc8548cds.dtb\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
- "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
- PCIE_ENV \
- PCI_ENV \
- PCI_ENV1 \
- PCI_ENV2 \
- ENET_ENV
+ "fdtfile=mpc8548cds.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index c414bf0..90ef3d6 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8555@0"
-#define OF_SOC "soc8555@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
-#define OF_PCI "pci@e0008000"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -422,6 +417,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -434,6 +430,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index a8f362f..d4e0de0 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -289,13 +289,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8560@0"
-#define OF_SOC "soc8560@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -450,6 +446,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -471,6 +468,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
@@ -525,6 +523,8 @@
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index b9366cc..59f490e 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -33,7 +33,11 @@
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-#define CONFIG_PCI
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller */
+#define CONFIG_PCIE1 1 /* PCIE controller */
+#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
@@ -87,6 +91,9 @@ extern unsigned long get_clock_freq(void);
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
/*
* DDR Setup
*/
@@ -290,14 +297,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8568@0"
-#define OF_SOC "soc8568@e0000000"
-#define OF_QE "qe@e0080000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -325,12 +327,12 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
-#define CFG_PEX_MEM_BASE 0xa0000000
-#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
-#define CFG_PEX_IO_BASE 0x00000000
-#define CFG_PEX_IO_PHYS 0xe2800000
-#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe2800000
+#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */
#define CFG_SRIO_MEM_BASE 0xc0000000
@@ -383,6 +385,11 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
@@ -440,6 +447,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -452,6 +460,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/e500.h b/include/e500.h
index 8e3bf8c..0d73260 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -12,6 +12,7 @@ typedef struct
{
unsigned long freqProcessor;
unsigned long freqSystemBus;
+ unsigned long freqDDRBus;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
diff --git a/include/ioports.h b/include/ioports.h
index cfba667..1134ea5 100644
--- a/include/ioports.h
+++ b/include/ioports.h
@@ -26,7 +26,7 @@ typedef struct {
* a 0x20 byte boundary
*/
#ifdef CONFIG_MPC85xx
-#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
#else
#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
#endif