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-rw-r--r--CREDITS5
-rw-r--r--MAINTAINERS7
-rwxr-xr-xMAKEALL4
-rw-r--r--Makefile12
-rw-r--r--board/amcc/bamboo/bamboo.c321
-rw-r--r--board/amcc/bamboo/init.S3
-rw-r--r--board/amcc/bamboo/u-boot.lds2
-rw-r--r--board/amcc/bubinga/bubinga.c13
-rw-r--r--board/amcc/common/flash.c18
-rw-r--r--board/amcc/luan/luan.c7
-rw-r--r--board/amcc/taihu/Makefile49
-rw-r--r--board/amcc/taihu/config.mk24
-rw-r--r--board/amcc/taihu/flash.c1083
-rw-r--r--board/amcc/taihu/lcd.c257
-rw-r--r--board/amcc/taihu/taihu.c240
-rw-r--r--board/amcc/taihu/u-boot.lds150
-rw-r--r--board/amcc/taihu/update.c132
-rw-r--r--board/amcc/yucca/yucca.c34
-rw-r--r--board/esd/plu405/fpgadata.c2339
-rw-r--r--board/lwmon5/lwmon5.c89
-rw-r--r--board/lwmon5/sdram.c38
-rw-r--r--board/netstal/common/flash.c528
-rw-r--r--board/netstal/common/nm_bsp.c41
-rw-r--r--board/netstal/hcu4/Makefile49
-rw-r--r--board/netstal/hcu4/README.txt59
-rw-r--r--board/netstal/hcu4/config.mk28
-rw-r--r--board/netstal/hcu4/hcu4.c400
-rw-r--r--board/netstal/hcu4/u-boot.lds140
-rw-r--r--board/netstal/hcu5/Makefile49
-rw-r--r--board/netstal/hcu5/README.txt174
-rw-r--r--board/netstal/hcu5/config.mk30
-rw-r--r--board/netstal/hcu5/hcu5.c525
-rw-r--r--board/netstal/hcu5/init.S79
-rw-r--r--board/netstal/hcu5/sdram.c302
-rw-r--r--board/netstal/hcu5/u-boot.lds144
-rw-r--r--board/zeus/Makefile51
-rw-r--r--board/zeus/config.mk24
-rw-r--r--board/zeus/u-boot.lds133
-rw-r--r--board/zeus/update.c105
-rw-r--r--board/zeus/zeus.c511
-rw-r--r--common/flash.c10
-rw-r--r--common/soft_spi.c2
-rw-r--r--cpu/ppc4xx/440spe_pcie.c47
-rw-r--r--cpu/ppc4xx/440spe_pcie.h19
-rw-r--r--cpu/ppc4xx/44x_spd_ddr.c3
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c58
-rw-r--r--cpu/ppc4xx/4xx_enet.c8
-rw-r--r--cpu/ppc4xx/gpio.c6
-rw-r--r--cpu/ppc4xx/sdram.c32
-rw-r--r--cpu/ppc4xx/sdram.h2
-rw-r--r--cpu/ppc4xx/serial.c9
-rw-r--r--cpu/ppc4xx/speed.c33
-rw-r--r--cpu/ppc4xx/start.S61
-rw-r--r--cpu/ppc4xx/tlb.c62
-rw-r--r--cpu/ppc4xx/traps.c49
-rw-r--r--cpu/ppc4xx/usb.c6
-rw-r--r--doc/README.bamboo62
-rw-r--r--doc/README.zeus73
-rw-r--r--dtt/Makefile2
-rw-r--r--dtt/ds1775.c156
-rw-r--r--include/asm-ppc/mmu.h3
-rw-r--r--include/configs/bamboo.h2
-rw-r--r--include/configs/hcu4.h348
-rw-r--r--include/configs/hcu5.h393
-rw-r--r--include/configs/luan.h5
-rw-r--r--include/configs/lwmon5.h56
-rw-r--r--include/configs/taihu.h476
-rw-r--r--include/configs/zeus.h382
-rw-r--r--include/dtt.h8
-rw-r--r--include/post.h1
-rw-r--r--include/ppc405.h16
-rw-r--r--include/ppc440.h13
-rw-r--r--lib_ppc/extable.c2
-rw-r--r--post/board/lwmon5/Makefile29
-rw-r--r--post/board/lwmon5/ecc.c267
-rw-r--r--post/cpu/ppc4xx/cache.c16
-rw-r--r--post/cpu/ppc4xx/cache_4xx.S44
-rw-r--r--post/cpu/ppc4xx/ether.c9
-rw-r--r--post/cpu/ppc4xx/fpu.c2
-rw-r--r--post/cpu/ppc4xx/uart.c176
-rw-r--r--post/tests.c13
81 files changed, 9729 insertions, 1431 deletions
diff --git a/CREDITS b/CREDITS
index 4c8b896..b08305b 100644
--- a/CREDITS
+++ b/CREDITS
@@ -160,6 +160,11 @@ N: Thomas Frieden
E: ThomasF@hyperion-entertainment.com
D: Support for AmigaOne
+N: Niklaus Giger
+E: niklaus.giger@netstal.com
+D: Support for HCU(x) boards
+W: www.netstal.com
+
N: Paul Gortmaker
E: paul.gortmaker@windriver.com
D: Support for WRS SBC8347/8349 boards
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b17739..f812431 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -160,6 +160,11 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
WUH405 PPC405EP
CMS700 PPC405EP
+Niklaus Giger <niklaus.giger@netstal.com>
+
+ HCU4 PPC405GPr
+ HCU5 PPC440EPx
+
Frank Gottschling <fgottschling@eltec.de>
MHPC MPC8xx
@@ -252,6 +257,7 @@ Tolunay Orkun <torkun@nextio.com>
John Otken <jotken@softadvances.com>
luan PPC440SP
+ taihu PPC405EP
Keith Outwater <Keith_Outwater@mvis.com>
@@ -296,6 +302,7 @@ Stefan Roese <sr@denx.de>
walnut PPC405GP
yellowstone PPC440GR
yosemite PPC440EP
+ zeus PPC405EP
P3M750 PPC750FX/GX/GL
diff --git a/MAKEALL b/MAKEALL
index 7fb10b3..1219fb3 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -180,6 +180,8 @@ LIST_4xx=" \
ERIC \
EXBITGEN \
G2000 \
+ hcu4 \
+ hcu5 \
HH405 \
HUB405 \
JSE \
@@ -206,6 +208,7 @@ LIST_4xx=" \
sc3 \
sequoia \
sequoia_nand \
+ taihu \
taishan \
VOH405 \
VOM405 \
@@ -217,6 +220,7 @@ LIST_4xx=" \
yellowstone \
yosemite \
yucca \
+ zeus \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 95e9e36..9dee948 100644
--- a/Makefile
+++ b/Makefile
@@ -1142,6 +1142,12 @@ EXBITGEN_config: unconfig
G2000_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
+hcu4_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
+
+hcu5_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
+
HH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
@@ -1261,6 +1267,9 @@ rainier_nand_config: unconfig
sc3_config:unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
+taihu_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
+
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
@@ -1298,6 +1307,9 @@ yellowstone_config: unconfig
yucca_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
+zeus_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
+
#########################################################################
## MPC8220 Systems
#########################################################################
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index caf6690..00c793a 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
-unsigned char cfg_simulate_spd_eeprom[128];
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+/*************************************************************************
+ *
+ * Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ * 13 row add bits, 10 column add bits (but 12 row used only).
+ * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ * 12 row add bits, 10 column add bits.
+ * Prepare a subset (only the used ones) of SPD data
+ *
+ * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ * the corresponding bank is divided by 2 due to number of Row addresses
+ * 12 in the ECC module
+ *
+ * Assumes: 64 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+const unsigned char cfg_simulate_spd_eeprom[128] = {
+ 0x80, /* number of SPD bytes used: 128 */
+ 0x08, /* total number bytes in SPD device = 256 */
+ 0x07, /* DDR ram */
+#ifdef CONFIG_DDR_ECC
+ 0x0C, /* num Row Addr: 12 */
+#else
+ 0x0D, /* num Row Addr: 13 */
+#endif
+ 0x09, /* numColAddr: 9 */
+ 0x01, /* numBanks: 1 */
+ 0x20, /* Module data width: 32 bits */
+ 0x00, /* Module data width continued: +0 */
+ 0x04, /* 2.5 Volt */
+ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+#ifdef CONFIG_DDR_ECC
+ 0x02, /* ECC ON : 02 OFF : 00 */
+#else
+ 0x00, /* ECC ON : 02 OFF : 00 */
+#endif
+ 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */
+ 0,
+ 0,
+ 0,
+ 0x01, /* wcsbc = 1 */
+ 0,
+ 0,
+ 0x0C, /* casBit (2,2.5) */
+ 0,
+ 0,
+ 0x00, /* not registered: 0 registered : 0x02*/
+ 0,
+ 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+ 0,
+ 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+ 0,
+ 0x50, /* tRpNs = 20 ns */
+ 0,
+ 0x50, /* tRcdNs = 20 ns */
+ 45, /* tRasNs */
+#ifdef CONFIG_DDR_ECC
+ 0x08, /* bankSizeID: 32MB */
+#else
+ 0x10, /* bankSizeID: 64MB */
+#endif
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+#endif
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
{
@@ -291,73 +452,12 @@ int checkboard(void)
return (0);
}
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
-/*************************************************************************
- *
- * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- * 13 row add bits, 10 column add bits (but 12 row used only).
- * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- * 12 row add bits, 10 column add bits.
- * Prepare a subset (only the used ones) of SPD data
- *
- * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- * the corresponding bank is divided by 2 due to number of Row addresses
- * 12 in the ECC module
- *
- * Assumes: 64 MB, ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-static void init_spd_array(void)
-{
- cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
- cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
-
-#ifdef CONFIG_DDR_ECC
- cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
- cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
- cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
-#else
- cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
- cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
- cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
-#endif
-
- cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
- cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
- cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
- cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
- cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
- cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
- cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
- cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
- cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
- cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
-
- cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
-
- cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
-
- cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
- cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
- cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
- cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
-}
-#endif
long int initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
- /*
- * First write simulated values in eeprom array for onboard bank 0
- */
- init_spd_array();
-
dram_size = spd_sdram();
return dram_size;
@@ -371,11 +471,12 @@ int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
- unsigned long k, n;
+ unsigned long k, n, *p32, ctr;
+ const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
mtmsr(0);
- for (k = 0; k < CFG_KBYTES_SDRAM;
+ for (k = 0; k < CFG_MBYTES_SDRAM*1024;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
@@ -399,6 +500,34 @@ int testdram(void)
}
}
}
+
+ /*
+ * Perform a sequence test to ensure that all
+ * memory locations are uniquely addressable
+ */
+ ctr = 0;
+ p32 = 0;
+ while ((unsigned long)p32 != bend) {
+ if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+ printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
+ *p32++ = ctr++;
+ }
+
+ ctr = 0;
+ p32 = 0;
+ while ((unsigned long)p32 != bend) {
+ if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+ printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
+
+ if (*p32 != ctr) {
+ printf("SDRAM test fails at: %08x\n", p32);
+ return 1;
+ }
+
+ ctr++;
+ p32++;
+ }
+
printf("SDRAM test passes\n");
return 0;
}
@@ -1211,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config)
/*----------------------------------------------------------------------------+
| init_default_gpio
+----------------------------------------------------------------------------*/
-void init_default_gpio(void)
+void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
int i;
@@ -1281,7 +1410,7 @@ void init_default_gpio(void)
|
+----------------------------------------------------------------------------*/
-void update_uart_ios(uart_config_nb_t uart_config)
+void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
{
switch (uart_config)
{
@@ -1409,7 +1538,7 @@ void update_uart_ios(uart_config_nb_t uart_config)
/*----------------------------------------------------------------------------+
| update_ndfc_ios(void).
+----------------------------------------------------------------------------*/
-void update_ndfc_ios(void)
+void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
/* Update GPIO Configuration Table */
gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
@@ -1427,7 +1556,7 @@ void update_ndfc_ios(void)
/*----------------------------------------------------------------------------+
| update_zii_ios(void).
+----------------------------------------------------------------------------*/
-void update_zii_ios(void)
+void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
/* Update GPIO Configuration Table */
gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
@@ -1477,7 +1606,7 @@ void update_zii_ios(void)
/*----------------------------------------------------------------------------+
| update_uic_0_3_irq_ios().
+----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(void)
+void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
@@ -1495,7 +1624,7 @@ void update_uic_0_3_irq_ios(void)
/*----------------------------------------------------------------------------+
| update_uic_4_9_irq_ios().
+----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(void)
+void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
@@ -1516,7 +1645,7 @@ void update_uic_4_9_irq_ios(void)
/*----------------------------------------------------------------------------+
| update_dma_a_b_ios().
+----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(void)
+void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
@@ -1537,7 +1666,7 @@ void update_dma_a_b_ios(void)
/*----------------------------------------------------------------------------+
| update_dma_c_d_ios().
+----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(void)
+void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
@@ -1562,7 +1691,7 @@ void update_dma_c_d_ios(void)
/*----------------------------------------------------------------------------+
| update_ebc_master_ios().
+----------------------------------------------------------------------------*/
-void update_ebc_master_ios(void)
+void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
@@ -1580,7 +1709,7 @@ void update_ebc_master_ios(void)
/*----------------------------------------------------------------------------+
| update_usb2_device_ios().
+----------------------------------------------------------------------------*/
-void update_usb2_device_ios(void)
+void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
@@ -1611,20 +1740,21 @@ void update_usb2_device_ios(void)
/*----------------------------------------------------------------------------+
| update_pci_patch_ios().
+----------------------------------------------------------------------------*/
-void update_pci_patch_ios(void)
+void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
{
gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
}
/*----------------------------------------------------------------------------+
- | set_chip_gpio_configuration(unsigned char gpio_core)
+ | set_chip_gpio_configuration(unsigned char gpio_core,
+ | gpio_param_s (*gpio_tab)[GPIO_MAX])
| Put the core impacted by clock modification and sharing in reset.
| Config the select registers to resolve the sharing depending of the config.
| Configure the GPIO registers.
|
+----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core)
+void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
{
unsigned char i=0, j=0, reg_offset = 0;
unsigned long gpio_reg, gpio_core_add;
@@ -1778,11 +1908,12 @@ void configure_ppc440ep_pins(void)
CORE_NOT_SELECTED /* PCI_PATCH */
};
+ gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
/* Table Default Initialisation + FPGA Access */
- init_default_gpio();
- set_chip_gpio_configuration(GPIO0);
- set_chip_gpio_configuration(GPIO1);
+ init_default_gpio(gpio_tab);
+ set_chip_gpio_configuration(GPIO0, gpio_tab);
+ set_chip_gpio_configuration(GPIO1, gpio_tab);
/* Update Table */
force_bup_core_selection(ppc440ep_core_selection, &config_val);
@@ -1817,7 +1948,7 @@ void configure_ppc440ep_pins(void)
/* UIC 0:3 Selection */
if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
{
- update_uic_0_3_irq_ios();
+ update_uic_0_3_irq_ios(gpio_tab);
dma_a_b_unselect_in_fpga();
}
@@ -1825,21 +1956,21 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
- update_uic_4_9_irq_ios();
+ update_uic_4_9_irq_ios(gpio_tab);
}
/* DMA AB Selection */
if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
- update_dma_a_b_ios();
+ update_dma_a_b_ios(gpio_tab);
dma_a_b_selection_in_fpga();
}
/* DMA CD Selection */
if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
{
- update_dma_c_d_ios();
+ update_dma_c_d_ios(gpio_tab);
dma_c_d_selection_in_fpga();
}
@@ -1848,14 +1979,14 @@ void configure_ppc440ep_pins(void)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_ebc_master_ios();
+ update_ebc_master_ios(gpio_tab);
}
/* PCI Patch Enable */
if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
{
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_pci_patch_ios();
+ update_pci_patch_ios(gpio_tab);
}
/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
@@ -1871,7 +2002,7 @@ void configure_ppc440ep_pins(void)
/* USB2.0 Device Selection */
if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
{
- update_usb2_device_ios();
+ update_usb2_device_ios(gpio_tab);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
@@ -1904,7 +2035,7 @@ void configure_ppc440ep_pins(void)
/* NAND Flash Selection */
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
- update_ndfc_ios();
+ update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
@@ -1933,7 +2064,7 @@ void configure_ppc440ep_pins(void)
/* MII Selection */
if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
{
- update_zii_ios();
+ update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
mtsdr(sdr_mfr, sdr0_mfr);
@@ -1944,7 +2075,7 @@ void configure_ppc440ep_pins(void)
/* RMII Selection */
if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
{
- update_zii_ios();
+ update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
mtsdr(sdr_mfr, sdr0_mfr);
@@ -1955,7 +2086,7 @@ void configure_ppc440ep_pins(void)
/* SMII Selection */
if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
{
- update_zii_ios();
+ update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
mtsdr(sdr_mfr, sdr0_mfr);
@@ -1992,7 +2123,7 @@ void configure_ppc440ep_pins(void)
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
break;
}
- update_uart_ios(uart_configuration);
+ update_uart_ios(uart_configuration, gpio_tab);
/* UART Selection in all cases */
uart_selection_in_fpga(uart_configuration);
@@ -2014,8 +2145,8 @@ void configure_ppc440ep_pins(void)
/* Perform effective access to hardware */
mtsdr(sdr_pfc1, sdr0_pfc1);
- set_chip_gpio_configuration(GPIO0);
- set_chip_gpio_configuration(GPIO1);
+ set_chip_gpio_configuration(GPIO0, gpio_tab);
+ set_chip_gpio_configuration(GPIO1, gpio_tab);
/* USB2.0 Device Reset must be done after GPIO setting */
if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 1459eec..f4d2ae3 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -51,13 +51,12 @@ tlbtab:
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#else
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-
/* PCI base & peripherals */
tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index f6d7183..0375618 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -141,8 +141,6 @@ SECTIONS
*(COMMON)
}
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
_end = . ;
PROVIDE (end = .);
}
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index fe6ce8a..66e7509 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -20,10 +20,12 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-long int spd_sdram(void);
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
+
+long int spd_sdram(void);
int board_early_init_f(void)
{
@@ -34,6 +36,15 @@ int board_early_init_f(void)
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter if selected
+ */
+ if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
+ mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+ else
+ mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
+
return 0;
}
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index e6429ec..eba0511 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
+ info->start[1] = base + 0x00002000;
+ info->start[2] = base + 0x00004000;
+ info->start[3] = base + 0x00006000;
+ info->start[4] = base + 0x00008000;
+ info->start[5] = base + 0x0000a000;
+ info->start[6] = base + 0x0000c000;
+ info->start[7] = base + 0x0000e000;
+ for (i = 8; i < info->sector_count; i++) {
info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
+ base + ((i-7) * 0x00010000);
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 2eff3b3..7b16f8a 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -104,6 +104,13 @@ int checkboard(void)
return 0;
}
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
/*************************************************************************
* int testdram()
diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile
new file mode 100644
index 0000000..9731c6e
--- /dev/null
+++ b/board/amcc/taihu/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o flash.o lcd.o update.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/taihu/config.mk b/board/amcc/taihu/config.mk
new file mode 100644
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/amcc/taihu/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c
new file mode 100644
index 0000000..290259e
--- /dev/null
+++ b/board/amcc/taihu/flash.c
@@ -0,0 +1,1083 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define CFG_FLASH_CHAR_SIZE unsigned char
+#define CFG_FLASH_CHAR_ADDR0 (0x0aaa)
+#define CFG_FLASH_CHAR_ADDR1 (0x0555)
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef FLASH_BASE1_PRELIM
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1=0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ if (size_b0) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+ /* Also protect sector containing initial power-up instruction */
+ /* (flash_protect() checks address range - other call ignored) */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+ }
+#ifdef FLASH_BASE1_PRELIM
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2;
+
+ if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+ size_b1, size_b1 << 20);
+ }
+
+ if (size_b1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
+ flash_info[1].size = size_b1;
+ }
+#endif
+ return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000*2);
+ }
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000*2);
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
+
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMLV128U:
+ printf("AM29LV128U (128 Mbit * 2, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_S29GL128N:
+ printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef FLASH_BASE1_PRELIM
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ if ((ulong)addr == FLASH_BASE1_PRELIM) {
+ return flash_get_size_2(addr, info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return 0; /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ }
+ else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000 * 2);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return info->size;
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return 0;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef FLASH_BASE1_PRELIM
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return 2;
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ CFG_FLASH_CHAR_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ udelay(1000);
+
+ value = (CFG_FLASH_CHAR_SIZE)addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return 0; /* no or unknown flash */
+ }
+
+ value = (CFG_FLASH_CHAR_SIZE)addr2[2]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
+ if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
+ && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
+ info->flash_id += FLASH_AMLV128U;
+ info->sector_count = 256;
+ info->size = 0x01000000;
+ } else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
+ && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
+ info->flash_id += FLASH_S29GL128N;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ }
+ else
+ info->flash_id = FLASH_UNKNOWN;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00020000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0;
+ return info->size;
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
+ (CFG_FLASH_WORD_SIZE) 0x80808080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
+ addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return 2;
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#endif /* FLASH_BASE1_PRELIM */
diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c
new file mode 100644
index 0000000..3d042df
--- /dev/null
+++ b/board/amcc/taihu/lcd.c
@@ -0,0 +1,257 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define LCD_CMD_ADDR 0x50100002
+#define LCD_DATA_ADDR 0x50100003
+#define LCD_BLK_CTRL CPLD_REG1_ADDR
+
+static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
+static int addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+ out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
+}
+
+static void lcd_putc(int val)
+{
+ int i = 100;
+ char addr;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ addr = in_8((u8 *) LCD_CMD_ADDR);
+ udelay(50);
+ if ((addr != 0) && (addr % 0x10 == 0)) {
+ addr_flag ^= 0x40;
+ out_8((u8 *) LCD_CMD_ADDR, addr_flag);
+ }
+
+ udelay(50);
+ out_8((u8 *) LCD_DATA_ADDR, val);
+ udelay(50);
+}
+
+static void lcd_puts(char *s)
+{
+ char *p = s;
+ int i = 100;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ while (*p)
+ lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+ int i = 100;
+ char *p = amcc_logo;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ while (*p)
+ lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+ puts("LCD: ");
+ out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
+ udelay(50);
+ out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
+ udelay(50);
+ out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
+ udelay(2000);
+ out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
+ udelay(50);
+ lcd_bl_ctrl(0x02); /* set backlight on */
+ lcd_put_logo();
+ puts("ready\n");
+
+ return 0;
+}
+
+static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ out_8((u8 *) LCD_CMD_ADDR, 0x01);
+ udelay(2000);
+
+ return 0;
+}
+
+static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc < 2) {
+ printf("%s", cmdtp->usage);
+ return 1;
+ }
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
+static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc < 2) {
+ printf("%s", cmdtp->usage);
+ return 1;
+ }
+ lcd_putc((char)argv[1][0]);
+
+ return 0;
+}
+
+static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ ulong count;
+ ulong dir;
+ char cur_addr;
+
+ if (argc < 3) {
+ printf("%s", cmdtp->usage);
+ return 1;
+ }
+
+ count = simple_strtoul(argv[1], NULL, 16);
+ if (count > 31) {
+ printf("unable to shift > 0x20\n");
+ count = 0;
+ }
+
+ dir = simple_strtoul(argv[2], NULL, 16);
+ cur_addr = in_8((u8 *) LCD_CMD_ADDR);
+ udelay(50);
+
+ if (dir == 0x0) {
+ if (addr_flag == 0x80) {
+ if (count >= (cur_addr & 0xf)) {
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ udelay(50);
+ count = 0;
+ }
+ } else {
+ if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ addr_flag = 0x80;
+ udelay(50);
+ count = 0x0;
+ } else if (count >= ( cur_addr & 0xf)) {
+ count -= cur_addr & 0xf ;
+ out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
+ addr_flag = 0x80;
+ udelay(50);
+ }
+ }
+ } else {
+ if (addr_flag == 0x80) {
+ if (count >= (0x1f - (cur_addr & 0xf))) {
+ count = 0x0;
+ addr_flag = 0xc0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
+ udelay(50);
+ } else if ((count + (cur_addr & 0xf ))>= 0x0f) {
+ count = count + (cur_addr & 0xf) - 0x0f;
+ addr_flag = 0xc0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xc0);
+ udelay(50);
+ }
+ } else if ((count + (cur_addr & 0xf )) >= 0x0f) {
+ count = 0x0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
+ udelay(50);
+ }
+ }
+ while (count--) {
+ if (dir == 0)
+ out_8((u8 *) LCD_CMD_ADDR, 0x10);
+ else
+ out_8((u8 *) LCD_CMD_ADDR, 0x14);
+ udelay(50);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lcd_cls, 1, 1, do_lcd_clear,
+ "lcd_cls - lcd clear display\n",
+ NULL
+ );
+
+U_BOOT_CMD(
+ lcd_puts, 2, 1, do_lcd_puts,
+ "lcd_puts - display string on lcd\n",
+ "<string> - <string> to be displayed\n"
+ );
+
+U_BOOT_CMD(
+ lcd_putc, 2, 1, do_lcd_putc,
+ "lcd_putc - display char on lcd\n",
+ "<char> - <char> to be displayed\n"
+ );
+
+U_BOOT_CMD(
+ lcd_cur, 3, 1, do_lcd_cur,
+ "lcd_cur - shift cursor on lcd\n",
+ "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
+ " <count> - 0..31\n"
+ " <dir> - 0=backward 1=forward\n"
+ );
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
new file mode 100644
index 0000000..ea83671
--- /dev/null
+++ b/board/amcc/taihu/taihu.c
@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <asm/gpio.h>
+
+extern int lcd_init(void);
+
+/*
+ * board_early_init_f
+ */
+int board_early_init_f(void)
+{
+ lcd_init();
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000);
+ mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
+ mtdcr(uictr, 0x00000000); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+
+ mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
+ mtebc(pb3cr, CFG_EBC_PB3CR);
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter
+ */
+ mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+ return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
+}
+
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+ char stat;
+ int i;
+
+ stat = in_8((u8 *) CPLD_REG0_ADDR);
+ printf("SW2 status: ");
+ for (i=0; i<4; i++) /* 4-position */
+ printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
+ printf("\n");
+ return 0;
+}
+
+U_BOOT_CMD (
+ sw2_stat, 1, 1, do_sw_stat,
+ "sw2_stat - show status of switch 2\n",
+ NULL
+ );
+
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+ int led_no;
+
+ if (argc != 3) {
+ printf("%s", cmd_tp->usage);
+ return -1;
+ }
+
+ led_no = simple_strtoul(argv[1], NULL, 16);
+ if (led_no != 1 && led_no != 2) {
+ printf("%s", cmd_tp->usage);
+ return -1;
+ }
+
+ if (strcmp(argv[2],"off") == 0x0) {
+ if (led_no == 1)
+ gpio_write_bit(30, 1);
+ else
+ gpio_write_bit(31, 1);
+ } else if (strcmp(argv[2],"on") == 0x0) {
+ if (led_no == 1)
+ gpio_write_bit(30, 0);
+ else
+ gpio_write_bit(31, 0);
+ } else {
+ printf("%s", cmd_tp->usage);
+ return -1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ led_ctl, 3, 1, do_led_ctl,
+ "led_ctl - make led 1 or 2 on or off\n",
+ "<led_no> <on/off> - make led <led_no> on/off,\n"
+ "\tled_no is 1 or 2\t"
+ );
+
+#define SPI_CS_GPIO0 0
+#define SPI_SCLK_GPIO14 14
+#define SPI_DIN_GPIO15 15
+#define SPI_DOUT_GPIO16 16
+
+void spi_scl(int bit)
+{
+ gpio_write_bit(SPI_SCLK_GPIO14, bit);
+}
+
+void spi_sda(int bit)
+{
+ gpio_write_bit(SPI_DOUT_GPIO16, bit);
+}
+
+unsigned char spi_read(void)
+{
+ return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+}
+
+void taihu_spi_chipsel(int cs)
+{
+ gpio_write_bit(SPI_CS_GPIO0, cs);
+}
+
+spi_chipsel_type spi_chipsel[]= {
+ taihu_spi_chipsel
+};
+
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#ifdef CONFIG_PCI
+static unsigned char int_lines[32] = {
+ 29, 30, 27, 28, 29, 30, 25, 27,
+ 29, 30, 27, 28, 29, 30, 27, 28,
+ 29, 30, 27, 28, 29, 30, 27, 28,
+ 29, 30, 27, 28, 29, 30, 27, 28};
+
+static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+ hose->fixup_irq = taihu_pci_fixup_irq;
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+#ifdef CFG_DRAM_TEST
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+ unsigned long msr;
+ unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_EE));
+
+ for (k = 0; k < total_kbytes ;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0)
+ printf("%3d MB\r", k / 1024);
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ mtmsr(msr);
+
+ return 0;
+}
+#endif /* CFG_DRAM_TEST */
diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds
new file mode 100644
index 0000000..be03092
--- /dev/null
+++ b/board/amcc/taihu/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c
new file mode 100644
index 0000000..55ad535
--- /dev/null
+++ b/board/amcc/taihu/update.c
@@ -0,0 +1,132 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#define PCI_M66EN 0x10
+
+static uchar buf_33[] =
+{
+ 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+ 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x0d~0x0e:vendor id 0x1014*/
+ 0x14,
+ 0x00, /* 0x0f~0x10:device id 0x0000*/
+ 0x00,
+ 0x00, /* 0x11:revision 0x00 */
+ 0x00, /* 0x12~0x14:class 0x000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x15~0x16:subsystem vendor id */
+ 0xe8,
+ 0x00, /* 0x17~0x18:subsystem device id */
+ 0x00,
+ 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+ 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+ 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
+ 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+ 0xbe, /* 0x1d: tun[24-31]=0xbe */
+ 0x00,
+ 0x00
+};
+
+static uchar buf_66[] =
+{
+ 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+ 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x0d~0x0e:vendor id 0x1014*/
+ 0x14,
+ 0x00, /* 0x0f~0x10:device id 0x0000*/
+ 0x00,
+ 0x00, /* 0x11:revision 0x00 */
+ 0x00, /* 0x12~0x14:class 0x000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x15~0x16:subsystem vendor id */
+ 0xe8,
+ 0x00, /* 0x17~0x18:subsystem device id */
+ 0x00,
+ 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+ 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+ 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
+ 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+ 0xbe, /* 0x1d: tun[24-31]=0xbe */
+ 0x00,
+ 0x00
+};
+
+static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
+{
+ ulong len = 0x20;
+ uchar chip = CFG_I2C_EEPROM_ADDR;
+ uchar *pbuf;
+ uchar base;
+ int i;
+
+ if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
+ pbuf = buf_33;
+ base = 0x00;
+ } else {
+ pbuf = buf_66;
+ base = 0x40;
+ }
+
+ for (i = 0; i< len; i++, base++) {
+ if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
+ printf("i2c_write fail\n");
+ return 1;
+ }
+ udelay(11000);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ update_boot_eeprom, 1, 1, update_boot_eeprom,
+ "update_boot_eeprom - update boot eeprom content\n",
+ NULL
+ );
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 7316c34..d08fcf3 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -562,6 +562,40 @@ int checkboard (void)
return 0;
}
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+ if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+ return 1;
+ else
+ return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+ /*
+ * Yucca boards with 440SPe rev. A need a slightly different setup
+ * for the MCIF0_WRDTR register.
+ */
+ if (ppc440spe_rev_a())
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+ return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+ /*
+ * Yucca boards with 440SPe rev. A need a slightly different setup
+ * for the MCIF0_CLKTR register.
+ */
+ if (ppc440spe_rev_a())
+ return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+ return default_val;
+}
+
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c
index f6656c1..dc8c88b 100644
--- a/board/esd/plu405/fpgadata.c
+++ b/board/esd/plu405/fpgadata.c
@@ -1,1160 +1,1179 @@
- 0x1f,0x8b,0x08,0x08,0x9d,0x76,0x5c,0x3f,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35,
- 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x6c,0x1d,0x55,
- 0x76,0xc7,0xcf,0xfc,0xb0,0x3d,0xf6,0x7b,0xf1,0x9b,0x24,0x76,0xeb,0x6e,0x82,0x33,
- 0xfe,0x41,0xf4,0x48,0x9f,0x5f,0x5e,0x9c,0x1f,0x18,0x63,0xec,0x89,0x13,0xed,0x5a,
- 0x4b,0xda,0x58,0x2a,0xad,0x56,0x15,0x62,0x0d,0x9b,0xad,0xa2,0xca,0x44,0xa6,0xdb,
- 0x56,0x51,0xba,0x0d,0xd7,0x71,0x20,0x06,0x7b,0x89,0xa1,0x48,0x04,0x9a,0xd2,0x17,
- 0x88,0x84,0x05,0xd6,0xea,0xe5,0x47,0x89,0x21,0x29,0x4c,0x8c,0x81,0x07,0x4d,0x83,
- 0x9b,0xa0,0x2a,0x1b,0x68,0x78,0x50,0x2f,0x98,0x10,0xb2,0xce,0x8f,0x06,0x93,0x38,
- 0x71,0xef,0x9d,0x99,0x7b,0xe7,0xce,0xaf,0x67,0xaf,0xf7,0x8f,0x3d,0x99,0x77,0x35,
- 0xdc,0x73,0xde,0x9d,0x73,0x3e,0xf3,0x3d,0xe7,0x41,0x71,0x6c,0xd2,0xfa,0x1f,0x80,
- 0xf0,0x20,0xa8,0x5d,0x9d,0x7f,0xb7,0x2a,0xb5,0xfa,0xa7,0x2b,0x7e,0x9a,0x4a,0x25,
- 0xb7,0xfc,0x6c,0x13,0x3c,0x04,0x91,0xfa,0x5f,0xac,0x4e,0xfd,0xfc,0x6f,0x1f,0x59,
- 0xb1,0x6a,0x15,0xfc,0x0c,0xff,0x2b,0x95,0x5a,0xb9,0x3c,0x75,0xd7,0xf2,0x54,0x03,
- 0x6c,0x82,0xe2,0x15,0xab,0x1a,0x57,0xae,0x68,0xac,0x5f,0x05,0x3f,0x07,0x61,0xe5,
- 0xfe,0x19,0xfc,0xf7,0xea,0xf3,0x7f,0xfe,0x57,0x29,0x40,0x02,0x00,0x14,0xa5,0x84,
- 0x0e,0xf2,0xff,0x91,0x94,0xa0,0x09,0x80,0x5a,0xea,0x52,0x60,0x90,0x7f,0x83,0xfd,
- 0x79,0x71,0x0a,0x34,0xfe,0xdf,0x42,0x0a,0x74,0x68,0x07,0xbd,0x1f,0x16,0xa8,0x30,
- 0xeb,0x9f,0xa0,0xcb,0x88,0xda,0xbf,0xe7,0xfa,0x99,0x0f,0x51,0xe8,0x32,0xe7,0xaf,
- 0xe5,0x72,0x9a,0x9a,0x62,0x6a,0x2e,0xf7,0x07,0x76,0xff,0xb3,0x73,0xba,0xff,0x35,
- 0x7a,0xff,0xdf,0x77,0x3d,0x2c,0x98,0xc3,0x72,0x00,0x99,0xed,0xc7,0x0a,0x8f,0x0c,
- 0x78,0x87,0x1d,0xa0,0x42,0x21,0x08,0xc4,0xa8,0x00,0xd1,0x75,0xff,0x51,0xba,0xfe,
- 0x78,0xc1,0x2d,0x98,0x41,0x2d,0xe3,0xa5,0x5b,0xa5,0x2d,0xea,0x0d,0xf4,0x07,0xb9,
- 0xd8,0x94,0x84,0xaf,0xec,0x6c,0xb1,0x8c,0xcf,0x90,0x69,0x4c,0xca,0x5d,0xf6,0xfa,
- 0x91,0x8a,0x8b,0x70,0x14,0x25,0x0d,0x65,0x8f,0x98,0x94,0xb1,0xf1,0x79,0xdf,0xb0,
- 0x68,0x5e,0xc9,0x45,0x1c,0x43,0xca,0xc8,0x34,0x8a,0x59,0xe8,0x87,0x43,0x10,0xcf,
- 0xfe,0x20,0x25,0x9e,0xc0,0x46,0xad,0xb1,0xc8,0x32,0x12,0x46,0x84,0x18,0xff,0x64,
- 0x19,0x97,0x05,0x7a,0x7f,0x03,0x86,0xe0,0x28,0xbe,0xa8,0x0c,0x8b,0xc4,0x48,0x1a,
- 0x91,0x8c,0x78,0xc1,0x6d,0xf4,0x65,0x60,0x12,0xbb,0x64,0xfd,0xad,0x2d,0xbf,0x00,
- 0x37,0xa0,0xd1,0x28,0xcd,0x48,0xc4,0x58,0x63,0xc4,0x2c,0xa3,0xd9,0x32,0x3e,0xb1,
- 0x8c,0x31,0xa0,0xf7,0x4f,0x0b,0xc7,0x60,0x06,0x5a,0x8c,0xd8,0xa4,0xf4,0x4b,0x6a,
- 0x4c,0xfb,0x8c,0x41,0x76,0x7f,0x43,0x1d,0x32,0xef,0x16,0x7d,0x53,0x4a,0x10,0xe3,
- 0x38,0x7f,0x5b,0xfa,0x1f,0x5a,0x78,0x15,0x34,0xba,0xbe,0x20,0x61,0x6e,0x52,0x59,
- 0x05,0x09,0xf8,0x46,0xb4,0xb7,0x7d,0xb7,0xc7,0x91,0xcb,0xf8,0xf4,0xdb,0xeb,0xe5,
- 0x0d,0x66,0x34,0x8a,0xcb,0xc4,0xa8,0x2f,0x2c,0x2c,0x50,0x53,0x72,0xbb,0xbd,0x7e,
- 0x4a,0x7d,0x00,0x8e,0xa0,0xba,0x5c,0xf1,0x4f,0xc4,0x4a,0x78,0x05,0xd5,0x4d,0x44,
- 0xb6,0x8a,0xe7,0x10,0xb9,0x42,0x0c,0xb0,0x8d,0x5b,0xec,0xfe,0x6d,0xca,0x06,0xb8,
- 0x82,0x37,0x39,0x4f,0x95,0x4a,0x8d,0x2b,0xdd,0x4d,0x13,0xb1,0x54,0xcd,0x49,0x38,
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- 0x9f,0xb1,0x42,0x1a,0x1f,0x45,0xb6,0xe2,0x13,0x1b,0xa8,0x21,0xd1,0x48,0x7a,0xe2,
- 0x6f,0x1b,0xe7,0x59,0xfc,0x4f,0x54,0xec,0x85,0x23,0x50,0x67,0x44,0xba,0xc4,0x4f,
- 0x4d,0xa3,0x94,0x1a,0x11,0xce,0xb8,0x2c,0xd3,0xfb,0x6b,0xf0,0x22,0x76,0xea,0xe1,
- 0x5c,0xe4,0x27,0xe2,0x39,0x81,0x78,0xd7,0xc7,0xb9,0xc9,0x8c,0x1c,0x8b,0x7f,0xa7,
- 0xdc,0x6f,0x05,0x6d,0x58,0x3c,0x21,0x10,0xe3,0x07,0xae,0xf3,0x66,0x1b,0xa7,0xd8,
- 0xf9,0x9c,0x28,0x9f,0x80,0xeb,0xd0,0x8c,0x62,0x83,0x3d,0xb6,0x91,0x96,0x88,0xb1,
- 0x9d,0x1a,0xe6,0x95,0xeb,0x6c,0x3f,0x6d,0x42,0x1a,0xa6,0xa0,0x19,0x62,0x48,0xca,
- 0x99,0x46,0x29,0x31,0x86,0xf9,0x2b,0xd8,0x38,0x05,0xf4,0xfe,0x8a,0xba,0x1f,0xbe,
- 0x87,0x66,0x3d,0x36,0x20,0x6d,0xb2,0x8d,0x75,0xe3,0xf4,0x0a,0x33,0x46,0xd8,0x7e,
- 0x10,0x4e,0xb5,0x6f,0x40,0x52,0x8f,0xec,0x91,0x6c,0x63,0x40,0x1c,0x17,0xa8,0x61,
- 0x5e,0x29,0x1d,0xc0,0xfe,0xd2,0x2c,0xd8,0x50,0x50,0x6b,0x2d,0x7b,0x46,0xac,0x65,
- 0xeb,0x65,0xd7,0x7a,0x6c,0xbc,0xc7,0xce,0x83,0x56,0x26,0xc3,0x01,0x48,0xb4,0xf7,
- 0x0d,0x2c,0x58,0x4f,0x0c,0x3d,0xa2,0x8a,0xa3,0x6e,0xa3,0x44,0x15,0x47,0x04,0x7a,
- 0x1e,0xb6,0xce,0xeb,0xa0,0x4e,0x69,0x8e,0xe3,0x5e,0x7f,0x4f,0x4a,0xf4,0x7c,0xee,
- 0x29,0xb7,0x9d,0x1a,0xb3,0xbd,0xdb,0x8d,0xdd,0x94,0x5d,0xfe,0x96,0x0e,0x48,0x5f,
- 0x16,0xd2,0xf3,0x50,0x51,0x60,0x5d,0x5c,0x32,0x56,0x53,0xeb,0x0b,0x0b,0x33,0xde,
- 0x63,0xe7,0xa7,0x41,0xc9,0xc9,0xc3,0x90,0x54,0x22,0x48,0xd4,0xcc,0x6d,0x60,0x83,
- 0xec,0x27,0xe9,0x32,0x4e,0xb2,0x78,0xb6,0x95,0xef,0x24,0x4e,0xb5,0x46,0xd4,0xc2,
- 0x9d,0xca,0x01,0xa1,0xd3,0x76,0x53,0x20,0xfe,0x16,0x32,0xc7,0x4f,0xb1,0xfc,0xb3,
- 0x47,0xde,0x6f,0x06,0x6d,0xd1,0x40,0x09,0x31,0x96,0xb9,0xc2,0xe8,0xc4,0x93,0x9d,
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+ 0xa3,0xcf,0xe9,0x85,0x39,0x6a,0x7e,0x78,0xf6,0x11,0x8e,0x58,0xf8,0xb6,0xc6,0xbf,
+ 0x8b,0xf5,0x0f,0x3f,0x0a,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0xfa,0xd4,
+ 0x65,0x66,0x07,0xc9,0xb3,0x03,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x7a,
+ 0xb7,0xcc,0xec,0x50,0xe3,0xd9,0x81,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62,
+ 0xbd,0x5b,0x66,0x76,0xf0,0xcc,0xec,0xf0,0xb1,0x53,0x61,0xb1,0x58,0x2c,0x16,0x8b,
+ 0xc5,0x62,0xb1,0x58,0xff,0xa3,0x22,0xfa,0x7d,0x1c,0x3c,0xfb,0x23,0x02,0x4d,0xbf,
+ 0x5a,0xa9,0x46,0xa0,0xde,0xfb,0xf3,0x84,0xf4,0xb5,0x13,0x11,0x6c,0x88,0xe2,0x98,
+ 0x7f,0x7d,0xb9,0x73,0xdd,0x1b,0x3b,0x1c,0x29,0xc2,0xf0,0x33,0x01,0x00,
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index d916284..830ec19 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -45,16 +45,16 @@ int board_early_init_f(void)
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
- mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
- mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
+ mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
+ mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
- mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
+ mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
+ mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic1sr, 0xffffffff); /* clear all */
@@ -62,9 +62,9 @@ int board_early_init_f(void)
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
- mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
+ mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
/* Trace Pins are disabled. SDR0_PFC0 Register */
mtsdr(SDR0_PFC0, 0x0);
@@ -158,13 +158,13 @@ int misc_init_r(void)
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
- &flash_info[0]);
+ &flash_info[1]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
+ &flash_info[1]);
/*
* USB suff...
@@ -221,8 +221,8 @@ int misc_init_r(void)
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
- /* Lime memory clock adjusted to 133MHz */
- out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+ /* Lime memory clock adjusted to 100MHz */
+ out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
/* Wait untill time expired. Because of requirements in lime manual */
udelay(300);
/* Write lime controller memory parameters */
@@ -237,6 +237,64 @@ int misc_init_r(void)
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+ /*
+ * Init display controller
+ */
+ /* Setup dot clock (internal PLL, division rate 1/16) */
+ out_be32((void *)0xc1fd0100, 0x00000f00);
+
+ /* Lime L0 init (16 bpp, 640x480) */
+ out_be32((void *)0xc1fd0020, 0x801401df);
+ out_be32((void *)0xc1fd0024, 0x0);
+ out_be32((void *)0xc1fd0028, 0x0);
+ out_be32((void *)0xc1fd002c, 0x0);
+ out_be32((void *)0xc1fd0110, 0x0);
+ out_be32((void *)0xc1fd0114, 0x0);
+ out_be32((void *)0xc1fd0118, 0x01df0280);
+
+ /* Display timing init */
+ out_be32((void *)0xc1fd0004, 0x031f0000);
+ out_be32((void *)0xc1fd0008, 0x027f027f);
+ out_be32((void *)0xc1fd000c, 0x015f028f);
+ out_be32((void *)0xc1fd0010, 0x020c0000);
+ out_be32((void *)0xc1fd0014, 0x01df01ea);
+ out_be32((void *)0xc1fd0018, 0x0);
+ out_be32((void *)0xc1fd001c, 0x01e00280);
+
+#if 1
+ /*
+ * Clear framebuffer using Lime's drawing engine
+ * (draw blue rect. with white border around it)
+ */
+ /* Setup mode and fbbase, xres, fg, bg */
+ out_be32((void *)0xc1ff0420, 0x8300);
+ out_be32((void *)0xc1ff0440, 0x0000);
+ out_be32((void *)0xc1ff0444, 0x0280);
+ out_be32((void *)0xc1ff0480, 0x7fff);
+ out_be32((void *)0xc1ff0484, 0x0000);
+ /* Reset clipping rectangle */
+ out_be32((void *)0xc1ff0454, 0x0000);
+ out_be32((void *)0xc1ff0458, 0x0280);
+ out_be32((void *)0xc1ff045c, 0x0000);
+ out_be32((void *)0xc1ff0460, 0x01e0);
+ /* Draw white rect. */
+ out_be32((void *)0xc1ff04a0, 0x09410000);
+ out_be32((void *)0xc1ff04a0, 0x00000000);
+ out_be32((void *)0xc1ff04a0, 0x01e00280);
+ udelay(2000);
+ /* Draw blue rect. */
+ out_be32((void *)0xc1ff0480, 0x001f);
+ out_be32((void *)0xc1ff04a0, 0x09410000);
+ out_be32((void *)0xc1ff04a0, 0x00010001);
+ out_be32((void *)0xc1ff04a0, 0x01de027e);
+#endif
+ /* Display enable, L0 layer */
+ out_be32((void *)0xc1fd0100, 0x80010f00);
+
+ /* TFT-LCD enable - PWM duty, lamp on */
+ out_be32((void *)0xc4000024, 0x64);
+ out_be32((void *)0xc4000020, 0x701);
+
return 0;
}
@@ -463,3 +521,14 @@ void hw_watchdog_reset(void)
val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
gpio_write_bit(CFG_GPIO_WATCHDOG, val);
}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return (ctrlc());
+}
+#endif
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 9a4a8ee..f906b85 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -54,7 +54,6 @@
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
@@ -474,7 +473,7 @@ static void program_ecc(u32 start_address,
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
-#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/*
* Some boards (like lwmon5) need to preserve the memory
* content upon ECC generation (for the log-buffer).
@@ -487,6 +486,11 @@ static void program_ecc(u32 start_address,
current_address = start_address;
while (current_address < end_address) {
+ /*
+ * TODO: Th following sequence doesn't work correctly.
+ * Just invalidating and flushing the cache doesn't
+ * seem to trigger the re-write of the memory.
+ */
ppcDcbi(current_address);
ppcDcbf(current_address);
current_address += CFG_CACHELINE_SIZE;
@@ -515,19 +519,6 @@ static void program_ecc(u32 start_address,
}
#endif
-static __inline__ u32 get_mcsr(void)
-{
- u32 val;
-
- asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
- return val;
-}
-
-static __inline__ void set_mcsr(u32 val)
-{
- asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@@ -535,8 +526,6 @@ static __inline__ void set_mcsr(u32 val)
************************************************************************/
long int initdram (int board_type)
{
- u32 val;
-
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/* CL=3 */
mtsdram(DDR0_02, 0x00000000);
@@ -641,14 +630,6 @@ long int initdram (int board_type)
* Perform data eye search if requested.
*/
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- val = get_mcsr();
- set_mcsr(val);
#endif
#ifdef CONFIG_DDR_ECC
@@ -658,5 +639,12 @@ long int initdram (int board_type)
program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#endif
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
return (CFG_MBYTES_SDRAM << 20);
}
diff --git a/board/netstal/common/flash.c b/board/netstal/common/flash.c
new file mode 100644
index 0000000..be2cb37
--- /dev/null
+++ b/board/netstal/common/flash.c
@@ -0,0 +1,528 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ *
+ * Modified 6/6/2007
+ * Added isync
+ * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#if CFG_MAX_FLASH_BANKS != 1
+#error "CFG_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+
+ /* Init: no FLASHes known */
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM,
+ &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ /* Setup offsets */
+ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void) flash_protect (FLAG_PROTECT_SET,
+ FLASH_BASE0_PRELIM,
+ FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+ &flash_info[0]);
+ flash_info[0].size = size_b0;
+
+ return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/*
+ * This implementation assumes that the flash chips are uniform sector
+ * devices. This is true for all likely flash devices on a HCUx.
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ unsigned idx;
+ unsigned long sector_size = info->size / info->sector_count;
+
+ for (idx = 0; idx < info->sector_count; idx += 1) {
+ info->start[idx] = base + (idx * sector_size);
+ }
+}
+
+/*-----------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf ("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf ("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf ("SST ");
+ break;
+ case FLASH_MAN_STM:
+ printf ("ST Micro ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ /* (Reduced table of only parts expected in HCUx boards.) */
+ switch (info->flash_id) {
+ case FLASH_MAN_AMD | FLASH_AM040:
+ printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_MAN_STM | FLASH_AM040:
+ printf ("MM29W040W (512 Kbit, uniform sector size)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *) info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------*/
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ asm("isync");
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ asm("isync");
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ asm("isync");
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+ asm("isync");
+
+ value = addr2[0];
+ asm("isync");
+
+ switch (value) {
+ case (FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (FLASH_WORD_SIZE)STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ printf("Unknown flash manufacturer code: 0x%x at %p\n",
+ value, addr);
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ switch (value) {
+ case (FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* Calculate the sector offsets (Use HCUx Optimized code). */
+ flash_get_offsets(base, info);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address,
+ *(A7 .. A0) = 0x02
+ * D0 = 1 if protected
+ */
+ addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (FLASH_WORD_SIZE *) info->start[0];
+ *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr =
+ (FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors not erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+ printf ("Erasing sector %p\n", addr2); /* CLH */
+
+ if ((info->flash_id & FLASH_VENDMASK) ==
+ FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ /* block erase */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00500050;
+ for (i = 0; i < 50; i++) udelay (1000);
+ } else {
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ /* sector erase */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00300030;
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7 (info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+#if 0
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+ wait_for_DQ7 (info, l_sect);
+
+DONE:
+#endif
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 =
+ (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c
new file mode 100644
index 0000000..a9de45e
--- /dev/null
+++ b/board/netstal/common/nm_bsp.c
@@ -0,0 +1,41 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BSP
+/*
+ * Command nm_bsp: Netstal Maschinen BSP specific command
+ */
+int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__,
+ flag, argc, argv[0]);
+ printf("Netstal Maschinen BSP specific command. None at the moment.\n");
+ return 0;
+}
+
+U_BOOT_CMD(
+ nm_bsp, 1, 1, nm_bsp,
+ "nm_bsp - Netstal Maschinen BSP specific command. \n",
+ "Help for Netstal Maschinen BSP specific command.\n"
+ );
+#endif
diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile
new file mode 100644
index 0000000..d9825a5
--- /dev/null
+++ b/board/netstal/hcu4/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2007 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+vpath flash.c ../common
+COBJS = $(BOARD).o flash.o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/netstal/hcu4/README.txt b/board/netstal/hcu4/README.txt
new file mode 100644
index 0000000..1e9c64a
--- /dev/null
+++ b/board/netstal/hcu4/README.txt
@@ -0,0 +1,59 @@
+HCU4 Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+0x70000000
+
+Chip-Select 3: CAN Interface
+----------------------------
+0x7800000
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+Our IO-Bus (slow version)
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+Our IO-Bus (fast, but not yet use)
+
+
+Memory Bank 1 -- SDRAM
+-------------------------------------
+
+0x00000000 - 0x1ffffff # Default 32 MB
diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk
new file mode 100644
index 0000000..376609a
--- /dev/null
+++ b/board/netstal/hcu4/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: HCU4 boards
+#
+
+TEXT_BASE = 0xFFFa0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
new file mode 100644
index 0000000..2b95604
--- /dev/null
+++ b/board/netstal/hcu4/hcu4.c
@@ -0,0 +1,400 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm-ppc/u-boot.h>
+#include "../common/nm_bsp.c"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
+
+#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
+
+#define DO_UGLY_SDRAM_WORKAROUND
+
+enum {
+ /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
+ HW_GENERATION_HCU2 = 0x10,
+ HW_GENERATION_HCU3 = 0x10,
+ HW_GENERATION_HCU4 = 0x20,
+ HW_GENERATION_MCU = 0x08,
+ HW_GENERATION_MCU20 = 0x0a,
+ HW_GENERATION_MCU25 = 0x09,
+};
+
+void sysLedSet(u32 value);
+long int spd_sdram(int(read_spd)(uint addr));
+
+#ifdef CONFIG_SPD_EEPROM
+#define DEBUG
+#endif
+
+#if defined(DEBUG)
+void show_sdram_registers(void);
+#endif
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+#define CPC0_CR0 0xb1 /* Chip control register 0 */
+#define CPC0_CR1 0xb2 /* Chip control register 1 */
+/* Attention: If you want 1 microsecs times from the external oscillator
+ * use 0x00804051. But this causes problems with u-boot and linux!
+ */
+#define CPC0_CR1_VALUE 0x00004051
+#define CPC0_ECR 0xaa /* Edge condition register */
+#define EBC0_CFG 0x23 /* External Peripheral Control Register */
+#define CPC0_EIRR 0xb6 /* External Interrupt Register */
+
+
+int board_early_init_f (void)
+{
+ /*-------------------------------------------------------------------+
+ | Interrupt controller setup for the HCU4 board.
+ | Note: IRQ 0-15 405GP internally generated; high; level sensitive
+ | IRQ 16 405GP internally generated; low; level sensitive
+ | IRQ 17-24 RESERVED/UNUSED
+ | IRQ 31 (EXT IRQ 6) (unused)
+ +-------------------------------------------------------------------*/
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (uicer, 0x00000000); /* disable all ints */
+ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
+ mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
+ mtdcr (uictr, 0x10000000); /* set int trigger levels */
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
+ mtdcr(CPC0_ECR, 0x60606000);
+ mtdcr(CPC0_EIRR, 0x7c000000);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+ return board_early_init_f ();
+}
+#endif
+
+int checkboard (void)
+{
+ unsigned int j;
+ u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
+ u16 generation = *boardVersReg & 0xf0;
+ u16 index = *boardVersReg & 0x0f;
+
+ /* Force /RTS to active. The board it not wired quite
+ correctly to use cts/rtc flow control, so just force the
+ /RST active and forget about it. */
+ writeb (readb (0xef600404) | 0x03, 0xef600404);
+ printf ("\nNetstal Maschinen AG ");
+ if (generation == HW_GENERATION_HCU3)
+ printf ("HCU3: index %d\n\n", index);
+ else if (generation == HW_GENERATION_HCU4)
+ printf ("HCU4: index %d\n\n", index);
+ /* GPIO here noch nicht richtig initialisert !!! */
+ sysLedSet(0);
+ for (j = 0; j < 7; j++) {
+ sysLedSet(1 << j);
+ udelay(50 * 1000);
+ }
+
+ return 0;
+}
+
+u32 sysLedGet(void)
+{
+ return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
+}
+
+void sysLedSet(u32 value /* value to place in LEDs */)
+{
+ u32 tmp = ~value;
+ u32 *ledReg;
+
+ tmp = (tmp << 23) | 0x7FFFFF;
+ ledReg = (u32 *)GPIO0_OR;
+ *ledReg = tmp;
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram or initdram
+ * used for HCUx
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+#if defined(DEBUG)
+void show_sdram_registers(void)
+{
+ u32 value;
+
+ printf ("SDRAM Controller Registers --\n");
+ mfsdram(mem_mcopt1, value);
+ printf (" SDRAM0_CFG : 0x%08x\n", value);
+ mfsdram(mem_status, value);
+ printf (" SDRAM0_STATUS: 0x%08x\n", value);
+ mfsdram(mem_mb0cf, value);
+ printf (" SDRAM0_B0CR : 0x%08x\n", value);
+ mfsdram(mem_mb1cf, value);
+ printf (" SDRAM0_B1CR : 0x%08x\n", value);
+ mfsdram(mem_sdtr1, value);
+ printf (" SDRAM0_TR : 0x%08x\n", value);
+ mfsdram(mem_rtr, value);
+ printf (" SDRAM0_RTR : 0x%08x\n", value);
+}
+#endif
+
+/*
+ * this is even after checkboard. It returns the size of the SDRAM
+ * that we have installed. This function is called by board_init_f
+ * in lib_ppc/board.c to initialize the memory and return what I
+ * found. These are default value, which will be overridden later.
+ */
+
+long int fixed_hcu4_sdram (int board_type)
+{
+#ifdef DEBUG
+ printf (__FUNCTION__);
+#endif
+ /* disable memory controller */
+ mtdcr (memcfga, mem_mcopt1);
+ mtdcr (memcfgd, 0x00000000);
+
+ udelay (500);
+
+ /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+ mtdcr (memcfga, mem_besra);
+ mtdcr (memcfgd, 0xffffffff);
+
+ /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+ mtdcr (memcfga, mem_besrb);
+ mtdcr (memcfgd, 0xffffffff);
+
+ /* Clear SDRAM0_ECCCFG (disable ECC) */
+ mtdcr (memcfga, mem_ecccf);
+ mtdcr (memcfgd, 0x00000000);
+
+ /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+ mtdcr (memcfga, mem_eccerr);
+ mtdcr (memcfgd, 0xffffffff);
+
+ /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
+ * TODO ngngng
+ */
+ mtdcr (memcfga, mem_sdtr1);
+ mtdcr (memcfgd, 0x008a4015);
+
+ /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
+ * TODO ngngng
+ */
+ mtdcr (memcfga, mem_mb0cf);
+ mtdcr (memcfgd, 0x00062001);
+
+ /* refresh timer = 0x400 */
+ mtdcr (memcfga, mem_rtr);
+ mtdcr (memcfgd, 0x04000000);
+
+ /* Power management idle timer set to the default. */
+ mtdcr (memcfga, mem_pmit);
+ mtdcr (memcfgd, 0x07c00000);
+
+ udelay (500);
+
+ /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
+ mtdcr (memcfga, mem_mcopt1);
+ mtdcr (memcfgd, 0x90800000);
+
+#ifdef DEBUG
+ printf ("%s: done\n", __FUNCTION__);
+#endif
+ return SDRAM_LEN;
+}
+
+/*---------------------------------------------------------------------------+
+ * getSerialNr
+ *---------------------------------------------------------------------------*/
+static u32 getSerialNr(void)
+{
+ u32 *serial = (u32 *)CFG_FLASH_BASE;
+
+ if (*serial == 0xffffffff)
+ return get_ticks();
+
+ return *serial;
+}
+
+
+/*---------------------------------------------------------------------------+
+ * misc_init_r.
+ *---------------------------------------------------------------------------*/
+
+int misc_init_r(void)
+{
+ char *s = getenv("ethaddr");
+ char *e;
+ int i;
+ u32 serial = getSerialNr();
+
+ for (i = 0; i < 6; ++i) {
+ gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+
+ if (gd->bd->bi_enetaddr[3] == 0 &&
+ gd->bd->bi_enetaddr[4] == 0 &&
+ gd->bd->bi_enetaddr[5] == 0) {
+ char ethaddr[22];
+ /* [0..3] Must be in sync with CONFIG_ETHADDR */
+ gd->bd->bi_enetaddr[0] = 0x00;
+ gd->bd->bi_enetaddr[1] = 0x60;
+ gd->bd->bi_enetaddr[2] = 0x13;
+ gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
+ gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
+ gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff;
+ sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
+ gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
+ gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
+ gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
+ printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
+ ethaddr, serial);
+ setenv ("ethaddr", ethaddr);
+ }
+ return 0;
+}
+
+#ifdef DO_UGLY_SDRAM_WORKAROUND
+#include "i2c.h"
+
+void set_spd_default_value(unsigned int spd_addr,uchar def_val)
+{
+ uchar value;
+ int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
+
+ if (res == 0 && value == 0xff) {
+ res = i2c_write(SPD_EEPROM_ADDRESS,
+ spd_addr, 1, &def_val, 1) ;
+#ifdef DEBUG
+ printf("%s: Setting spd offset %3d to %3d res %d\n",
+ __FUNCTION__, spd_addr, def_val, res);
+#endif
+ }
+}
+#endif
+
+long int initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if !defined(CONFIG_SPD_EEPROM)
+ dram_size = fixed_hcu4_sdram();
+#else
+#ifdef DO_UGLY_SDRAM_WORKAROUND
+ /* Workaround if you have no working I2C-EEPROM-SPD-configuration */
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ set_spd_default_value(2, 4); /* SDRAM Type */
+ set_spd_default_value(7, 0); /* module width, high byte */
+ set_spd_default_value(12, 1); /* Refresh or 0x81 */
+
+ /* Only correct for HCU3 with 32 MB RAM*/
+ /* Number of bytes used by module manufacturer */
+ set_spd_default_value( 0, 128);
+ set_spd_default_value( 1, 11 ); /* Total SPD memory size */
+ set_spd_default_value( 2, 4 ); /* Memory type */
+ set_spd_default_value( 3, 12 ); /* Number of row address bits */
+ set_spd_default_value( 4, 9 ); /* Number of column address bits */
+ set_spd_default_value( 5, 1 ); /* Number of module rows */
+ set_spd_default_value( 6, 32 ); /* Module data width, LSB */
+ set_spd_default_value( 7, 0 ); /* Module data width, MSB */
+ set_spd_default_value( 8, 1 ); /* Module interface signal levels */
+ /* SDRAM cycle time for highest CL (Tclk) */
+ set_spd_default_value( 9, 112);
+ /* SDRAM access time from clock for highest CL (Tac) */
+ set_spd_default_value(10, 84 );
+ set_spd_default_value(11, 2 ); /* Module configuration type */
+ set_spd_default_value(12, 128); /* Refresh rate/type */
+ set_spd_default_value(13, 16 ); /* Primary SDRAM width */
+ set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
+ /* SDRAM device attributes, min clock delay for back to back */
+ /*random column addresses (Tccd) */
+ set_spd_default_value(15, 1 );
+ /* SDRAM device attributes, burst lengths supported */
+ set_spd_default_value(16, 143);
+ /* SDRAM device attributes, number of banks on SDRAM device */
+ set_spd_default_value(17, 4 );
+ /* SDRAM device attributes, CAS latency */
+ set_spd_default_value(18, 6 );
+ /* SDRAM device attributes, CS latency */
+ set_spd_default_value(19, 1 );
+ /* SDRAM device attributes, WE latency */
+ set_spd_default_value(20, 1 );
+ set_spd_default_value(21, 0 ); /* SDRAM module attributes */
+ /* SDRAM device attributes, general */
+ set_spd_default_value(22, 14 );
+ /* SDRAM cycle time for 2nd highest CL (Tclk) */
+ set_spd_default_value(23, 117);
+ /* SDRAM access time from clock for2nd highest CL (Tac) */
+ set_spd_default_value(24, 84 );
+ /* SDRAM cycle time for 3rd highest CL (Tclk) */
+ set_spd_default_value(25, 0 );
+ /* SDRAM access time from clock for3rd highest CL (Tac) */
+ set_spd_default_value(26, 0 );
+ set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
+ /* Minimum row active to row active delay (Trrd) */
+ set_spd_default_value(28, 14 );
+ set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
+ set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
+ set_spd_default_value(31, 8 ); /* Module bank density */
+ /* Command and Address signal input setup time */
+ set_spd_default_value(32, 21 );
+ /* Command and Address signal input hold time */
+ set_spd_default_value(33, 8 );
+ set_spd_default_value(34, 21 ); /* Data signal input setup time */
+ set_spd_default_value(35, 8 ); /* Data signal input hold time */
+#endif /* DO_UGLY_SDRAM_WORKAROUND */
+ dram_size = spd_sdram(0);
+#endif
+
+#ifdef DEBUG
+ show_sdram_registers();
+#endif
+
+#if defined(CFG_DRAM_TEST)
+ bcu4_testdram(dram_size);
+ printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));
+#endif
+
+ return dram_size;
+}
diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds
new file mode 100644
index 0000000..b6e28f8
--- /dev/null
+++ b/board/netstal/hcu4/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text : {
+ /* The start.o file includes the initial jump vector that
+ must be located in the beginning. It is the basic run-
+ time function that calls all other functions. */
+ cpu/ppc4xx/start.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
new file mode 100644
index 0000000..eee310b
--- /dev/null
+++ b/board/netstal/hcu5/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2007 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+vpath flash.c ../common
+COBJS = $(BOARD).o sdram.o flash.o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt
new file mode 100644
index 0000000..3118da9
--- /dev/null
+++ b/board/netstal/hcu5/README.txt
@@ -0,0 +1,174 @@
+HCU5 configuration details and startup sequence
+
+(C) Copyright 2007 Netstal Maschinen AG
+ Niklaus Giger (Niklaus.Giger@netstal.com)
+
+TODO:
+-----
+- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
+ - Does not occur if both EMAC are connected
+- Fix RTS/CTS problem (HW?)
+ CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
+ Switching to interrupt driven serial input mode
+- Make vxWorks start from u-boot. Possible reasons
+ - Does vxWorks need an entry for the Machine Check interrupt like this
+ tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
+
+Caveats:
+--------
+Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
+see hcu5.c.
+
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xe0010000- 0xe0013fff CFG_OCM_BASE
+The 440EPx includes a 16K on-chip memory that can be placed however
+software chooses.
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC440EPX
+chip.
+
+Chip-Select 2: Flash Memory
+---------------------------
+
+Not used
+
+Chip-Select 3: CAN Interface
+----------------------------
+0xc800000: 2 Intel 82527 CAN-Controller
+
+
+Chip-Select 4: IMC-bus standard
+-------------------------------
+
+0xcc00000: Netstal specific IO-Bus
+
+
+Chip-Select 5: IMC-bus fast (inactive)
+--------------------------------------
+
+0xce00000: Netstal specific IO-Bus (fast, but not yet used)
+
+
+Memory Bank 1 -- DDR2
+-------------------------------------
+
+0x00000000 - 0xfffffff # Default 256 MB
+
+PCI ??
+
+USB ??
+Only USB_STORAGE is enabled to load vxWorks
+from a memory stick.
+
+System-LEDs ??? (Analog zu HCU4 ???)
+
+Startup sequence
+----------------
+
+(cpu/ppc4xx/resetvec.S)
+depending on configs option
+call _start_440 _start_pci oder _start
+
+(cpu/ppc4xx/start.S)
+
+_start_440:
+ initialize register like
+ CCR0
+ debug
+ setup interrupt vectors
+ configure cache regions
+ clear and setup TLB
+ enable internal RAM
+ jump start_ram
+ which in turn will jump to start
+_start:
+ Clear and set up some registers.
+ Debug setup
+ Setup the internal SRAM
+ Setup the stack in internal SRAM
+ setup stack pointer (r1)
+ setup GOT
+ call cpu_init_f /* run low-level CPU init code (from Flash) */
+
+ call cpu_init_f
+ board_init_f: (lib_ppc\board.c)
+ init_sequence defines a list of function to be called
+ board_early_init_f: (board/netstal/hcu5/hcu5.c)
+ We are using Bootstrap-Option A
+ if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
+ Setup the GPIO pins
+ Setup the interrupt controller polarities, triggers, etc.
+ Ethernet, PCI, USB enable
+ setup BOOT FLASH (Chip timing)
+ init_baudrate,
+ serial_init
+ checkcpu
+ misc_init_f #ifdef
+ init_func_i2c #ifdef
+ post_init_f #ifdef
+ init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
+ (EYE function removed!!)
+ test_dram call
+
+ * Reserve memory at end of RAM for (top down in that order):
+ * - kernel log buffer
+ * - protected RAM
+ * - LCD framebuffer
+ * - monitor code
+ * - board info struct
+ Save local variables to board info struct
+ call relocate_code() does not return
+ relocate_code: (cpu/ppc4xx/start.S)
+-------------------------------------------------------
+From now on our copy is in RAM and we will run from there,
+ starting with board_init_r
+-------------------------------------------------------
+ board_init_r: (lib_ppc\board.c)
+ setup bd function pointers
+ trap_init
+ flash_init: (board/netstal/hcu5/flash.c)
+ /* setup for u-boot erase, update */
+ setup bd flash info
+ cpu_init_r: (cpu/ppc4xx/cpu_init.c)
+ peripheral chip select in using defines like
+ CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h
+ mem_malloc_init
+ malloc_bin_reloc
+ spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+ env_relocated
+ misc_init_r(bd): (board/netstal/hcu5.c)
+ ethaddr mit serial number ergänzen
+ Then we will somehow go into the command loop
+
+Most of the HW specific code for the HCU5 may be found in
+include/configs/hcu5.h
+board/netstal/hcu5/*
+cpu/ppc4xx/*
+lib_ppc/*
+include/ppc440.h
+
+Drivers for serial etc are found under drivers/
+
+Don't ask question if you did not look at the README !!
+Most CFG_* and CONFIG_* switches are mentioned/explained there.
diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk
new file mode 100644
index 0000000..cfd5744
--- /dev/null
+++ b/board/netstal/hcu5/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2005 Netstal Maschinen AG
+# Niklaus Giger (ng@netstal.com)
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Netstal Maschinen AG: HCU5 boards
+#
+
+TEXT_BASE = 0xFFFa0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG -g
+endif
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
new file mode 100644
index 0000000..23df081
--- /dev/null
+++ b/board/netstal/hcu5/hcu5.c
@@ -0,0 +1,525 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sysLedSet(u32 value);
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#undef BOOTSTRAP_OPTION_A_ACTIVE
+
+#define SDR0_CP440 0x0180
+
+#define SYSTEM_RESET 0x30000000
+#define CHIP_RESET 0x20000000
+
+#define SDR0_ECID0 0x0080
+#define SDR0_ECID1 0x0081
+#define SDR0_ECID2 0x0082
+#define SDR0_ECID3 0x0083
+
+#define SYS_IO_ADDRESS 0xcce00000
+
+#define DEFAULT_ETH_ADDR "ethaddr"
+/* ethaddr for first or etha1ddr for second ethernet */
+
+enum {
+ /* HW_GENERATION_HCU1 is no longer supported */
+ HW_GENERATION_HCU2 = 0x10,
+ HW_GENERATION_HCU3 = 0x10,
+ HW_GENERATION_HCU4 = 0x20,
+ HW_GENERATION_HCU5 = 0x30,
+ HW_GENERATION_MCU = 0x08,
+ HW_GENERATION_MCU20 = 0x0a,
+ HW_GENERATION_MCU25 = 0x09,
+};
+
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+
+int board_early_init_f(void)
+{
+ u32 reg;
+
+#ifdef BOOTSTRAP_OPTION_A_ACTIVE
+ /* Booting with Bootstrap Option A
+ * First boot, with CPR0_ICFG_RLI_MASK == 0
+ * no we setup varios boot strapping register,
+ * then we do reset the PPC440 using a chip reset
+ * Unfortunately, we cannot use this option, as Nto1 is not set
+ * with Bootstrap Option A and cannot be changed later on by SW
+ * There are no other possible boostrap options with a 8 bit ROM
+ * See Errata (Version 1.04) CHIP_9
+ */
+
+ u32 cpr0icfg;
+ u32 dbcr;
+
+ mfcpr(CPR0_ICFG, cpr0icfg);
+ if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
+ mtcpr(CPR0_MALD, 0x02000000);
+ mtcpr(CPR0_OPBD, 0x02000000);
+ mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
+ mtcpr(CPR0_PLLC, 0x40000238);
+ mtcpr(CPR0_PLLD, 0x01010414);
+ mtcpr(CPR0_PRIMAD, 0x01000000);
+ mtcpr(CPR0_PRIMBD, 0x01000000);
+ mtcpr(CPR0_SPCID, 0x03000000);
+ mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
+ mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
+ mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
+
+ /*
+ * Initiate system reset in debug control register DBCR
+ */
+ dbcr = mfspr(dbcr0);
+ mtspr(dbcr0, dbcr | CHIP_RESET);
+ }
+ mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
+#endif
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /* test-only: take GPIO init from pcs440ep ???? in config file */
+ out32(GPIO0_OR, 0x00000000);
+ out32(GPIO0_TCR, 0x7C2FF1CF);
+ out32(GPIO0_OSRL, 0x40055000);
+ out32(GPIO0_OSRH, 0x00000000);
+ out32(GPIO0_TSRL, 0x40055000);
+ out32(GPIO0_TSRH, 0x00000400);
+ out32(GPIO0_ISR1L, 0x40000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x00000000);
+ out32(GPIO0_ISR2H, 0x00000000);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
+
+ out32(GPIO1_OR, 0x00000000);
+ out32(GPIO1_TCR, 0xC6007FFF);
+ out32(GPIO1_OSRL, 0x00140000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x00000000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x05415555);
+ out32(GPIO1_ISR1H, 0x40000000);
+ out32(GPIO1_ISR2L, 0x00000000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x00000000);
+ out32(GPIO1_ISR3H, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
+ mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ pci_pre_init(0);
+
+ /* setup BOOT FLASH */
+ mtsdr(SDR0_CUST0, 0xC0082350);
+
+ return 0;
+}
+
+int board_pre_init(void)
+{
+ return board_early_init_f();
+}
+
+int checkboard(void)
+{
+ unsigned int j;
+ u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
+ u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
+ u16 generation = *boardVersReg & 0xf0;
+ u16 index = *boardVersReg & 0x0f;
+ u32 ecid0, ecid1, ecid2, ecid3;
+
+ printf("Netstal Maschinen AG: ");
+ if (generation == HW_GENERATION_HCU3)
+ printf("HCU3: index %d", index);
+ else if (generation == HW_GENERATION_HCU4)
+ printf("HCU4: index %d", index);
+ else if (generation == HW_GENERATION_HCU5)
+ printf("HCU5: index %d", index);
+ printf(" HW 0x%02x\n", *hwVersReg & 0xff);
+ mfsdr(SDR0_ECID0, ecid0);
+ mfsdr(SDR0_ECID1, ecid1);
+ mfsdr(SDR0_ECID2, ecid2);
+ mfsdr(SDR0_ECID3, ecid3);
+
+ printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
+ for (j = 0;j < 6; j++) {
+ sysLedSet(1 << j);
+ udelay(200 * 1000);
+ }
+
+ return 0;
+}
+
+u32 sysLedGet(void)
+{
+ return in16(SYS_IO_ADDRESS) & 0x3f;
+}
+
+void sysLedSet(u32 value /* value to place in LEDs */)
+{
+ out16(SYS_IO_ADDRESS, value);
+}
+
+/*---------------------------------------------------------------------------+
+ * getSerialNr
+ *---------------------------------------------------------------------------*/
+static u32 getSerialNr(void)
+{
+ u32 *serial = (u32 *)CFG_FLASH_BASE;
+
+ if (*serial == 0xffffffff)
+ return get_ticks();
+
+ return *serial;
+}
+
+
+/*---------------------------------------------------------------------------+
+ * misc_init_r.
+ *---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+ char *s = getenv(DEFAULT_ETH_ADDR);
+ char *e;
+ int i;
+ u32 serial = getSerialNr();
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+
+ for (i = 0; i < 6; ++i) {
+ gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+
+ if (gd->bd->bi_enetaddr[3] == 0 &&
+ gd->bd->bi_enetaddr[4] == 0 &&
+ gd->bd->bi_enetaddr[5] == 0) {
+ char ethaddr[22];
+
+ /* Must be in sync with CONFIG_ETHADDR */
+ gd->bd->bi_enetaddr[0] = 0x00;
+ gd->bd->bi_enetaddr[1] = 0x60;
+ gd->bd->bi_enetaddr[2] = 0x13;
+ gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
+ gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
+ /* byte[5].bit 0 must be zero */
+ gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
+ gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
+ gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
+ gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
+ printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
+ ethaddr, serial);
+ setenv(DEFAULT_ETH_ADDR, ethaddr);
+ }
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ /*
+ * USB stuff...
+ */
+
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*clear resets*/
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ return 0;
+}
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*-------------------------------------------------------------------+
+ * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
+ * Workaround: Disable write pipelining to DDR SDRAM by setting
+ * PLB0_ACR[WRP] = 0.
+ *-------------------------------------------------------------------*/
+
+ /*-------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
+ mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
+
+ /*-------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
+ mtdcr(plb4_acr, addr); /* Sequoia */
+
+ /*-------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
+
+ /* mtdcr(plb0_acr, addr); */ /* Sequoia */
+ mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) ;
+ /* mtdcr(plb1_acr, addr); */ /* Sequoia */
+ mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*-------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *-------------------------------------------------------------*/
+ /*-------------------------------------------------------------+
+ | PowerPC440EPX PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
+ | 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +-------------------------------------------------------------*/
+ /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0MA, 0x00000000);
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM0MA, 0xE0000001);
+
+ /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1MA, 0x00000000);
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ /* 512M + No prefetching, and enable region */
+ out32r(PCIX0_PMM1MA, 0xE0000001);
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*------------------------------------------------------------------+
+ * Set up Configuration registers
+ *------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*---------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif
+/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S
new file mode 100644
index 0000000..5ab6cd2
--- /dev/null
+++ b/board/netstal/hcu5/init.S
@@ -0,0 +1,79 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /* vxWorks needs this entry for the Machine Check interrupt, */
+ /* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
+
+ /*
+ * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for EBC (CFG_CPLD) */
+ /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
+ /* CAN */
+ tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ /* IMC + CPLD */
+ tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ /* IMC-Fast */
+ tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /* TLB for SDRAM will be added by initdram (sdram.c) */
+
+ tlbtab_end
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
new file mode 100644
index 0000000..4039195
--- /dev/null
+++ b/board/netstal/hcu5/sdram.c
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2007
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <ppc440.h>
+
+void sysLedSet(u32 value);
+void dcbz_area(u32 start_address, u32 num_bytes);
+void dflush(void);
+
+#define DDR_DCR_BASE 0x10
+#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
+#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
+
+#define DDR0_01_INT_MASK_MASK 0x000000FF
+#define DDR0_00_INT_ACK_ALL 0x7F000000
+#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
+
+#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
+#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
+
+#define DDR0_22 0x16
+/* ECC */
+#define DDR0_22_CTRL_RAW_MASK 0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
+#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
+#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+
+#ifdef CFG_ENABLE_SDRAM_CACHE
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
+#else
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
+#endif
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+
+#ifdef CONFIG_ADD_RAM_INFO
+void board_add_ram_info(int use_default)
+{
+ PPC440_SYS_INFO board_cfg;
+ u32 val;
+ mfsdram(DDR0_22, val);
+ val &= DDR0_22_CTRL_RAW_MASK;
+ switch (val) {
+ case DDR0_22_CTRL_RAW_ECC_DISABLE:
+ puts(" (ECC disabled");
+ break;
+ case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
+ puts(" (ECC check only");
+ break;
+ case DDR0_22_CTRL_RAW_NO_ECC_RAM:
+ puts(" (no ECC ram");
+ break;
+ case DDR0_22_CTRL_RAW_ECC_ENABLE:
+ puts(" (ECC enabled");
+ break;
+ }
+
+ get_sys_info(&board_cfg);
+ printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+ mfsdram(DDR0_03, val);
+ val = DDR0_03_CASLAT_DECODE(val);
+ printf(", CL%d)", val);
+}
+#endif
+
+/*--------------------------------------------------------------------
+ * wait_for_dlllock.
+ *--------------------------------------------------------------------*/
+static int wait_for_dlllock(void)
+{
+ unsigned long val;
+ int wait = 0;
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_17);
+ val = DDR0_17_DLLLOCKREG_UNLOCKED;
+
+ while (wait != 0xffff) {
+ val = mfdcr(ddrcfgd);
+ if ((val & DDR0_17_DLLLOCKREG_MASK) ==
+ DDR0_17_DLLLOCKREG_LOCKED)
+ /* dlllockreg bit on */
+ return 0;
+ else
+ wait++;
+ }
+ debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+ debug("Waiting for dlllockreg bit to raise\n");
+
+ return -1;
+}
+
+/***********************************************************************
+ *
+ * sdram_panic -- Panic if we cannot configure the sdram correctly
+ *
+ ************************************************************************/
+void sdram_panic(const char *reason)
+{
+ printf("\n%s: reason %s", __FUNCTION__, reason);
+ sysLedSet(0xff);
+ while (1) {
+ }
+ /* Never return */
+}
+
+#ifdef CONFIG_DDR_ECC
+static void blank_string(int size)
+{
+ int i;
+
+ for (i=0; i<size; i++)
+ putc('\b');
+ for (i=0; i<size; i++)
+ putc(' ');
+ for (i=0; i<size; i++)
+ putc('\b');
+}
+/*---------------------------------------------------------------------------+
+ * program_ecc.
+ *---------------------------------------------------------------------------*/
+static void program_ecc(unsigned long start_address, unsigned long num_bytes,
+ unsigned long tlb_word2_i_value)
+{
+ unsigned long current_address= start_address;
+ int loopi = 0;
+ u32 val;
+
+ char str[] = "ECC generation -";
+ char slash[] = "\\|/-\\|/-";
+
+ sync();
+ eieio();
+
+ puts(str);
+
+ if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
+ /* ECC bit set method for non-cached memory */
+ /* This takes various seconds */
+ for(current_address = 0; current_address < num_bytes;
+ current_address += sizeof(u32)) {
+ *(u32 *)current_address = 0;
+ if ((current_address % (2 << 20)) == 0) {
+ putc('\b');
+ putc(slash[loopi++ % 8]);
+ }
+ }
+ } else {
+ /* ECC bit set method for cached memory */
+ /* Fast method, no noticeable delay */
+ dcbz_area(start_address, num_bytes);
+ dflush();
+ }
+ blank_string(strlen(str));
+
+ /* Clear error status */
+ mfsdram(DDR0_00, val);
+ mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+ /* Set 'int_mask' parameter to functionnal value */
+ mfsdram(DDR0_01, val);
+ mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
+ DDR0_01_INT_MASK_ALL_OFF));
+
+ return;
+}
+
+#endif
+
+/***********************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+#define HCU_HW_SDRAM_CONFIG_MASK 0x7
+#define INVALID_HW_CONFIG "Invalid HW-Config"
+ u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
+ unsigned int dram_size = 0;
+
+ mtsdram(DDR0_02, 0x00000000);
+
+ /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02030602);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020307);
+ switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
+ case 0:
+ dram_size = 128 * 1024 * 1024 ;
+ mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
+ mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
+ mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
+ break;
+ case 1:
+ dram_size = 256 * 1024 * 1024 ;
+ mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
+ mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
+ mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
+ break;
+ default:
+ sdram_panic(INVALID_HW_CONFIG);
+ break;
+ }
+ dram_size -= 16 * 1024 * 1024;
+ mtsdram(DDR0_07, 0x00090100);
+ /*
+ * TCPD=200 cycles of clock input is required to lock the DLL.
+ * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
+ */
+ mtsdram(DDR0_08, 0x02C80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1D000000);
+ mtsdram(DDR0_18, 0x1D1D1D1D);
+ mtsdram(DDR0_19, 0x1D1D1D1D);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+ #define ECC_RAM 0x03267F0B
+ #define NO_ECC_RAM 0x00267F0B
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, ECC_RAM);
+#else
+ mtsdram(DDR0_22, NO_ECC_RAM);
+#endif
+
+ mtsdram(DDR0_23, 0x00000000);
+ mtsdram(DDR0_24, 0x01020001);
+ mtsdram(DDR0_26, 0x2D930517);
+ mtsdram(DDR0_27, 0x00008236);
+ mtsdram(DDR0_28, 0x00000000);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000006);
+ mtsdram(DDR0_44, 0x00000003);
+ mtsdram(DDR0_02, 0x00000001);
+ wait_for_dlllock();
+ mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
+
+ /*
+ * Program tlb entries for this size (dynamic)
+ */
+ program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
+ /*
+ * Setup 2nd TLB with same physical address but different virtual
+ * address with cache enabled. This is done for fast ECC generation.
+ */
+ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+
+#ifdef CONFIG_DDR_ECC
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
+#endif
+
+ return (dram_size);
+}
diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds
new file mode 100644
index 0000000..6d255a9
--- /dev/null
+++ b/board/netstal/hcu5/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/zeus/Makefile b/board/zeus/Makefile
new file mode 100644
index 0000000..f0d4e9f
--- /dev/null
+++ b/board/zeus/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o update.o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/zeus/config.mk b/board/zeus/config.mk
new file mode 100644
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/zeus/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/zeus/u-boot.lds b/board/zeus/u-boot.lds
new file mode 100644
index 0000000..73b83eb
--- /dev/null
+++ b/board/zeus/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/zeus/update.c b/board/zeus/update.c
new file mode 100644
index 0000000..c76519f
--- /dev/null
+++ b/board/zeus/update.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+#if defined(CONFIG_ZEUS)
+
+u8 buf_zeus_ce[] = {
+/*00 01 02 03 04 05 06 07 */
+ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08 09 0a 0b 0c 0d 0e 0f */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10 11 12 13 14 15 16 17 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18 19 1a 1b 1c 1d 1e 1f */
+ 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
+
+u8 buf_zeus_pe[] = {
+
+/* CPU_CLOCK_DIV 1 = 00
+ CPU_PLB_FREQ_DIV 3 = 10
+ OPB_PLB_FREQ_DIV 2 = 01
+ EBC_PLB_FREQ_DIV 2 = 00
+ MAL_PLB_FREQ_DIV 1 = 00
+ PCI_PLB_FRQ_DIV 3 = 10
+ PLL_PLLOUTA = IS SET
+ PLL_OPERATING = IS NOT SET
+ PLL_FDB_MUL 10 = 1010
+ PLL_FWD_DIV_A 3 = 101
+ PLL_FWD_DIV_B 3 = 101
+ TUNE = 0x2be */
+/*00 01 02 03 04 05 06 07 */
+ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08 09 0a 0b 0c 0d 0e 0f */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10 11 12 13 14 15 16 17 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18 19 1a 1b 1c 1d 1e 1f */
+ 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
+
+static int update_boot_eeprom(void)
+{
+ u32 len = 0x20;
+ u8 chip = CFG_I2C_EEPROM_ADDR;
+ u8 *pbuf;
+ u8 base;
+ int i;
+
+ if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
+ pbuf = buf_zeus_pe;
+ base = 0x40;
+ } else {
+ pbuf = buf_zeus_ce;
+ base = 0x00;
+ }
+
+ for (i = 0; i < len; i++, base++) {
+ if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
+ printf("i2c_write fail\n");
+ return 1;
+ }
+ udelay(11000);
+ }
+
+ return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
+{
+ return update_boot_eeprom();
+}
+
+U_BOOT_CMD (
+ update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+ "update_boot_eeprom - update boot eeprom content\n",
+ NULL
+);
+
+#endif
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
new file mode 100644
index 0000000..4ab853f
--- /dev/null
+++ b/board/zeus/zeus.c
@@ -0,0 +1,511 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REBOOT_MAGIC 0x07081967
+#define REBOOT_NOP 0x00000000
+#define REBOOT_DO_POST 0x00000001
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern env_t *env_ptr;
+extern uchar default_environment[];
+
+ulong flash_get_size(ulong base, int banknum);
+void env_crc_update(void);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+static u32 start_time;
+
+int board_early_init_f(void)
+{
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000);
+ mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
+ mtdcr(uictr, 0x00000000); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ */
+ mtdcr(cpc0_pci, CPC0_PCI_SPE);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 pbcr;
+ int size_val = 0;
+ u32 post_magic;
+ u32 post_val;
+
+ post_magic = in_be32((void *)CFG_POST_MAGIC);
+ post_val = in_be32((void *)CFG_POST_VAL);
+ if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
+ /*
+ * Set special bootline bootparameter to pass this POST boot
+ * mode to Linux to reset the username/password
+ */
+ setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
+
+ /*
+ * Normally don't run POST tests, only when enabled
+ * via the sw-reset button. So disable further tests
+ * upon next bootup here.
+ */
+ out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
+ } else {
+ /*
+ * Only run POST when initiated via the sw-reset button mechanism
+ */
+ post_word_store(0);
+ }
+
+ /*
+ * Get current time
+ */
+ start_time = get_timer(0);
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ mfebc(pb0cr, pbcr);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(pb0cr, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: Zeus-");
+
+ if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
+ puts("PE");
+ else
+ puts("CE");
+
+ puts(" of BulletEndPoint");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ /* both LED's off */
+ gpio_write_bit(CFG_GPIO_LED_RED, 0);
+ gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
+ udelay(10000);
+ /* and on again */
+ gpio_write_bit(CFG_GPIO_LED_RED, 1);
+ gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
+
+ return (0);
+}
+
+static u32 detect_sdram_size(void)
+{
+ u32 val;
+ u32 size;
+
+ mfsdram(mem_mb0cf, val);
+ size = (4 << 20) << ((val & 0x000e0000) >> 17);
+
+ /*
+ * Check if 2nd bank is enabled too
+ */
+ mfsdram(mem_mb1cf, val);
+ if (val & 1)
+ size += (4 << 20) << ((val & 0x000e0000) >> 17);
+
+ return size;
+}
+
+long int initdram (int board_type)
+{
+ return detect_sdram_size();
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+ unsigned long msr;
+ unsigned long total_kbytes;
+
+ total_kbytes = detect_sdram_size();
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_EE));
+
+ for (k = 0; k < total_kbytes ;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ mtmsr(msr);
+
+ return 0;
+}
+#endif
+
+static int default_env_var(char *buf, char *var)
+{
+ char *ptr;
+ char *val;
+
+ /*
+ * Find env variable
+ */
+ ptr = strstr(buf + 4, var);
+ if (ptr == NULL) {
+ printf("ERROR: %s not found!\n", var);
+ return -1;
+ }
+ ptr += strlen(var) + 1;
+
+ /*
+ * Now the ethaddr needs to be updated in the "normal"
+ * environment storage -> redundant flash.
+ */
+ val = ptr;
+ setenv(var, val);
+ printf("Updated %s from eeprom to %s!\n", var, val);
+
+ return 0;
+}
+
+static int restore_default(void)
+{
+ char *buf;
+ char *buf_save;
+ u32 crc;
+
+ /*
+ * Unprotect and erase environment area
+ */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ flash_sect_erase(CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1);
+
+ /*
+ * Now restore default environment from U-Boot image
+ * -> ipaddr, serverip...
+ */
+ memset(env_ptr, 0, sizeof(env_t));
+ memcpy(env_ptr->data, default_environment, ENV_SIZE);
+#ifdef CFG_REDUNDAND_ENVIRONMENT
+ env_ptr->flags = 0xFF;
+#endif
+ env_crc_update();
+ gd->env_valid = 1;
+
+ /*
+ * Read board specific values from I2C EEPROM
+ * and set env variables accordingly
+ * -> ethaddr, eth1addr, serial#
+ */
+ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+ if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+ (u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
+ puts("\nError reading EEPROM!\n");
+ } else {
+ crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
+ if (crc != *(u32 *)buf) {
+ printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf);
+ return -1;
+ }
+
+ default_env_var(buf, "ethaddr");
+ buf += 8 + 18;
+ default_env_var(buf, "eth1addr");
+ buf += 9 + 18;
+ default_env_var(buf, "serial#");
+ }
+
+ /*
+ * Finally save updated env variables back to flash
+ */
+ saveenv();
+
+ free(buf_save);
+
+ return 0;
+}
+
+int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char *buf;
+ char *buf_save;
+ char str[32];
+ u32 crc;
+ char var[32];
+
+ if (argc < 4) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+ memset(buf, 0, FACTORY_RESET_ENV_SIZE);
+
+ strcpy(var, "ethaddr");
+ printf("Setting %s to %s\n", var, argv[1]);
+ sprintf(str, "%s=%s", var, argv[1]);
+ strcpy(buf + 4, str);
+ buf += strlen(str) + 1;
+
+ strcpy(var, "eth1addr");
+ printf("Setting %s to %s\n", var, argv[2]);
+ sprintf(str, "%s=%s", var, argv[2]);
+ strcpy(buf + 4, str);
+ buf += strlen(str) + 1;
+
+ strcpy(var, "serial#");
+ printf("Setting %s to %s\n", var, argv[3]);
+ sprintf(str, "%s=%s", var, argv[3]);
+ strcpy(buf + 4, str);
+
+ crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
+ *(u32 *)buf_save = crc;
+
+ if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+ (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
+ puts("\nError writing EEPROM!\n");
+ return -1;
+ }
+
+ free(buf_save);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setdef, 4, 1, do_set_default,
+ "setdef - write board-specific values to EEPROM (ethaddr...)\n",
+ "ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
+ );
+
+static inline int sw_reset_pressed(void)
+{
+ return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
+}
+
+int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
+{
+ int delta;
+ int count = 0;
+ int post = 0;
+ int factory_reset = 0;
+
+ if (!sw_reset_pressed()) {
+ printf("SW-Reset already high (Button released)\n");
+ printf("-> No action taken!\n");
+ return 0;
+ }
+
+ printf("Waiting for SW-Reset button to be released.");
+
+ while (1) {
+ delta = get_timer(start_time);
+ if (!sw_reset_pressed())
+ break;
+
+ if ((delta > CFG_TIME_POST) && !post) {
+ printf("\nWhen released now, POST tests will be started.");
+ gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
+ post = 1;
+ }
+
+ if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
+ printf("\nWhen released now, factory default values"
+ " will be restored.");
+ gpio_write_bit(CFG_GPIO_LED_RED, 0);
+ factory_reset = 1;
+ }
+
+ udelay(1000);
+ if (!(count++ % 1000))
+ printf(".");
+ }
+
+
+ printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
+
+ if (delta > CFG_TIME_FACTORY_RESET) {
+ printf("Starting factory reset value restoration...\n");
+
+ /*
+ * Restore default setting
+ */
+ restore_default();
+
+ /*
+ * Reset the board for default to become valid
+ */
+ do_reset(NULL, 0, 0, NULL);
+
+ return 0;
+ }
+
+ if (delta > CFG_TIME_POST) {
+ printf("Starting POST configuration...\n");
+
+ /*
+ * Enable POST upon next bootup
+ */
+ out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
+ out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
+ post_bootmode_init();
+
+ /*
+ * Reset the logbuffer for a clean start
+ */
+ logbuff_reset();
+
+ do_reset(NULL, 0, 0, NULL);
+
+ return 0;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ chkreset, 1, 1, do_chkreset,
+ "chkreset- Check for status of SW-reset button and act accordingly\n",
+ NULL
+);
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ u32 post_magic;
+ u32 post_val;
+
+ post_magic = in_be32((void *)CFG_POST_MAGIC);
+ post_val = in_be32((void *)CFG_POST_VAL);
+
+ if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
+ return 1;
+ else
+ return 0;
+}
+#endif /* CONFIG_POST */
diff --git a/common/flash.c b/common/flash.c
index a64bc98..888ff9c 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -47,16 +47,16 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
short s_end = info->sector_count - 1; /* index of last sector */
int i;
- debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n",
- (flag & FLAG_PROTECT_SET) ? "ON" :
- (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???",
- from, to);
-
/* Do nothing if input data is bad. */
if (info->sector_count == 0 || info->size == 0 || to < from) {
return;
}
+ debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n",
+ (flag & FLAG_PROTECT_SET) ? "ON" :
+ (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???",
+ from, to);
+
/* There is nothing to do if we have no data about the flash
* or the protect range and flash range don't overlap.
*/
diff --git a/common/soft_spi.c b/common/soft_spi.c
index 00a57de..e425061 100644
--- a/common/soft_spi.c
+++ b/common/soft_spi.c
@@ -79,7 +79,9 @@ void spi_init (void)
*/
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
{
+#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
uchar tmpdin = 0;
uchar tmpdout = 0;
int j;
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index d6c4be5..bf68cc1 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
@@ -40,6 +40,34 @@ enum {
LNKW_X8 = 0x8
};
+static inline int pcie_in_8(const volatile unsigned char __iomem *addr)
+{
+ int ret;
+
+ PCIE_IN(lbzx, ret, addr);
+
+ return ret;
+}
+
+static inline int pcie_in_le16(const volatile unsigned short __iomem *addr)
+{
+ int ret;
+
+ PCIE_IN(lhbrx, ret, addr)
+
+ return ret;
+}
+
+static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr)
+{
+ unsigned ret;
+
+ PCIE_IN(lwbrx, ret, addr);
+
+ return ret;
+}
+
+
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
@@ -55,13 +83,13 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
switch (len) {
case 1:
- *val = in_8(hose->cfg_data + offset);
+ *val = pcie_in_8(hose->cfg_data + offset);
break;
case 2:
- *val = in_le16((u16 *)(hose->cfg_data + offset));
+ *val = pcie_in_le16((u16 *)(hose->cfg_data + offset));
break;
default:
- *val = in_le32((u32 *)(hose->cfg_data + offset));
+ *val = pcie_in_le32((u32*)(hose->cfg_data + offset));
break;
}
return 0;
@@ -783,9 +811,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
/*
* Set bus numbers on our root port
*/
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+ if (ppc440spe_revB()) {
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+ out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+ } else {
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
+ }
/*
* Set up outbound translation to hose->mem_space from PLB
diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h
index 2becc77..eb7cecf 100644
--- a/cpu/ppc4xx/440spe_pcie.h
+++ b/cpu/ppc4xx/440spe_pcie.h
@@ -145,8 +145,8 @@
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
-#define PECFG_PIM1LAL 0x348
-#define PECFG_PIM1LAH 0x34c
+#define PECFG_PIM1LAL 0x348
+#define PECFG_PIM1LAH 0x34c
#define PECFG_PIM01SAL 0x350
#define PECFG_PIM01SAH 0x354
@@ -161,6 +161,21 @@
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
+#define PCIE_IN(opcode, ret, addr) \
+ __asm__ __volatile__( \
+ "sync\n" \
+ #opcode " %0,0,%1\n" \
+ "1: twi 0,%0,0\n" \
+ "isync\n" \
+ "b 3f\n" \
+ "2: li %0,-1\n" \
+ "3:\n" \
+ ".section __ex_table,\"a\"\n" \
+ ".balign 4\n" \
+ ".long 1b,2b\n" \
+ ".previous\n" \
+ : "=r" (ret) : "r" (addr), "m" (*addr));
+
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);
void yucca_setup_pcie_fpga_rootpoint(int port);
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index 6d6fba1..4a4c6f2 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -269,9 +269,8 @@ struct bank_param {
typedef struct bank_param BANKPARMS;
#ifdef CFG_SIMULATE_SPD_EEPROM
-extern unsigned char cfg_simulate_spd_eeprom[128];
+extern const unsigned char cfg_simulate_spd_eeprom[128];
#endif
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static unsigned char spd_read(uchar chip, uint addr);
static void get_spd_info(unsigned long *dimm_populated,
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 5fef27b..18b90ba 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -109,7 +109,7 @@
/* Defines for the Read Cycle Delay test */
#define NUMMEMTESTS 8
#define NUMMEMWORDS 8
-#define NUMLOOPS 256 /* memory test loops */
+#define NUMLOOPS 64 /* memory test loops */
#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
@@ -138,6 +138,26 @@ void __spd_ddr_init_hang (void)
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+/*
+ * To provide an interface for board specific config values in this common
+ * DDR setup code, we implement he "weak" default functions here. They return
+ * the default value back to the caller.
+ *
+ * Please see include/configs/yucca.h for an example fora board specific
+ * implementation.
+ */
+u32 __ddr_wrdtr(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
+
+u32 __ddr_clktr(u32 default_val)
+{
+ return default_val;
+}
+u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
+
/* Private Structure Definitions */
@@ -154,7 +174,6 @@ typedef enum ddr_cas_id {
* Prototypes
*-----------------------------------------------------------------------------*/
static unsigned long sdram_memsize(void);
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static void get_spd_info(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
@@ -216,9 +235,7 @@ static void test(void);
#else
static void DQS_calibration_process(void);
#endif
-#if defined(DEBUG)
static void ppc440sp_sdram_register_dump(void);
-#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
@@ -469,17 +486,14 @@ long int initdram(int board_type)
*-----------------------------------------------------------------*/
mfsdram(SDRAM_WRDTR, val);
mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
- (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
+ ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
/*------------------------------------------------------------------
* Set the SDRAM Clock Timing Register
*-----------------------------------------------------------------*/
mfsdram(SDRAM_CLKTR, val);
-#ifdef CFG_44x_DDR2_CKTR_180
- mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
-#else
- mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
-#endif
+ mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
+ ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
/*------------------------------------------------------------------
* Program the BxCF registers.
@@ -538,7 +552,12 @@ long int initdram(int board_type)
dram_size = sdram_memsize();
/* and program tlb entries for this size (dynamic) */
- program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
+ /*
+ * Program TLB entries with caches enabled, for best performace
+ * while auto-calibrating and ECC generation
+ */
+ program_tlb(0, 0, dram_size, 0);
/*------------------------------------------------------------------
* DQS calibration.
@@ -549,12 +568,18 @@ long int initdram(int board_type)
/*------------------------------------------------------------------
* If ecc is enabled, initialize the parity bits.
*-----------------------------------------------------------------*/
- program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
+ program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
#endif
-#ifdef DEBUG
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(0, dram_size);
+ program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
ppc440sp_sdram_register_dump();
-#endif
return dram_size;
}
@@ -2703,6 +2728,7 @@ calibration_loop:
printf("\nERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
+ ppc440sp_sdram_register_dump();
spd_ddr_init_hang ();
}
@@ -3028,5 +3054,9 @@ static void ppc440sp_sdram_register_dump(void)
dcr_data = mfdcr(SDRAM_R3BAS);
printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
}
+#else
+static void ppc440sp_sdram_register_dump(void)
+{
+}
#endif
#endif /* CONFIG_SPD_EEPROM */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index d782791..cc8e734 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -1415,10 +1415,8 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
|| (loop_count >= NUM_RX_BUFF))
break;
+
loop_count++;
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
handled++;
data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
if (data_len) {
@@ -1468,6 +1466,10 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
if (NUM_RX_BUFF == hw_p->rx_i_index)
hw_p->rx_i_index = 0;
+ hw_p->rx_slot++;
+ if (NUM_RX_BUFF == hw_p->rx_slot)
+ hw_p->rx_slot = 0;
+
/* AS.HARNOIS
* free receive buffer only when
* buffer has been handled (eth_rx)
diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index 5235203..50f2fdf 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -186,6 +186,7 @@ void gpio_set_chip_configuration(void)
out32(GPIO0_TCR, reg);
}
+#ifdef GPIO1
if (gpio_core == GPIO1) {
/*
* Setup output value
@@ -193,16 +194,17 @@ void gpio_set_chip_configuration(void)
* 0 -> low level
* else -> don't touch
*/
- reg = in32(GPIO0_OR);
+ reg = in32(GPIO1_OR);
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
reg |= (0x80000000 >> (i));
else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
reg &= ~(0x80000000 >> (i));
- out32(GPIO0_OR, reg);
+ out32(GPIO1_OR, reg);
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
out32(GPIO1_TCR, reg);
}
+#endif /* GPIO1 */
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index d520cd3..2724d91 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -187,14 +187,14 @@ void sdram_init(void)
/*
* Disable memory controller.
*/
- mtsdram0(mem_mcopt1, 0x00000000);
+ mtsdram(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
- mtsdram0(mem_mb0cf, mb0cf[i].reg);
- mtsdram0(mem_sdtr1, sdtr1);
- mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
+ mtsdram(mem_mb0cf, mb0cf[i].reg);
+ mtsdram(mem_sdtr1, sdtr1);
+ mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@@ -203,14 +203,34 @@ void sdram_init(void)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
- mtsdram0(mem_mcopt1, 0x80800000);
+ mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
/*
- * OK, size detected -> all done
+ * OK, size detected. Enable second bank if
+ * defined (assumes same type as bank 0)
*/
+#ifdef CONFIG_SDRAM_BANK1
+ u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
+
+ mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+ mtsdram(mem_mcopt1, 0x80800000);
+ udelay(10000);
+
+ /*
+ * Check if 2nd bank is really available.
+ * If the size not equal to the size of the first
+ * bank, then disable the 2nd bank completely.
+ */
+ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
+ mb0cf[i].size) {
+ mtsdram(mem_mb1cf, 0);
+ mtsdram(mem_mcopt1, 0);
+ }
+#endif
return;
}
}
diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h
index 62b5442..4fb9b1a 100644
--- a/cpu/ppc4xx/sdram.h
+++ b/cpu/ppc4xx/sdram.h
@@ -29,8 +29,6 @@
#include <config.h>
-#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-
#define ONE_BILLION 1000000000
struct sdram_conf_s {
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 3f67136..60712b1 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -448,12 +448,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned long i;
unsigned long est; /* current estimate */
unsigned long plloutb;
+ unsigned long cpr_pllc;
u32 reg;
+ /* check the pll feedback source */
+ mfcpr(cprpllc, cpr_pllc);
+
get_sys_info(&sysinfo);
- plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
- / sysinfo.pllFwdDivB);
+ plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
+ sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) /
+ sysinfo.pllFwdDivB);
udiv = 256; /* Assume lowest possible serial clk */
div = plloutb / (16 * baudrate); /* total divisor */
umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 028b11a..da5330a 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -771,6 +771,7 @@ ulong get_PCI_freq (void)
void get_sys_info (PPC405_SYS_INFO * sysInfo)
{
unsigned long cpr_plld;
+ unsigned long cpr_pllc;
unsigned long cpr_primad;
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
unsigned long primad_cpudv;
@@ -780,6 +781,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
* Read PLL Mode registers
*/
mfcpr(cprplld, cpr_plld);
+ mfcpr(cprpllc, cpr_pllc);
/*
* Determine forward divider A
@@ -787,20 +789,18 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
/*
- * Determine forward divider B (should be equal to A)
+ * Determine forward divider B
*/
sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
- if (sysInfo->pllFwdDivB == 0) {
+ if (sysInfo->pllFwdDivB == 0)
sysInfo->pllFwdDivB = 8;
- }
/*
* Determine FBK_DIV.
*/
sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
- if (sysInfo->pllFbkDiv == 0) {
+ if (sysInfo->pllFbkDiv == 0)
sysInfo->pllFbkDiv = 256;
- }
/*
* Read CPR_PRIMAD register
@@ -810,30 +810,30 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
* Determine PLB_DIV.
*/
sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
- if (sysInfo->pllPlbDiv == 0) {
+ if (sysInfo->pllPlbDiv == 0)
sysInfo->pllPlbDiv = 16;
- }
/*
* Determine EXTBUS_DIV.
*/
sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
- if (sysInfo->pllExtBusDiv == 0) {
+ if (sysInfo->pllExtBusDiv == 0)
sysInfo->pllExtBusDiv = 16;
- }
/*
* Determine OPB_DIV.
*/
sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
- if (sysInfo->pllOpbDiv == 0) {
+ if (sysInfo->pllOpbDiv == 0)
sysInfo->pllOpbDiv = 16;
- }
/*
* Determine the M factor
*/
- m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
+ if (cpr_pllc & PLLC_SRC_MASK)
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
+ else
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
/*
* Determine VCO clock frequency
@@ -845,16 +845,17 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
* Determine CPU clock frequency
*/
primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
- if (primad_cpudv == 0) {
+ if (primad_cpudv == 0)
primad_cpudv = 16;
- }
- sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
+ sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) /
+ sysInfo->pllFwdDiv / primad_cpudv;
/*
* Determine PLB clock frequency
*/
- sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
+ sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
+ sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
}
/********************************************
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 8ecaaea..9626b65 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1870,28 +1870,6 @@ ppc405ep_init:
mtdcr ebccfgd,r3
#endif
-#ifndef CFG_CPC0_PCI
- li r3,CPC0_PCI_HOST_CFG_EN
-#ifdef CONFIG_BUBINGA
- /*
- !-----------------------------------------------------------------------
- ! Check FPGA for PCI internal/external arbitration
- ! If board is set to internal arbitration, update cpc0_pci
- !-----------------------------------------------------------------------
- */
- addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
- ori r5,r5,FPGA_REG1@l
- lbz r5,0x0(r5) /* read to get PCI arb selection */
- andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
- beq ..pci_cfg_set /* if not set, then bypass reg write*/
-#endif
- ori r3,r3,CPC0_PCI_ARBIT_EN
-#else /* CFG_CPC0_PCI */
- li r3,CFG_CPC0_PCI
-#endif /* CFG_CPC0_PCI */
-..pci_cfg_set:
- mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
-
/*
!-----------------------------------------------------------------------
! Check to see if chip is in bypass mode.
@@ -1947,11 +1925,50 @@ ppc405ep_init:
..no_pllset:
#endif /* CONFIG_BUBINGA */
+#ifdef CONFIG_TAIHU
+ mfdcr r4, CPC0_BOOT
+ andi. r5, r4, CPC0_BOOT_SEP@l
+ bne strap_1 /* serial eeprom present */
+ addis r5,0,CPLD_REG0_ADDR@h
+ ori r5,r5,CPLD_REG0_ADDR@l
+ andi. r5, r5, 0x10
+ bne _pci_66mhz
+#endif /* CONFIG_TAIHU */
+
+#if defined(CONFIG_ZEUS)
+ mfdcr r4, CPC0_BOOT
+ andi. r5, r4, CPC0_BOOT_SEP@l
+ bne strap_1 /* serial eeprom present */
+ lis r3,0x0000
+ addi r3,r3,0x3030
+ lis r4,0x8042
+ addi r4,r4,0x223e
+ b 1f
+strap_1:
+ mfdcr r3, CPC0_PLLMR0
+ mfdcr r4, CPC0_PLLMR1
+ b 1f
+#endif
+
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
ori r4,r4,PLLMR1_DEFAULT@l /* */
+#ifdef CONFIG_TAIHU
+ b 1f
+_pci_66mhz:
+ addis r3,0,PLLMR0_DEFAULT_PCI66@h
+ ori r3,r3,PLLMR0_DEFAULT_PCI66@l
+ addis r4,0,PLLMR1_DEFAULT_PCI66@h
+ ori r4,r4,PLLMR1_DEFAULT_PCI66@l
+ b 1f
+strap_1:
+ mfdcr r3, CPC0_PLLMR0
+ mfdcr r4, CPC0_PLLMR1
+#endif /* CONFIG_TAIHU */
+
+1:
b pll_write /* Write the CPC0_PLLMR with new value */
pll_done:
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index 049a785..098694c 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -25,7 +25,6 @@
#if defined(CONFIG_440)
-#include <ppc4xx.h>
#include <ppc440.h>
#include <asm/io.h>
#include <asm/mmu.h>
@@ -36,6 +35,67 @@ typedef struct region {
unsigned long tlb_word2_i_value;
} region_t;
+void remove_tlb(u32 vaddr, u32 size)
+{
+ int i;
+ u32 tlb_word0_value;
+ u32 tlb_vaddr;
+ u32 tlb_size = 0;
+
+ /* First, find the index of a TLB entry not being used */
+ for (i=0; i<PPC4XX_TLB_SIZE; i++) {
+ tlb_word0_value = mftlb1(i);
+ tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
+ if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
+ (tlb_vaddr >= vaddr)) {
+ /*
+ * TLB is enabled and start address is lower or equal
+ * than the area we are looking for. Now we only have
+ * to check the size/end address for a match.
+ */
+ switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
+ case TLB_WORD0_SIZE_1KB:
+ tlb_size = 1 << 10;
+ break;
+ case TLB_WORD0_SIZE_4KB:
+ tlb_size = 4 << 10;
+ break;
+ case TLB_WORD0_SIZE_16KB:
+ tlb_size = 16 << 10;
+ break;
+ case TLB_WORD0_SIZE_64KB:
+ tlb_size = 64 << 10;
+ break;
+ case TLB_WORD0_SIZE_256KB:
+ tlb_size = 256 << 10;
+ break;
+ case TLB_WORD0_SIZE_1MB:
+ tlb_size = 1 << 20;
+ break;
+ case TLB_WORD0_SIZE_16MB:
+ tlb_size = 16 << 20;
+ break;
+ case TLB_WORD0_SIZE_256MB:
+ tlb_size = 256 << 20;
+ break;
+ }
+
+ /*
+ * Now check the end-address if it's in the range
+ */
+ if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
+ /*
+ * Found a TLB in the range.
+ * Disable it by writing 0 to tlb0 word.
+ */
+ mttlb1(i, 0);
+ }
+ }
+
+ /* Execute an ISYNC instruction so that the new TLB entry takes effect */
+ asm("isync");
+}
+
static int add_tlb_entry(unsigned long phys_addr,
unsigned long virt_addr,
unsigned long tlb_word0_size_value,
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 899cdbd..f5365cb 100644
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -147,14 +147,21 @@ MachineCheckException(struct pt_regs *regs)
unsigned long fixup, val;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
u32 value2;
+ int corr_ecc = 0;
+ int uncorr_ecc = 0;
#endif
- /* Probing PCI using config cycles cause this exception
- * when a device is not present. Catch it and return to
- * the PCI exception handler.
+ /* Probing PCI(E) using config cycles may cause this exception
+ * when a device is not present. To gracefully recover in such
+ * scenarios config read/write routines need to be instrumented in
+ * order to return via fixup handler. For examples refer to
+ * pcie_in_8(), pcie_in_le16() and pcie_in_le32()
*/
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
+ val = mfspr(MCSR);
+ /* Clear MCSR */
+ mtspr(SPRN_MCSR, val);
return;
}
@@ -214,14 +221,22 @@ MachineCheckException(struct pt_regs *regs)
printf("DDR0: At least one interrupt active\n");
if (val & 0x40)
printf("DDR0: DRAM initialization complete.\n");
- if (val & 0x20)
+ if (val & 0x20) {
printf("DDR0: Multiple uncorrectable ECC events.\n");
- if (val & 0x10)
+ uncorr_ecc = 1;
+ }
+ if (val & 0x10) {
printf("DDR0: Single uncorrectable ECC event.\n");
- if (val & 0x08)
+ uncorr_ecc = 1;
+ }
+ if (val & 0x08) {
printf("DDR0: Multiple correctable ECC events.\n");
- if (val & 0x04)
+ corr_ecc = 1;
+ }
+ if (val & 0x04) {
printf("DDR0: Single correctable ECC event.\n");
+ corr_ecc = 1;
+ }
if (val & 0x02)
printf("Multiple accesses outside the defined"
" physical memory space detected\n");
@@ -252,11 +267,11 @@ MachineCheckException(struct pt_regs *regs)
printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
}
mfsdram(DDR0_23, val);
- if ( (val >> 16) & 0xff)
+ if (((val >> 16) & 0xff) && corr_ecc)
printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
(val >> 16) & 0xff);
mfsdram(DDR0_23, val);
- if ( (val >> 8) & 0xff)
+ if (((val >> 8) & 0xff) && uncorr_ecc)
printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
(val >> 8) & 0xff);
mfsdram(DDR0_33, val);
@@ -264,28 +279,28 @@ MachineCheckException(struct pt_regs *regs)
printf("DDR0: Address of command that caused an "
"Out-of-Range interrupt %p\n", val);
mfsdram(DDR0_34, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_35, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_36, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_37, val);
- if (val)
+ if (val && uncorr_ecc)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_38, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_39, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_40, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
mfsdram(DDR0_41, val);
- if (val)
+ if (val && corr_ecc)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
#endif /* CONFIG_440EPX */
#endif /* CONFIG_440 */
diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c
index 2837b37..272ed8c 100644
--- a/cpu/ppc4xx/usb.c
+++ b/cpu/ppc4xx/usb.c
@@ -27,7 +27,7 @@
#include "usbdev.h"
-int usb_cpu_init()
+int usb_cpu_init(void)
{
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
@@ -37,12 +37,12 @@ int usb_cpu_init()
return 0;
}
-int usb_cpu_stop()
+int usb_cpu_stop(void)
{
return 0;
}
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
{
return 0;
}
diff --git a/doc/README.bamboo b/doc/README.bamboo
index b50be01..e139c6d 100644
--- a/doc/README.bamboo
+++ b/doc/README.bamboo
@@ -1,3 +1,65 @@
+The 2 important dipswitches are configured as shown below:
+
+SW1 (for 33MHz SysClk)
+----------------------
+S1 S2 S3 S4 S5 S6 S7 S8
+OFF OFF OFF OFF OFF OFF OFF ON
+
+SW7 (for Op-Code Flash and Boot Option H)
+-----------------------------------------
+S1 S2 S3 S4 S5 S6 S7 S8
+OFF OFF OFF ON OFF OFF OFF OFF
+
+The EEPROM at location 0x52 is loaded with these 16 bytes:
+C47042A6 05D7A190 40082350 0d050000
+
+SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
+SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
+SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
+SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
+SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
+SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
+SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
+SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
+SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
+SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
+SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
+SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
+SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
+SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
+SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
+SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
+SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
+SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
+SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
+SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
+SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
+SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
+SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
+SDR0_SDSTP0[NE]: 0 : NDFC: disabled
+SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
+SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
+SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
+SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
+SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
+SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
+SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
+SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
+SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
+SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
+SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
+
+PPC440EP Clocking Configuration
+
+SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
+OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
+
+The above information is reported by Eugene O'Brien
+<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
+
+2007-08-06, Stefan Roese <sr@denx.de>
+---------------------------------------------------------------------
+
The configuration for the AMCC 440EP eval board "Bamboo" was changed
to only use 384 kbytes of FLASH for the U-Boot image. This way the
redundant environment can be saved in the remaining 2 sectors of the
diff --git a/doc/README.zeus b/doc/README.zeus
new file mode 100644
index 0000000..1848d8c
--- /dev/null
+++ b/doc/README.zeus
@@ -0,0 +1,73 @@
+
+Storage of the board specific values (ethaddr...)
+-------------------------------------------------
+
+The board specific environment variables that should be unique
+for each individual board, can be stored in the I2C EEPROM. This
+will be done from offset 0x80 with the length of 0x80 bytes. The
+following command can be used to store the values here:
+
+=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
+
+ ethaddr eth1addr serial#
+
+Now those 3 values are stored into the I2C EEPROM. A CRC is added
+to make sure that the values get not corrupted.
+
+
+SW-Reset Pushbutton handling:
+-----------------------------
+
+The SW-reset push button is connected to a GPIO input too. This
+way U-Boot can "see" how long the SW-reset was pressed, and a
+specific action can be taken. Two different actions are supported:
+
+a) Release after more than 5 seconds and less then 10 seconds:
+ -> Run POST
+
+ Please note, that the POST test will take a while (approx. 1 min
+ on the 128MByte board). This is mainly due to the system memory
+ test.
+
+b) Release after more than 10 seconds:
+ -> Restore factory default settings
+
+ The factory default values are restored. The default environment
+ variables are restored (ipaddr, serverip...) and the board
+ specific values (ethaddr, eth1addr and serial#) are restored
+ to the environment from the I2C EEPROM. Also a bootline parameter
+ is added to the Linux bootline to signal the Linux kernel upon
+ the next startup, that the factory defaults should be restored.
+
+The command to check this sw-reset status and act accordingly is
+
+=> chkreset
+
+This command is added to the default "bootcmd", so that it is called
+automatically upon startup.
+
+Also, the 2 LED's are used to indicate the current status of this
+command (time passed since pushing the button). When the POST test
+will be run, the green LED will be switched off, and when the
+factory restore will be initiated, the reg LED will be switched off.
+
+
+Loggin of POST results:
+-----------------------
+
+The results of the POST tests are logged in a logbuffer located at the end
+of the onboard memory. It can be accessed with the U-Boot command "log":
+
+=> log show
+<4>POST memory PASSED
+<4>POST cache PASSED
+<4>POST cpu PASSED
+<4>POST uart PASSED
+<4>POST ethernet PASSED
+
+The DENX Linux kernel tree has support for this log buffer included. Exactly
+this buffer is used for logging of all kernel messages too. By enabling the
+compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
+can access the U-Boot log messages from Linux too.
+
+2007-08-10, Stefan Roese <sr@denx.de>
diff --git a/dtt/Makefile b/dtt/Makefile
index e6cb128..c6a670a 100644
--- a/dtt/Makefile
+++ b/dtt/Makefile
@@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdtt.a
-COBJS = lm75.o ds1621.o adm1021.o lm81.o
+COBJS = lm75.o ds1621.o adm1021.o lm81.o ds1775.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/dtt/ds1775.c b/dtt/ds1775.c
new file mode 100644
index 0000000..e44cee3
--- /dev/null
+++ b/dtt/ds1775.c
@@ -0,0 +1,156 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DTT_DS1775
+#include <i2c.h>
+#include <dtt.h>
+
+#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */
+
+int dtt_read(int sensor, int reg)
+{
+ int dlen;
+ uchar data[2];
+
+ /*
+ * Calculate sensor address and command
+ */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */
+
+ /*
+ * Prepare to handle 2 byte result
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST))
+ dlen = 2;
+ else
+ dlen = 1;
+
+ /*
+ * Now try to read the register
+ */
+ if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ /*
+ * Handle 2 byte result
+ */
+ if (dlen == 2)
+ return ((int)((short)data[1] + (((short)data[0]) << 8)));
+
+ return (int) data[0];
+}
+
+
+int dtt_write(int sensor, int reg, int val)
+{
+ int dlen;
+ uchar data[2];
+
+ /*
+ * Calculate sensor address and register
+ */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
+
+ /*
+ * Handle various data sizes
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) {
+ dlen = 2;
+ data[0] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[1] = (char)(val & 0xff);
+ } else {
+ dlen = 1;
+ data[0] = (char)(val & 0xff);
+ }
+
+ /*
+ * Write value to device
+ */
+ if (i2c_write(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ return 0;
+}
+
+
+static int _dtt_init(int sensor)
+{
+ int val;
+
+ /*
+ * Setup High Temp
+ */
+ val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_OS, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ /*
+ * Setup Low Temp - hysteresis
+ */
+ val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ /*
+ * Setup configuraton register
+ *
+ * Fault Tolerance limits 4, Thermometer resolution bits is 9,
+ * Polarity = Active Low,continuous conversion mode, Thermostat
+ * mode is interrupt mode
+ */
+ val = 0xa;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ return 0;
+}
+
+
+int dtt_init (void)
+{
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
+
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("DTT%d: FAILED\n", i+1);
+ else
+ printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
+ }
+
+ return (0);
+}
+
+
+int dtt_get_temp(int sensor)
+{
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+}
+
+
+#endif /* CONFIG_DTT_DS1775 */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 48fd982..b3cfa9b 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -645,6 +645,9 @@ void mttlb3(unsigned long index, unsigned long value);
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void remove_tlb(u32 vaddr, u32 size);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 19b29aa..14c5638 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -222,6 +222,8 @@
#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
+#define CONFIG_PROG_SDRAM_TLB
+#undef CFG_DRAM_TEST
/*-----------------------------------------------------------------------
* I2C
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
new file mode 100644
index 0000000..577f459
--- /dev/null
+++ b/include/configs/hcu4.h
@@ -0,0 +1,348 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU4 1 /* Board is HCU4 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */
+#define CONFIG_405GP 1
+#define CONFIG_4xx 1
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+*----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/* ... with on-chip memory here (4KBytes) */
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
+/* Do not set up locked dcache as init ram. */
+#undef CFG_INIT_DCACHE_CS
+
+/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CFG_TEMP_STACK_OCM 1
+
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE 9600
+
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM configuration */
+#define PROM_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the first internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 0
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu4
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/home/diagnose/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/hcu4/uImage\0" \
+ "load=tftp 100000 hcu4/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu4_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/* SPD EEPROM (sdram speed config) disabled */
+#define CONFIG_SPD_EEPROM 1
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB1AP 0x03041200
+#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB2AP 0x02054500
+#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB3AP 0x01840300
+#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB4AP 0x01800300
+#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
new file mode 100644
index 0000000..d0bf251
--- /dev/null
+++ b/include/configs/hcu5.h
@@ -0,0 +1,393 @@
+/*
+ * (C) Copyright 2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU5 1 /* Board is HCU5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xfff00000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CONFIG_BAUDRATE 9600
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO, but
+ CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM and bootstrap configuration */
+#define PROM_SIZE 2048
+#define CFG_BOOSTRAP_OPTION_OFFSET 512
+#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
+#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the second internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 1
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu5
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "bootfile=hcu5/uImage\0" \
+ "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
+ "load=tftp 100000 hcu5/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_CS_1 0xC8000000 /* CAN */
+#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
+#define CFG_CPLD CFG_CS_2
+#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ * Memory Bank 0 (BOOT-FLASH) initialization
+ */
+#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Memory Bank 1 CAN-Chips initialization */
+#define CFG_EBC_PB1AP 0x02054500
+#define CFG_EBC_PB1CR 0xC8018000
+
+/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
+#define CFG_EBC_PB2AP 0x01840300
+#define CFG_EBC_PB2CR 0xCC0BA000
+
+/* Memory Bank 3 IMC-Bus fast mode initialization */
+#define CFG_EBC_PB3AP 0x01800300
+#define CFG_EBC_PB3CR 0xCE0BA000
+
+/* Memory Bank 4 (not used) initialization */
+#undef CFG_EBC_PB4AP
+#undef CFG_EBC_PB4CR
+
+/* Memory Bank 5 (not used) initialization */
+#undef CFG_EBC_PB5AP
+#undef CFG_EBC_PB5CR
+
+#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
+#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+ #define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 72aae09..26dbec9 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -136,7 +136,6 @@
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
#define CONFIG_DDR_ECC 1 /* with ECC support */
-#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */
/*-----------------------------------------------------------------------
* I2C
@@ -213,7 +212,6 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-
/*
* BOOTP options
*/
@@ -222,7 +220,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -230,7 +227,6 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
@@ -242,7 +238,6 @@
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index ef9ab22..604b7d1 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -46,7 +46,7 @@
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_LIME_BASE_0 0xc0000000
#define CFG_LIME_BASE_1 0xc1000000
@@ -74,11 +74,13 @@
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@@ -103,9 +105,11 @@
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH0 0xFC000000
+#define CFG_FLASH1 0xF8000000
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@@ -133,8 +137,26 @@
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
+#define CFG_POST_ECC_ON CFG_POST_ECC
+#else
+#define CFG_POST_ECC_ON 0
#endif
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_ECC_ON | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_FPU | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CONFIG_LOGBUFFER
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
@@ -162,6 +184,8 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=lwmon5\0" \
"netdev=eth0\0" \
+ "unlock=yes\0" \
+ "logversion=2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -183,6 +207,8 @@
"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
"cp.b 200000 FFF80000 80000\0" \
"upd=run load;run update\0" \
+ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
+ "autoscr 200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -223,7 +249,6 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-
/*
* BOOTP options
*/
@@ -232,7 +257,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -247,6 +271,7 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
@@ -259,7 +284,6 @@
#define CONFIG_CMD_USB
#endif
-
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
@@ -322,7 +346,7 @@
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03050200
-#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000)
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
/* Memory Bank 1 (Lime) initialization */
#define CFG_EBC_PB1AP 0x01004380
@@ -342,14 +366,24 @@
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
/* SDRAM Clock frequency adjustment register */
-#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
-/* Lime Clock frequency is to set 133MHz */
+#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
+/* Lime Clock frequency is to set 100MHz */
+#define CFG_LIME_CLOCK_100MHZ 0x00000
+#if 0
+/* Lime Clock frequency for 133MHz */
#define CFG_LIME_CLOCK_133MHZ 0x10000
+#endif
/* SDRAM Parameter register */
#define CFG_LIME_MMR 0xC1FCFFFC
-/* SDRAM parameter value */
+/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ and pixel flare on display when 133MHz was configured. According to
+ SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+#ifdef CFG_LIME_CLOCK_133MHZ
+#define CFG_LIME_MMR_VALUE 0x414FB7F3
+#else
#define CFG_LIME_MMR_VALUE 0x414FB7F2
+#endif
/*-----------------------------------------------------------------------
* GPIO Setup
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
new file mode 100644
index 0000000..d623e56
--- /dev/null
+++ b/include/configs/taihu.h
@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_TAIHU 1 /* on a taihu board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
+#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootfile=/tftpboot/taihu/uImage\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
+ "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
+ "cp.b 200000 FFFC0000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x14 /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SPI
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
+#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
+#define CFG_SDRAM_BANKS 2
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_UART1_CONSOLE 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+#define CONFIG_SOFT_SPI
+#define SPI_SCL spi_scl
+#define SPI_SDA spi_sda
+#define SPI_READ spi_read()
+#define SPI_DELAY udelay(2)
+#ifndef __ASSEMBLY__
+void spi_scl(int);
+void spi_sda(int);
+unsigned char spi_read(void);
+#endif
+
+/* standard dtt sensor configuration */
+#define CONFIG_DTT_DS1775 1
+#define CONFIG_DTT_SENSORS { 0 }
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CONFIG_EEPRO100 1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFE00000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PPC405 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
+} \
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization */
+#define CFG_EBC_PB0AP 0x03815600
+#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CFG_EBC_PB1AP 0x05815600
+#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (USB device) initialization */
+#define CFG_EBC_PB2AP 0x03016600
+#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (LCM and D-flip-flop) initialization */
+#define CFG_EBC_PB3AP 0x158FF600
+#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (not install) initialization */
+#define CFG_EBC_PB4AP 0x158FF600
+#define CFG_EBC_PB4CR 0x5021A000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
+#define CFG_GPIO0_OSRL 0x00000110
+#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
+#define CFG_GPIO0_ISR1L 0x15545440
+#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
+#define CFG_GPIO0_ODR 0x00000000 /* open drain */
+
+#define GPIO0 0 /* GPIO controller 0 */
+
+/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
+
+#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
+#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
+#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
+#define GPIO_IS2(x) (x+GPIOx_IS1L)
+#define GPIO_IS3(x) (x+GPIOx_IS1L)
+
+#define CPLD_REG0_ADDR 0x50100000
+#define CPLD_REG1_ADDR 0x50100001
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
new file mode 100644
index 0000000..605755a
--- /dev/null
+++ b/include/configs/zeus.h
@@ -0,0 +1,382 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * zeus.h - configuration for Zeus board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ZEUS 1 /* Board is Zeus */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EP 1 /* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x01 /* PHY address */
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_CACHE | \
+ CFG_POST_UART | \
+ CFG_POST_ETHER)
+
+#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CFG_POST_UART_TABLE {UART0_BASE}
+
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
+#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * The layout of the I2C EEPROM, used for bootstrap setup and for board-
+ * specific values, like ethaddr... that can be restored via the sw-reset
+ * button
+ */
+#define FACTORY_RESET_I2C_EEPROM 0x50
+#define FACTORY_RESET_ENV_OFFS 0x80
+#define FACTORY_RESET_ENV_SIZE 0x80
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+/* extra data in OCM */
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
+#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash 16M) initialization */
+#define CFG_EBC_PB0AP 0x05815600
+#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
+#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
+#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
+#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
+#define CFG_GPIO0_TSRH 0x00000000
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
+#define CFG_GPIO0_ODR 0x00000000
+
+#define CFG_GPIO_SW_RESET 1
+#define CFG_GPIO_ZEUS_PE 12
+#define CFG_GPIO_LED_RED 22
+#define CFG_GPIO_LED_GREEN 23
+
+/* Time in milli-seconds */
+#define CFG_TIME_POST 5000
+#define CFG_TIME_FACTORY_RESET 10000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
+#define CONFIG_IPADDR 192.168.1.10
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_GATEWAYIP 192.168.1.100
+#define CONFIG_ETHADDR 50:00:00:00:06:00
+#define CONFIG_ETH1ADDR 50:00:00:00:06:01
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "logversion=2\0" \
+ "hostname=zeus\0" \
+ "netdev=eth0\0" \
+ "ethact=ppc_4xx_eth0\0" \
+ "netmask=255.255.255.0\0" \
+ "ramdisk_size=50000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw" \
+ " nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw" \
+ " ramdisk=${ramdisk_size}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0," \
+ "${baudrate}\0" \
+ "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "run nfsargs addip addtty;bootm\0" \
+ "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "tftp ${ramdisk_mem_addr} ${file_fs};" \
+ "run ramargs addip addtty;" \
+ "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
+ "rootpath=/target_fs/zeus\0" \
+ "kernel_fl_addr=ff000000\0" \
+ "kernel_mem_addr=200000\0" \
+ "ramdisk_fl_addr=ff300000\0" \
+ "ramdisk_mem_addr=4000000\0" \
+ "uboot_fl_addr=fffc0000\0" \
+ "uboot_mem_addr=100000\0" \
+ "file_uboot=/zeus/u-boot.bin\0" \
+ "tftp_uboot=tftp 100000 ${file_uboot}\0" \
+ "update_uboot=protect off fffc0000 ffffffff;" \
+ "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
+ "protect on fffc0000 ffffffff\0" \
+ "upd_uboot=run tftp_uboot;run update_uboot\0" \
+ "file_kernel=/zeus/uImage_ba\0" \
+ "tftp_kernel=tftp 100000 ${file_kernel}\0" \
+ "update_kernel=protect off ff000000 ff17ffff;" \
+ "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
+ "upd_kernel=run tftp_kernel;run update_kernel\0" \
+ "file_fs=/zeus/rootfs_ba.img\0" \
+ "tftp_fs=tftp 100000 ${file_fs}\0" \
+ "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
+ "cp.b 100000 ff300000 580000\0" \
+ "upd_fs=run tftp_fs;run update_fs\0" \
+ "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
+ ""
+
+#endif /* __CONFIG_H */
diff --git a/include/dtt.h b/include/dtt.h
index 842a761..2e8c690 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -29,6 +29,7 @@
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
defined(CONFIG_DTT_LM81) || \
defined(CONFIG_DTT_ADM1021)
@@ -78,6 +79,13 @@ extern int dtt_get_temp(int sensor);
#define DTT_CONFIG 0xAC
#endif
+#if defined(CONFIG_DTT_DS1775)
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_OS 0x3
+#endif
+
#if defined(CONFIG_DTT_ADM1021)
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01
diff --git a/include/post.h b/include/post.h
index 8259e5d..c8062bb 100644
--- a/include/post.h
+++ b/include/post.h
@@ -92,6 +92,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#define CFG_POST_FPU 0x00004000
+#define CFG_POST_ECC 0x00008000
#endif /* CONFIG_POST */
diff --git a/include/ppc405.h b/include/ppc405.h
index 8e64731..0c7bf3e 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -541,6 +541,18 @@
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
/*
* PLL Voltage Controlled Oscillator (VCO) definitions
@@ -617,6 +629,8 @@
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
+#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
+
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
@@ -1226,6 +1240,8 @@
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
+#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
#ifndef __ASSEMBLY__
diff --git a/include/ppc440.h b/include/ppc440.h
index 93c10f1..38809f3 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -3354,6 +3354,19 @@ typedef struct {
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
+static inline u32 get_mcsr(void)
+{
+ u32 val;
+
+ asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+ return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+ asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c
index 8354411..2d995fa 100644
--- a/lib_ppc/extable.c
+++ b/lib_ppc/extable.c
@@ -89,7 +89,7 @@ search_exception_table(unsigned long addr)
/* if the serial port does not hang in exception, printf can be used */
#if !defined(CFG_SERIAL_HANG_IN_EXCEPTION)
if (ex_tab_message)
- printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
+ debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
#endif
if (ret) return ret;
diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile
new file mode 100644
index 0000000..c3f54e3
--- /dev/null
+++ b/post/board/lwmon5/Makefile
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+LIB = libpostlwmon5.a
+
+COBJS = ecc.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c
new file mode 100644
index 0000000..3fa3ba6
--- /dev/null
+++ b/post/board/lwmon5/ecc.c
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2007
+ * Developed for DENX Software Engineering GmbH.
+ *
+ * Author: Pavel Kolesnikov <concord@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_ECC
+
+/*
+ * MEMORY ECC test
+ *
+ * This test performs the checks ECC facility of memory.
+ */
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <ppc440.h>
+
+#include "../../../board/lwmon5/sdram.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const static unsigned char syndrome_codes[] = {
+ 0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
+ 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
+ 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
+ 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
+ 0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
+ 0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
+ 0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
+ 0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
+ 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
+};
+
+#define ECC_START_ADDR 0x10
+#define ECC_STOP_ADDR 0x2000
+#define ECC_PATTERN 0x0101010101010101ull
+#define ECC_PATTERN_CORR 0x0101010101010100ull
+#define ECC_PATTERN_UNCORR 0x010101010101010Full
+
+static int test_ecc_error(void)
+{
+ unsigned long value;
+ unsigned long hdata, ldata, haddr, laddr;
+ unsigned int bit;
+
+ int ret = 0;
+
+ mfsdram(DDR0_23, value);
+
+ for (bit = 0; bit < sizeof(syndrome_codes); bit++)
+ if (syndrome_codes[bit] == ((value >> 16) & 0xff))
+ break;
+
+ mfsdram(DDR0_00, value);
+
+ if (value & DDR0_00_INT_STATUS_BIT0) {
+ debug("Bit0. A single access outside the defined PHYSICAL"
+ " memory space detected\n");
+ mfsdram(DDR0_32, laddr);
+ mfsdram(DDR0_33, haddr);
+ debug(" addr = 0x%08x%08x\n", haddr, laddr);
+ ret = 1;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT1) {
+ debug("Bit1. Multiple accesses outside the defined PHYSICAL"
+ " memory space detected\n");
+ ret = 2;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT2) {
+ debug("Bit2. Single correctable ECC event detected\n");
+ mfsdram(DDR0_38, laddr);
+ mfsdram(DDR0_39, haddr);
+ mfsdram(DDR0_40, ldata);
+ mfsdram(DDR0_41, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 3;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT3) {
+ debug("Bit3. Multiple correctable ECC events detected\n");
+ mfsdram(DDR0_38, laddr);
+ mfsdram(DDR0_39, haddr);
+ mfsdram(DDR0_40, ldata);
+ mfsdram(DDR0_41, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 4;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT4) {
+ debug("Bit4. Single uncorrectable ECC event detected\n");
+ mfsdram(DDR0_34, laddr);
+ mfsdram(DDR0_35, haddr);
+ mfsdram(DDR0_36, ldata);
+ mfsdram(DDR0_37, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 5;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT5) {
+ debug("Bit5. Multiple uncorrectable ECC events detected\n");
+ mfsdram(DDR0_34, laddr);
+ mfsdram(DDR0_35, haddr);
+ mfsdram(DDR0_36, ldata);
+ mfsdram(DDR0_37, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 6;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT6) {
+ debug("Bit6. DRAM initialization complete\n");
+ ret = 7;
+ }
+
+ /* error status cleared */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ return ret;
+}
+
+static int test_ecc(unsigned long ecc_addr)
+{
+ volatile unsigned long long *ecc_mem;
+ unsigned long value;
+ unsigned long ecc_data;
+ volatile unsigned long *lecc_mem;
+ int pret, ret = 0;
+
+ sync();
+ eieio();
+ WATCHDOG_RESET();
+
+ ecc_mem = (unsigned long long *)ecc_addr;
+ lecc_mem = (ulong *)ecc_addr;
+ *ecc_mem = ECC_PATTERN;
+ pret = test_ecc_error();
+ if (pret != 0)
+ ret = 1;
+
+ /* disconnect ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_DISABLE);
+
+ /* injecting error */
+ *ecc_mem = ECC_PATTERN_CORR;
+
+ /* enable ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+
+ ecc_data = *lecc_mem;
+ pret = test_ecc_error();
+ /* if read data ok, 1 correctable error must be fixed */
+ if (pret != 3)
+ ret = 1;
+
+ /* test for uncorrectable error */
+ /* disconnect from ecc storage */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_NO_ECC_RAM);
+
+ /* injecting multiply bit error */
+
+ *ecc_mem = ECC_PATTERN_UNCORR;
+
+ /* enable ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+
+ ecc_data = *lecc_mem;
+ /* what the data should be read? */
+
+ pret = test_ecc_error();
+ /* info about uncorrectable error must appear */
+ if (pret != 5)
+ ret = 1;
+
+ sync();
+ eieio();
+
+ return ret;
+}
+
+int ecc_post_test (int flags)
+{
+ int ret = 0;
+ unsigned long value;
+ unsigned long iaddr;
+
+#if CONFIG_DDR_ECC
+ sync();
+ eieio();
+
+ /* mask all int */
+ mfsdram(DDR0_01, value);
+ mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
+ | DDR0_01_INT_MASK_ALL_OFF);
+
+ /* clear error status */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ /* enable full support of ECC */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+
+ for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) {
+ ret = test_ecc(iaddr);
+ if (ret)
+ break;
+ }
+
+ /* clear error status */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ /*
+ * Clear possible errors resulting from ECC testing.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+#endif
+
+ return ret;
+
+}
+
+#endif /* CONFIG_POST & CFG_POST_ECC */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index e1f989e..109ca1f 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -53,14 +53,25 @@ int cache_post_test6 (int tlb, void *p, int size);
static int tlb = -1; /* index to the victim TLB entry */
+#ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
+#endif
int cache_post_test (int flags)
{
void* virt = (void*)CFG_POST_CACHE_ADDR;
- int ints, i, res = 0;
- u32 word0;
+ int ints;
+ int res = 0;
+
+ /*
+ * All 44x variants deal with cache management differently
+ * because they have the address translation always enabled.
+ * The 40x ppc's don't use address translation in U-Boot at all,
+ * so we have to distinguish here between 40x and 44x.
+ */
+#ifdef CONFIG_440
+ int word0, i;
if (tlb < 0) {
/*
@@ -83,6 +94,7 @@ int cache_post_test (int flags)
}
}
}
+#endif
ints = disable_interrupts ();
WATCHDOG_RESET ();
diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S
index dddd76b..d5cb075 100644
--- a/post/cpu/ppc4xx/cache_4xx.S
+++ b/post/cpu/ppc4xx/cache_4xx.S
@@ -37,6 +37,13 @@
.text
+ /*
+ * All 44x variants deal with cache management differently
+ * because they have the address translation always enabled.
+ * The 40x ppc's don't use address translation in U-Boot at all,
+ * so we have to distinguish here between 40x and 44x.
+ */
+#ifdef CONFIG_440
/* void cache_post_disable (int tlb)
*/
cache_post_disable:
@@ -68,6 +75,43 @@ cache_post_wb:
sync
isync
blr
+#else
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+ lis r0, 0x0000
+ ori r0, r0, 0x0000
+ mtdccr r0
+ sync
+ isync
+ blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+ lis r0, 0x8000
+ ori r0, r0, 0x0000
+ mtdccr r0
+ lis r0, 0x8000
+ ori r0, r0, 0x0000
+ mtdcwr r0
+ sync
+ isync
+ blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+ lis r0, 0x8000
+ ori r0, r0, 0x0000
+ mtdccr r0
+ lis r0, 0x0000
+ ori r0, r0, 0x0000
+ mtdcwr r0
+ sync
+ isync
+ blr
+#endif
/* void cache_post_dinvalidate (void *p, int size)
*/
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index 391c815..ab23ca5 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -68,10 +68,10 @@ static char *rx_buf;
static void ether_post_init (int devnum, int hw_addr)
{
int i;
- unsigned mode_reg;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ unsigned mode_reg;
sys_info_t sysinfo;
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
@@ -185,10 +185,17 @@ static void ether_post_init (int devnum, int hw_addr)
mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
/* set internal loopback mode */
+#ifdef CFG_POST_ETHER_EXT_LOOPBACK
+ out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+ in32 (EMAC_M1));
+#else
out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
EMAC_M1_MF_100MBPS | EMAC_M1_IST |
in32 (EMAC_M1));
+#endif
/* set transmit enable & receive enable */
out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
index 27e9ed0..0c26fe0 100644
--- a/post/cpu/ppc4xx/fpu.c
+++ b/post/cpu/ppc4xx/fpu.c
@@ -29,8 +29,8 @@
#if defined(CONFIG_440EP) || \
defined(CONFIG_440EPX)
-#include <ppc4xx.h>
#include <asm/processor.h>
+#include <ppc4xx.h>
int fpu_status(void)
diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c
index b047d42..7c3ed40 100644
--- a/post/cpu/ppc4xx/uart.c
+++ b/post/cpu/ppc4xx/uart.c
@@ -38,24 +38,77 @@
#if CONFIG_POST & CFG_POST_UART
+/*
+ * This table defines the UART's that should be tested and can
+ * be overridden in the board config file
+ */
+#ifndef CFG_POST_UART_TABLE
+#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
+#endif
+
#include <asm/processor.h>
#include <serial.h>
+#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#else
+#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
+#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+#if defined(CONFIG_440GP)
+#define CR0_MASK 0x3fff0000
+#define CR0_EXTCLK_ENA 0x00600000
+#define CR0_UDIV_POS 16
+#define UDIV_SUBTRACT 1
+#define UART0_SDR cntrl0
+#define MFREG(a, d) d = mfdcr(a)
+#define MTREG(a, d) mtdcr(a, d)
+#else /* #if defined(CONFIG_440GP) */
+/* all other 440 PPC's access clock divider via sdr register */
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPe)
#define UART2_SDR sdr_uart2
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx)
#define UART3_SDR sdr_uart3
+#endif
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
+#endif /* #if defined(CONFIG_440GP) */
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define UCR0_MASK 0x0000007f
+#define UCR1_MASK 0x00007f00
+#define UCR0_UDIV_POS 0
+#define UCR1_UDIV_POS 8
+#define UDIV_MAX 127
+#else /* CONFIG_405GP || CONFIG_405CR */
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define CR0_MASK 0x00001fff
+#define CR0_EXTCLK_ENA 0x000000c0
+#define CR0_UDIV_POS 1
+#define UDIV_MAX 32
+#endif
#define UART_RBR 0x00
#define UART_THR 0x00
@@ -71,8 +124,8 @@
#define UART_DLM 0x01
/*
- Line Status Register.
-*/
+ * Line Status Register.
+ */
#define asyncLSRDataReady1 0x01
#define asyncLSROverrunError1 0x02
#define asyncLSRParityError1 0x04
@@ -84,6 +137,50 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_440)
+#if !defined(CFG_EXT_SERIAL_CLOCK)
+static void serial_divs (int baudrate, unsigned long *pudiv,
+ unsigned short *pbdiv)
+{
+ sys_info_t sysinfo;
+ unsigned long div; /* total divisor udiv * bdiv */
+ unsigned long umin; /* minimum udiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
+ unsigned long i;
+ unsigned long est; /* current estimate */
+
+ get_sys_info(&sysinfo);
+
+ udiv = 32; /* Assume lowest possible serial clk */
+ div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
+ umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
+ diff = 32; /* highest possible */
+
+ /* i is the test udiv value -- start with the largest
+ * possible (32) to minimize serial clock and constrain
+ * search to umin.
+ */
+ for (i = 32; i > umin; i--) {
+ ibdiv = div / i;
+ est = i * ibdiv;
+ idiff = (est > div) ? (est-div) : (div-est);
+ if (idiff == 0) {
+ udiv = i;
+ break; /* can't do better */
+ } else if (idiff < diff) {
+ udiv = i; /* best so far */
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pudiv = udiv;
+ *pbdiv = div / udiv;
+}
+#endif
+
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg;
@@ -147,6 +244,77 @@ static int uart_post_init (unsigned long dev_base)
return 0;
}
+#else /* CONFIG_440 */
+
+static int uart_post_init (unsigned long dev_base)
+{
+ unsigned long reg;
+ unsigned long tmp;
+ unsigned long clk;
+ unsigned long udiv;
+ unsigned short bdiv;
+ volatile char val;
+ int i;
+
+ for (i = 0; i < 3500; i++) {
+ if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
+ break;
+ udelay (100);
+ }
+
+#if defined(CONFIG_405EZ)
+ serial_divs(gd->baudrate, &udiv, &bdiv);
+ clk = tmp = reg = 0;
+#else
+#ifdef CONFIG_405EP
+ reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
+ clk = gd->cpu_clk;
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
+ udiv = UDIV_MAX;
+ reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
+ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
+ mtdcr (cpc0_ucr, reg);
+#else /* CONFIG_405EP */
+ reg = mfdcr(cntrl0) & ~CR0_MASK;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ clk = CFG_EXT_SERIAL_CLOCK;
+ udiv = 1;
+ reg |= CR0_EXTCLK_ENA;
+#else
+ clk = gd->cpu_clk;
+#ifdef CFG_405_UART_ERRATA_59
+ udiv = 31; /* Errata 59: stuck at 31 */
+#else
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
+ udiv = UDIV_MAX;
+#endif
+#endif
+ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
+ mtdcr (cntrl0, reg);
+#endif /* CONFIG_405EP */
+ tmp = gd->baudrate * udiv * 16;
+ bdiv = (clk + tmp / 2) / tmp;
+#endif /* CONFIG_405EZ */
+
+ out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
+ out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
+ out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+ out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
+ out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
+ val = in8(dev_base + UART_LSR); /* clear line status */
+ val = in8(dev_base + UART_RBR); /* read receive buffer */
+ out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
+ out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
+
+ return (0);
+}
+#endif /* CONFIG_440 */
+
static void uart_post_putc (unsigned long dev_base, char c)
{
int i;
@@ -198,9 +366,7 @@ done:
int uart_post_test (int flags)
{
int i, res = 0;
- static unsigned long base[] = {
- UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
- };
+ static unsigned long base[] = CFG_POST_UART_TABLE;
for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
if (test_ctlr (base[i], i))
diff --git a/post/tests.c b/post/tests.c
index f3604b2..e1c3d28 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -46,6 +46,7 @@ extern int spr_post_test (int flags);
extern int sysmon_post_test (int flags);
extern int dsp_post_test (int flags);
extern int codec_post_test (int flags);
+extern int ecc_post_test (int flags);
extern int sysmon_init_f (void);
@@ -236,6 +237,18 @@ struct post_test post_list[] =
CFG_POST_CODEC
},
#endif
+#if CONFIG_POST & CFG_POST_ECC
+ {
+ "ECC test",
+ "ecc",
+ "This test checks ECC facility of memory.",
+ POST_ROM | POST_ALWAYS,
+ &ecc_post_test,
+ NULL,
+ NULL,
+ CFG_POST_ECC
+ },
+#endif
};
unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);