diff options
| -rw-r--r-- | MAINTAINERS | 2 | ||||
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | README | 1 | ||||
| -rw-r--r-- | board/qemu-mips/README | 6 | ||||
| -rw-r--r-- | board/qemu-mips/qemu-mips.c | 2 | ||||
| -rw-r--r-- | common/cmd_ide.c | 4 | ||||
| -rw-r--r-- | common/image.c | 1 | ||||
| -rw-r--r-- | cpu/74xx_7xx/cache.S | 21 | ||||
| -rw-r--r-- | cpu/arm920t/s3c24x0/usb.c | 2 | ||||
| -rw-r--r-- | cpu/mpc86xx/cache.S | 2 | ||||
| -rw-r--r-- | disk/part.c | 92 | ||||
| -rw-r--r-- | doc/README.nand-boot-ppc440 | 2 | ||||
| -rw-r--r-- | include/.gitignore | 4 | ||||
| -rw-r--r-- | include/configs/ml401.h | 21 | ||||
| -rw-r--r-- | include/configs/xupv2p.h | 21 |
15 files changed, 122 insertions, 61 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 58f833c..ac7572c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -607,7 +607,7 @@ Thomas Lange <thomas@corelatus.se> dbau1x00 MIPS32 Au1000 gth2 MIPS32 Au1000 -Vlad Lungu <vlad@comsys.ro> +Vlad Lungu <vlad.lungu@windriver.com> qemu_mips MIPS32 ######################################################################### @@ -424,7 +424,7 @@ $(obj)System.map: $(obj)u-boot # This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. # the dep file is only include in this top level makefile to determine when # to regenerate the autoconf.mk file. -$(obj)include/autoconf.mk: $(obj)include/config.h $(VERSION_FILE) +$(obj)include/autoconf.mk: $(obj)include/config.h @$(XECHO) Generating include/autoconf.mk ; \ set -e ; \ : Generate the dependancies ; \ @@ -623,7 +623,6 @@ The following options need to be configured: CONFIG_CMD_SPI * SPI serial bus support CONFIG_CMD_USB * USB support CONFIG_CMD_VFD * VFD support (TRAB) - CONFIG_CMD_BSP * Board SPecific functions CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_FSL * Microblaze FSL support diff --git a/board/qemu-mips/README b/board/qemu-mips/README index 39570b1..4c1f8ed 100644 --- a/board/qemu-mips/README +++ b/board/qemu-mips/README @@ -1,4 +1,4 @@ -By Vlad Lungu vlad@comsys.ro 2007-Oct-01 +By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01 ---------------------------------------- Qemu is a full system emulator. See @@ -9,3 +9,7 @@ Limitations & comments Supports the "-m mips" configuration of qemu: serial,NE2000,IDE. Support is big endian only for now (or at least this is what I tested). Derived from au1x00 with a lot of things cut out. + +Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with +recent qemu versions. When using emulated flash, launch with +-pflash <filename> and erase mips_bios.bin. diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c index a6ad7b9..6869074 100644 --- a/board/qemu-mips/qemu-mips.c +++ b/board/qemu-mips/qemu-mips.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Vlad Lungu vlad@comsys.ro + * Vlad Lungu vlad.lungu@windriver.com * * See file CREDITS for list of people who contributed to this * project. diff --git a/common/cmd_ide.c b/common/cmd_ide.c index ead7e10..cac99d5 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -52,10 +52,6 @@ # include <status_led.h> #endif -#ifndef __PPC__ -#include <asm/io.h> -#endif - #ifdef CONFIG_IDE_8xx_DIRECT DECLARE_GLOBAL_DATA_PTR; #endif diff --git a/common/image.c b/common/image.c index 4a024d4..051d298 100644 --- a/common/image.c +++ b/common/image.c @@ -93,6 +93,7 @@ static table_entry_t uimage_arch[] = { { IH_ARCH_MIPS64, "mips64", "MIPS 64 Bit", }, { IH_ARCH_NIOS, "nios", "NIOS", }, { IH_ARCH_NIOS2, "nios2", "NIOS II", }, + { IH_ARCH_PPC, "powerpc", "PowerPC", }, { IH_ARCH_PPC, "ppc", "PowerPC", }, { IH_ARCH_S390, "s390", "IBM S390", }, { IH_ARCH_SH, "sh", "SuperH", }, diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index a793d79..3a745cb 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -329,14 +329,28 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I and polling L2IP or L2I */ _GLOBAL(l2cache_invalidate) sync + mfspr r3, l2cr oris r3, r3, L2CR_L2I@h sync mtspr l2cr, r3 sync + mfspr r3, PVR + sync + rlwinm r3, r3, 16,16,31 + cmpli 0,r3,0x8000 /* 7451, 7441 */ + beq 0,inv_7450 + cmpli 0,r3,0x8001 /* 7455, 7445 */ + beq 0,inv_7450 + cmpli 0,r3,0x8002 /* 7457, 7447 */ + beq 0,inv_7450 + cmpli 0,r3,0x8003 /* 7447A */ + beq 0,inv_7450 + cmpli 0,r3,0x8004 /* 7448 */ + beq 0,inv_7450 invl2: mfspr r3, l2cr andi. r3, r3, L2CR_L2IP @@ -348,6 +362,11 @@ invl2: mtspr l2cr, r3 sync blr +inv_7450: + mfspr r3, l2cr + andis. r3, r3, L2CR_L2I@h + bne inv_7450 + blr /* * Enable L2 cache diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index ef5d5bf..421ebb4 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -69,4 +69,4 @@ int usb_cpu_init_fail (void) } # endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index f316b3e..2e4ea02 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate) invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2I@h + andis. r3, r3, L2CR_L2I@h bne invl2 blr diff --git a/disk/part.c b/disk/part.c index 3c71208..316e254 100644 --- a/disk/part.c +++ b/disk/part.c @@ -109,44 +109,45 @@ void dev_print (block_dev_desc_t *dev_desc) lbaint_t lba512; #endif - if (dev_desc->type==DEV_TYPE_UNKNOWN) { - puts ("not available\n"); - return; - } - if (dev_desc->if_type==IF_TYPE_SCSI) { - printf ("(%d:%d) ", dev_desc->target,dev_desc->lun); - } - if (dev_desc->if_type==IF_TYPE_IDE) { - printf ("Model: %s Firm: %s Ser#: %s\n", + switch (dev_desc->type) { + case IF_TYPE_SCSI: + printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n", + dev_desc->target,dev_desc->lun, dev_desc->vendor, - dev_desc->revision, - dev_desc->product); - } - if (dev_desc->if_type==IF_TYPE_SATA) { + dev_desc->product, + dev_desc->revision); + break; + case IF_TYPE_IDE: + case IF_TYPE_SATA: printf ("Model: %s Firm: %s Ser#: %s\n", dev_desc->vendor, dev_desc->revision, dev_desc->product); - } else { - printf ("Vendor: %s Prod.: %s Rev: %s\n", - dev_desc->vendor, - dev_desc->product, - dev_desc->revision); + break; + case DEV_TYPE_UNKNOWN: + default: + puts ("not available\n"); + return; } puts (" Type: "); if (dev_desc->removable) puts ("Removable "); switch (dev_desc->type & 0x1F) { - case DEV_TYPE_HARDDISK: puts ("Hard Disk"); - break; - case DEV_TYPE_CDROM: puts ("CD ROM"); - break; - case DEV_TYPE_OPDISK: puts ("Optical Device"); - break; - case DEV_TYPE_TAPE: puts ("Tape"); - break; - default: printf ("# %02X #", dev_desc->type & 0x1F); - break; + case DEV_TYPE_HARDDISK: + puts ("Hard Disk"); + break; + case DEV_TYPE_CDROM: + puts ("CD ROM"); + break; + case DEV_TYPE_OPDISK: + puts ("Optical Device"); + break; + case DEV_TYPE_TAPE: + puts ("Tape"); + break; + default: + printf ("# %02X #", dev_desc->type & 0x1F); + break; } puts ("\n"); if ((dev_desc->lba * dev_desc->blksz)>0L) { @@ -281,20 +282,27 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc) { puts ("\nPartition Map for "); switch (dev_desc->if_type) { - case IF_TYPE_IDE: puts ("IDE"); - break; - case IF_TYPE_SATA: puts ("SATA"); - break; - case IF_TYPE_SCSI: puts ("SCSI"); - break; - case IF_TYPE_ATAPI: puts ("ATAPI"); - break; - case IF_TYPE_USB: puts ("USB"); - break; - case IF_TYPE_DOC: puts ("DOC"); - break; - default: puts ("UNKNOWN"); - break; + case IF_TYPE_IDE: + puts ("IDE"); + break; + case IF_TYPE_SATA: + puts ("SATA"); + break; + case IF_TYPE_SCSI: + puts ("SCSI"); + break; + case IF_TYPE_ATAPI: + puts ("ATAPI"); + break; + case IF_TYPE_USB: + puts ("USB"); + break; + case IF_TYPE_DOC: + puts ("DOC"); + break; + default: + puts ("UNKNOWN"); + break; } printf (" device %d -- Partition Type: %s\n\n", dev_desc->dev, type); diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440 index a1c1d8c..1e9c102 100644 --- a/doc/README.nand-boot-ppc440 +++ b/doc/README.nand-boot-ppc440 @@ -9,7 +9,7 @@ The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, completely without NOR FLASH. This can be done by using the NAND boot feature of the 440 NAND flash controller (NDFC). -Here a short desciption of the different boot stages: +Here a short description of the different boot stages: a) IPL (Initial Program Loader, integrated inside CPU) ------------------------------------------------------ diff --git a/include/.gitignore b/include/.gitignore index 03a533c..ef7dd5f 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,7 +1,7 @@ /autoconf.mk* /asm -/asm-blackfin/arch -/asm-ppc/arch +/asm-*/arch +/asm-*/proc /bmp_logo.h /config.h /config.mk diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 360e2e1..7e0df87 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -56,9 +56,11 @@ /* ethernet */ #ifdef XILINX_EMAC_BASEADDR #define CONFIG_XILINX_EMAC 1 +#define CFG_ENET #else #ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 +#define CFG_ENET #endif #endif #undef ET_DEBUG @@ -70,18 +72,28 @@ #endif /* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR #define CFG_INTC_0 1 #define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR #define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif /* timer */ +#ifdef XILINX_TIMER_BASEADDR +#if (XILINX_TIMER_IRQ != -1) #define CFG_TIMER_0 1 #define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR #define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ #define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#endif +#else +#ifdef XILINX_CLOCK_FREQ #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ - +#else +#error BAD CLOCK FREQ +#endif +#endif /* FSL */ /* #define CFG_FSL_2 */ /* #define FSL_INTR_2 1 */ @@ -195,7 +207,12 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL -#define CONFIG_CMD_PING + +#ifndef CFG_ENET + #undef CONFIG_CMD_NET +#else + #define CONFIG_CMD_PING +#endif #if defined(CONFIG_SYSTEMACE) #define CONFIG_CMD_EXT2 diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 30fb303..c738567 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -63,9 +63,11 @@ /* ethernet */ #ifdef XILINX_EMAC_BASEADDR #define CONFIG_XILINX_EMAC 1 +#define CFG_ENET #else #ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 +#define CFG_ENET #endif #endif #undef ET_DEBUG @@ -77,18 +79,28 @@ #endif /* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR #define CFG_INTC_0 1 #define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR #define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif /* timer */ +#ifdef XILINX_TIMER_BASEADDR +#if (XILINX_TIMER_IRQ != -1) #define CFG_TIMER_0 1 #define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR #define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ #define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#endif +#else +#ifdef XILINX_CLOCK_FREQ #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ - +#else +#error BAD CLOCK FREQ +#endif +#endif /* * memory layout - Example * TEXT_BASE = 0x3600_0000; @@ -162,7 +174,12 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING + +#ifndef CFG_ENET + #undef CONFIG_CMD_NET +#else + #define CONFIG_CMD_PING +#endif #ifdef XILINX_SYSACE_BASEADDR #define CONFIG_CMD_EXT2 |