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-rwxr-xr-xMAKEALL1
-rw-r--r--Makefile11
-rw-r--r--README4
-rw-r--r--board/eNET/Makefile57
-rw-r--r--board/eNET/config.mk24
-rw-r--r--board/eNET/eNET.c167
-rw-r--r--board/eNET/eNET_start.S50
-rw-r--r--board/eNET/eNET_start16.S90
-rw-r--r--board/eNET/hardware.h35
-rw-r--r--board/eNET/u-boot.lds90
-rw-r--r--board/sc520_cdp/u-boot.lds6
-rw-r--r--board/sc520_spunk/u-boot.lds6
-rw-r--r--common/cmd_mem.c45
-rw-r--r--common/main.c27
-rw-r--r--cpu/i386/Makefile2
-rw-r--r--cpu/i386/cpu.c17
-rw-r--r--cpu/i386/interrupts.c19
-rw-r--r--cpu/i386/resetvec.S (renamed from cpu/i386/reset.S)2
-rw-r--r--cpu/i386/sc520.c14
-rw-r--r--doc/README.nios_CONFIG_SYS_NIOS_CPU (renamed from README.nios_CONFIG_SYS_NIOS_CPU)0
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/ds4510.c424
-rw-r--r--drivers/mtd/jedec_flash.c14
-rw-r--r--drivers/mtd/spi/atmel.c3
-rw-r--r--drivers/mtd/spi/stmicro.c3
-rw-r--r--drivers/serial/Makefile2
-rwxr-xr-xdrivers/serial/vct.c (renamed from drivers/serial/vcth.c)8
-rw-r--r--fs/fat/fat.c8
-rw-r--r--include/asm-i386/interrupt.h29
-rw-r--r--include/asm-ppc/cpm_8260.h28
-rw-r--r--include/configs/eNET.h248
-rw-r--r--include/configs/sc520_cdp.h1
-rw-r--r--include/configs/sc520_spunk.h1
-rw-r--r--include/div64.h10
-rw-r--r--include/ds4510.h75
-rw-r--r--include/post.h13
-rw-r--r--lib_m68k/interrupts.c4
-rw-r--r--post/lib_ppc/fpu/20001122-1.c2
-rw-r--r--post/lib_ppc/fpu/20010114-2.c2
-rw-r--r--post/lib_ppc/fpu/20010226-1.c2
-rw-r--r--post/lib_ppc/fpu/980619-1.c2
-rw-r--r--post/lib_ppc/fpu/Makefile1
-rw-r--r--post/lib_ppc/fpu/acc1.c2
-rw-r--r--post/lib_ppc/fpu/compare-fp-1.c2
-rw-r--r--post/lib_ppc/fpu/fpu.c2
-rw-r--r--post/lib_ppc/fpu/mul-subnormal-single-1.c2
-rw-r--r--tools/easylogo/easylogo.c98
47 files changed, 1576 insertions, 78 deletions
diff --git a/MAKEALL b/MAKEALL
index a1a49f7..29faaa5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -660,6 +660,7 @@ LIST_mips_el=" \
LIST_I486=" \
sc520_cdp \
+ sc520_eNET \
sc520_spunk \
sc520_spunk_rel \
"
diff --git a/Makefile b/Makefile
index eff3379..4aeae07 100644
--- a/Makefile
+++ b/Makefile
@@ -197,7 +197,7 @@ include $(TOPDIR)/config.mk
OBJS = cpu/$(CPU)/start.o
ifeq ($(CPU),i386)
OBJS += cpu/$(CPU)/start16.o
-OBJS += cpu/$(CPU)/reset.o
+OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),ppc4xx)
OBJS += cpu/$(CPU)/resetvec.o
@@ -3008,14 +3008,17 @@ smdk6400_config : unconfig
#########################################################################
## AMD SC520 CDP
#########################################################################
+eNET_config : unconfig
+ @$(MKCONFIG) $(@:_config=) i386 i386 eNET NULL sc520
+
sc520_cdp_config : unconfig
- @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp
+ @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp NULL sc520
sc520_spunk_config : unconfig
- @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
+ @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520
sc520_spunk_rel_config : unconfig
- @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
+ @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520
#========================================================================
# MIPS
diff --git a/README b/README
index 132650e..ad792d3 100644
--- a/README
+++ b/README
@@ -592,6 +592,10 @@ The following options need to be configured:
CONFIG_CMD_DHCP * DHCP support
CONFIG_CMD_DIAG * Diagnostics
CONFIG_CMD_DOC * Disk-On-Chip Support
+ CONFIG_CMD_DS4510 * ds4510 I2C gpio commands
+ CONFIG_CMD_DS4510_INFO * ds4510 I2C info command
+ CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd
+ CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
CONFIG_CMD_DTT * Digital Therm and Thermostat
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EEPROM * EEPROM read/write support
diff --git a/board/eNET/Makefile b/board/eNET/Makefile
new file mode 100644
index 0000000..4813b4b
--- /dev/null
+++ b/board/eNET/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := eNET.o
+SOBJS := eNET_start16.o eNET_start.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/eNET/config.mk b/board/eNET/config.mk
new file mode 100644
index 0000000..a763841
--- /dev/null
+++ b/board/eNET/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x38040000
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
new file mode 100644
index 0000000..57dd635
--- /dev/null
+++ b/board/eNET/eNET.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/ic/sc520.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+#include "hardware.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SC520_CDP_DEBUG
+
+#ifdef SC520_CDP_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
+
+void init_sc520_enet (void)
+{
+ /* Set CPU Speed to 100MHz */
+ write_mmcr_byte(SC520_CPUCTL, 1);
+ gd->cpu_clk = 100000000;
+
+ /* wait at least one millisecond */
+ asm("movl $0x2000,%%ecx\n"
+ "wait_loop: pushl %%ecx\n"
+ "popl %%ecx\n"
+ "loop wait_loop\n": : : "ecx");
+
+ /* turn on the SDRAM write buffer */
+ write_mmcr_byte(SC520_DBCTL, 0x11);
+
+ /* turn on the cache and disable write through */
+ asm("movl %%cr0, %%eax\n"
+ "andl $0x9fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n" : : : "eax");
+}
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_init(void)
+{
+ init_sc520_enet();
+
+ write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
+ write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
+ write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
+ write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
+ write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
+ write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
+ write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
+
+ write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
+ write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
+ write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
+ write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
+ write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
+ write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
+ write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
+
+ write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
+ write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
+ write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
+ write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
+ write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
+ write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
+ write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
+ write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
+ write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
+ write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
+ write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
+ write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
+/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
+/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+
+ /* Disable Watchdog */
+ write_mmcr_word(0x0cb0, 0x3333);
+ write_mmcr_word(0x0cb0, 0xcccc);
+ write_mmcr_word(0x0cb0, 0x0000);
+
+ /* Chip Select Configuration */
+ write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
+ write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
+ write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
+
+ write_mmcr_byte(SC520_ADDDECCTL, 0x02);
+ write_mmcr_byte(SC520_UART1CTL, 0x07);
+ write_mmcr_byte(SC520_SYSARBCTL,0x06);
+ write_mmcr_word(SC520_SYSARBMENB, 0x0003);
+
+ /* Crystal is 33.000MHz */
+ gd->bus_clk = 33000000;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ init_sc520_dram();
+ return 0;
+}
+
+void show_boot_progress(int val)
+{
+ uchar led_mask;
+
+ led_mask = 0x00;
+
+ if (val < 0)
+ led_mask |= LED_ERR_BITMASK;
+
+ led_mask |= (uchar)(val & 0x001f);
+ outb(led_mask, LED_LATCH_ADDRESS);
+}
+
+
+int last_stage_init(void)
+{
+ int minor;
+ int major;
+
+ major = minor = 0;
+
+ printf("Serck Controls eNET\n");
+
+ return 0;
+}
+
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
new file mode 100644
index 0000000..1b07d62
--- /dev/null
+++ b/board/eNET/eNET_start.S
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "hardware.h"
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp *%ebp /* return to caller */
+
+.globl show_boot_progress_asm
+show_boot_progress_asm:
+
+ movb %al, %dl /* Create Working Copy */
+ andb $0x80, %dl /* Mask in only Error bit */
+ shrb $0x02, %dl /* Shift Error bit to Error LED */
+ andb $0x0f, %al /* Mask out 'Error' bit */
+ orb %dl, %al /* Mask in ERR LED */
+ movw $LED_LATCH_ADDRESS, %dx
+ outb %al, %dx
+ jmp *%ebp /* return to caller */
+
+.globl cpu_halt_asm
+cpu_halt_asm:
+ movb $0x0f, %al
+ movw $LED_LATCH_ADDRESS, %dx
+ outb %al, %dx
+ hlt
+ jmp cpu_halt_asm
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
new file mode 100644
index 0000000..48e4d83
--- /dev/null
+++ b/board/eNET/eNET_start16.S
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+/* #include <asm/ic/sc520_defs.h> */
+
+#include "hardware.h"
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+ /* Alias MMCR to 0xdf000 */
+ movw $0xfffc, %dx
+ movl $0x800df0cb, %eax
+ outl %eax, %dx
+
+ /* Set ds to point to MMCR alias */
+ movw $0xdf00, %ax
+ movw %ax, %ds
+
+ /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
+ movl $0x00c0, %edi /* SC520_PAR14 */
+ movl $0x8bfff800, %eax /* TODO: Check this */
+ movl %eax, (%di)
+
+ /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
+ movl $0x00c4, %edi /* SC520_PAR15 */
+ movl $0x38201000, %eax
+ movl %eax, (%di)
+
+ /* Disable SDRAM write buffer */
+ movw $0x0040, %di /* SC520_DBCTL */
+ xorw %ax, %ax
+ movb %al, (%di)
+
+ /* Disabe MMCR alias */
+ movw $0xfffc, %dx
+ movl $0x000000cb, %eax
+ outl %eax, %dx
+
+ /* the return address is stored in bp */
+ jmp *%bp
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+ /* Alias MMCR to 0xdf000 */
+ movw $0xfffc, %dx
+ movl $0x800df0cb, %eax
+ outl %eax, %dx
+
+ /* Set ds to point to MMCR alias */
+ movw $0xdf00, %ax
+ movw %ax, %ds
+
+ /* issue software reset thorugh MMCR */
+ movl $0xd72, %edi
+ movb $0x01, %al
+ movb %al, (%di)
+
+1: hlt
+ jmp 1
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
new file mode 100644
index 0000000..42474a6
--- /dev/null
+++ b/board/eNET/hardware.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+
+#define LED_LATCH_ADDRESS 0x1002
+#define LED_RUN_BITMASK 0x01
+#define LED_1_BITMASK 0x02
+#define LED_2_BITMASK 0x04
+#define LED_RX_BITMASK 0x08
+#define LED_TX_BITMASK 0x10
+#define LED_ERR_BITMASK 0x20
+
+#endif /* HARDWARE_H_ */
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
new file mode 100644
index 0000000..671305a
--- /dev/null
+++ b/board/eNET/u-boot.lds
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x38040000; /* Location of bootcode in flash */
+ .text : { *(.text); }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
+
+ _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
+
+ . = 0x03FF0000; /* Ram data segment to use */
+ _i386boot_romdata_dest = ABSOLUTE(.);
+ .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
+ _i386boot_romdata_start = LOADADDR(.data);
+
+ . = ALIGN(4);
+ .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+ _i386boot_cmd_start = LOADADDR(.u_boot_cmd);
+
+ _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
+
+ . = ALIGN(4);
+ _i386boot_bss_start = ABSOLUTE(.);
+ .bss (NOLOAD) : { *(.bss) }
+ _i386boot_bss_size = SIZEOF(.bss);
+
+ /* 16bit realmode trampoline code */
+ .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
+
+ _i386boot_realmode = LOADADDR(.realmode);
+ _i386boot_realmode_size = SIZEOF(.realmode);
+
+ /* 16bit BIOS emulation code (just enough to boot Linux) */
+ .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+
+ _i386boot_bios = LOADADDR(.bios);
+ _i386boot_bios_size = SIZEOF(.bios);
+
+ /* The load addresses below assumes that the flash
+ * will be mapped so that 0x387f0000 == 0xffff0000
+ * at reset time
+ *
+ * The fe00 and ff00 offsets of the start32 and start16
+ * segments are arbitrary, the just have to be mapped
+ * at reset and the code have to fit.
+ * The fff0 offset of resetvec is important, however.
+ */
+
+ . = 0xfffffe00;
+ .start32 : AT (0x3807fe00) { *(.start32); }
+
+ . = 0xf800;
+ .start16 : AT (0x3807f800) { *(.start16); }
+
+ . = 0xfff0;
+ .resetvec : AT (0x3807fff0) { *(.resetvec); }
+ _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
+}
diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds
index 719ecba..0f5011a 100644
--- a/board/sc520_cdp/u-boot.lds
+++ b/board/sc520_cdp/u-boot.lds
@@ -75,7 +75,7 @@ SECTIONS
* The fe00 and ff00 offsets of the start32 and start16
* segments are arbitrary, the just have to be mapped
* at reset and the code have to fit.
- * The fff0 offset of reset is important, however.
+ * The fff0 offset of resetvec is important, however.
*/
@@ -86,6 +86,6 @@ SECTIONS
.start16 : AT (0x387fff00) { *(.start16); }
. = 0xfff0;
- .reset : AT (0x387ffff0) { *(.reset); }
- _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+ .resetvec : AT (0x387ffff0) { *(.resetvec); }
+ _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
}
diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds
index 4d6603c..d2436bc 100644
--- a/board/sc520_spunk/u-boot.lds
+++ b/board/sc520_spunk/u-boot.lds
@@ -76,7 +76,7 @@ SECTIONS
* The fe00 and ff00 offsets of the start32 and start16
* segments are arbitrary, the just have to be mapped
* at reset and the code have to fit.
- * The fff0 offset of reset is important, however.
+ * The fff0 offset of resetvec is important, however.
*/
@@ -87,6 +87,6 @@ SECTIONS
.start16 : AT (0x387fff00) { *(.start16); }
. = 0xfff0;
- .reset : AT (0x387ffff0) { *(.reset); }
- _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+ .resetvec : AT (0x387ffff0) { *(.resetvec); }
+ _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
}
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 400cfd7..c209d62 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -672,6 +672,8 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong val;
ulong readback;
int rcode = 0;
+ int iterations = 1;
+ int iteration_limit;
#if defined(CONFIG_SYS_ALT_MEMTEST)
vu_long len;
@@ -687,7 +689,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */
#endif
int j;
- int iterations = 1;
static const ulong bitpattern[] = {
0x00000001, /* single bit */
@@ -704,23 +705,25 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong pattern;
#endif
- if (argc > 1) {
+ if (argc > 1)
start = (ulong *)simple_strtoul(argv[1], NULL, 16);
- } else {
+ else
start = (ulong *)CONFIG_SYS_MEMTEST_START;
- }
- if (argc > 2) {
+ if (argc > 2)
end = (ulong *)simple_strtoul(argv[2], NULL, 16);
- } else {
+ else
end = (ulong *)(CONFIG_SYS_MEMTEST_END);
- }
- if (argc > 3) {
+ if (argc > 3)
pattern = (ulong)simple_strtoul(argv[3], NULL, 16);
- } else {
+ else
pattern = 0;
- }
+
+ if (argc > 4)
+ iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16);
+ else
+ iteration_limit = 0;
#if defined(CONFIG_SYS_ALT_MEMTEST)
printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end);
@@ -733,8 +736,15 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
+
+ if (iteration_limit && iterations > iteration_limit) {
+ printf("Tested %d iteration(s) without errors.\n",
+ iterations-1);
+ return 0;
+ }
+
printf("Iteration: %6d\r", iterations);
- PRINTF("Iteration: %6d\n", iterations);
+ PRINTF("\n");
iterations++;
/*
@@ -926,6 +936,13 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
+ if (iteration_limit && iterations > iteration_limit) {
+ printf("Tested %d iteration(s) without errors.\n",
+ iterations-1);
+ return 0;
+ }
+ ++iterations;
+
printf ("\rPattern %08lX Writing..."
"%12s"
"\b\b\b\b\b\b\b\b\b\b",
@@ -1276,9 +1293,9 @@ U_BOOT_CMD(
#endif /* CONFIG_LOOPW */
U_BOOT_CMD(
- mtest, 4, 1, do_mem_mtest,
- "mtest - simple RAM test\n",
- "[start [end [pattern]]]\n"
+ mtest, 5, 1, do_mem_mtest,
+ "mtest - simple RAM test\n",
+ "[start [end [pattern [iterations]]]]\n"
" - simple RAM read/write test\n"
);
diff --git a/common/main.c b/common/main.c
index a999a5d..4c4f780 100644
--- a/common/main.c
+++ b/common/main.c
@@ -158,7 +158,19 @@ static __inline__ int abortboot(int bootdelay)
/* In order to keep up with incoming data, check timeout only
* when catch up.
*/
- while (!abort && get_ticks() <= etime) {
+ do {
+ if (tstc()) {
+ if (presskey_len < presskey_max) {
+ presskey [presskey_len ++] = getc();
+ }
+ else {
+ for (i = 0; i < presskey_max - 1; i ++)
+ presskey [i] = presskey [i + 1];
+
+ presskey [i] = getc();
+ }
+ }
+
for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
if (delaykey[i].len > 0 &&
presskey_len >= delaykey[i].len &&
@@ -178,19 +190,8 @@ static __inline__ int abortboot(int bootdelay)
abort = 1;
}
}
+ } while (!abort && get_ticks() <= etime);
- if (tstc()) {
- if (presskey_len < presskey_max) {
- presskey [presskey_len ++] = getc();
- }
- else {
- for (i = 0; i < presskey_max - 1; i ++)
- presskey [i] = presskey [i + 1];
-
- presskey [i] = getc();
- }
- }
- }
# if DEBUG_BOOTKEYS
if (!abort)
puts("key timeout\n");
diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile
index 50534b6..f20675a 100644
--- a/cpu/i386/Makefile
+++ b/cpu/i386/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
-START = start.o start16.o reset.o
+START = start.o start16.o resetvec.o
COBJS = serial.o interrupts.o cpu.o timer.o sc520.o
SOBJS = sc520_asm.o
diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c
index 5fd37c7..b9af5f8 100644
--- a/cpu/i386/cpu.c
+++ b/cpu/i386/cpu.c
@@ -35,6 +35,7 @@
#include <common.h>
#include <command.h>
+#include <asm/interrupt.h>
int cpu_init(void)
{
@@ -64,3 +65,19 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2)
asm("wbinvd\n");
return;
}
+
+void __attribute__ ((regparm(0))) generate_gpf(void);
+
+/* segment 0x70 is an arbitrary segment which does not exist */
+asm(".globl generate_gpf\n"
+ "generate_gpf:\n"
+ "ljmp $0x70, $0x47114711\n");
+
+void __reset_cpu(ulong addr)
+{
+ printf("Resetting using i386 Triple Fault\n");
+ set_vector(13, generate_gpf); /* general protection fault handler */
+ set_vector(8, generate_gpf); /* double fault handler */
+ generate_gpf(); /* start the show */
+}
+void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c
index f6dbcca..badb30b 100644
--- a/cpu/i386/interrupts.c
+++ b/cpu/i386/interrupts.c
@@ -26,6 +26,7 @@
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/ibmpc.h>
+#include <asm/interrupt.h>
struct idt_entry {
@@ -376,7 +377,7 @@ asm ("idt_ptr:\n"
".long idt\n" /* offset */
".word 0x18\n");/* data segment */
-static void set_vector(int intnum, void *routine)
+void set_vector(int intnum, void *routine)
{
idt[intnum].base_high = (u16)((u32)(routine)>>16);
idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
@@ -507,19 +508,3 @@ int disable_interrupts(void)
return (flags&0x200); /* IE flags is bit 9 */
}
-
-
-#ifdef CONFIG_SYS_RESET_GENERIC
-
-void __attribute__ ((regparm(0))) generate_gpf(void);
-asm(".globl generate_gpf\n"
- "generate_gpf:\n"
- "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
- * exist */
-void reset_cpu(ulong addr)
-{
- set_vector(13, generate_gpf); /* general protection fault handler */
- set_vector(8, generate_gpf); /* double fault handler */
- generate_gpf(); /* start the show */
-}
-#endif
diff --git a/cpu/i386/reset.S b/cpu/i386/resetvec.S
index 07a7384..d9222dd 100644
--- a/cpu/i386/reset.S
+++ b/cpu/i386/resetvec.S
@@ -26,7 +26,7 @@
.extern start16
-.section .reset, "ax"
+.section .resetvec, "ax"
.code16
reset_vector:
cli
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index cb6bc03..12e8f38 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -25,9 +25,6 @@
* but idependent of implementation */
#include <config.h>
-
-#ifdef CONFIG_SC520
-
#include <common.h>
#include <config.h>
#include <pci.h>
@@ -507,4 +504,13 @@ u8 ssi_rx_byte(void)
return read_mmcr_byte(SC520_SSIRCV);
}
-#endif /* CONFIG_SC520 */
+#ifdef CONFIG_SYS_RESET_SC520
+void reset_cpu(ulong addr)
+{
+ printf("Resetting using SC520 MMCR\n");
+ /* Write a '1' to the SYS_RST of the RESCFG MMCR */
+ write_mmcr_word(SC520_RESCFG, 0x0001);
+
+ /* NOTREACHED */
+}
+#endif
diff --git a/README.nios_CONFIG_SYS_NIOS_CPU b/doc/README.nios_CONFIG_SYS_NIOS_CPU
index 3547c34..3547c34 100644
--- a/README.nios_CONFIG_SYS_NIOS_CPU
+++ b/doc/README.nios_CONFIG_SYS_NIOS_CPU
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 01e0f39..ea2bf87 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmisc.a
COBJS-$(CONFIG_ALI152X) += ali512x.o
+COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c
new file mode 100644
index 0000000..4cd2fc2
--- /dev/null
+++ b/drivers/misc/ds4510.c
@@ -0,0 +1,424 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Driver for DS4510, a CPU supervisor with integrated EEPROM, SRAM,
+ * and 4 programmable non-volatile GPIO pins.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <command.h>
+#include <ds4510.h>
+
+/* Default to an address that hopefully won't corrupt other i2c devices */
+#ifndef CONFIG_SYS_I2C_DS4510_ADDR
+#define CONFIG_SYS_I2C_DS4510_ADDR (~0)
+#endif
+
+enum {
+ DS4510_CMD_INFO,
+ DS4510_CMD_DEVICE,
+ DS4510_CMD_NV,
+ DS4510_CMD_RSTDELAY,
+ DS4510_CMD_OUTPUT,
+ DS4510_CMD_INPUT,
+ DS4510_CMD_PULLUP,
+ DS4510_CMD_EEPROM,
+ DS4510_CMD_SEEPROM,
+ DS4510_CMD_SRAM,
+};
+
+/*
+ * Write to DS4510, taking page boundaries into account
+ */
+int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
+{
+ int wrlen;
+ int i = 0;
+
+ do {
+ wrlen = DS4510_EEPROM_PAGE_SIZE -
+ DS4510_EEPROM_PAGE_OFFSET(offset);
+ if (count < wrlen)
+ wrlen = count;
+ if (i2c_write(chip, offset, 1, &buf[i], wrlen))
+ return -1;
+
+ /*
+ * This delay isn't needed for SRAM writes but shouldn't delay
+ * things too much, so do it unconditionally for simplicity
+ */
+ udelay(DS4510_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+ count -= wrlen;
+ offset += wrlen;
+ i += wrlen;
+ } while (count > 0);
+
+ return 0;
+}
+
+/*
+ * General read from DS4510
+ */
+int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
+{
+ return i2c_read(chip, offset, 1, buf, count);
+}
+
+/*
+ * Write SEE bit in config register.
+ * nv = 0 - Writes to SEEPROM registers behave like EEPROM
+ * nv = 1 - Writes to SEEPROM registers behave like SRAM
+ */
+int ds4510_see_write(uint8_t chip, uint8_t nv)
+{
+ uint8_t data;
+
+ if (i2c_read(chip, DS4510_CFG, 1, &data, 1))
+ return -1;
+
+ if (nv) /* Treat SEEPROM bits as EEPROM */
+ data &= ~DS4510_CFG_SEE;
+ else /* Treat SEEPROM bits as SRAM */
+ data |= DS4510_CFG_SEE;
+
+ return ds4510_mem_write(chip, DS4510_CFG, &data, 1);
+}
+
+/*
+ * Write de-assertion of reset signal delay
+ */
+int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
+{
+ uint8_t data;
+
+ if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1))
+ return -1;
+
+ data &= ~DS4510_RSTDELAY_MASK;
+ data |= delay & DS4510_RSTDELAY_MASK;
+
+ return ds4510_mem_write(chip, DS4510_RSTDELAY, &data, 1);
+}
+
+/*
+ * Write pullup characteristics of IO pins
+ */
+int ds4510_pullup_write(uint8_t chip, uint8_t val)
+{
+ val &= DS4510_IO_MASK;
+
+ return ds4510_mem_write(chip, DS4510_PULLUP, (uint8_t *)&val, 1);
+}
+
+/*
+ * Read pullup characteristics of IO pins
+ */
+int ds4510_pullup_read(uint8_t chip)
+{
+ uint8_t val;
+
+ if (i2c_read(chip, DS4510_PULLUP, 1, &val, 1))
+ return -1;
+
+ return val & DS4510_IO_MASK;
+}
+
+/*
+ * Write drive level of IO pins
+ */
+int ds4510_gpio_write(uint8_t chip, uint8_t val)
+{
+ uint8_t data;
+ int i;
+
+ for (i = 0; i < DS4510_NUM_IO; i++) {
+ if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1))
+ return -1;
+
+ if (val & (0x1 << i))
+ data |= 0x1;
+ else
+ data &= ~0x1;
+
+ if (ds4510_mem_write(chip, DS4510_IO0 - i, &data, 1))
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Read drive level of IO pins
+ */
+int ds4510_gpio_read(uint8_t chip)
+{
+ uint8_t data;
+ int val = 0;
+ int i;
+
+ for (i = 0; i < DS4510_NUM_IO; i++) {
+ if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1))
+ return -1;
+
+ if (data & 1)
+ val |= (1 << i);
+ }
+
+ return val;
+}
+
+/*
+ * Read physical level of IO pins
+ */
+int ds4510_gpio_read_val(uint8_t chip)
+{
+ uint8_t val;
+
+ if (i2c_read(chip, DS4510_IO_STATUS, 1, &val, 1))
+ return -1;
+
+ return val & DS4510_IO_MASK;
+}
+
+#ifdef CONFIG_CMD_DS4510
+#ifdef CONFIG_CMD_DS4510_INFO
+/*
+ * Display DS4510 information
+ */
+static int ds4510_info(uint8_t chip)
+{
+ int i;
+ int tmp;
+ uint8_t data;
+
+ printf("DS4510 @ 0x%x:\n\n", chip);
+
+ if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1))
+ return -1;
+ printf("rstdelay = 0x%x\n\n", data & DS4510_RSTDELAY_MASK);
+
+ if (i2c_read(chip, DS4510_CFG, 1, &data, 1))
+ return -1;
+ printf("config = 0x%x\n", data);
+ printf(" /ready = %d\n", data & DS4510_CFG_READY ? 1 : 0);
+ printf(" trip pt = %d\n", data & DS4510_CFG_TRIP_POINT ? 1 : 0);
+ printf(" rst sts = %d\n", data & DS4510_CFG_RESET ? 1 : 0);
+ printf(" /see = %d\n", data & DS4510_CFG_SEE ? 1 : 0);
+ printf(" swrst = %d\n\n", data & DS4510_CFG_SWRST ? 1 : 0);
+
+ printf("gpio pins: 3210\n");
+ printf("---------------\n");
+ printf("pullup ");
+
+ tmp = ds4510_pullup_read(chip);
+ if (tmp == -1)
+ return tmp;
+ for (i = DS4510_NUM_IO - 1; i >= 0; i--)
+ printf("%d", (tmp & (1 << i)) ? 1 : 0);
+ printf("\n");
+
+ printf("driven ");
+ tmp = ds4510_gpio_read(chip);
+ if (tmp == -1)
+ return -1;
+ for (i = DS4510_NUM_IO - 1; i >= 0; i--)
+ printf("%d", (tmp & (1 << i)) ? 1 : 0);
+ printf("\n");
+
+ printf("read ");
+ tmp = ds4510_gpio_read_val(chip);
+ if (tmp == -1)
+ return -1;
+ for (i = DS4510_NUM_IO - 1; i >= 0; i--)
+ printf("%d", (tmp & (1 << i)) ? 1 : 0);
+ printf("\n");
+
+ return 0;
+}
+#endif /* CONFIG_CMD_DS4510_INFO */
+
+cmd_tbl_t cmd_ds4510[] = {
+ U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""),
+ U_BOOT_CMD_MKENT(nv, 3, 0, (void *)DS4510_CMD_NV, "", ""),
+ U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""),
+ U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""),
+ U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""),
+#ifdef CONFIG_CMD_DS4510_INFO
+ U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""),
+#endif
+#ifdef CONFIG_CMD_DS4510_RST
+ U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""),
+#endif
+#ifdef CONFIG_CMD_DS4510_MEM
+ U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""),
+ U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""),
+ U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""),
+#endif
+};
+
+int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR;
+ cmd_tbl_t *c;
+ ulong ul_arg2 = 0;
+ ulong ul_arg3 = 0;
+ int tmp;
+#ifdef CONFIG_CMD_DS4510_MEM
+ ulong addr;
+ ulong off;
+ ulong cnt;
+ int end;
+ int (*rw_func)(uint8_t, int, uint8_t *, int);
+#endif
+
+ c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510));
+
+ /* All commands but "device" require 'maxargs' arguments */
+ if (!c || !((argc == (c->maxargs)) ||
+ (((int)c->cmd == DS4510_CMD_DEVICE) &&
+ (argc == (c->maxargs - 1))))) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ /* arg2 used as chip addr and pin number */
+ if (argc > 2)
+ ul_arg2 = simple_strtoul(argv[2], NULL, 16);
+
+ /* arg3 used as output/pullup value */
+ if (argc > 3)
+ ul_arg3 = simple_strtoul(argv[3], NULL, 16);
+
+ switch ((int)c->cmd) {
+ case DS4510_CMD_DEVICE:
+ if (argc == 3)
+ chip = ul_arg2;
+ printf("Current device address: 0x%x\n", chip);
+ return 0;
+ case DS4510_CMD_NV:
+ return ds4510_see_write(chip, ul_arg2);
+ case DS4510_CMD_OUTPUT:
+ tmp = ds4510_gpio_read(chip);
+ if (tmp == -1)
+ return -1;
+ if (ul_arg3)
+ tmp |= (1 << ul_arg2);
+ else
+ tmp &= ~(1 << ul_arg2);
+ return ds4510_gpio_write(chip, tmp);
+ case DS4510_CMD_INPUT:
+ tmp = ds4510_gpio_read_val(chip);
+ if (tmp == -1)
+ return -1;
+ return (tmp & (1 << ul_arg2)) != 0;
+ case DS4510_CMD_PULLUP:
+ tmp = ds4510_pullup_read(chip);
+ if (tmp == -1)
+ return -1;
+ if (ul_arg3)
+ tmp |= (1 << ul_arg2);
+ else
+ tmp &= ~(1 << ul_arg2);
+ return ds4510_pullup_write(chip, tmp);
+#ifdef CONFIG_CMD_DS4510_INFO
+ case DS4510_CMD_INFO:
+ return ds4510_info(chip);
+#endif
+#ifdef CONFIG_CMD_DS4510_RST
+ case DS4510_CMD_RSTDELAY:
+ return ds4510_rstdelay_write(chip, ul_arg2);
+#endif
+#ifdef CONFIG_CMD_DS4510_MEM
+ case DS4510_CMD_EEPROM:
+ end = DS4510_EEPROM + DS4510_EEPROM_SIZE;
+ off = DS4510_EEPROM;
+ break;
+ case DS4510_CMD_SEEPROM:
+ end = DS4510_SEEPROM + DS4510_SEEPROM_SIZE;
+ off = DS4510_SEEPROM;
+ break;
+ case DS4510_CMD_SRAM:
+ end = DS4510_SRAM + DS4510_SRAM_SIZE;
+ off = DS4510_SRAM;
+ break;
+#endif
+ default:
+ /* We should never get here... */
+ return 1;
+ }
+
+#ifdef CONFIG_CMD_DS4510_MEM
+ /* Only eeprom, seeprom, and sram commands should make it here */
+ if (strcmp(argv[2], "read") == 0) {
+ rw_func = ds4510_mem_read;
+ } else if (strcmp(argv[2], "write") == 0) {
+ rw_func = ds4510_mem_write;
+ } else {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ addr = simple_strtoul(argv[3], NULL, 16);
+ off += simple_strtoul(argv[4], NULL, 16);
+ cnt = simple_strtoul(argv[5], NULL, 16);
+
+ if ((off + cnt) > end) {
+ printf("ERROR: invalid len\n");
+ return -1;
+ }
+
+ return rw_func(chip, off, (uint8_t *)addr, cnt);
+#endif
+}
+
+U_BOOT_CMD(
+ ds4510, 6, 1, do_ds4510,
+ "ds4510 - ds4510 eeprom/seeprom/sram/gpio access\n",
+ "device [dev]\n"
+ " - show or set current device address\n"
+#ifdef CONFIG_CMD_DS4510_INFO
+ "ds4510 info\n"
+ " - display ds4510 info\n"
+#endif
+ "ds4510 output pin 0|1\n"
+ " - set pin low or high-Z\n"
+ "ds4510 input pin\n"
+ " - read value of pin\n"
+ "ds4510 pullup pin 0|1\n"
+ " - disable/enable pullup on specified pin\n"
+ "ds4510 nv 0|1\n"
+ " - make gpio and seeprom writes volatile/non-volatile\n"
+#ifdef CONFIG_CMD_DS4510_RST
+ "ds4510 rstdelay 0-3\n"
+ " - set reset output delay\n"
+#endif
+#ifdef CONFIG_CMD_DS4510_MEM
+ "ds4510 eeprom read addr off cnt\n"
+ "ds4510 eeprom write addr off cnt\n"
+ " - read/write 'cnt' bytes at EEPROM offset 'off'\n"
+ "ds4510 seeprom read addr off cnt\n"
+ "ds4510 seeprom write addr off cnt\n"
+ " - read/write 'cnt' bytes at SRAM-shadowed EEPROM offset 'off'\n"
+ "ds4510 sram read addr off cnt\n"
+ "ds4510 sram write addr off cnt\n"
+ " - read/write 'cnt' bytes at SRAM offset 'off'\n"
+#endif
+);
+#endif /* CONFIG_CMD_DS4510 */
diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c
index 226e1e4..2d99d4d 100644
--- a/drivers/mtd/jedec_flash.c
+++ b/drivers/mtd/jedec_flash.c
@@ -215,6 +215,20 @@ static const struct amd_flash_info jedec_table[] = {
ERASEINFO(0x01000,128),
}
},
+ {
+ .mfr_id = STM_MANUFACT,
+ .dev_id = STM_ID_M29W040B,
+ .name = "ST Micro M29W040B",
+ .uaddr = {
+ [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
+ },
+ .DevSize = SIZE_512KiB,
+ .CmdSet = P_ID_AMD_STD,
+ .NumEraseRegions= 1,
+ .regions = {
+ ERASEINFO(0x10000,8),
+ }
+ },
#endif
#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
{
diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c
index 10fcf0c..a5f51ca 100644
--- a/drivers/mtd/spi/atmel.c
+++ b/drivers/mtd/spi/atmel.c
@@ -39,9 +39,10 @@ struct atmel_spi_flash_params {
const char *name;
};
+/* spi_flash needs to be first so upper layers can free() it */
struct atmel_spi_flash {
- const struct atmel_spi_flash_params *params;
struct spi_flash flash;
+ const struct atmel_spi_flash_params *params;
};
static inline struct atmel_spi_flash *
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 86324e4..e7dda91 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -64,9 +64,10 @@ struct stmicro_spi_flash_params {
const char *name;
};
+/* spi_flash needs to be first so upper layers can free() it */
struct stmicro_spi_flash {
- const struct stmicro_spi_flash_params *params;
struct spi_flash flash;
+ const struct stmicro_spi_flash_params *params;
};
static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 17235ff..c7a1882 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -38,7 +38,7 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_USB_TTY) += usbtty.o
-COBJS-$(CONFIG_VCTH_SERIAL) += vcth.o
+COBJS-$(CONFIG_VCT_SERIAL) += vct.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/serial/vcth.c b/drivers/serial/vct.c
index 2c847d0..556c114 100755
--- a/drivers/serial/vcth.c
+++ b/drivers/serial/vct.c
@@ -21,7 +21,11 @@
#include <common.h>
#include <asm/io.h>
+#ifdef CONFIG_VCT_PLATINUMAVC
+#define UART_1_BASE 0xBDC30000
+#else
#define UART_1_BASE 0xBF89C000
+#endif
#define UART_RBR_OFF 0x00 /* receiver buffer reg */
#define UART_THR_OFF 0x00 /* transmit holding reg */
@@ -53,7 +57,7 @@
#define UART_7DATA_BITS 0x0002 /* 7 [bits] 1 bits 2 */
#define UART_8DATA_BITS 0x0003 /* 8 [bits] 1 bits 2 */
-static void vcth_uart_set_baud_rate(u32 address, u32 dh, u32 dl)
+static void vct_uart_set_baud_rate(u32 address, u32 dh, u32 dl)
{
u32 val = __raw_readl(UART_1_BASE + UART_LCR_OFF);
@@ -74,7 +78,7 @@ static void vcth_uart_set_baud_rate(u32 address, u32 dh, u32 dl)
int serial_init(void)
{
__raw_writel(UART_DIS_ALL_INTER, UART_1_BASE + UART_IER_OFF);
- vcth_uart_set_baud_rate(UART_1_BASE, 0, UART_115200_BDR);
+ vct_uart_set_baud_rate(UART_1_BASE, 0, UART_115200_BDR);
__raw_writel(UART_8DATA_BITS, UART_1_BASE + UART_LCR_OFF);
return 0;
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index a9dde7d..28c7805 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -434,7 +434,8 @@ slot2str(dir_slot *slotptr, char *l_name, int *idx)
* into 'retdent'
* Return 0 on success, -1 otherwise.
*/
-__u8 get_vfatname_block[MAX_CLUSTSIZE];
+__attribute__ ((__aligned__(__alignof__(dir_entry))))
+__u8 get_vfatname_block[MAX_CLUSTSIZE];
static int
get_vfatname(fsdata *mydata, int curclust, __u8 *cluster,
dir_entry *retdent, char *l_name)
@@ -520,6 +521,7 @@ mkcksum(const char *str)
* Get the directory entry associated with 'filename' from the directory
* starting at 'startsect'
*/
+__attribute__ ((__aligned__(__alignof__(dir_entry))))
__u8 get_dentfromdir_block[MAX_CLUSTSIZE];
static dir_entry *get_dentfromdir (fsdata * mydata, int startsect,
char *filename, dir_entry * retdent,
@@ -725,8 +727,8 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize)
return -1;
}
-
-__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */
+__attribute__ ((__aligned__(__alignof__(dir_entry))))
+__u8 do_fat_read_block[MAX_CLUSTSIZE];
long
do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
int dols)
diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h
new file mode 100644
index 0000000..315b400
--- /dev/null
+++ b/include/asm-i386/interrupt.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_INTERRUPT_H_
+#define __ASM_INTERRUPT_H_ 1
+
+void set_vector(int intnum, void *routine);
+
+#endif
diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h
index 7e06940..8302404 100644
--- a/include/asm-ppc/cpm_8260.h
+++ b/include/asm-ppc/cpm_8260.h
@@ -546,6 +546,34 @@ typedef struct scc_trans {
#define BD_SCC_TX_LAST ((ushort)0x0800)
+/* SCC as HDLC controller - taken from commproc.h
+ */
+typedef struct scc_hdlc {
+ sccp_t sh_genscc;
+ /*
+ * HDLC specific parameter RAM
+ */
+ uchar res[4]; /* reserved */
+ ulong sh_cmask; /* CRC constant */
+ ulong sh_cpres; /* CRC preset */
+ ushort sh_disfc; /* discarded frame counter */
+ ushort sh_crcec; /* CRC error counter */
+ ushort sh_abtsc; /* abort sequence counter */
+ ushort sh_nmarc; /* nonmatching address rx cnt */
+ ushort sh_retrc; /* frame retransmission cnt */
+ ushort sh_mflr; /* maximum frame length reg */
+ ushort sh_maxcnt; /* maximum length counter */
+ ushort sh_rfthr; /* received frames threshold */
+ ushort sh_rfcnt; /* received frames count */
+ ushort sh_hmask; /* user defined frm addr mask */
+ ushort sh_haddr1; /* user defined frm address 1 */
+ ushort sh_haddr2; /* user defined frm address 2 */
+ ushort sh_haddr3; /* user defined frm address 3 */
+ ushort sh_haddr4; /* user defined frm address 4 */
+ ushort tmp; /* temp */
+ ushort tmp_mb; /* temp */
+} scc_hdlc_t;
+
/* How about some FCCs.....
*/
#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
new file mode 100644
index 0000000..8f9e972
--- /dev/null
+++ b/include/configs/eNET.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Stuff still to be dealt with -
+ */
+#define CONFIG_RTC_MC146818
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define DEBUG_PARSER
+
+#define CONFIG_X86 1 /* Intel X86 CPU */
+#define CONFIG_SC520 1 /* AMD SC520 */
+#define CONFIG_SC520_SSI
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+#define CONFIG_LAST_STAGE_INIT 1
+
+/*
+ * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
+ * bottom (processor) board MUST be removed!
+ */
+#undef CONFIG_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
+
+ /*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#undef CONFIG_VIDEO /* No Video Hardware */
+#undef CONFIG_CFB_CONSOLE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
+
+#define CONFIG_BAUDRATE 9600
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+#undef CONFIG_CMD_IRQ /* IRQ Information */
+
+#define CONFIG_BOOTDELAY 15
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
+/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
+
+ /* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * SDRAM Configuration
+ */
+#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
+#define CONFIG_NR_DRAM_BANKS 4
+
+/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
+#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
+#undef CONFIG_SYS_SDRAM_REFRESH_RATE
+#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
+#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */
+#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */
+#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */
+#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */
+#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
+ * in the SC520 on the CDP */
+
+/*-----------------------------------------------------------------------
+ * Memory organization
+ */
+#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
+#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
+#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
+#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
+#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+ /*-----------------------------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
+#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2}
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+ /*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+
+ /*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#undef CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* pci plug-and-play */
+#undef CONFIG_PCI_SCAN_SHOW
+#undef CONFIG_SYS_FIRST_PCI_IRQ
+#undef CONFIG_SYS_SECOND_PCI_IRQ
+#undef CONFIG_SYS_THIRD_PCI_IRQ
+#undef CONFIG_SYS_FORTH_PCI_IRQ
+
+/*-----------------------------------------------------------------------
+ * Hardware watchdog configuration
+ */
+#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000
+#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0
+#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
+#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0
+
+/*-----------------------------------------------------------------------
+ * FPGA configuration
+ */
+#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
+#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
+#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
+#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
+#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
+#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
+#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
+#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
+#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
+#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
+#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
+
+#ifndef __ASSEMBLER__
+extern unsigned long ip;
+
+#define PRINTIP asm ("call next_line\n" \
+ "next_line:\n" \
+ "pop %%eax\n" \
+ "movl %%eax, %0\n" \
+ :"=r"(ip) \
+ : /* No Input Registers */ \
+ :"%eax"); \
+ printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
+
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index bf8693e..9f2357b 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -47,7 +47,6 @@
#define CONFIG_SYS_SDRAM_CAS_LATENCY_3T
#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
-#define CONFIG_SYS_RESET_GENERIC 1 /* use tripple-fault to reset cpu */
#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */
#undef CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */
#define CONFIG_SYS_TIMER_GENERIC 1 /* use the i8254 PIT timers */
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index fbdbedd..50af732 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -45,7 +45,6 @@
#define CONFIG_SYS_SDRAM_CAS_LATENCY_3T
#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
-#define CONFIG_SYS_RESET_GENERIC 1 /* use tripple-fault to reset cpu */
#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */
#undef CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */
#define CONFIG_SYS_TIMER_GENERIC 1 /* use the i8254 PIT timers */
diff --git a/include/div64.h b/include/div64.h
index c495aef..d833144 100644
--- a/include/div64.h
+++ b/include/div64.h
@@ -36,4 +36,14 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
__rem; \
})
+/* Wrapper for do_div(). Doesn't modify dividend and returns
+ * the result, not reminder.
+ */
+static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor)
+{
+ uint64_t __res = dividend;
+ do_div(__res, divisor);
+ return(__res);
+}
+
#endif /* _ASM_GENERIC_DIV64_H */
diff --git a/include/ds4510.h b/include/ds4510.h
new file mode 100644
index 0000000..40480af
--- /dev/null
+++ b/include/ds4510.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DS4510_H_
+#define __DS4510_H_
+
+/* General defines */
+#define DS4510_NUM_IO 0x04
+#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1)
+#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/* EEPROM from 0x00 - 0x39 */
+#define DS4510_EEPROM 0x00
+#define DS4510_EEPROM_SIZE 0x40
+#define DS4510_EEPROM_PAGE_SIZE 0x08
+#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
+
+/* SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_SEEPROM 0xf0
+#define DS4510_SEEPROM_SIZE 0x08
+
+/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_PULLUP 0xF0
+#define DS4510_PULLUP_DIS 0x00
+#define DS4510_PULLUP_EN 0x01
+#define DS4510_RSTDELAY 0xF1
+#define DS4510_RSTDELAY_MASK 0x03
+#define DS4510_RSTDELAY_125 0x00
+#define DS4510_RSTDELAY_250 0x01
+#define DS4510_RSTDELAY_500 0x02
+#define DS4510_RSTDELAY_1000 0x03
+#define DS4510_IO3 0xF4
+#define DS4510_IO2 0xF5
+#define DS4510_IO1 0xF6
+#define DS4510_IO0 0xF7
+
+/* Status configuration registers from 0xf8 - 0xf9*/
+#define DS4510_IO_STATUS 0xF8
+#define DS4510_CFG 0xF9
+#define DS4510_CFG_READY 0x80
+#define DS4510_CFG_TRIP_POINT 0x40
+#define DS4510_CFG_RESET 0x20
+#define DS4510_CFG_SEE 0x10
+#define DS4510_CFG_SWRST 0x08
+
+/* SRAM from 0xfa - 0xff */
+#define DS4510_SRAM 0xfa
+#define DS4510_SRAM_SIZE 0x06
+
+int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count);
+int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count);
+int ds4510_see_write(uint8_t chip, uint8_t nv);
+int ds4510_rstdelay_write(uint8_t chip, uint8_t delay);
+int ds4510_pullup_write(uint8_t chip, uint8_t val);
+int ds4510_pullup_read(uint8_t chip);
+int ds4510_gpio_write(uint8_t chip, uint8_t val);
+int ds4510_gpio_read(uint8_t chip);
+int ds4510_gpio_read_val(uint8_t chip);
+
+#endif /* __DS4510_H_ */
diff --git a/include/post.h b/include/post.h
index 97583b7..fe96312 100644
--- a/include/post.h
+++ b/include/post.h
@@ -80,6 +80,19 @@ extern struct post_test post_list[];
extern unsigned int post_list_size;
extern int post_hotkeys_pressed(void);
+/*
+ * If GCC is configured to use a version of GAS that supports
+ * the .gnu_attribute directive, it will use that directive to
+ * record certain properties of the output code.
+ * This feature is new to GCC 4.3.0.
+ * .gnu_attribute is new to GAS 2.18.
+ */
+#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3)
+/* Tag_GNU_Power_ABI_FP/soft-float */
+#define GNU_FPOST_ATTR asm(".gnu_attribute 4, 2");
+#else
+#define GNU_FPOST_ATTR
+#endif /* __GNUC__ */
#endif /* __ASSEMBLY__ */
#define CONFIG_SYS_POST_RTC 0x00000001
diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c
index 2dc079b..133494f 100644
--- a/lib_m68k/interrupts.c
+++ b/lib_m68k/interrupts.c
@@ -61,7 +61,7 @@ static __inline__ void set_sr (unsigned short sr)
*/
void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
{
- if ((vec < 0) || (vec > NR_IRQS)) {
+ if ((vec < 0) || (vec >= NR_IRQS)) {
printf ("irq_install_handler: wrong interrupt vector %d\n",
vec);
return;
@@ -73,7 +73,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
void irq_free_handler (int vec)
{
- if ((vec < 0) || (vec > NR_IRQS)) {
+ if ((vec < 0) || (vec >= NR_IRQS)) {
return;
}
diff --git a/post/lib_ppc/fpu/20001122-1.c b/post/lib_ppc/fpu/20001122-1.c
index a8537fa..bef80c5 100644
--- a/post/lib_ppc/fpu/20001122-1.c
+++ b/post/lib_ppc/fpu/20001122-1.c
@@ -30,6 +30,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
int fpu_post_test_math1 (void)
{
volatile double a, *p;
diff --git a/post/lib_ppc/fpu/20010114-2.c b/post/lib_ppc/fpu/20010114-2.c
index 91e3631..ee564e8 100644
--- a/post/lib_ppc/fpu/20010114-2.c
+++ b/post/lib_ppc/fpu/20010114-2.c
@@ -30,6 +30,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
static float rintf (float x)
{
volatile float TWO23 = 8388608.0;
diff --git a/post/lib_ppc/fpu/20010226-1.c b/post/lib_ppc/fpu/20010226-1.c
index b00386b..099ca4a 100644
--- a/post/lib_ppc/fpu/20010226-1.c
+++ b/post/lib_ppc/fpu/20010226-1.c
@@ -30,6 +30,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
int fpu_post_test_math3 (void)
{
volatile long double dfrom = 1.1;
diff --git a/post/lib_ppc/fpu/980619-1.c b/post/lib_ppc/fpu/980619-1.c
index ceb2b76..46a31ae 100644
--- a/post/lib_ppc/fpu/980619-1.c
+++ b/post/lib_ppc/fpu/980619-1.c
@@ -30,6 +30,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
int fpu_post_test_math4 (void)
{
volatile float reale = 1.0f;
diff --git a/post/lib_ppc/fpu/Makefile b/post/lib_ppc/fpu/Makefile
index db43593..a681539 100644
--- a/post/lib_ppc/fpu/Makefile
+++ b/post/lib_ppc/fpu/Makefile
@@ -29,4 +29,5 @@ COBJS-$(CONFIG_HAS_POST) += acc1.o compare-fp-1.o mul-subnormal-single-1.o
include $(TOPDIR)/post/rules.mk
+CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//)
CFLAGS += -mhard-float -fkeep-inline-functions
diff --git a/post/lib_ppc/fpu/acc1.c b/post/lib_ppc/fpu/acc1.c
index 8a65193..9fca9b3 100644
--- a/post/lib_ppc/fpu/acc1.c
+++ b/post/lib_ppc/fpu/acc1.c
@@ -30,6 +30,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
static double func (const double *array)
{
double d = *array;
diff --git a/post/lib_ppc/fpu/compare-fp-1.c b/post/lib_ppc/fpu/compare-fp-1.c
index ab47657..f836b29 100644
--- a/post/lib_ppc/fpu/compare-fp-1.c
+++ b/post/lib_ppc/fpu/compare-fp-1.c
@@ -32,6 +32,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
static int failed;
#define TEST(c) if ((c) != ok) failed++
diff --git a/post/lib_ppc/fpu/fpu.c b/post/lib_ppc/fpu/fpu.c
index 846b76d..3f3adea 100644
--- a/post/lib_ppc/fpu/fpu.c
+++ b/post/lib_ppc/fpu/fpu.c
@@ -40,6 +40,8 @@
#include <watchdog.h>
+GNU_FPOST_ATTR
+
extern int fpu_status (void);
extern void fpu_enable (void);
extern void fpu_disable (void);
diff --git a/post/lib_ppc/fpu/mul-subnormal-single-1.c b/post/lib_ppc/fpu/mul-subnormal-single-1.c
index 9c514e1..1f3732d 100644
--- a/post/lib_ppc/fpu/mul-subnormal-single-1.c
+++ b/post/lib_ppc/fpu/mul-subnormal-single-1.c
@@ -32,6 +32,8 @@
#if CONFIG_POST & CONFIG_SYS_POST_FPU
+GNU_FPOST_ATTR
+
union uf
{
unsigned int u;
diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c
index 00a1e4e..41e5838 100644
--- a/tools/easylogo/easylogo.c
+++ b/tools/easylogo/easylogo.c
@@ -3,15 +3,19 @@
** ==============================
** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
** AIRVENT SAM s.p.a - RIMINI(ITALY)
+** (C) 2007-2008 Mike Frysinger <vapier@gentoo.org>
**
** This is still under construction!
*/
+#include <errno.h>
#include <getopt.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <unistd.h>
+#include <sys/stat.h>
#pragma pack(1)
@@ -49,6 +53,17 @@ typedef struct {
int width, height, pixels, bpp, pixel_size, size, palette_size, yuyv;
} image_t;
+void *xmalloc (size_t size)
+{
+ void *ret = malloc (size);
+ if (!ret) {
+ fprintf (stderr, "\nerror: malloc(%zu) failed: %s",
+ size, strerror(errno));
+ exit (1);
+ }
+ return ret;
+}
+
void StringUpperCase (char *str)
{
int count = strlen (str);
@@ -171,7 +186,7 @@ int image_load_tga (image_t * image, char *filename)
image->pixel_size = ((image->bpp - 1) / 8) + 1;
image->pixels = image->width * image->height;
image->size = image->pixels * image->pixel_size;
- image->data = malloc (image->size);
+ image->data = xmalloc (image->size);
if (image->bpp != 24) {
printf ("Bpp not supported: %d!\n", image->bpp);
@@ -192,7 +207,7 @@ int image_load_tga (image_t * image, char *filename)
/* Swapping image */
if (!(header.ImageDescriptorByte & 0x20)) {
- unsigned char *temp = malloc (image->size);
+ unsigned char *temp = xmalloc (image->size);
int linesize = image->pixel_size * image->width;
void *dest = image->data,
*source = temp + image->size - linesize;
@@ -239,7 +254,7 @@ int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image)
yuyv_image->pixels = yuyv_image->width * yuyv_image->height;
yuyv_image->size = yuyv_image->pixels * yuyv_image->pixel_size;
dest = (unsigned short *) (yuyv_image->data =
- malloc (yuyv_image->size));
+ xmalloc (yuyv_image->size));
yuyv_image->palette = 0;
yuyv_image->palette_size = 0;
@@ -261,6 +276,8 @@ int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image)
return 0;
}
+int use_gzip = 0;
+
int image_save_header (image_t * image, char *filename, char *varname)
{
FILE *file = fopen (filename, "w");
@@ -283,6 +300,65 @@ int image_save_header (image_t * image, char *filename, char *varname)
fprintf (file, " *\t\t'x'\t\tis the horizontal position\n");
fprintf (file, " *\t\t'y'\t\tis the vertical position\n */\n\n");
+ /* gzip compress */
+ if (use_gzip & 0x1) {
+ const char *errstr = NULL;
+ unsigned char *compressed;
+ struct stat st;
+ FILE *gz;
+ char *gzfilename = xmalloc(strlen (filename) + 20);
+ char *gzcmd = xmalloc(strlen (filename) + 20);
+
+ sprintf (gzfilename, "%s.gz", filename);
+ sprintf (gzcmd, "gzip > %s", gzfilename);
+ gz = popen (gzcmd, "w");
+ if (!gz) {
+ errstr = "\nerror: popen() failed";
+ goto done;
+ }
+ if (fwrite (image->data, image->size, 1, gz) != 1) {
+ errstr = "\nerror: writing data to gzip failed";
+ goto done;
+ }
+ if (pclose (gz)) {
+ errstr = "\nerror: gzip process failed";
+ goto done;
+ }
+
+ gz = fopen (gzfilename, "r");
+ if (!gz) {
+ errstr = "\nerror: open() on gzip data failed";
+ goto done;
+ }
+ if (stat (gzfilename, &st)) {
+ errstr = "\nerror: stat() on gzip file failed";
+ goto done;
+ }
+ compressed = xmalloc (st.st_size);
+ if (fread (compressed, st.st_size, 1, gz) != 1) {
+ errstr = "\nerror: reading gzip data failed";
+ goto done;
+ }
+ fclose (gz);
+
+ unlink (gzfilename);
+
+ dataptr = compressed;
+ count = st.st_size;
+ fprintf (file, "#define EASYLOGO_ENABLE_GZIP %i\n\n", count);
+ if (use_gzip & 0x2)
+ fprintf (file, "static unsigned char EASYLOGO_DECOMP_BUFFER[%i];\n\n", image->size);
+
+ done:
+ free (gzfilename);
+ free (gzcmd);
+
+ if (errstr) {
+ perror (errstr);
+ return -1;
+ }
+ }
+
/* Headers */
fprintf (file, "#include <video_easylogo.h>\n\n");
/* Macros */
@@ -300,8 +376,8 @@ int image_save_header (image_t * image, char *filename, char *varname)
fprintf (file, "#define DEF_%s_SIZE\t\t%d\n\n", def_name,
image->size);
/* Declaration */
- fprintf (file, "unsigned char DEF_%s_DATA[DEF_%s_SIZE] = {\n",
- def_name, def_name);
+ fprintf (file, "unsigned char DEF_%s_DATA[] = {\n",
+ def_name);
/* Data */
while (count)
@@ -359,6 +435,8 @@ static void usage (int exit_status)
"\n"
"Options:\n"
" -r Output RGB instead of YUYV\n"
+ " -g Compress with gzip\n"
+ " -b Preallocate space in bss for decompressing image\n"
" -h Help output\n"
"\n"
"Where: 'inputfile' is the TGA image to load\n"
@@ -377,7 +455,7 @@ int main (int argc, char *argv[])
image_t rgb_logo, yuyv_logo;
- while ((c = getopt(argc, argv, "hr")) > 0) {
+ while ((c = getopt(argc, argv, "hrgb")) > 0) {
switch (c) {
case 'h':
usage (0);
@@ -386,6 +464,14 @@ int main (int argc, char *argv[])
use_rgb = true;
puts ("Using 24-bit RGB Output Fromat");
break;
+ case 'g':
+ use_gzip |= 0x1;
+ puts ("Compressing with gzip");
+ break;
+ case 'b':
+ use_gzip |= 0x2;
+ puts ("Preallocating bss space for decompressing image");
+ break;
default:
usage (1);
break;