diff options
| -rw-r--r-- | board/sbc8548/sbc8548.c | 6 | ||||
| -rw-r--r-- | cpu/mpc85xx/interrupts.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 18 | ||||
| -rw-r--r-- | include/configs/sbc8548.h | 2 |
4 files changed, 19 insertions, 9 deletions
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 65052e6..d57548a 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -56,9 +56,10 @@ int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile u_char *rev= (void *)CFG_BD_REV; printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", - (volatile)(*(u_char *)CFG_BD_REV) >> 4); + (*rev) >> 4); /* * Initialize local bus. @@ -533,12 +534,12 @@ void ft_pci_setup(void *blob, bd_t *bd) { int node, tmp[2]; - const char *path; node = fdt_path_offset(blob, "/aliases"); tmp[0] = 0; if (node >= 0) { #ifdef CONFIG_PCI1 + const char *path; path = fdt_getprop(blob, node, "pci0", NULL); if (path) { tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; @@ -546,6 +547,7 @@ ft_pci_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE1 + const char *path; path = fdt_getprop(blob, node, "pci1", NULL); if (path) { tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 18e5377..4fe1fac 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -91,7 +91,7 @@ int interrupt_init (void) set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eb24dbc..15b804d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -992,7 +992,6 @@ trap_reloc: blr -#ifdef CFG_INIT_RAM_LOCK .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1002,11 +1001,20 @@ unlock_ram_in_cache: andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 -1: icbi r0,r3 - dcbi r0,r3 +1: dcbi r0,r3 addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b - sync /* Wait for all icbi to complete on bus */ + sync + + /* Invalidate the TLB entries for the cache */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 isync blr -#endif diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 0a7a904..516203a 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -168,7 +168,7 @@ #define CFG_OR0_PRELIM 0xff806e65 #define CFG_OR6_PRELIM 0xfc006e65 -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM |