diff options
| -rw-r--r-- | board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c | 7 | ||||
| -rw-r--r-- | board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c | 7 |
2 files changed, 12 insertions, 2 deletions
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c index 8ddaded..54a6d08 100644 --- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c @@ -500,6 +500,10 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + /* Disable the QSPI2 root clock */ + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + /* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | @@ -515,7 +519,8 @@ static void setup_gpmi_nand(void) MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK | + MXC_CCM_CCGR4_QSPI2_ENFC_MASK); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); diff --git a/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c index 70fe481..1e4bcbd 100644 --- a/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c +++ b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c @@ -546,6 +546,10 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + /* Disable the QSPI2 root clock */ + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + /* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | @@ -561,7 +565,8 @@ static void setup_gpmi_nand(void) MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK | + MXC_CCM_CCGR4_QSPI2_ENFC_MASK); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |