diff options
| -rw-r--r-- | MAINTAINERS | 1 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc512x/iopin.c | 54 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_512x.h | 13 | ||||
| -rw-r--r-- | board/ifm/ac14xx/Makefile | 34 | ||||
| -rw-r--r-- | board/ifm/ac14xx/ac14xx.c | 617 | ||||
| -rw-r--r-- | boards.cfg | 1 | ||||
| -rw-r--r-- | include/configs/ac14xx.h | 591 |
7 files changed, 1311 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index b6c7615..12c38d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -234,6 +234,7 @@ Wolfgang Grandegger <wg@denx.de> Anatolij Gustschin <agust@denx.de> + ac14xx MPC5121e O2D MPC5200 O2D300 MPC5200 O2DNT2 MPC5200 diff --git a/arch/powerpc/cpu/mpc512x/iopin.c b/arch/powerpc/cpu/mpc512x/iopin.c index be20947..1a39101 100644 --- a/arch/powerpc/cpu/mpc512x/iopin.c +++ b/arch/powerpc/cpu/mpc512x/iopin.c @@ -47,3 +47,57 @@ void iopin_initialize(iopin_t *ioregs_init, int len) } return; } + +void iopin_initialize_bits(iopin_t *ioregs_init, int len) +{ + short i, j, p; + u32 *reg, mask; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + reg = (u32 *)&(im->io_ctrl); + + /* iterate over table entries */ + for (i = 0; i < len; i++) { + /* iterate over pins within a table entry */ + for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) { + /* replace all settings at once */ + out_be32(reg + j, ioregs_init[i].val); + } else { + /* + * only replace individual parts, but + * REPLACE them instead of just ORing + * them in and "inheriting" previously + * set bits which we don't want + */ + mask = 0; + if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX) + mask |= IO_PIN_FMUX(3); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD) + mask |= IO_PIN_HOLD(3); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL) + mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG) + mask |= IO_PIN_ST(1); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR) + mask |= IO_PIN_DS(3); + /* + * DON'T do the "mask, then insert" + * in place on the register, it may + * break access to external hardware + * (like boot ROMs) when configuring + * LPB related pins, while the code to + * configure the pin is read from this + * very address region + */ + clrsetbits_be32(reg + j, mask, + ioregs_init[i].val & mask); + } + } + } +} diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 383e872..a330ad6 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -879,6 +879,19 @@ typedef struct iopin_t { void iopin_initialize(iopin_t *,int); /* + * support to adjust individual parts of the IO pin setup + */ + +#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ +#define IO_PIN_OVER_FMUX (1 << 1) +#define IO_PIN_OVER_HOLD (1 << 2) +#define IO_PIN_OVER_PULL (1 << 3) +#define IO_PIN_OVER_STRIG (1 << 4) +#define IO_PIN_OVER_DRVSTR (1 << 5) + +void iopin_initialize_bits(iopin_t *, int); + +/* * IIM */ typedef struct iim512x { diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile new file mode 100644 index 0000000..9a76f32 --- /dev/null +++ b/board/ifm/ac14xx/Makefile @@ -0,0 +1,34 @@ +# +# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c new file mode 100644 index 0000000..7442591 --- /dev/null +++ b/board/ifm/ac14xx/ac14xx.c @@ -0,0 +1,617 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2009 Dave Srl www.dave.eu + * (C) Copyright 2010 ifm ecomatic GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/bitops.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/mpc512x.h> +#include <fdt_support.h> +#ifdef CONFIG_MISC_INIT_R +#include <i2c.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void gpio_configure(void) +{ + immap_t *im; + gpio512x_t *gpioregs; + + im = (immap_t *) CONFIG_SYS_IMMR; + gpioregs = &im->gpio; + out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */ + out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */ + + /* + * out_be32(&gpioregs->gpdir, 0xC2293020); + * workaround for a hardware affect: configure direction in pieces, + * setting all outputs at once drops the reset line too low and + * makes us lose the MII connection (breaks ethernet for us) + */ + out_be32(&gpioregs->gpdir, 0x02003060); /* direction */ + setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */ + + /* to turn from red to yellow when U-Boot runs */ + setbits_be32(&gpioregs->gpdat, 0x00002020); + out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */ + out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */ + out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */ + out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */ +} + +/* the physical location of the pins */ +#define GPIOKEY_ROW_BITMASK 0x40000000 +#define GPIOKEY_ROW_UPPER 0 +#define GPIOKEY_ROW_LOWER 1 + +#define GPIOKEY_COL0_BITMASK 0x20000000 +#define GPIOKEY_COL1_BITMASK 0x10000000 +#define GPIOKEY_COL2_BITMASK 0x08000000 + +/* the logical presentation of pressed keys */ +#define GPIOKEY_BIT_FNLEFT (1 << 5) +#define GPIOKEY_BIT_FNRIGHT (1 << 4) +#define GPIOKEY_BIT_DIRUP (1 << 3) +#define GPIOKEY_BIT_DIRLEFT (1 << 2) +#define GPIOKEY_BIT_DIRRIGHT (1 << 1) +#define GPIOKEY_BIT_DIRDOWN (1 << 0) + +/* the hotkey combination which starts recovery */ +#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \ + GPIOKEY_BIT_DIRDOWN) + +static void gpio_selectrow(gpio512x_t *gpioregs, u32 row) +{ + + if (row) + setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); + else + clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); + udelay(10); +} + +static u32 gpio_querykbd(void) +{ + immap_t *im; + gpio512x_t *gpioregs; + u32 keybits; + u32 input; + + im = (immap_t *)CONFIG_SYS_IMMR; + gpioregs = &im->gpio; + keybits = 0; + + /* query upper row */ + gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER); + input = in_be32(&gpioregs->gpdat); + if ((input & GPIOKEY_COL0_BITMASK) == 0) + keybits |= GPIOKEY_BIT_FNLEFT; + if ((input & GPIOKEY_COL1_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRUP; + if ((input & GPIOKEY_COL2_BITMASK) == 0) + keybits |= GPIOKEY_BIT_FNRIGHT; + + /* query lower row */ + gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER); + input = in_be32(&gpioregs->gpdat); + if ((input & GPIOKEY_COL0_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRLEFT; + if ((input & GPIOKEY_COL1_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRRIGHT; + if ((input & GPIOKEY_COL2_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRDOWN; + + /* return bit pattern for keys */ + return keybits; +} + +/* excerpt from the recovery's hw_info.h */ + +static int eeprom_diag = 1; + +struct __attribute__ ((__packed__)) eeprom_layout { + char magic[3]; /** 'ifm' */ + u8 len[2]; /** content length without magic/len fields */ + u8 version[3]; /** structure version */ + u8 type; /** type of PCB */ + u8 reserved[0x37]; /** padding up to offset 0x40 */ + u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */ +}; + +#define HW_COMP_MAINCPU 2 + +static struct eeprom_layout eeprom_content; +static int eeprom_was_read; /* has_been_read */ +static int eeprom_is_valid; +static int eeprom_version; + +#define get_eeprom_field_int(name) ({ \ + int value; \ + int idx; \ + value = 0; \ + for (idx = 0; idx < sizeof(name); idx++) { \ + value <<= 8; \ + value |= name[idx]; \ + } \ + value; \ +}) + +static int read_eeprom(void) +{ + int eeprom_datalen; + int ret; + + if (eeprom_was_read) + return 0; + + eeprom_is_valid = 0; + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *)&eeprom_content, sizeof(eeprom_content)); + if (eeprom_diag) { + printf("DIAG: %s() read rc[%d], size[%d]\n", + __func__, ret, sizeof(eeprom_content)); + } + + if (ret != 0) + return -1; + + eeprom_was_read = 1; + + /* + * check validity of EEPROM content + * (check version, length, optionally checksum) + */ + eeprom_is_valid = 1; + eeprom_datalen = get_eeprom_field_int(eeprom_content.len); + eeprom_version = get_eeprom_field_int(eeprom_content.version); + + if (eeprom_diag) { + printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n", + __func__, eeprom_content.magic[0], + eeprom_content.magic[1], eeprom_content.magic[2], + eeprom_datalen, eeprom_version, eeprom_content.type); + } + if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0) + eeprom_is_valid = 0; + if (eeprom_datalen < sizeof(struct eeprom_layout) - 5) + eeprom_is_valid = 0; + if ((eeprom_version != 1) && (eeprom_version != 2)) + eeprom_is_valid = 0; + if (eeprom_content.type != HW_COMP_MAINCPU) + eeprom_is_valid = 0; + + if (eeprom_diag) + printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid); + + return ret; +} + +int mac_read_from_eeprom(void) +{ + const u8 *mac; + + if (read_eeprom()) { + printf("I2C EEPROM read failed.\n"); + return -1; + } + + if (!eeprom_is_valid) { + printf("I2C EEPROM content not valid\n"); + return -1; + } + + mac = NULL; + switch (eeprom_version) { + case 1: + case 2: + mac = (const u8 *)&eeprom_content.macaddress; + break; + } + + if (mac && is_valid_ether_addr(mac)) { + eth_setenv_enetaddr("ethaddr", mac); + printf("DIAG: %s() MAC value [%s]\n", + __func__, getenv("ethaddr")); + } + + return 0; +} + +/* + * BEWARE! + * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2 + * which the ADS, Aria or PDM360NG boards are using + * (the steps outlined here refer to the Micron datasheet) + */ +u32 sdram_init_seq[] = { + /* item 6, at least one NOP after CKE went high */ + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* item 7, precharge all; item 8, tRP (20ns) */ + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + /* item 9, extended mode register; item 10, tMRD 10ns) */ + CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 11, (base) mode register _with_ reset DLL; + * item 12, tMRD (10ns) + */ + CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL | + CONFIG_SYS_MICRON_BMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* item 13, precharge all; item 14, tRP (20ns) */ + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 15, auto refresh (i.e. refresh with CKE held high); + * item 16, tRFC (70ns) + */ + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 17, auto refresh (i.e. refresh with CKE held high); + * item 18, tRFC (70ns) + */ + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */ + CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 21, "actually done", but make sure 200 DRAM clock cycles + * have passed after DLL reset before READ requests are issued + * (200 cycles at 160MHz -> 1.25 usec) + */ + /* EMPTY, optional, we don't do it */ +}; + +phys_size_t initdram(int board_type) +{ + return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq)); +} + +int misc_init_r(void) +{ + u32 keys; + char *s; + int want_recovery; + + /* we use bus I2C-0 for the on-board eeprom */ + i2c_set_bus_num(0); + + /* setup GPIO directions and initial values */ + gpio_configure(); + + /* + * check the GPIO keyboard, + * enforced start of the recovery when + * - the appropriate keys were pressed + * - a previous installation was aborted or has failed + * - "some" external software told us to + */ + want_recovery = 0; + keys = gpio_querykbd(); + printf("GPIO keyboard status [0x%08X]\n", keys); + /* XXX insist in the _exact_ combination? */ + if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) { + printf("GPIO keyboard requested RECOVERY\n"); + /* XXX TODO + * refine the logic to detect the first keypress, and + * wait to recheck IF it was the recovery combination? + */ + want_recovery = 1; + } + s = getenv("install_in_progress"); + if ((s != NULL) && (*s != '\0')) { + printf("previous installation aborted, running RECOVERY\n"); + want_recovery = 1; + } + s = getenv("install_failed"); + if ((s != NULL) && (*s != '\0')) { + printf("previous installation FAILED, running RECOVERY\n"); + want_recovery = 1; + } + s = getenv("want_recovery"); + if ((s != NULL) && (*s != '\0')) { + printf("running RECOVERY according to the request\n"); + want_recovery = 1; + } + + if (want_recovery) + setenv("bootcmd", "run recovery"); + + /* + * boot the recovery system without waiting; boot the + * production system without waiting by default, only + * insert a pause (to provide a chance to get a prompt) + * when GPIO keys were pressed during power on + */ + if (want_recovery) + setenv("bootdelay", "0"); + else if (!keys) + setenv("bootdelay", "0"); + else + setenv("bootdelay", "2"); + + /* get the ethernet MAC from I2C EEPROM */ + mac_read_from_eeprom(); + + return 0; +} + +/* setup specific IO pad configuration */ +static iopin_t ioregs_init[] = { + { /* LPC CS3 */ + offsetof(struct ioctrl512x, io_control_nfc_ce0), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* LPC CS1 */ + offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS2 */ + offsetof(struct ioctrl512x, io_control_lpc_cs2), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS4, CS5 */ + offsetof(struct ioctrl512x, io_control_pata_ce1), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* SDHC CLK, CMD, D0, D1, D2, D3 */ + offsetof(struct ioctrl512x, io_control_pata_ior), 6, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* GPIO keyboard */ + offsetof(struct ioctrl512x, io_control_pci_ad30), 4, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO DN1 PF, LCD power, DN2 PF */ + offsetof(struct ioctrl512x, io_control_pci_ad26), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset AS-i */ + offsetof(struct ioctrl512x, io_control_pci_ad21), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset safety */ + offsetof(struct ioctrl512x, io_control_pci_ad19), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset netX */ + offsetof(struct ioctrl512x, io_control_pci_ad16), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO ma2 en */ + offsetof(struct ioctrl512x, io_control_pci_ad15), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO SD CD, SD WP */ + offsetof(struct ioctrl512x, io_control_pci_ad08), 2, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* FEC RX DV */ + offsetof(struct ioctrl512x, io_control_pci_ad06), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(2), + }, + { /* GPIO AS-i prog, AS-i done, LCD backlight */ + offsetof(struct ioctrl512x, io_control_pci_ad05), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO AS-i wdg */ + offsetof(struct ioctrl512x, io_control_pci_req2), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO safety wdg */ + offsetof(struct ioctrl512x, io_control_pci_req1), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO netX wdg */ + offsetof(struct ioctrl512x, io_control_pci_req0), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO IRQ powerfail */ + offsetof(struct ioctrl512x, io_control_pci_inta), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO AS-i PWRD */ + offsetof(struct ioctrl512x, io_control_pci_frame), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO LED0, LED1 */ + offsetof(struct ioctrl512x, io_control_pci_idsel), 2, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */ + offsetof(struct ioctrl512x, io_control_pci_irdy), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* DIU clk */ + offsetof(struct ioctrl512x, io_control_spdif_txclk), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(2), + }, + { /* FEC TX ER, CRS */ + offsetof(struct ioctrl512x, io_control_spdif_tx), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */ + offsetof(struct ioctrl512x, io_control_irq0), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* + * FEC col, tx en, tx clk, txd 0-3, mdc, rx er, + * rdx 3-0, mdio, rx clk + */ + offsetof(struct ioctrl512x, io_control_psc0_0), 15, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + /* optional: make sure PSC3 remains the serial console */ + { /* LPC CS6 */ + offsetof(struct ioctrl512x, io_control_psc3_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + /* make sure PSC4 remains available for SPI, + *BUT* PSC4_1 is a GPIO kind of SS! */ + { /* enforce drive strength on the SPI pin */ + offsetof(struct ioctrl512x, io_control_psc4_0), 5, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { + offsetof(struct ioctrl512x, io_control_psc4_1), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + /* optional: make sure PSC5 remains available for SPI */ + { /* enforce drive strength on the SPI pin */ + offsetof(struct ioctrl512x, io_control_psc5_0), 5, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(1), + }, + { /* LPC TSIZ1 */ + offsetof(struct ioctrl512x, io_control_psc6_0), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* DIU hsync */ + offsetof(struct ioctrl512x, io_control_psc6_1), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* DIU vsync */ + offsetof(struct ioctrl512x, io_control_psc6_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* PSC7, part of DIU RGB */ + offsetof(struct ioctrl512x, io_control_psc7_0), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* PSC7, safety UART */ + offsetof(struct ioctrl512x, io_control_psc7_2), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(0) | IO_PIN_DS(1), + }, + { /* DIU (part of) RGB[] */ + offsetof(struct ioctrl512x, io_control_psc8_3), 16, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* DIU data enable */ + offsetof(struct ioctrl512x, io_control_psc11_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + /* reduce LPB drive strength for improved EMI */ + { /* LPC OE, LPC RW */ + offsetof(struct ioctrl512x, io_control_lpc_oe), 2, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC AX03 through LPC AD00 */ + offsetof(struct ioctrl512x, io_control_lpc_ax03), 36, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS5 */ + offsetof(struct ioctrl512x, io_control_pata_ce2), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* SDHC CLK */ + offsetof(struct ioctrl512x, io_control_nfc_wp), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* SDHC DATA */ + offsetof(struct ioctrl512x, io_control_nfc_ale), 4, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, +}; + +int checkboard(void) +{ + puts("Board: ifm AC14xx\n"); + + /* initialize function mux & slew rate IO inter alia on IO Pins */ + iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init)); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ @@ -481,6 +481,7 @@ aria powerpc mpc512x - daveden mecp5123 powerpc mpc512x - esd mpc5121ads powerpc mpc512x mpc5121ads freescale mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2 +ac14xx powerpc mpc512x ac14xx ifm cmi_mpc5xx powerpc mpc5xx cmi PATI powerpc mpc5xx pati mpl a3m071 powerpc mpc5xxx a3m071 diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h new file mode 100644 index 0000000..ac7e877 --- /dev/null +++ b/include/configs/ac14xx.h @@ -0,0 +1,591 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2010 DAVE Srl <www.dave.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ifm AC14xx (MPC5121e based) board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AC14XX 1 +/* + * Memory map for the ifm AC14xx board: + * + * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) + * 0x8000_0000-0x803F_FFFF IMMR (4 MB) + * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx) + * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */ +#define SCFR1_IPS_DIV 2 +#define SCFR1_LPC_DIV 2 +#define SCFR1_NFC_DIV 2 +#define SCFR1_DIU_DIV 240 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) + +/* more aggressive 'mtest' over a wider address range */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x0FE00000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 + +/* + * DDR Controller Configuration XXX TODO + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ + +/* + * NOTE: although this board uses DDR1 only, the common source brings defaults + * for DDR2 init sequences, that's why we have to keep those here as well + */ + +/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */ +#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0)) + +#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \ + | (1 << 31) /* RST_B */ \ + | (1 << 30) /* CKE */ \ + | (1 << 29) /* CLK_ON */ \ + | (0 << 28) /* CMD_MODE */ \ + | (5 << 25) /* DRAM_ROW_SELECT */ \ + | (5 << 21) /* DRAM_BANK_SELECT */ \ + | (0 << 18) /* SELF_REF_EN */ \ + | (0 << 17) /* 16BIT_MODE */ \ + | (4 << 13) /* RDLY */ \ + | (1 << 12) /* HALF_DQS_DLY */ \ + | (0 << 11) /* QUART_DQS_DLY */ \ + | (1 << 8) /* WDLY */ \ + | (0 << 7) /* EARLY_ODT */ \ + | (0 << 6) /* ON_DIE_TERMINATE */ \ + | (0 << 5) /* FIFO_OV_CLEAR */ \ + | (0 << 4) /* FIFO_UV_CLEAR */ \ + | (0 << 1) /* FIFO_OV_EN */ \ + | (0 << 0) /* FIFO_UV_EN */ \ + ) + +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864 + +/* register address only, i.e. template without values */ +#define CONFIG_SYS_MICRON_BMODE 0x01000000 +#define CONFIG_SYS_MICRON_EMODE 0x01010000 +#define CONFIG_SYS_MICRON_EMODE2 0x01020000 +#define CONFIG_SYS_MICRON_EMODE3 0x01030000 +/* + * values for mode registers (without mode register address) + */ +/* CAS 2.5 (6), burst seq (0) and length 4 (2) */ +#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062 +#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100 +/* DLL enable, reduced drive strength */ +#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002 + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (0 << 10) | /* A10->DQS# */ \ + (0 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (0 << 2) | /* Rtt0 */ \ + (1 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) +#define CONFIG_SYS_MICRON_EMR2 0x01020000 +#define CONFIG_SYS_MICRON_EMR3 0x01030000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 +#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 +#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (1 << 10) | /* A10->DQS# */ \ + (7 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (1 << 2) | /* Rtt0 */ \ + (0 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) + +/* + * Backward compatible definitions, + * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c + */ +#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) +#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) +#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) + +/* DDR Priority Manager Configuration */ +#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 +#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 +#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 +#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { \ + CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \ + } +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_PROTECTION + +/* + * SRAM support + */ +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * CS related parameters + * TODO document these + */ +/* CS0 Flash */ +#define CONFIG_SYS_CS0_CFG 0x00031110 +#define CONFIG_SYS_CS0_START 0xFC000000 +#define CONFIG_SYS_CS0_SIZE 0x04000000 +/* CS1 FRAM */ +#define CONFIG_SYS_CS1_CFG 0x00011000 +#define CONFIG_SYS_CS1_START 0xE0000000 +#define CONFIG_SYS_CS1_SIZE 0x00010000 +/* CS2 AS-i 1 */ +#define CONFIG_SYS_CS2_CFG 0x00009100 +#define CONFIG_SYS_CS2_START 0xE0100000 +#define CONFIG_SYS_CS2_SIZE 0x00080000 +/* CS3 netX */ +#define CONFIG_SYS_CS3_CFG 0x000A1140 +#define CONFIG_SYS_CS3_START 0xE0300000 +#define CONFIG_SYS_CS3_SIZE 0x00020000 +/* CS5 safety */ +#define CONFIG_SYS_CS5_CFG 0x0011F000 +#define CONFIG_SYS_CS5_START 0xE0400000 +#define CONFIG_SYS_CS5_SIZE 0x00010000 +/* CS6 AS-i 2 */ +#define CONFIG_SYS_CS6_CFG 0x00009100 +#define CONFIG_SYS_CS6_START 0xE0200000 +#define CONFIG_SYS_CS6_SIZE 0x00080000 + +/* Don't use alternative CS timing for any CS */ +#define CONFIG_SYS_CS_ALETIMING 0x00000000 +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x00000020 +#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020 + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) +#else +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ +#define CONFIG_SYS_PSC3 +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +/* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSC_EN(7) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + + +#define CONFIG_CMDLINE_EDITING 1 /* command line history */ + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS + +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for Atmel AT24C01: + * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1F +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the flash sector size */ +#define CONFIG_ENV_ADDR 0xFFF40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_FUSE +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_EXT2 +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ +#endif + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ICE) +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME ac14xx +#define CONFIG_BOOTFILE "ac14xx/uImage" +#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" + +/* default load addr for tftp and bootm */ +#define CONFIG_LOADADDR 400000 + +#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ + +/* XXX TODO need to specify the builtin environment */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ + "muster_nr=00\0" \ + "fromram=run ramargs addip addtty; " \ + "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \ + "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \ + "tftp ${ramdisk_addr_r} k6m2/uFS-${muster_nr}; " \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "fromnfs=run nfsargs addip addtty; " \ + "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \ + "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fromflash=run nfsargs addip addtty; " \ + "bootm fc020000 - fc000000\0" \ + "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \ + "recovery=run mtdargsrec addip addtty; " \ + "bootm ffd20000 - ffee0000\0" \ + "production=run ramargs addip addtty; " \ + "bootm fc020000 fc400000 fc000000\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \ + "prodmtd=run mtdargs addip addtty; " \ + "bootm fc020000 - fc000000\0" \ + "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=600000\0" \ + "fdt_addr_r=a00000\0" \ + "ramdisk_addr_r=b00000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FC020000\0" \ + "fdt_addr=FC000000\0" \ + "ramdisk_addr=FC400000\0" \ + "verify=n\0" \ + "ramdiskfile=ac14xx/uRamdisk\0" \ + "u-boot=ac14xx/u-boot.bin\0" \ + "bootfile=ac14xx/uImage\0" \ + "fdtfile=ac14xx/ac14xx.dtb\0" \ + "rootpath=/opt/eldk/ppc_6xx\n" \ + "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ + "hostname=ac14xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}-${muster_nr}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run production" + +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 + +#define OF_CPU "PowerPC,5121@0" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +#endif /* __CONFIG_H */ |