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-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c105
-rw-r--r--board/freescale/mx6qsabresd/mx6qsabresd.c130
-rw-r--r--include/configs/mx6qsabre_common.h10
3 files changed, 245 insertions, 0 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 7724e5d..245b1a8 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -29,6 +29,10 @@
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
+#ifdef CONFIG_I2C_MXC
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+#endif
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
@@ -37,6 +41,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define I2C_EXP_RST IMX_GPIO_NR(1, 15)
+#define I2C3_STEER IMX_GPIO_NR(5, 4)
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -63,6 +69,29 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#ifdef CONFIG_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C2 pfuze */
+struct i2c_pads_info i2c_pad_info1 = {
+ /* don't support Sabreauto REVA */
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+#endif
+
int dram_init(void)
{
gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
@@ -113,6 +142,73 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+#ifdef CONFIG_I2C_MXC
+static int setup_pmic_voltages(void)
+{
+ unsigned char value, rev_id = 0 ;
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (!i2c_probe(0x8)) {
+ if (i2c_read(0x8, 0, 1, &value, 1)) {
+ printf("Read device ID error!\n");
+ return -1;
+ }
+ if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
+ printf("Read Rev ID error!\n");
+ return -1;
+ }
+ printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
+ /* set SW1AB staby volatage 0.975V*/
+ if (i2c_read(0x8, 0x21, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0x3f;
+ value |= 0x1b;
+ if (i2c_write(0x8, 0x21, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ if (i2c_read(0x8, 0x24, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0xc0;
+ value |= 0x40;
+ if (i2c_write(0x8, 0x24, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+
+ /* set SW1C staby volatage 0.975V*/
+ if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
+ printf("Read SW1CSTBY error!\n");
+ return -1;
+ }
+ value &= ~0x3f;
+ value |= 0x1b;
+ if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
+ printf("Set SW1CSTBY error!\n");
+ return -1;
+ }
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ if (i2c_read(0x8, 0x32, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0xc0;
+ value |= 0x40;
+ if (i2c_write(0x8, 0x32, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
@@ -397,10 +493,19 @@ static const struct boot_mode board_boot_modes[] = {
int board_late_init(void)
{
+ int ret;
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+#ifdef CONFIG_I2C_MXC
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE, &i2c_pad_info1);
+ ret = setup_pmic_voltages();
+ if (ret)
+ return -1;
+#endif
+
return 0;
}
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 6438631..a014596 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -28,6 +28,10 @@
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
+#if CONFIG_I2C_MXC
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+#endif
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
@@ -51,6 +55,28 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#if CONFIG_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C2 Camera, MIPI, pfuze */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+#endif
+
int dram_init(void)
{
gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
@@ -155,6 +181,101 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
+#ifdef CONFIG_I2C_MXC
+static int setup_pmic_voltages(void)
+{
+ unsigned char value, rev_id = 0 ;
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (!i2c_probe(0x8)) {
+ if (i2c_read(0x8, 0, 1, &value, 1)) {
+ printf("Read device ID error!\n");
+ return -1;
+ }
+ if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
+ printf("Read Rev ID error!\n");
+ return -1;
+ }
+ printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
+ /*For camera streaks issue,swap VGEN5 and VGEN3 to power camera.
+ *sperate VDDHIGH_IN and camera 2.8V power supply, after switch:
+ *VGEN5 for VDDHIGH_IN and increase to 3V to align with datasheet
+ *VGEN3 for camera 2.8V power supply
+ */
+ /*increase VGEN3 from 2.5 to 2.8V*/
+ if (i2c_read(0x8, 0x6e, 1, &value, 1)) {
+ printf("Read VGEN3 error!\n");
+ return -1;
+ }
+ value &= ~0xf;
+ value |= 0xa;
+ if (i2c_write(0x8, 0x6e, 1, &value, 1)) {
+ printf("Set VGEN3 error!\n");
+ return -1;
+ }
+ /*increase VGEN5 from 2.8 to 3V*/
+ if (i2c_read(0x8, 0x70, 1, &value, 1)) {
+ printf("Read VGEN5 error!\n");
+ return -1;
+ }
+ value &= ~0xf;
+ value |= 0xc;
+ if (i2c_write(0x8, 0x70, 1, &value, 1)) {
+ printf("Set VGEN5 error!\n");
+ return -1;
+ }
+ /* set SW1AB staby volatage 0.975V*/
+ if (i2c_read(0x8, 0x21, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0x3f;
+ value |= 0x1b;
+ if (i2c_write(0x8, 0x21, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ if (i2c_read(0x8, 0x24, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0xc0;
+ value |= 0x40;
+ if (i2c_write(0x8, 0x24, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+
+ /* set SW1C staby volatage 0.975V*/
+ if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
+ printf("Read SW1CSTBY error!\n");
+ return -1;
+ }
+ value &= ~0x3f;
+ value |= 0x1b;
+ if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
+ printf("Set SW1CSTBY error!\n");
+ return -1;
+ }
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ if (i2c_read(0x8, 0x32, 1, &value, 1)) {
+ printf("Read SW1ABSTBY error!\n");
+ return -1;
+ }
+ value &= ~0xc0;
+ value |= 0x40;
+ if (i2c_write(0x8, 0x32, 1, &value, 1)) {
+ printf("Set SW1ABSTBY error!\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
@@ -306,10 +427,19 @@ static const struct boot_mode board_boot_modes[] = {
int board_late_init(void)
{
+ int ret = 0;
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+#ifdef CONFIG_I2C_MXC
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SLAVE, &i2c_pad_info1);
+ ret = setup_pmic_voltages();
+ if (ret)
+ return -1;
+#endif
+
return 0;
}
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index cb6d1bc..0576d47 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -287,4 +287,14 @@
#define CONFIG_CMD_CACHE
#endif
+/*
+ * I2C configs
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x8
+
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
generated by cgit v1.1 at 2024-11-21 16:48:43 +0000