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-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c20
-rw-r--r--include/configs/mx6qarm2.h4
-rw-r--r--include/configs/mx6qsabre_common.h4
-rw-r--r--include/configs/mx6slevk.h4
4 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 7409df8..f4bac7a 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -24,6 +24,8 @@
*/
#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@@ -439,3 +441,21 @@ const struct boot_mode soc_boot_modes[] = {
void s_init(void)
{
}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ writel(1, &pl310->pl310_ctrl);
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ writel(0, &pl310->pl310_ctrl);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 67cf252..125b4cc 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -25,6 +25,10 @@
#define CONFIG_MX6
#define CONFIG_MX6Q
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x00A02000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include "mx6_common.h"
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index ee6ea00..644a378 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -19,6 +19,10 @@
#define CONFIG_MX6
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x00A02000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include "mx6_common.h"
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 48a3d84..0a649eb 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -19,6 +19,10 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x00A02000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define MACH_TYPE_MX6SLEVK 4307
#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK