diff options
| -rw-r--r-- | MAINTAINERS | 4 | ||||
| -rwxr-xr-x | MAKEALL | 1 | ||||
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | board/ip04/Makefile | 54 | ||||
| -rw-r--r-- | board/ip04/config.mk | 35 | ||||
| -rw-r--r-- | board/ip04/ip04.c | 42 | ||||
| -rw-r--r-- | include/configs/ip04.h | 157 |
7 files changed, 294 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index bb03f17..b617953 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1008,6 +1008,10 @@ Anton Shurpin <shurpin.aa@niistt.ru> BF561-ACVILON BF561 +Brent Kandetzki <brentk@teleco.com> + + IP04 BF532 + ######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -905,6 +905,7 @@ LIST_blackfin=" \ cm-bf548 \ cm-bf561 \ ibf-dsp561 \ + ip04 \ tcm-bf518 \ tcm-bf537 \ " @@ -3554,7 +3554,7 @@ BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 \ tcm-bf518 tcm-bf537 # Misc third party boards -BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp +BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp ip04 # I-SYST Micromodule BFIN_BOARDS += ibf-dsp561 diff --git a/board/ip04/Makefile b/board/ip04/Makefile new file mode 100644 index 0000000..e7ce304 --- /dev/null +++ b/board/ip04/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2010 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ip04/config.mk b/board/ip04/config.mk new file mode 100644 index 0000000..bc14257 --- /dev/null +++ b/board/ip04/config.mk @@ -0,0 +1,35 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c new file mode 100644 index 0000000..c8ae512 --- /dev/null +++ b/board/ip04/ip04.c @@ -0,0 +1,42 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2007 David Rowe, + * (c) 2006 Ivan Danov + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <net.h> +#include <netdev.h> +#include <asm/net.h> + +int checkboard(void) +{ + printf("Board: IP04 IP-PBX\n"); + printf(" http://www.rowetel.com/ucasterisk/ip04.html\n"); + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} + +int misc_init_r(void) +{ + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(enetaddr); + eth_setenv_enetaddr("ethaddr", enetaddr); + } + + return 0; +} +#endif diff --git a/include/configs/ip04.h b/include/configs/ip04.h new file mode 100644 index 0000000..425a745 --- /dev/null +++ b/include/configs/ip04.h @@ -0,0 +1,157 @@ +/* + * U-boot - Configuration file for IP04 board (having BF532 processor) + * + * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com + * + * Copyright (c) 2005-2010 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __CONFIG_IP04_H__ +#define __CONFIG_IP04_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf532-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 10000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 40 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 3 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x408 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 +#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_HOSTNAME IP04 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_NO_SROM +#define CONFIG_DM9000_BASE 0x20100000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + + +/* + * Flash Settings + */ +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_SYS_NO_FLASH /* we have only NAND */ + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_PREBOOT "echo starting from spi flash" +#define CONFIG_ENV_OFFSET 0x30000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + + +/* + * NAND Settings + */ +#define CONFIG_NAND_PLAT +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_READY PF10 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \ + bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \ + bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \ + bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \ + } while (0) + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R /* needed for MAC address */ +#define CONFIG_UART_CONSOLE 0 + +#undef CONFIG_SHOW_BOOT_PROGRESS +/* Enable this if bootretry required; currently it's disabled */ +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif |