diff options
| -rw-r--r-- | board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c | 173 | ||||
| -rwxr-xr-x | board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c | 82 | ||||
| -rw-r--r-- | include/configs/mx6sx_17x17_arm2.h | 8 | ||||
| -rw-r--r-- | include/configs/mx6sx_19x19_ddr3_arm2.h | 7 | ||||
| -rwxr-xr-x | include/configs/mx6sx_arm2.h | 41 |
5 files changed, 268 insertions, 43 deletions
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c index 38391ad..a0c248b 100644 --- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ @@ -84,7 +84,7 @@ struct i2c_pads_info i2c_pad_info2 = { int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = PHYS_SDRAM_SIZE; return 0; } @@ -94,6 +94,15 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6SX_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc3_pads[] = { MX6SX_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -105,6 +114,22 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6SX_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; #ifdef CONFIG_FEC_MXC @@ -145,15 +170,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Assume boot SD always present */ -} - #ifdef CONFIG_QSPI #define QSPI_PAD_CTRL1 \ @@ -186,15 +202,105 @@ int board_qspi_init(void) } #endif - #ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) + +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 dev_no; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + /* need ubstract 2 to map to the mmc device id + * see the comments in board_mmc_init function + */ + + dev_no--; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /*always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /*always present */ + break; + } + + return ret; +} + int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD2 (SDA) + * mmc1 SD3 (SDB) + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + u32 dev_no = mmc_get_env_devno(); + + setenv_ulong("mmcdev", dev_no); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); } + #endif #ifdef CONFIG_SPLASH_SCREEN @@ -483,7 +589,7 @@ int board_init(void) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); #endif -#ifdef CONFIG_FEC_MXC +#ifdef CONFIG_FEC_MXC setup_fec(); #endif @@ -505,6 +611,10 @@ int board_late_init(void) return -1; #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + return 0; } @@ -515,7 +625,36 @@ u32 get_board_rev(void) int checkboard(void) { - puts("Board: MX6SX 17x17 EVB\n"); + puts("Board: MX6SX 17x17 ARM2\n"); return 0; } + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} +#endif diff --git a/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c b/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c index 971b215..932a69f 100755 --- a/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c +++ b/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c @@ -81,7 +81,7 @@ struct i2c_pads_info i2c_pad_info2 = { int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = PHYS_SDRAM_SIZE; return 0; } @@ -138,15 +138,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Assume boot SD always present */ -} - #ifdef CONFIG_QSPI #define QSPI_PAD_CTRL1 \ @@ -178,13 +169,48 @@ int board_qspi_init(void) #endif #ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 dev_no; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + return dev_no; +} +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} int board_mmc_init(bd_t *bis) { + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (SDA) + */ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } + +void board_late_mmc_init(void) +{ + char cmd[32]; + u32 dev_no = mmc_get_env_devno(); + + setenv_ulong("mmcdev", dev_no); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + #endif #ifdef CONFIG_SPLASH_SCREEN @@ -238,7 +264,8 @@ int board_eth_init(bd_t *bis) setup_iomux_fec1(); - ret = cpu_eth_init(bis); + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC1 MXC: %s:failed\n", __func__); @@ -493,6 +520,10 @@ int board_late_init(void) return -1; #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + return 0; } @@ -507,3 +538,32 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} +#endif diff --git a/include/configs/mx6sx_17x17_arm2.h b/include/configs/mx6sx_17x17_arm2.h index 0cfc276..e32939e 100644 --- a/include/configs/mx6sx_17x17_arm2.h +++ b/include/configs/mx6sx_17x17_arm2.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2014 Freescale Semiconductor, Inc. * - * Configuration settings for the Freescale i.MX6SX 17x17 EVK board. + * Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -9,5 +9,11 @@ * the License, or (at your option) any later version. */ +#ifndef __MX6SX_17X17_ARM2_CONFIG_H +#define __MX6SX_17X17_ARM2_CONFIG_H + #include "mx6sx_arm2.h" +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 1 +#endif diff --git a/include/configs/mx6sx_19x19_ddr3_arm2.h b/include/configs/mx6sx_19x19_ddr3_arm2.h index 0cfc276..8506495 100644 --- a/include/configs/mx6sx_19x19_ddr3_arm2.h +++ b/include/configs/mx6sx_19x19_ddr3_arm2.h @@ -1,13 +1,18 @@ /* * Copyright (C) 2014 Freescale Semiconductor, Inc. * - * Configuration settings for the Freescale i.MX6SX 17x17 EVK board. + * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ +#ifndef __MX6SX_19X19_DDR3_ARM2_CONFIG_H +#define __MX6SX_19X19_DDR3_ARM2_CONFIG_H #include "mx6sx_arm2.h" +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif diff --git a/include/configs/mx6sx_arm2.h b/include/configs/mx6sx_arm2.h index a1629e8..2d8b33c 100755 --- a/include/configs/mx6sx_arm2.h +++ b/include/configs/mx6sx_arm2.h @@ -76,7 +76,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII #define CONFIG_CMD_NET -/* #define CONFIG_FEC_MXC */ +#define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII @@ -114,11 +114,6 @@ #define CONFIG_SF_DEFAULT_SPEED 40000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 40000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 - #endif /* CONFIG_CMD_SF */ #endif /* CONFIG_CMD_SPI */ @@ -181,7 +176,6 @@ "fdt_addr=0x84000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -258,7 +252,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 @@ -283,22 +277,30 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #ifdef CONFIG_SYS_BOOT_QSPI #define CONFIG_SYS_USE_QSPI -#define CONFIG_ENV_IS_NOWHERE /* No QSPI env for now */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_ENV_IS_IN_SPI_FLASH #else #define CONFIG_ENV_IS_IN_MMC #endif -#define CONFIG_SYS_MMC_ENV_DEV 0 + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +#define CONFIG_SYS_DCACHE_OFF #ifndef CONFIG_SYS_DCACHE_OFF #define CONFIG_CMD_CACHE #endif @@ -323,4 +325,17 @@ #endif #endif /* CONFIG_SPLASH_SCREEN */ +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + #endif /* __CONFIG_H */ |