diff options
| -rw-r--r-- | board/freescale/mx6qsabreauto/mx6solo.cfg | 122 | ||||
| -rw-r--r-- | boards.cfg | 1 |
2 files changed, 123 insertions, 0 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6solo.cfg b/board/freescale/mx6qsabreauto/mx6solo.cfg new file mode 100644 index 0000000..e0e58e1 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6solo.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000028 +DATA 4, 0x020e04c0, 0x00000028 +DATA 4, 0x020e04c4, 0x00000028 +DATA 4, 0x020e04c8, 0x00000028 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000028 +DATA 4, 0x020e0770, 0x00000028 +DATA 4, 0x020e0778, 0x00000028 +DATA 4, 0x020e077c, 0x00000028 +DATA 4, 0x020e0470, 0x00000028 +DATA 4, 0x020e0474, 0x00000028 +DATA 4, 0x020e0478, 0x00000028 +DATA 4, 0x020e047c, 0x00000028 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x421C0216 +DATA 4, 0x021b0840, 0x017B017A +DATA 4, 0x021b0848, 0x4B4A4E4C +DATA 4, 0x021b0850, 0x3F3F3334 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020025 +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x676B5313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x006B1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0000, 0x84190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x00025565 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F @@ -262,6 +262,7 @@ mx6qsabreauto arm armv7 mx6qsabreauto freesca mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q,DEFAULT_FDT_FILE="imx6q-sabresd.dtb",DDR_MB=1024 mx6solosabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/mx6qsabresd/mx6solo_4x_mt41j128.cfg,MX6DL,DEFAULT_FDT_FILE="imx6dl-sabresd.dtb",DDR_MB=512 +mx6solosabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6solo.cfg,MX6DL,DEFAULT_FDT_FILE="imx6dl-sabreauto.dtb",DDR_MB=1024 eco5pk arm armv7 eco5pk 8dtech omap3 nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 |