diff options
47 files changed, 3589 insertions, 393 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 45e2dd4..8603085 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1226,7 +1226,7 @@ Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> # Board CPU # ######################################################################### -Mike Frysinger <vapier@gentoo.org> +Sonic Zhang <sonic.adi@gmail.com> Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF506F-EZKIT BF506 @@ -1243,6 +1243,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF538F-EZKIT BF538 BF548-EZKIT BF548 BF561-EZKIT BF561 + BF609-EZKIT BF609 M.Hasewinkel (MHA) <info@ssv-embedded.de> diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 6a0bcca..b9fdb07 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -68,7 +68,9 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) /* Reset upon a double exception rather than just hanging. * Do not do bfin_read on SWRST as that will reset status bits. */ +# ifdef SWRST bfin_write_SWRST(DOUBLE_FAULT); +# endif #endif serial_early_puts("Board init flash\n"); @@ -92,7 +94,7 @@ int irq_init(void) #elif defined(SICA_IMASK0) bfin_write_SICA_IMASK0(0); bfin_write_SICA_IMASK1(0); -#else +#elif defined(SIC_IMASK) bfin_write_SIC_IMASK(0); #endif /* Set up a dummy NMI handler if needed. */ diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index 5674d42..f684be5 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -66,6 +66,14 @@ static struct gpio_port_t * const gpio_array[] = { (struct gpio_port_t *)PORTH_FER, (struct gpio_port_t *)PORTI_FER, (struct gpio_port_t *)PORTJ_FER, +#elif defined(CONFIG_BF60x) + (struct gpio_port_t *)PORTA_FER, + (struct gpio_port_t *)PORTB_FER, + (struct gpio_port_t *)PORTC_FER, + (struct gpio_port_t *)PORTD_FER, + (struct gpio_port_t *)PORTE_FER, + (struct gpio_port_t *)PORTF_FER, + (struct gpio_port_t *)PORTG_FER, #else # error no gpio arrays defined #endif @@ -216,6 +224,12 @@ static void port_setup(unsigned gpio, unsigned short usage) else gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); SSYNC(); +#elif defined(CONFIG_BF60x) + if (usage == GPIO_USAGE) + gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio); + else + gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio); + SSYNC(); #endif } @@ -290,7 +304,7 @@ static void portmux_setup(unsigned short per) } } } -#elif defined(CONFIG_BF54x) +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x) inline void portmux_setup(unsigned short per) { u32 pmux; @@ -330,7 +344,7 @@ inline void portmux_setup(unsigned short per) # define portmux_setup(...) do { } while (0) #endif -#ifndef CONFIG_BF54x +#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x) /*********************************************************** * * FUNCTIONS: Blackfin General Purpose Ports Access Functions @@ -534,7 +548,7 @@ int peripheral_request(unsigned short per, const char *label) * be requested and used by several drivers */ -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) { #else if (!(per & P_MAYSHARE)) { @@ -651,7 +665,7 @@ int bfin_gpio_request(unsigned gpio, const char *label) gpio, get_label(gpio)); return -EBUSY; } -#ifndef CONFIG_BF54x +#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x) else { /* Reset POLAR setting when acquiring a gpio for the first time */ set_gpio_polar(gpio, 0); } @@ -732,12 +746,16 @@ void bfin_special_gpio_free(unsigned gpio) static inline void __bfin_gpio_direction_input(unsigned gpio) { -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); #else gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); #endif +#if defined(CONFIG_BF60x) + gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio); +#else gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); +#endif } int bfin_gpio_direction_input(unsigned gpio) @@ -785,9 +803,13 @@ int bfin_gpio_direction_output(unsigned gpio, int value) local_irq_save(flags); +#if defined(CONFIG_BF60x) + gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio); +#else gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); +#endif gpio_set_value(gpio, value); -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); #else gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); @@ -801,7 +823,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value) int bfin_gpio_get_value(unsigned gpio) { -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio))); #else unsigned long flags; diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index fb3a101..1a06680 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -15,20 +15,141 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/bootrom.h> #include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> #define BUG() while (1) { asm volatile("emuexcpt;"); } #include "serial.h" +#ifndef __ADSPBF60x__ +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#else /* __ADSPBF60x__ */ +#include <asm/mach-common/bits/cgu.h> + +#define CONFIG_BFIN_GET_DCLK_M \ + ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000)) + +#ifndef CONFIG_DMC_DDRCFG +#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \ + (CONFIG_BFIN_GET_DCLK_M != 133) && \ + (CONFIG_BFIN_GET_DCLK_M != 150) && \ + (CONFIG_BFIN_GET_DCLK_M != 166) && \ + (CONFIG_BFIN_GET_DCLK_M != 200) && \ + (CONFIG_BFIN_GET_DCLK_M != 225) && \ + (CONFIG_BFIN_GET_DCLK_M != 250)) +#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" +#endif +#endif + +/* DMC control bits */ +#define SRREQ 0x8 + +/* DMC status bits */ +#define IDLE 0x1 +#define MEMINITDONE 0x4 +#define SRACK 0x8 +#define PDACK 0x10 +#define DPDACK 0x20 +#define DLLCALDONE 0x2000 +#define PENDREF 0xF0000 +#define PHYRDPHASE 0xF00000 +#define PHYRDPHASE_OFFSET 20 + +/* DMC DLL control bits */ +#define DLLCALRDCNT 0xFF +#define DATACYC_OFFSET 8 + +struct ddr_config { + u32 ddr_clk; + u32 dmc_ddrctl; + u32 dmc_ddrcfg; + u32 dmc_ddrtr0; + u32 dmc_ddrtr1; + u32 dmc_ddrtr2; + u32 dmc_ddrmr; + u32 dmc_ddrmr1; +}; + +static struct ddr_config ddr_config_table[] = { + [0] = { + .ddr_clk = 125, /* 125MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20705212, + .dmc_ddrtr1 = 0x201003CF, + .dmc_ddrtr2 = 0x00320107, + .dmc_ddrmr = 0x00000422, + .dmc_ddrmr1 = 0x4, + }, + [1] = { + .ddr_clk = 133, /* 133MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20806313, + .dmc_ddrtr1 = 0x2013040D, + .dmc_ddrtr2 = 0x00320108, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [2] = { + .ddr_clk = 150, /* 150MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x20160492, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [3] = { + .ddr_clk = 166, /* 166MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x2016050E, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [4] = { + .ddr_clk = 200, /* 200MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20a07323, + .dmc_ddrtr1 = 0x2016050f, + .dmc_ddrtr2 = 0x00320509, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [5] = { + .ddr_clk = 225, /* 225MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x302006DB, + .dmc_ddrtr2 = 0x0032020D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, + [6] = { + .ddr_clk = 250, /* 250MHz */ + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x3020079E, + .dmc_ddrtr2 = 0x0032050D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, +}; +#endif /* __ADSPBF60x__ */ + __attribute__((always_inline)) static inline void serial_init(void) { - uint32_t uart_base = UART_DLL; + uint32_t uart_base = UART_BASE; -#ifdef __ADSPBF54x__ +#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__) # ifdef BFIN_BOOT_UART_USE_RTS # define BFIN_UART_USE_RTS 1 # else @@ -38,7 +159,12 @@ static inline void serial_init(void) size_t i; /* force RTS rather than relying on auto RTS */ +#if BFIN_UART_HW_VER < 4 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL); +#else + bfin_write32(&pUART->control, bfin_read32(&pUART->control) | + FCPOL); +#endif /* Wait for the line to clear up. We cannot rely on UART * registers as none of them reflect the status of the RSR. @@ -68,13 +194,14 @@ static inline void serial_init(void) #endif if (BFIN_DEBUG_EARLY_SERIAL) { - int ucen = bfin_read16(&pUART->gctl) & UCEN; + int enabled = serial_early_enabled(uart_base); + serial_early_init(uart_base); /* If the UART is off, that means we need to program * the baud rate ourselves initially. */ - if (ucen != UCEN) + if (!enabled) serial_early_set_baud(uart_base, CONFIG_BAUDRATE); } } @@ -82,12 +209,17 @@ static inline void serial_init(void) __attribute__((always_inline)) static inline void serial_deinit(void) { -#ifdef __ADSPBF54x__ - uint32_t uart_base = UART_DLL; +#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__) + uint32_t uart_base = UART_BASE; if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { /* clear forced RTS rather than relying on auto RTS */ +#if BFIN_UART_HW_VER < 4 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); +#else + bfin_write32(&pUART->control, bfin_read32(&pUART->control) & + ~FCPOL); +#endif } #endif } @@ -95,7 +227,7 @@ static inline void serial_deinit(void) __attribute__((always_inline)) static inline void serial_putc(char c) { - uint32_t uart_base = UART_DLL; + uint32_t uart_base = UART_BASE; if (!BFIN_DEBUG_EARLY_SERIAL) return; @@ -103,9 +235,9 @@ static inline void serial_putc(char c) if (c == '\n') serial_putc('\r'); - bfin_write16(&pUART->thr, c); + bfin_write(&pUART->thr, c); - while (!(bfin_read16(&pUART->lsr) & TEMT)) + while (!(_lsr_read(pUART) & TEMT)) continue; } @@ -152,6 +284,24 @@ program_nmi_handler(void) # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD #endif +#ifdef __ADSPBF60x__ + +#ifndef CONFIG_CGU_CTL_VAL +# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF) +#endif + +#ifndef CONFIG_CGU_DIV_VAL +# define CONFIG_CGU_DIV_VAL \ + ((CONFIG_CCLK_DIV << CSEL_P) | \ + (CONFIG_SCLK0_DIV << S0SEL_P) | \ + (CONFIG_SCLK_DIV << SYSSEL_P) | \ + (CONFIG_SCLK1_DIV << S1SEL_P) | \ + (CONFIG_DCLK_DIV << DSEL_P) | \ + (CONFIG_OCLK_DIV << OSEL_P)) +#endif + +#else /* __ADSPBF60x__ */ + /* PLL_DIV defines */ #ifndef CONFIG_PLL_DIV_VAL # if (CONFIG_CCLK_DIV == 1) @@ -275,6 +425,8 @@ program_nmi_handler(void) # endif #endif +#endif /* __ADSPBF60x__ */ + __attribute__((always_inline)) static inline void program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) { @@ -283,8 +435,14 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) /* Save the clock pieces that are used in baud rate calculation */ if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { serial_putc('b'); +#ifdef __ADSPBF60x__ + *sdivB = bfin_read_CGU_DIV(); + *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7); + *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f; +#else *sdivB = bfin_read_PLL_DIV() & 0xf; *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; +#endif *divB = serial_early_get_div(); serial_putc('c'); } @@ -303,8 +461,21 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { serial_putc('e'); +#ifdef __ADSPBF60x__ + bfin_write_SEC_GCTL(0x2); + SSYNC(); + bfin_write_SEC_FCTL(0xc1); + bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6); + + bfin_write_SEC_CCTL(0x2); + SSYNC(); + bfin_write_SEC_GCTL(0x1); + bfin_write_SEC_CCTL(0x1); +#endif bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); +#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART bfin_write_WDOG_CTL(0); +#endif serial_putc('f'); } #endif @@ -316,6 +487,7 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) * boot. Once we switch over to u-boot's SPI flash driver, we'll * increase the speed appropriately. */ +#ifdef SPI_BAUD if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { serial_putc('h'); if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) @@ -323,6 +495,7 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); serial_putc('i'); } +#endif serial_putc('j'); } @@ -335,6 +508,15 @@ maybe_self_refresh(ADI_BOOT_DATA *bs) if (!CONFIG_MEM_SIZE) return false; +#ifdef __ADSPBF60x__ + /* resume from hibernate, return false let ddr initialize */ + if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) { + serial_putc('b'); + return false; + } + +#else /* __ADSPBF60x__ */ + /* If external memory is enabled, put it into self refresh first. */ #if defined(EBIU_RSTCTL) if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { @@ -350,6 +532,7 @@ maybe_self_refresh(ADI_BOOT_DATA *bs) } #endif +#endif /* __ADSPBF60x__ */ serial_putc('c'); return false; @@ -362,6 +545,37 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) serial_putc('a'); +#ifdef __ADSPBF60x__ + if (bfin_read_DMC0_STAT() & MEMINITDONE) { + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); + SSYNC(); + while (!(bfin_read_DMC0_STAT() & SRACK)) + continue; + } + + /* Don't set the same value of MSEL and DF to CGU_CTL */ + if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK)) + != CONFIG_CGU_CTL_VAL) { + bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL); + bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL); + while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) || + !(bfin_read_CGU_STAT() & PLLLK)) + continue; + } + + bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT); + while (bfin_read_CGU_STAT() & CLKSALGN) + continue; + + if (bfin_read_DMC0_STAT() & MEMINITDONE) { + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); + SSYNC(); + while (bfin_read_DMC0_STAT() & SRACK) + continue; + } + +#else /* __ADSPBF60x__ */ + vr_ctl = bfin_read_VR_CTL(); serial_putc('b'); @@ -433,7 +647,7 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) #elif defined(SICA_IWR0) bfin_write_SICA_IWR0(1); bfin_write_SICA_IWR1(0); -#else +#elif defined(SIC_IWR) bfin_write_SIC_IWR(1); #endif @@ -482,13 +696,15 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) #elif defined(SICA_IWR0) bfin_write_SICA_IWR0(-1); bfin_write_SICA_IWR1(-1); -#else +#elif defined(SIC_IWR) bfin_write_SIC_IWR(-1); #endif serial_putc('n'); } +#endif /* __ADSPBF60x__ */ + serial_putc('o'); return vr_ctl; @@ -505,16 +721,25 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) * for dividing which means we'd generate a libgcc reference. */ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { - serial_putc('b'); unsigned int sdivR, vcoR; - sdivR = bfin_read_PLL_DIV() & 0xf; - vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; int dividend = sdivB * divB * vcoR; int divisor = vcoB * sdivR; unsigned int quotient; + + serial_putc('b'); + +#ifdef __ADSPBF60x__ + sdivR = bfin_read_CGU_DIV(); + sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7); + vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f; +#else + sdivR = bfin_read_PLL_DIV() & 0xf; + vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; +#endif + for (quotient = 0; dividend > 0; ++quotient) dividend -= divisor; - serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230); + serial_early_put_div(quotient - ANOMALY_05000230); serial_putc('c'); } @@ -531,6 +756,85 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) serial_putc('b'); +#ifdef __ADSPBF60x__ + int dlldatacycle; + int dll_ctl; + int i = 0; + + if (CONFIG_BFIN_GET_DCLK_M == 125) + i = 0; + else if (CONFIG_BFIN_GET_DCLK_M == 133) + i = 1; + else if (CONFIG_BFIN_GET_DCLK_M == 150) + i = 2; + else if (CONFIG_BFIN_GET_DCLK_M == 166) + i = 3; + else if (CONFIG_BFIN_GET_DCLK_M == 200) + i = 4; + else if (CONFIG_BFIN_GET_DCLK_M == 225) + i = 5; + else if (CONFIG_BFIN_GET_DCLK_M == 250) + i = 6; + +#if 0 + for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++) + if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk) + break; +#endif + +#ifndef CONFIG_DMC_DDRCFG + bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); +#else + bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG); +#endif +#ifndef CONFIG_DMC_DDRTR0 + bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); +#else + bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0); +#endif +#ifndef CONFIG_DMC_DDRTR1 + bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); +#else + bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1); +#endif +#ifndef CONFIG_DMC_DDRTR2 + bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); +#else + bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2); +#endif +#ifndef CONFIG_DMC_DDRMR + bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); +#else + bfin_write_DMC0_MR(CONFIG_DMC_DDRMR); +#endif +#ifndef CONFIG_DMC_DDREMR1 + bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); +#else + bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1); +#endif +#ifndef CONFIG_DMC_DDRCTL + bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); +#else + bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL); +#endif + + SSYNC(); + while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) + continue; + + dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> + PHYRDPHASE_OFFSET; + dll_ctl = bfin_read_DMC0_DLLCTL(); + dll_ctl &= 0x0ff; + bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); + + SSYNC(); + while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) + continue; + serial_putc('!'); + +#else /* __ADSPBF60x__ */ + /* Program the external memory controller before we come out of * self-refresh. This only works with our SDRAM controller. */ @@ -583,6 +887,7 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) # endif #endif +#endif /* __ADSPBF60x__ */ serial_putc('e'); } @@ -595,7 +900,46 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) return; serial_putc('b'); +#ifdef __ADSPBF60x__ + if (bfin_read32(DPM0_RESTORE0) != 0) { + uint32_t reg = bfin_read_DMC0_CTL(); + reg &= ~0x8; + bfin_write_DMC0_CTL(reg); + + while ((bfin_read_DMC0_STAT() & 0x8)) + continue; + while (!(bfin_read_DMC0_STAT() & 0x1)) + continue; + + serial_putc('z'); + uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4); + SSYNC(); /* make sure memory controller is done */ + if (hibernate_magic[0] == 0xDEADBEEF) { + serial_putc('c'); + SSYNC(); + bfin_write_EVT15(hibernate_magic[1]); + bfin_write_IMASK(EVT_IVG15); + __asm__ __volatile__ ( + /* load reti early to avoid anomaly 281 */ + "reti = %2;" + /* clear hibernate magic */ + "[%0] = %1;" + /* load stack pointer */ + "SP = [%0 + 8];" + /* lower ourselves from reset ivg to ivg15 */ + "raise 15;" + "nop;nop;nop;" + "rti;" + : + : "p"(hibernate_magic), + "d"(0x2000 /* jump.s 0 */), + "d"(0xffa00000) + ); + } + + } +#else /* Are we coming out of hibernate (suspend to memory) ? * The memory layout is: * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF) @@ -606,7 +950,8 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) */ if (ANOMALY_05000307 || vr_ctl & 0x8000) { uint32_t *hibernate_magic = 0; - __builtin_bfin_ssync(); /* make sure memory controller is done */ + + SSYNC(); if (hibernate_magic[0] == 0xDEADBEEF) { serial_putc('c'); bfin_write_EVT15(hibernate_magic[1]); @@ -627,6 +972,7 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) } serial_putc('d'); } +#endif serial_putc('e'); } diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h index e0aad6d..1fec7f3 100644 --- a/arch/blackfin/cpu/initcode.h +++ b/arch/blackfin/cpu/initcode.h @@ -15,6 +15,8 @@ # define serial_putc(c) #endif +#ifndef __ADSPBF60x__ + #ifndef CONFIG_EBIU_RSTCTL_VAL # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ #endif @@ -30,6 +32,8 @@ # error invalid EBIU_DDRQUE value: must not set reserved bits #endif +#endif /* __ADSPBF60x__ */ + __attribute__((always_inline)) static inline void program_async_controller(ADI_BOOT_DATA *bs) { @@ -45,10 +49,13 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('a'); +#ifdef __ADSPBF60x__ /* Program the async banks controller. */ +#ifdef EBIU_AMGCTL bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); +#endif serial_putc('b'); @@ -66,6 +73,51 @@ program_async_controller(ADI_BOOT_DATA *bs) #endif serial_putc('c'); + +#else /* __ADSPBF60x__ */ + /* Program the static memory controller. */ +# ifdef CONFIG_SMC_GCTL_VAL + bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL); +# endif +# ifdef CONFIG_SMC_B0CTL_VAL + bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL); +# endif +# ifdef CONFIG_SMC_B0TIM_VAL + bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL); +# endif +# ifdef CONFIG_SMC_B0ETIM_VAL + bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL); +# endif +# ifdef CONFIG_SMC_B1CTL_VAL + bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL); +# endif +# ifdef CONFIG_SMC_B1TIM_VAL + bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL); +# endif +# ifdef CONFIG_SMC_B1ETIM_VAL + bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL); +# endif +# ifdef CONFIG_SMC_B2CTL_VAL + bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL); +# endif +# ifdef CONFIG_SMC_B2TIM_VAL + bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL); +# endif +# ifdef CONFIG_SMC_B2ETIM_VAL + bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL); +# endif +# ifdef CONFIG_SMC_B3CTL_VAL + bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL); +# endif +# ifdef CONFIG_SMC_B3TIM_VAL + bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL); +# endif +# ifdef CONFIG_SMC_B3ETIM_VAL + bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL); +# endif + +#endif + serial_putc('d'); } #endif diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c index ff39035..b6718d3 100644 --- a/arch/blackfin/cpu/reset.c +++ b/arch/blackfin/cpu/reset.c @@ -23,6 +23,7 @@ __attribute__ ((__l1_text__, __noreturn__)) static void bfin_reset(void) { +#ifdef SWRST /* Wait for completion of "system" events such as cache line * line fills so that we avoid infinite stalls later on as * much as possible. This code is in L1, so it won't trigger @@ -66,10 +67,15 @@ static void bfin_reset(void) : "a" (15 * 1) : "LC1", "LB1", "LT1" ); +#endif while (1) +#if defined(__ADSPBF60x__) + bfin_write_RCU0_CTL(0x1); +#else /* Issue core reset */ asm("raise 1"); +#endif } /* We need to trampoline ourselves up into L1 since our linker diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c index 64340ec..9847e9f 100644 --- a/arch/blackfin/cpu/serial.c +++ b/arch/blackfin/cpu/serial.c @@ -43,7 +43,6 @@ #include <serial.h> #include <linux/compiler.h> #include <asm/blackfin.h> -#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,8 +51,8 @@ DECLARE_GLOBAL_DATA_PTR; #include "serial.h" #ifdef CONFIG_DEBUG_SERIAL -static uint16_t cached_lsr[256]; -static uint16_t cached_rbr[256]; +static uart_lsr_t cached_lsr[256]; +static uart_lsr_t cached_rbr[256]; static size_t cache_count; /* The LSR is read-to-clear on some parts, so we have to make sure status @@ -61,10 +60,10 @@ static size_t cache_count; * works around anomaly 05000099 at the same time by keeping a cumulative * tally of all the status bits. */ -static uint16_t uart_lsr_save; -static uint16_t uart_lsr_read(uint32_t uart_base) +static uart_lsr_t uart_lsr_save; +static uart_lsr_t uart_lsr_read(uint32_t uart_base) { - uint16_t lsr = bfin_read(&pUART->lsr); + uart_lsr_t lsr = _lsr_read(pUART); uart_lsr_save |= (lsr & (OE|PE|FE|BI)); return lsr | uart_lsr_save; } @@ -72,20 +71,20 @@ static uint16_t uart_lsr_read(uint32_t uart_base) static void uart_lsr_clear(uint32_t uart_base) { uart_lsr_save = 0; - bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1); + _lsr_write(pUART, -1); } #else /* When debugging is disabled, we only care about the DR bit, so if other * bits get set/cleared, we don't really care since we don't read them * anyways (and thus anomaly 05000099 is irrelevant). */ -static inline uint16_t uart_lsr_read(uint32_t uart_base) +static inline uart_lsr_t uart_lsr_read(uint32_t uart_base) { - return bfin_read(&pUART->lsr); + return _lsr_read(pUART); } static void uart_lsr_clear(uint32_t uart_base) { - bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1); + _lsr_write(pUART, -1); } #endif @@ -127,20 +126,14 @@ static int uart_getc(uint32_t uart_base) #ifdef CONFIG_DEBUG_SERIAL /* grab & clear the LSR */ - uint16_t uart_lsr_val = uart_lsr_read(uart_base); + uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base); cached_lsr[cache_count] = uart_lsr_val; cached_rbr[cache_count] = uart_rbr_val; cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr); if (uart_lsr_val & (OE|PE|FE|BI)) { - uint16_t dll, dlh; printf("\n[SERIAL ERROR]\n"); - ACCESS_LATCH(); - dll = bfin_read(&pUART->dll); - dlh = bfin_read(&pUART->dlh); - ACCESS_PORT_IER(); - printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh); do { --cache_count; printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count, @@ -160,6 +153,8 @@ static int uart_getc(uint32_t uart_base) # define LOOP(x) #endif +#if BFIN_UART_HW_VER < 4 + LOOP( static void uart_loop(uint32_t uart_base, int state) { @@ -178,6 +173,28 @@ static void uart_loop(uint32_t uart_base, int state) } ) +#else + +LOOP( +static void uart_loop(uint32_t uart_base, int state) +{ + u32 control; + + /* Drain the TX fifo first so bytes don't come back */ + while (!(uart_lsr_read(uart_base) & TEMT)) + continue; + + control = bfin_read(&pUART->control); + if (state) + control |= LOOP_ENA | MRTS; + else + control &= ~(LOOP_ENA | MRTS); + bfin_write(&pUART->control, control); +} +) + +#endif + #ifdef CONFIG_SYS_BFIN_UART static void uart_puts(uint32_t uart_base, const char *s) @@ -246,16 +263,16 @@ struct serial_device bfin_serial##n##_device = { \ LOOP(.loop = uart##n##_loop) \ }; -#ifdef UART0_DLL +#ifdef UART0_RBR DECL_BFIN_UART(0) #endif -#ifdef UART1_DLL +#ifdef UART1_RBR DECL_BFIN_UART(1) #endif -#ifdef UART2_DLL +#ifdef UART2_RBR DECL_BFIN_UART(2) #endif -#ifdef UART3_DLL +#ifdef UART3_RBR DECL_BFIN_UART(3) #endif @@ -274,16 +291,16 @@ __weak struct serial_device *default_serial_console(void) void bfin_serial_initialize(void) { -#ifdef UART0_DLL +#ifdef UART0_RBR serial_register(&bfin_serial0_device); #endif -#ifdef UART1_DLL +#ifdef UART1_RBR serial_register(&bfin_serial1_device); #endif -#ifdef UART2_DLL +#ifdef UART2_RBR serial_register(&bfin_serial2_device); #endif -#ifdef UART3_DLL +#ifdef UART3_RBR serial_register(&bfin_serial3_device); #endif } @@ -293,7 +310,7 @@ void bfin_serial_initialize(void) /* Symbol for our assembly to call. */ void serial_set_baud(uint32_t baud) { - serial_early_set_baud(UART_DLL, baud); + serial_early_set_baud(UART_BASE, baud); } /* Symbol for common u-boot code to call. @@ -307,7 +324,7 @@ void serial_setbrg(void) /* Symbol for our assembly to call. */ void serial_initialize(void) { - serial_early_init(UART_DLL); + serial_early_init(UART_BASE); } /* Symbol for common u-boot code to call. */ @@ -315,23 +332,23 @@ int serial_init(void) { serial_initialize(); serial_setbrg(); - uart_lsr_clear(UART_DLL); + uart_lsr_clear(UART_BASE); return 0; } int serial_tstc(void) { - return uart_tstc(UART_DLL); + return uart_tstc(UART_BASE); } int serial_getc(void) { - return uart_getc(UART_DLL); + return uart_getc(UART_BASE); } void serial_putc(const char c) { - uart_putc(UART_DLL, c); + uart_putc(UART_BASE, c); } void serial_puts(const char *s) @@ -343,7 +360,7 @@ void serial_puts(const char *s) LOOP( void serial_loop(int state) { - uart_loop(UART_DLL, state); + uart_loop(UART_BASE, state); } ) diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index 8a076dd..9200339 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -3,7 +3,7 @@ * any functions defined here must be always_inline since * initcode cannot have function calls. * - * Copyright (c) 2004-2007 Analog Devices Inc. + * Copyright (c) 2004-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -12,7 +12,7 @@ #define __BFIN_CPU_SERIAL_H__ #include <asm/blackfin.h> -#include <asm/mach-common/bits/uart.h> +#include <asm/portmux.h> #ifndef CONFIG_UART_CONSOLE # define CONFIG_UART_CONSOLE 0 @@ -24,88 +24,34 @@ # define BFIN_DEBUG_EARLY_SERIAL 0 #endif -#ifndef __ASSEMBLY__ - -#include <asm/portmux.h> - -#define LOB(x) ((x) & 0xFF) -#define HIB(x) (((x) >> 8) & 0xFF) - -#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__) +#if defined(__ADSPBF60x__) +# define BFIN_UART_HW_VER 4 +#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__) # define BFIN_UART_HW_VER 2 #else # define BFIN_UART_HW_VER 1 #endif -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m -struct bfin_mmr_serial { -#if BFIN_UART_HW_VER == 2 - __BFP(dll); - __BFP(dlh); - __BFP(gctl); - __BFP(lcr); - __BFP(mcr); - __BFP(lsr); - __BFP(msr); - __BFP(scr); - __BFP(ier_set); - __BFP(ier_clear); - __BFP(thr); - __BFP(rbr); -#else - union { - u16 dll; - u16 thr; - const u16 rbr; - }; - const u16 __spad0; - union { - u16 dlh; - u16 ier; - }; - const u16 __spad1; - const __BFP(iir); - __BFP(lcr); - __BFP(mcr); - __BFP(lsr); - __BFP(msr); - __BFP(scr); - const u32 __spad2; - __BFP(gctl); -#endif -}; -#undef __BFP - #define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx #define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) -#define MMR_UART(n) _PASTE_UART(n, UART, DLL) #define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin) #define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin) -#ifndef UART_DLL -# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE) -#else -# define UART0_DLL UART_DLL -# if CONFIG_UART_CONSOLE != 0 -# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART -# endif -#endif #define pUART ((volatile struct bfin_mmr_serial *)uart_base) -#if BFIN_UART_HW_VER == 2 -# define ACCESS_LATCH() -# define ACCESS_PORT_IER() +#ifndef __ASSEMBLY__ +__attribute__((always_inline)) +static inline void serial_do_portmux(void); +#endif + +#if BFIN_UART_HW_VER < 4 +# include "serial1.h" #else -# define ACCESS_LATCH() \ - bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB) -# define ACCESS_PORT_IER() \ - bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB) +# include "serial4.h" #endif +#ifndef __ASSEMBLY__ + __attribute__((always_inline)) static inline void serial_do_portmux(void) { @@ -115,143 +61,7 @@ static inline void serial_do_portmux(void) return; } -#if defined(__ADSPBF50x__) -# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); - switch (CONFIG_UART_CONSOLE) { - case 0: DO_MUX(G, 7, 7, 12, 13); break; /* Port G; mux 7; PG12 and PG13 */ - case 1: DO_MUX(F, 3, 3, 6, 7); break; /* Port F; mux 3; PF6 and PF7 */ - } - SSYNC(); -#elif defined(__ADSPBF51x__) -# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); - switch (CONFIG_UART_CONSOLE) { - case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */ - case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */ - } - SSYNC(); -#elif defined(__ADSPBF52x__) -# define DO_MUX(port, mux, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); - switch (CONFIG_UART_CONSOLE) { - case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */ - case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */ - } - SSYNC(); -#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) - const uint16_t func[] = { PFDE, PFTE, }; - bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); - bfin_write_PORTF_FER(bfin_read_PORTF_FER() | - (1 << P_IDENT(P_UART(RX))) | - (1 << P_IDENT(P_UART(TX)))); - SSYNC(); -#elif defined(__ADSPBF54x__) -# define DO_MUX(port, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); - switch (CONFIG_UART_CONSOLE) { - case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */ - case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */ - case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */ - case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */ - } - SSYNC(); -#elif defined(__ADSPBF561__) - /* UART pins could be GPIO, but they aren't pin muxed. */ -#else -# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) -# error "missing portmux logic for UART" -# endif -#endif -} - -__attribute__((always_inline)) -static inline int uart_init(uint32_t uart_base) -{ - /* always enable UART -- avoids anomalies 05000309 and 05000350 */ - bfin_write(&pUART->gctl, UCEN); - - /* Set LCR to Word Lengh 8-bit word select */ - bfin_write(&pUART->lcr, WLS_8); - - SSYNC(); - - return 0; -} - -__attribute__((always_inline)) -static inline int serial_early_init(uint32_t uart_base) -{ - /* handle portmux crap on different Blackfins */ - serial_do_portmux(); - - return uart_init(uart_base); -} - -__attribute__((always_inline)) -static inline int serial_early_uninit(uint32_t uart_base) -{ - /* disable the UART by clearing UCEN */ - bfin_write(&pUART->gctl, 0); - - return 0; -} - -__attribute__((always_inline)) -static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor) -{ - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH(); - SSYNC(); - - /* Program the divisor to get the baud rate we want */ - bfin_write(&pUART->dll, LOB(divisor)); - bfin_write(&pUART->dlh, HIB(divisor)); - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER(); - SSYNC(); -} - -__attribute__((always_inline)) -static inline uint16_t serial_early_get_div(void) -{ - uint32_t uart_base = UART_DLL; - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH(); - SSYNC(); - - uint8_t dll = bfin_read(&pUART->dll); - uint8_t dlh = bfin_read(&pUART->dlh); - uint16_t divisor = (dlh << 8) | dll; - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER(); - SSYNC(); - - return divisor; -} - -/* We cannot use get_sclk() early on as it uses caches in external memory */ -#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) -# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV) -#endif - -__attribute__((always_inline)) -static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) -{ - /* Translate from baud into divisor in terms of SCLK. The - * weird multiplication is to make sure we over sample just - * a little rather than under sample the incoming signals. - */ - serial_early_put_div(uart_base, - (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230); + serial_early_do_portmux(); } #ifndef BFIN_IN_INITCODE diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h new file mode 100644 index 0000000..a20175b --- /dev/null +++ b/arch/blackfin/cpu/serial1.h @@ -0,0 +1,348 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL1_H__ +#define __BFIN_CPU_SERIAL1_H__ + +#include <asm/mach-common/bits/uart.h> + +#ifndef __ASSEMBLY__ + +#define MMR_UART(n) _PASTE_UART(n, UART, DLL) +#ifdef UART_DLL +# define UART0_DLL UART_DLL +# if CONFIG_UART_CONSOLE != 0 +# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART +# endif +#endif +#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) + +#define LOB(x) ((x) & 0xFF) +#define HIB(x) (((x) >> 8) & 0xFF) + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +struct bfin_mmr_serial { +#if BFIN_UART_HW_VER == 2 + u16 dll; + u16 __pad_0; + u16 dlh; + u16 __pad_1; + u16 gctl; + u16 __pad_2; + u16 lcr; + u16 __pad_3; + u16 mcr; + u16 __pad_4; + u16 lsr; + u16 __pad_5; + u16 msr; + u16 __pad_6; + u16 scr; + u16 __pad_7; + u16 ier_set; + u16 __pad_8; + u16 ier_clear; + u16 __pad_9; + u16 thr; + u16 __pad_10; + u16 rbr; + u16 __pad_11; +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __spad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __spad1; + const u16 iir; + u16 __pad_0; + u16 lcr; + u16 __pad_1; + u16 mcr; + u16 __pad_2; + u16 lsr; + u16 __pad_3; + u16 msr; + u16 __pad_4; + u16 scr; + u16 __pad_5; + const u32 __spad2; + u16 gctl; + u16 __pad_6; +#endif +}; + +#define uart_lsr_t uint32_t +#define _lsr_read(p) bfin_read(&p->lsr) +#define _lsr_write(p, v) bfin_write(&p->lsr, v) + +#if BFIN_UART_HW_VER == 2 +# define ACCESS_LATCH() +# define ACCESS_PORT_IER() +#else +# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB) +# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB) +#endif + +__attribute__((always_inline)) +static inline void serial_early_do_mach_portmux(char port, int mux_mask, + int mux_func, int port_pin) +{ + switch (port) { +#if defined(__ADSPBF54x__) + case 'B': + bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin); + break; + case 'E': + bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin); + break; +#endif +#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__) + case 'F': + bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin); + break; + case 'G': + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin); + break; + case 'H': + bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin); + break; +#endif + default: + break; + } +} + +__attribute__((always_inline)) +static inline void serial_early_do_portmux(void) +{ +#if defined(__ADSPBF50x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */ + break; + case 1: + serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */ + serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */ + break; + } +#elif defined(__ADSPBF51x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */ + break; + case 1: + serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */ + serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */ + break; + } +#elif defined(__ADSPBF52x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, + PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, + PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */ + break; + case 1: + serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */ + serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */ + break; + } +#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) + const uint16_t func[] = { PFDE, PFTE, }; + bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | + (1 << P_IDENT(P_UART(RX))) | + (1 << P_IDENT(P_UART(TX)))); +#elif defined(__ADSPBF54x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */ + serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK, + PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */ + break; + case 1: + serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK, + PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */ + serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK, + PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */ + break; + case 2: + serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK, + PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */ + serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */ + break; + case 3: + serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK, + PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */ + serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */ + break; + } +#elif defined(__ADSPBF561__) + /* UART pins could be GPIO, but they aren't pin muxed. */ +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif +#endif + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint32_t uart_sclk(void) +{ +#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) + /* We cannot use get_sclk() early on as it uses + * caches in external memory + */ + return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV; +#else + return get_sclk(); +#endif +} + +__attribute__((always_inline)) +static inline int uart_init(uint32_t uart_base) +{ + /* always enable UART -- avoids anomalies 05000309 and 05000350 */ + bfin_write(&pUART->gctl, UCEN); + + /* Set LCR to Word Lengh 8-bit word select */ + bfin_write(&pUART->lcr, WLS_8); + + SSYNC(); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UCEN */ + bfin_write(&pUART->gctl, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_enabled(uint32_t uart_base) +{ + return bfin_read(&pUART->gctl) & UCEN; +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + /* Translate from baud into divisor in terms of SCLK. The + * weird multiplication is to make sure we over sample just + * a little rather than under sample the incoming signals. + */ + uint16_t divisor = (uart_sclk() + (baud * 8)) / (baud * 16) - + ANOMALY_05000230; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint16_t divisor) +{ + uint32_t uart_base = UART_BASE; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint16_t serial_early_get_div(void) +{ + uint32_t uart_base = UART_BASE; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + uint8_t dll = bfin_read(&pUART->dll); + uint8_t dlh = bfin_read(&pUART->dlh); + uint16_t divisor = (dlh << 8) | dll; + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); + + return divisor; +} + +#endif + +#endif diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/cpu/serial4.h new file mode 100644 index 0000000..887845c --- /dev/null +++ b/arch/blackfin/cpu/serial4.h @@ -0,0 +1,161 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL4_H__ +#define __BFIN_CPU_SERIAL4_H__ + +#include <asm/mach-common/bits/uart4.h> + +#ifndef __ASSEMBLY__ + +#define MMR_UART(n) _PASTE_UART(n, UART, REVID) +#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) + +struct bfin_mmr_serial { + u32 revid; + u32 control; + u32 status; + u32 scr; + u32 clock; + u32 emask; + u32 emaskst; + u32 emaskcl; + u32 rbr; + u32 thr; + u32 taip; + u32 tsr; + u32 rsr; + u32 txdiv_cnt; + u32 rxdiv_cnt; +}; +#define uart_lsr_t uint32_t +#define _lsr_read(p) bfin_read(&p->status) +#define _lsr_write(p, v) bfin_write(&p->status, v) + +__attribute__((always_inline)) +static inline void serial_early_do_mach_portmux(char port, int mux_mask, + int mux_func, int port_pin) +{ + switch (port) { + case 'D': + bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTD_FER_SET(port_pin); + break; + case 'G': + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTG_FER_SET(port_pin); + break; + } +} + +__attribute__((always_inline)) +static inline void serial_early_do_portmux(void) +{ +#if defined(__ADSPBF60x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */ + serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK, + PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */ + break; + case 1: + serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK, + PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK, + PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */ + break; + } +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif +#endif + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint32_t uart_sclk(void) +{ +#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) + /* We cannot use get_sclk() early on as it uses caches in + * external memory + */ + return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV / + CONFIG_SCLK0_DIV; +#else + return get_sclk0(); +#endif +} + +__attribute__((always_inline)) +static inline int uart_init(uint32_t uart_base) +{ + /* always enable UART to 8-bit mode */ + bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8); + + SSYNC(); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UEN */ + bfin_write(&pUART->control, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_enabled(uint32_t uart_base) +{ + return bfin_read(&pUART->control) & UEN; +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + uint32_t divisor = uart_sclk() / (baud * 16); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->clock, divisor); + SSYNC(); +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint32_t divisor) +{ + uint32_t uart_base = UART_BASE; + bfin_write(&pUART->clock, divisor); +} + +__attribute__((always_inline)) +static inline uint32_t serial_early_get_div(void) +{ + uint32_t uart_base = UART_BASE; + return bfin_read(&pUART->clock); +} + +#endif + +#endif diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 90b4d1a..7155fc8 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -65,6 +65,7 @@ ENTRY(_start) p5.h = HI(COREMMR_BASE); #ifdef CONFIG_HW_WATCHDOG +#ifndef __ADSPBF60x__ # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START # define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000 # endif @@ -78,6 +79,7 @@ ENTRY(_start) /* fire up the watchdog - R0.L above needs to be 0x0000 */ W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0; #endif +#endif /* Turn on the serial for debugging the init process */ serial_early_init diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h index a19f0f7..8608711 100644 --- a/arch/blackfin/include/asm/blackfin_cdef.h +++ b/arch/blackfin/include/asm/blackfin_cdef.h @@ -84,5 +84,8 @@ #ifdef __ADSPBF561__ # include "mach-bf561/BF561_cdef.h" #endif +#ifdef __ADSPBF609__ +# include "mach-bf609/BF609_cdef.h" +#endif #endif /* __MACH_CDEF_BLACKFIN__ */ diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h index f06d1f1..c96a3ec 100644 --- a/arch/blackfin/include/asm/blackfin_def.h +++ b/arch/blackfin/include/asm/blackfin_def.h @@ -136,5 +136,10 @@ # include "mach-bf561/anomaly.h" # include "mach-bf561/def_local.h" #endif +#ifdef __ADSPBF609__ +# include "mach-bf609/BF609_def.h" +# include "mach-bf609/anomaly.h" +# include "mach-bf609/def_local.h" +#endif #endif /* __MACH_DEF_BLACKFIN__ */ diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 49d0c9e..fc46ef4 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -61,6 +61,9 @@ extern u_long get_vco(void); extern u_long get_cclk(void); extern u_long get_sclk(void); +extern u_long get_sclk0(void); +extern u_long get_sclk1(void); +extern u_long get_dclk(void); # define bfin_revid() (bfin_read_CHIPID() >> 28) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index be5687c..d0fd537 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -29,6 +29,8 @@ #define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */ #define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ #define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ +#define BFIN_BOOT_RSI_MASTER 14 /* boot ldr from rsi */ +#define BFIN_BOOT_LP_SLAVE 15 /* boot ldr from link port */ #ifndef __ASSEMBLY__ static inline const char *get_bfin_boot_mode(int bfin_boot) @@ -47,6 +49,8 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) case BFIN_BOOT_16HOST_DMA: return "16bit dma"; case BFIN_BOOT_8HOST_DMA: return "8bit dma"; case BFIN_BOOT_NAND: return "nand flash"; + case BFIN_BOOT_RSI_MASTER: return "rsi master"; + case BFIN_BOOT_LP_SLAVE: return "link port slave"; default: return "INVALID"; } } diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index cc21e93..420380d 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -46,8 +46,13 @@ #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL /* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#if defined(__ADSPBF60x__) +#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) +#else +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) +#endif #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) @@ -59,14 +64,32 @@ #endif #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \ + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \ + CPLB_USER_WR | CPLB_VALID | \ + ANOMALY_05000158_WORKAROUND) +#else +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \ + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \ + CPLB_USER_WR | CPLB_VALID | \ + ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index 21ff1cf..ef1db6e 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h @@ -8,7 +8,12 @@ #ifndef _BLACKFIN_DMA_H_ #define _BLACKFIN_DMA_H_ +#include <linux/types.h> +#ifdef __ADSPBF60x__ +#include <asm/mach-common/bits/dde.h> +#else #include <asm/mach-common/bits/dma.h> +#endif struct dmasg_large { void *next_desc_addr; @@ -30,46 +35,70 @@ struct dmasg { } __attribute__((packed)); struct dma_register { +#ifdef __ADSPBF60x__ + void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ + u32 start_addr; /* DMA Start address register */ + u32 config; /* DMA Configuration register */ + + u32 x_count; /* DMA x_count register */ + s32 x_modify; /* DMA x_modify register */ + u32 y_count; /* DMA y_count register */ + s32 y_modify; /* DMA y_modify register */ + u32 __pad0[2]; + + void *curr_desc_ptr; /* DMA Curr Descriptor Pointer register */ + void *prev_desc_ptr; /* DMA Prev Descriptor Pointer register */ + void *curr_addr; /* DMA Current Address Pointer register */ + u32 status; /* DMA irq status register */ + u32 curr_x_count; /* DMA Current x-count register */ + u32 curr_y_count; /* DMA Current y-count register */ + u32 __pad1[2]; + + u32 bw_limit; /* DMA Bandwidth Limit Count */ + u32 curr_bw_limit; /* DMA curr Bandwidth Limit Count */ + u32 bw_monitor; /* DMA Bandwidth Monitor Count */ + u32 curr_bw_monitor; /* DMA curr Bandwidth Monitor Count */ +#else void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ - unsigned long start_addr; /* DMA Start address register */ + u32 start_addr; /* DMA Start address register */ - unsigned short cfg; /* DMA Configuration register */ - unsigned short dummy1; /* DMA Configuration register */ + u16 config; /* DMA Configuration register */ + u16 dummy1; /* DMA Configuration register */ - unsigned long reserved; + u32 reserved; - unsigned short x_count; /* DMA x_count register */ - unsigned short dummy2; + u16 x_count; /* DMA x_count register */ + u16 dummy2; - short x_modify; /* DMA x_modify register */ - unsigned short dummy3; + s16 x_modify; /* DMA x_modify register */ + u16 dummy3; - unsigned short y_count; /* DMA y_count register */ - unsigned short dummy4; + u16 y_count; /* DMA y_count register */ + u16 dummy4; - short y_modify; /* DMA y_modify register */ - unsigned short dummy5; + s16 y_modify; /* DMA y_modify register */ + u16 dummy5; - void *curr_desc_ptr; /* DMA Current Descriptor Pointer - register */ - unsigned long curr_addr_ptr; /* DMA Current Address Pointer - register */ - unsigned short irq_status; /* DMA irq status register */ - unsigned short dummy6; + void *curr_desc_ptr; /* DMA Current Descriptor Pointer register */ - unsigned short peripheral_map; /* DMA peripheral map register */ - unsigned short dummy7; + u32 curr_addr_ptr; /* DMA Current Address Pointer register */ - unsigned short curr_x_count; /* DMA Current x-count register */ - unsigned short dummy8; + u16 status; /* DMA irq status register */ + u16 dummy6; - unsigned long reserved2; + u16 peripheral_map; /* DMA peripheral map register */ + u16 dummy7; - unsigned short curr_y_count; /* DMA Current y-count register */ - unsigned short dummy9; + u16 curr_x_count; /* DMA Current x-count register */ + u16 dummy8; - unsigned long reserved3; + u32 reserved2; + u16 curr_y_count; /* DMA Current y-count register */ + u16 dummy9; + + u32 reserved3; +#endif }; #endif diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 224688f..05131b5 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -68,7 +68,7 @@ #ifndef __ASSEMBLY__ -#ifndef CONFIG_BF54x +#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x) void set_gpio_dir(unsigned, unsigned short); void set_gpio_inen(unsigned, unsigned short); void set_gpio_polar(unsigned, unsigned short); diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h index 3b61aaf..2bcd2d8 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_def.h @@ -149,6 +149,7 @@ #define UART_LSR 0xFFC00414 #define UART_SCR 0xFFC0041C #define UART_RBR 0xFFC00400 /* Receive Buffer */ +#define UART0_RBR UART_RBR #define UART_GCTL 0xFFC00424 #define SPT0_TX_CONFIG0 0xFFC00800 #define SPT0_TX_CONFIG1 0xFFC00804 diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index 46925f8..a7ff5a3 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -690,6 +690,7 @@ #define PPI1_FRAME 0xFFC01310 #define UART_THR 0xFFC00400 #define UART_RBR 0xFFC00400 +#define UART0_RBR UART_RBR #define UART_DLL 0xFFC00400 #define UART_DLH 0xFFC00404 #define UART_IER 0xFFC00404 diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h new file mode 100644 index 0000000..c590031 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h @@ -0,0 +1,192 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF609_proc__ +#define __BFIN_CDEF_ADSP_BF609_proc__ + +#include "../mach-common/ADSP-EDN-core_cdef.h" + +#define bfin_read_CGU_STAT() bfin_read32(CGU_STAT) +#define bfin_read_CGU_CLKOUTSEL() bfin_read32(CGU_CLKOUTSEL) +#define bfin_read_CGU_CTL() bfin_read32(CGU_CTL) +#define bfin_write_CGU_CTL(val) bfin_write32(CGU_CTL, val) +#define bfin_read_CGU_DIV() bfin_read32(CGU_DIV) +#define bfin_write_CGU_DIV(val) bfin_write32(CGU_DIV, val) + +#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL) +#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val) + +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) + +#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG) +#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val) +#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0) +#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val) +#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1) +#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val) +#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2) +#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val) +#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR) +#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val) +#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1) +#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) +#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) +#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) +#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) +#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) +#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) +#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val) + +#define bfin_read_SEC_CCTL() bfin_read32(SEC0_CCTL0) +#define bfin_write_SEC_CCTL(val) bfin_write32(SEC0_CCTL0, val) +#define bfin_read_SEC_GCTL() bfin_read32(SEC0_GCTL) +#define bfin_write_SEC_GCTL(val) bfin_write32(SEC0_GCTL, val) + +#define bfin_read_SEC_FCTL() bfin_read32(SEC0_FCTL) +#define bfin_write_SEC_FCTL(val) bfin_write32(SEC0_FCTL, val) +#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC0_SCTL0 + (sid) * 8)) +#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC0_SCTL0 \ + + (sid) * 8), val) + +#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL) +#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val) +#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT) +#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL) +#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val) +#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM) +#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val) +#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM) +#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val) +#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL) +#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val) +#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM) +#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val) +#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM) +#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val) +#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL) +#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val) +#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM) +#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val) +#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM) +#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val) +#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL) +#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val) +#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM) +#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val) +#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM) +#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val) + +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val) +#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read8(USB_DMA_IRQ) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write8(USB_DMA_IRQ, val) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val) +#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL) + +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_NXT) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_NXT, val) +#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_ADDRSTART) +#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_ADDRSTART, val) +#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CFG) +#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CFG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_XCNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_XCNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_XMOD) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_XMOD, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_YCNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_YCNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_YMOD) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_YMOD, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_CUR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_CUR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_ADDR_CUR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_ADDR_CUR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_STAT) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_STAT, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_XCNT_CUR) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_XCNT_CUR, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_YCNT_CUR) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_YCNT_CUR, val) + +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_CTL() bfin_read32(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write32(WDOG_CTL, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_SPI_BAUD() bfin_read32(SPI0_CLK) +#define bfin_write_SPI_BAUD(val) bfin_write32(SPI0_CLK, val) + +#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER) +#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val) +#define bfin_write_PORTD_FER_CLR(val) bfin_write32(PORTD_FER_CLR, val) +#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) +#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) +#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER) +#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val) +#define bfin_write_PORTG_FER_CLR(val) bfin_write32(PORTG_FER_CLR, val) +#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) + +#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ) +#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_ESTAT() bfin_read32(RSI_ESTAT) +#define bfin_write_RSI_ESTAT(val) bfin_write32(RSI_ESTAT, val) +#define bfin_read_RSI_EMASK() bfin_read32(RSI_EMASK) +#define bfin_write_RSI_EMASK(val) bfin_write32(RSI_EMASK, val) +#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) + +#endif /* __BFIN_CDEF_ADSP_BF609_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h new file mode 100644 index 0000000..8c1dcd0 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -0,0 +1,247 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF609_proc__ +#define __BFIN_DEF_ADSP_BF609_proc__ + +#include "../mach-common/ADSP-EDN-core_def.h" + +#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */ +#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */ +#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */ +#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */ +#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */ +#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */ +#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */ +#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */ +#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */ +#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */ +#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */ +#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */ +#define RSI_IMSK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */ +#define RSI_IMSK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */ +#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */ +#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Ack Timeout Register */ +#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */ +#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */ +#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */ +#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */ +#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */ +#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */ +#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Id Register */ +#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Id Register */ +#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Id Register */ +#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Id Register */ + +#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */ +#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */ + +#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */ +#define UART0_CTL 0xFFC02004 /* UART0 Control Register */ +#define UART0_STAT 0xFFC02008 /* UART0 Status Register */ +#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */ +#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */ +#define UART0_IMSK 0xFFC02014 /* UART0 Interrupt Mask Register */ +#define UART0_IMSK_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */ +#define UART0_IMSK_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */ +#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */ +#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */ +#define UART0_TAIP 0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */ +#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */ +#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */ +#define UART0_TXCNT 0xFFC02034 /* UART0 Transmit Counter Register */ +#define UART0_RXCNT 0xFFC02038 /* UART0 Receive Counter Register */ +#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */ +#define UART1_CTL 0xFFC02404 /* UART1 Control Register */ +#define UART1_STAT 0xFFC02408 /* UART1 Status Register */ +#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */ +#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */ +#define UART1_IMSK 0xFFC02414 /* UART1 Interrupt Mask Register */ +#define UART1_IMSK_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */ +#define UART1_IMSK_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */ +#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */ +#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */ +#define UART1_TAIP 0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */ +#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */ +#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */ +#define UART1_TXCNT 0xFFC02434 /* UART1 Transmit Counter Register */ +#define UART1_RXCNT 0xFFC02438 /* UART1 Receive Counter Register */ + +#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable */ +#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set */ +#define PORTA_FER_CLR 0xFFC03008 /* PORTA Port x Function Enable Clear */ +#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control */ +#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable */ +#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set */ +#define PORTB_FER_CLR 0xFFC03088 /* PORTB Port x Function Enable Clear */ +#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control */ +#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable */ +#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set */ +#define PORTC_FER_CLR 0xFFC03108 /* PORTC Port x Function Enable Clear */ +#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control */ +#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable */ +#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set */ +#define PORTD_FER_CLR 0xFFC03188 /* PORTD Port x Function Enable Clear */ +#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control */ +#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable */ +#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set */ +#define PORTE_FER_CLR 0xFFC03208 /* PORTE Port x Function Enable Clear */ +#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control */ +#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable */ +#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set */ +#define PORTF_FER_CLR 0xFFC03288 /* PORTF Port x Function Enable Clear */ +#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control */ +#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable */ +#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set */ +#define PORTG_FER_CLR 0xFFC03308 /* PORTG Port x Function Enable Clear */ +#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control */ + +#define SMC_GCTL 0xFFC16004 /* SMC Control Register */ +#define SMC_GSTAT 0xFFC16008 /* SMC Status Register */ +#define SMC_B0CTL 0xFFC1600C /* SMC Bank0 Control Register */ +#define SMC_B0TIM 0xFFC16010 /* SMC Bank0 Timing Register */ +#define SMC_B0ETIM 0xFFC16014 /* SMC Bank0 Extended Timing Register */ +#define SMC_B1CTL 0xFFC1601C /* SMC BANK1 Control Register */ +#define SMC_B1TIM 0xFFC16020 /* SMC BANK1 Timing Register */ +#define SMC_B1ETIM 0xFFC16024 /* SMC BANK1 Extended Timing Register */ +#define SMC_B2CTL 0xFFC1602C /* SMC BANK2 Control Register */ +#define SMC_B2TIM 0xFFC16030 /* SMC BANK2 Timing Register */ +#define SMC_B2ETIM 0xFFC16034 /* SMC BANK2 Extended Timing Register */ +#define SMC_B3CTL 0xFFC1603C /* SMC BANK3 Control Register */ +#define SMC_B3TIM 0xFFC16040 /* SMC BANK3 Timing Register */ +#define SMC_B3ETIM 0xFFC16044 /* SMC BANK3 Extended Timing Register */ + +#define WDOG_CTL 0xFFC17000 /* WDOG0 Control Register */ +#define WDOG_CNT 0xFFC17004 /* WDOG0 Count Register */ +#define WDOG_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */ +#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */ +#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */ +#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */ + +#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ +#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ + +#define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */ +#define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */ +#define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */ +#define DMA10_XCNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */ +#define DMA10_XMOD 0xFFC05010 /* DMA10 Inner Loop Address Increment */ +#define DMA10_YCNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value */ +#define DMA10_YMOD 0xFFC05018 /* DMA10 Outer Loop Address Increment */ +#define DMA10_DSCPTR_CUR 0xFFC05024 /* DMA10 Current Descriptor Pointer */ +#define DMA10_DSCPTR_PRV 0xFFC05028 /* DMA10 Previous Initial Desc Pointer */ +#define DMA10_ADDR_CUR 0xFFC0502C /* DMA10 Current Address */ +#define DMA10_STAT 0xFFC05030 /* DMA10 Status Register */ +#define DMA10_XCNT_CUR 0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/ +#define DMA10_YCNT_CUR 0xFFC05038 /* DMA10 Curr Row Count (2D only) */ +#define DMA10_BWLCNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */ +#define DMA10_BWLCNT_CUR 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */ +#define DMA10_BWMCNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */ +#define DMA10_BWMCNT_CUR 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/ + +#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT +#define DMA21_DSCPTR_NXT 0xFFC09000 /* DMA21 Pointer to Next Initial Desc */ +#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT +#define DMA22_DSCPTR_NXT 0xFFC09080 /* DMA22 Pointer to Next Initial Desc */ + +#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */ +#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */ +#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */ +#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */ +#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */ +#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */ +#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */ +#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */ +#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */ +#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */ +#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */ +#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */ +#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */ +#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */ +#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */ +#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */ +#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */ + +#define SEC0_CCTL0 0xFFCA4400 /* SEC0 Core Control Register n */ +#define SEC0_CCTL1 0xFFCA4440 /* SEC0 Core Control Register n */ +#define SEC0_FCTL 0xFFCA4010 /* SEC0 Fault Control Register */ +#define SEC0_GCTL 0xFFCA4000 /* SEC0 Global Control Register */ +#define SEC0_SCTL0 0xFFCA4800 /* SEC0 IRQ Source Control Register n */ + +#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */ +#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */ +#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */ +#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */ +#define RCU0_SIDIS 0xFFCA6010 /* RCU0 Sys Interface Disable Register */ +#define RCU0_SISTAT 0xFFCA6014 /* RCU0 Sys Interface Status Register */ +#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */ +#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */ +#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */ +#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */ + +#define CGU_CTL 0xFFCA8000 /* CGU0 Control Register */ +#define CGU_STAT 0xFFCA8004 /* CGU0 Status Register */ +#define CGU_DIV 0xFFCA8008 /* CGU0 Divisor Register */ +#define CGU_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */ + +#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */ +#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */ +#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable */ +#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable */ +#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status */ +#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */ +#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable */ +#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */ +#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */ +#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */ +#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */ +#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */ +#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */ +#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */ +#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */ +#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */ +#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */ +#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */ +#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */ +#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */ +#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */ +#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */ +#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */ +#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */ +#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */ +#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */ +#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */ +#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */ + +#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode*/ +#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */ +#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */ +#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */ +#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */ + + +#define CHIPID 0xffc00014 +/* CHIPID Masks */ +#define CHIPID_VERSION 0xF0000000 +#define CHIPID_FAMILY 0x0FFFF000 +#define CHIPID_MANUFACTURE 0x00000FFE + +#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */ +#define L1_DATA_A_SRAM_SIZE 0x8000 +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */ +#define L1_DATA_B_SRAM_SIZE 0x4000 +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) + +#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */ +#define L1_INST_SRAM_SIZE 0x8000 +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif /* __BFIN_DEF_ADSP_BF609_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf609/anomaly.h b/arch/blackfin/include/asm/mach-bf609/anomaly.h new file mode 100644 index 0000000..0a70f08 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/anomaly.h @@ -0,0 +1,97 @@ +/* + * Copyright 2004-2012 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + */ + +/* This file should be up to date with: + * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List + */ + +#if __SILICON_REVISION__ < 0 +# error will not work on BF609 silicon version +#endif + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ +#define ANOMALY_16000003 (1) +/* The EPPI Data Enable (DEN) Signal is Not Functional */ +#define ANOMALY_16000004 (1) +/* Using L1 Instruction Cache with Parity Enabled is Unreliable */ +#define ANOMALY_16000005 (1) +/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ +#define ANOMALY_16000006 (1) +/* DDR2 Memory Reads May Fail Intermittently */ +#define ANOMALY_16000007 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ +#define ANOMALY_16000008 (1) +/* TestSET Instruction Cannot Be Interrupted */ +#define ANOMALY_16000009 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_16000010 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_16000011 (1) +/* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */ +#define ANOMALY_16000012 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_16000013 (1) +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_16000014 (1) +/* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */ +#define ANOMALY_16000015 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_16000017 (1) +/* RSI Boot Cleanup Routine Does Not Clear Registers */ +#define ANOMALY_16000018 (1) +/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ +#define ANOMALY_16000019 (1) +/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ +#define ANOMALY_16000020 (1) +/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */ +#define ANOMALY_16000021 (1) +/* Boot Code Fails to Enable Parity Fault Detection */ +#define ANOMALY_16000022 (1) +/* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */ +#define ANOMALY_16000027 (1) +/* Interrupted Core Reads of MMRs May Cause Data Loss */ +#define ANOMALY_16000030 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000158 (0) +#define ANOMALY_05000189 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) +#define ANOMALY_05000363 (0) +#define ANOMALY_05000386 (0) +#define ANOMALY_05000480 (0) +#define ANOMALY_05000481 (1) + +/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */ +#define ANOMALY_05000491 ANOMALY_16000008 +#define ANOMALY_05000477 ANOMALY_16000009 +#define ANOMALY_05000443 ANOMALY_16000010 +#define ANOMALY_05000461 ANOMALY_16000011 +#define ANOMALY_05000426 ANOMALY_16000012 +#define ANOMALY_05000310 ANOMALY_16000013 +#define ANOMALY_05000245 ANOMALY_16000014 +#define ANOMALY_05000074 ANOMALY_16000015 +#define ANOMALY_05000416 ANOMALY_16000017 + + +#endif diff --git a/arch/blackfin/include/asm/mach-bf609/def_local.h b/arch/blackfin/include/asm/mach-bf609/def_local.h new file mode 100644 index 0000000..d4250e6 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/def_local.h @@ -0,0 +1,5 @@ +#include "gpio.h" +#include "portmux.h" +#include "ports.h" + +#define CONFIG_BF60x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf609/gpio.h b/arch/blackfin/include/asm/mach-bf609/gpio.h new file mode 100644 index 0000000..e297bcc --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/gpio.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 112 + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 +#define GPIO_PC15 47 +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 + +#ifndef __ASSEMBLY__ + +struct gpio_port_t { + unsigned long port_fer; + unsigned long port_fer_set; + unsigned long port_fer_clear; + unsigned long data; + unsigned long data_set; + unsigned long data_clear; + unsigned long dir; + unsigned long dir_set; + unsigned long dir_clear; + unsigned long inen; + unsigned long inen_set; + unsigned long inen_clear; + unsigned long port_mux; + unsigned long toggle; + unsigned long polar; + unsigned long polar_set; + unsigned long polar_clear; + unsigned long lock; + unsigned long spare; + unsigned long revid; +}; + +#endif + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h new file mode 100644 index 0000000..757570f --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/portmux.h @@ -0,0 +1,257 @@ +/* + * Copyright 2008-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +/* EMAC RMII Port Mux */ +#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_CRS, \ + P_MII0_MDC, \ + P_PTP0_PPS, \ + P_PTP1_PPS, \ + P_MII0_MDIO, 0} + +#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) + +#define P_RMII1 {\ + P_MII1_ETxD0, \ + P_MII1_ETxD1, \ + P_MII1_ETxEN, \ + P_MII1_ERxD0, \ + P_MII1_ERxD1, \ + P_MII1_ERxER, \ + P_MII1_TxCLK, \ + P_MII1_PHYINT, \ + P_MII1_CRS, \ + P_MII1_MDC, \ + P_MII1_MDIO, 0} + +/* PPI Port Mux */ +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1)) +#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1)) + +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1)) +#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1)) +#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1)) +#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1)) +#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1)) +#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) +#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1)) +#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1)) +#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1)) +#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1)) + +/* SPI Port Mux */ +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) + +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) + +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) + +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0)) + +#define GPIO_DEFAULT_BOOT_SPI_CS +#define P_DEFAULT_BOOT_SPI_CS + +/* UART Port Mux */ +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) + +/* Timer */ +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) + +/* RSI */ +#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) +#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) +#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2)) +#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2)) +#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2)) +#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2)) +#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2)) +#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2)) +#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) + +/* PTP */ +#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0)) +#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2)) +#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2)) + +#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2)) +#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2)) + +/* SMC Port Mux */ +#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) + +#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) + +#define P_ABE0 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1)) +#define P_ABE1 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1)) + +/* CAN */ +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h new file mode 100644 index 0000000..b361c7b --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf609/ports.h @@ -0,0 +1,103 @@ +/* + * Port Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT__ +#define __BFIN_PERIPHERAL_PORT__ + +/* PORTx_MUX Masks */ +#define PORT_x_MUX_0_MASK 0x00000003 +#define PORT_x_MUX_1_MASK 0x0000000C +#define PORT_x_MUX_2_MASK 0x00000030 +#define PORT_x_MUX_3_MASK 0x000000C0 +#define PORT_x_MUX_4_MASK 0x00000300 +#define PORT_x_MUX_5_MASK 0x00000C00 +#define PORT_x_MUX_6_MASK 0x00003000 +#define PORT_x_MUX_7_MASK 0x0000C000 +#define PORT_x_MUX_8_MASK 0x00030000 +#define PORT_x_MUX_9_MASK 0x000C0000 +#define PORT_x_MUX_10_MASK 0x00300000 +#define PORT_x_MUX_11_MASK 0x00C00000 +#define PORT_x_MUX_12_MASK 0x03000000 +#define PORT_x_MUX_13_MASK 0x0C000000 +#define PORT_x_MUX_14_MASK 0x30000000 +#define PORT_x_MUX_15_MASK 0xC0000000 + +#define PORT_x_MUX_FUNC_1 (0x0) +#define PORT_x_MUX_FUNC_2 (0x1) +#define PORT_x_MUX_FUNC_3 (0x2) +#define PORT_x_MUX_FUNC_4 (0x3) +#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0) +#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0) +#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0) +#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0) +#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2) +#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2) +#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2) +#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2) +#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4) +#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4) +#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4) +#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4) +#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6) +#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6) +#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6) +#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6) +#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8) +#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8) +#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8) +#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8) +#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10) +#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10) +#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10) +#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10) +#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12) +#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12) +#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12) +#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12) +#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) +#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) +#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) +#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) +#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16) +#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16) +#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16) +#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16) +#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18) +#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18) +#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18) +#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18) +#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20) +#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20) +#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20) +#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20) +#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22) +#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22) +#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22) +#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22) +#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24) +#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24) +#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24) +#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24) +#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26) +#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26) +#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26) +#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26) +#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28) +#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28) +#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28) +#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28) +#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30) +#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30) +#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30) +#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30) + +#include "../mach-common/bits/ports-a.h" +#include "../mach-common/bits/ports-b.h" +#include "../mach-common/bits/ports-c.h" +#include "../mach-common/bits/ports-d.h" +#include "../mach-common/bits/ports-e.h" +#include "../mach-common/bits/ports-f.h" +#include "../mach-common/bits/ports-g.h" + +#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h new file mode 100644 index 0000000..cdf7349 --- /dev/null +++ b/arch/blackfin/include/asm/mach-common/bits/cgu.h @@ -0,0 +1,80 @@ +/* + * CGU Masks + */ + +#ifndef __BFIN_PERIPHERAL_CGU__ +#define __BFIN_PERIPHERAL_CGU__ + +/* CGU_CTL Masks */ +#define DF (1 << 0) +#define MSEL (0x7f << MSEL_P) +#define WIDLE (1 << WIDLE_P) +#define LOCK (1 << LOCK_P) + +#define DF_P 0 +#define MSEL_P 8 +#define WIDLE_P 30 +#define LOCK_P 31 +#define MSEL_MASK 0x7F00 +#define DF_MASK 0x1 + +/* CGU_STAT Masks */ +#define PLLEN (1 << 0) +#define PLLBP (1 << 1) +#define PLLLK (1 << 2) +#define CLKSALGN (1 << 3) +#define CCBF0EN (1 << 4) +#define CCBF1EN (1 << 5) +#define SCBF0EN (1 << 6) +#define SCBF1EN (1 << 7) +#define DCBFEN (1 << 8) +#define OCBFEN (1 << 9) +#define ADRERR (1 << 16) +#define LWERR (1 << 17) +#define DIVERR (1 << 18) +#define WDFMSERR (1 << 19) +#define WDIVERR (1 << 20) +#define PLLLKERR (1 << 21) + +/* CGU_DIV Masks */ +#define CSEL (0x1f << CSEL_P) +#define S0SEL (3 << S0SEL_P) +#define SYSSEL (0x1f << SYSSEL_P) +#define S1SEL (3 << S1SEL_P) +#define DSEL (0x1f << DSEL_P) +#define OSEL (0x7f << OSEL_P) +#define ALGN (1 << ALGN_P) +#define UPDT (1 << UPDT_P) +#define LOCK (1 << LOCK_P) + +#define CSEL_P 0 +#define S0SEL_P 5 +#define SYSSEL_P 8 +#define S1SEL_P 13 +#define DSEL_P 16 +#define OSEL_P 22 +#define ALGN_P 29 +#define UPDT_P 30 +#define LOCK_P 31 + +/* CGU_CLKOUTSEL Masks */ +#define CLKOUTSEL (0xf << 0) +#define USBCLKSEL (0x3f << 16) +#define LOCK (1 << LOCK_P) + +#define LOCK_P 31 + +#define CLKOUTSEL_CLKIN 0x0 +#define CLKOUTSEL_CCLK 0x1 +#define CLKOUTSEL_SYSCLK 0x2 +#define CLKOUTSEL_SCLK0 0x3 +#define CLKOUTSEL_SCLK1 0x4 +#define CLKOUTSEL_DCLK 0x5 +#define CLKOUTSEL_USB_PLL 0x6 +#define CLKOUTSEL_OUTCLK 0x7 +#define CLKOUTSEL_USB_CLKIN 0x8 +#define CLKOUTSEL_WDOG 0x9 +#define CLKOUTSEL_PMON 0xA +#define CLKOUTSEL_GND 0xB + +#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h new file mode 100644 index 0000000..f7b0bb9 --- /dev/null +++ b/arch/blackfin/include/asm/mach-common/bits/dde.h @@ -0,0 +1,88 @@ +/* + * Distributed DMA Engine (DDE) Masks + */ + +#ifndef __BFIN_PERIPHERAL_DDE__ +#define __BFIN_PERIPHERAL_DDE__ + +/* DMA_CONFIG Masks */ +#define DMAEN (1 << DMAEN_P) /* DMA Channel Enable */ +#define WNR (1 << WNR_P) /* Channel Direction (W/R*) */ +#define SYNC (1 << SYNC_P) /* Sync Work Unit Transitions */ +#define CADDR (1 << CADDR_P) /* Use Current Address */ +#define PSIZE (7 << PSIZE_P) /* Peripheral Word Size */ +#define PSIZE_1 (0 << PSIZE_P) +#define PSIZE_2 (1 << PSIZE_P) +#define PSIZE_4 (2 << PSIZE_P) +#define PSIZE_8 (3 << PSIZE_P) +#define MSIZE (7 << MSIZE_P) /* Memory Transfer Size */ +#define MSIZE_1 (0 << MSIZE_P) +#define MSIZE_2 (1 << MSIZE_P) +#define MSIZE_4 (2 << MSIZE_P) +#define MSIZE_8 (3 << MSIZE_P) +#define MSIZE_16 (4 << MSIZE_P) +#define MSIZE_32 (5 << MSIZE_P) +#define FLOW (7 << FLOW_P) /* Next Operation */ +#define FLOW_STOP (0 << FLOW_P) /* Stop Mode */ +#define FLOW_AUTO (1 << FLOW_P) /* Autobuffer Mode */ +#define FLOW_DSCL (4 << FLOW_P) /* Descriptor List */ +#define FLOW_DSCA (5 << FLOW_P) /* Descriptor Array */ +#define FLOW_DSDL (6 << FLOW_P) /* Descriptor On Demand List */ +#define FLOW_DSDA (7 << FLOW_P) /* Descriptor On Demand Array */ +#define NDSIZE (7 << NDSIZE_P) /* Next Descriptor Set Size */ +#define NDSIZE_1 (0 << NDSIZE_P) +#define NDSIZE_2 (1 << NDSIZE_P) +#define NDSIZE_3 (2 << NDSIZE_P) +#define NDSIZE_4 (3 << NDSIZE_P) +#define NDSIZE_5 (4 << NDSIZE_P) +#define NDSIZE_6 (5 << NDSIZE_P) +#define NDSIZE_7 (6 << NDSIZE_P) +#define DI_EN_X (1 << INT_P) +#define DI_EN_Y (2 << INT_P) +#define DI_EN_P (3 << INT_P) +#define DI_EN (DI_EN_X) +#define DI_XCOUNT_EN (1 << INT_P) /* xcount expires interrupt */ +#define TRIG (3 << TRIG_P) /* Generate Trigger */ +#define TOVEN (1 << TOVEN_P) +#define DESCIDCPY (1 << DESCIDCPY_P) +#define TWOD (1 << TWOD_P) +#define PDRF (1 << PDRF_P) + +#define DMAEN_P 0 +#define WNR_P 1 +#define SYNC_P 2 +#define CADDR_P 3 +#define PSIZE_P 4 +#define MSIZE_P 8 +#define FLOW_P 12 +#define TWAIT_P 15 +#define NDSIZE_P 16 +#define INT_P 20 +#define TRIG_P 22 +#define TOVEN_P 24 +#define DESCIDCPY_P 25 +#define TWOD_P 26 +#define PDRF_P 28 + +/* DMA_STATUS Masks */ +#define DMA_DONE (1 << DMA_DONE_P) /* Work Unit/Row Done */ +#define DMA_ERR (1 << DMA_ERR_P) /* Error Interrupt */ +#define DMA_PIRQ (1 << DMA_PIRQ_P) /* Peri Intr Request */ +#define DMA_ERRC (7 << DMA_ERRC_P) /* Error Cause */ +#define DMA_RUN (7 << DMA_RUN_P) /* Run Status */ +#define DMA_PBWIDTH (3 << DMA_PBWIDTH_P) /* Peri Bus Width */ +#define DMA_MBWIDTH (3 << DMA_MBWIDTH_P) /* Memory Bus Width */ +#define DMA_FIFOFILL (7 << DMA_FIFOFILL_P) /* FIFO Fill Status */ +#define DMA_TWAIT (1 << DMA_TWAIT_P) /* Trigger Wait Stat */ + +#define DMA_DONE_P 0 +#define DMA_ERR_P 1 +#define DMA_PIRQ_P 2 +#define DMA_ERRC_P 4 +#define DMA_RUN_P 8 +#define DMA_PBWIDTH_P 12 +#define DMA_MBWIDTH_P 14 +#define DMA_FIFOFILL_P 16 +#define DMA_TWAIT_P 20 + +#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/dma.h b/arch/blackfin/include/asm/mach-common/bits/dma.h index 136313e..ac426ad 100644 --- a/arch/blackfin/include/asm/mach-common/bits/dma.h +++ b/arch/blackfin/include/asm/mach-common/bits/dma.h @@ -9,14 +9,54 @@ #define DMAEN 0x0001 /* DMA Channel Enable */ #define WNR 0x0002 /* Channel Direction (W/R*) */ #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ + +#ifdef CONFIG_BF60x + +#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ +#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */ +#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */ +#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */ +#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */ +#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */ +#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */ +#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ +#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ +#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ +#define DI_EN_X 0x00100000 /* Data Int Enable in X count */ +#define DI_EN_Y 0x00200000 /* Data Int Enable in Y count */ +#define DI_EN_P 0x00300000 /* Data Int Enable in Peri */ +#define DI_EN DI_EN_X /* Data Int Enable */ +#define NDSIZE_0 0x00000000 /* Next Desc Size = 0 */ +#define NDSIZE_1 0x00010000 /* Next Desc Size = 1 */ +#define NDSIZE_2 0x00020000 /* Next Desc Size = 2 */ +#define NDSIZE_3 0x00030000 /* Next Desc Size = 3 */ +#define NDSIZE_4 0x00040000 /* Next Desc Size = 4 */ +#define NDSIZE_5 0x00050000 /* Next Desc Size = 5 */ +#define NDSIZE_6 0x00060000 /* Next Desc Size = 6 */ +#define NDSIZE 0x00070000 /* Next Desc Size */ +#define NDSIZE_OFFSET 16 /* Next Desc Size Offset */ +#define DMAFLOW_LIST 0x00004000 /* Desc List Mode */ +#define DMAFLOW_ARRAY 0x00005000 /* Desc Array Mode */ +#define DMAFLOW_LIST_DEMAND 0x00006000 /* Desc Demand List Mode */ +#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Desc Demand Array Mode */ +#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Run (DFETCH) */ +#define DMA_RUN 0x00000200 /* DMA Channel Run */ +#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Run (WAIT TRIG)*/ +#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Run (WAIT ACK) */ + +#else + #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define PSIZE_16 WDSIZE_16 +#define PSIZE_32 WDSIZE_32 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ #define RESTART 0x0020 /* DMA Buffer Clear */ #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ #define DI_EN 0x0080 /* Data Interrupt Enable */ #define NDSIZE 0x0F00 /* Next Descriptor bitmask */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 */ #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ @@ -26,14 +66,13 @@ #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define FLOW_STOP 0x0000 /* Stop Mode */ -#define FLOW_AUTO 0x1000 /* Autobuffer Mode */ #define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ #define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ #define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ #define DMAEN_P 0 /* Channel Enable */ #define WNR_P 1 /* Channel Direction (W/R*) */ +#define WDSIZE_P 2 /* Transfer Word Size */ #define DMA2D_P 4 /* 2D/1D* Mode */ #define RESTART_P 5 /* Restart */ #define DI_SEL_P 6 /* Data Interrupt Select */ @@ -45,14 +84,19 @@ #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ +#endif +#define DMAFLOW 0x7000 /* Flow Control */ +#define FLOW_STOP 0x0000 /* Stop Mode */ +#define FLOW_AUTO 0x1000 /* Autobuffer Mode */ + #define DMA_DONE_P 0 /* DMA Done Indicator */ #define DMA_ERR_P 1 /* DMA Error Indicator */ #define DFETCH_P 2 /* Descriptor Fetch Indicator */ #define DMA_RUN_P 3 /* DMA Running Indicator */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define CTYPE 0x0040 /* DMA Channel Type (Mem/Peri) */ +#define CTYPE_P 6 /* DMA Channel Type BIT POSITION */ #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h index 39998f8..cfde236 100644 --- a/arch/blackfin/include/asm/mach-common/bits/mpu.h +++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h @@ -70,7 +70,11 @@ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define PAGE_SIZE_MASK 0x00030000 /* the bits for the page_size field */ +#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ +#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ +#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ +#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ +#define PAGE_SIZE_MASK 0x00070000 /* page_size field mask */ #define PAGE_SIZE_SHIFT 16 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h index 9009f26..fe0ba0f 100644 --- a/arch/blackfin/include/asm/mach-common/bits/pll.h +++ b/arch/blackfin/include/asm/mach-common/bits/pll.h @@ -16,6 +16,8 @@ #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ #define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ +#define MSEL_P 9 + /* PLL_DIV Masks */ #define SSEL 0x000F /* System Select */ #define CSEL 0x0030 /* Core Select */ @@ -29,6 +31,9 @@ #define CCLK_DIV4 CSEL_DIV4 #define CCLK_DIV8 CSEL_DIV8 +#define SSEL_P 0 +#define CSEL_P 4 + /* PLL_STAT Masks */ #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ #define FULL_ON 0x0002 /* Processor In Full On Mode */ diff --git a/arch/blackfin/include/asm/mach-common/bits/sdh.h b/arch/blackfin/include/asm/mach-common/bits/sdh.h index 8c5dd33..1c60d4b 100644 --- a/arch/blackfin/include/asm/mach-common/bits/sdh.h +++ b/arch/blackfin/include/asm/mach-common/bits/sdh.h @@ -12,18 +12,35 @@ #define CMD_INT_E 0x100 /* Command Interrupt */ #define CMD_PEND_E 0x200 /* Command Pending */ #define CMD_E 0x400 /* Command Enable */ +#ifdef RSI_BLKSZ +#define CMD_CRC_CHECK_D 0x800 /* CRC Check is disabled */ +#define CMD_DATA0_BUSY 0x1000 /* Check Busy State on DATA0 */ +#endif /* Bit masks for SDH_PWR_CTL */ +#ifndef RSI_BLKSZ #define PWR_ON 0x3 /* Power On */ #define SD_CMD_OD 0x40 /* Open Drain Output */ #define ROD_CTL 0x80 /* Rod Control */ +#endif /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ #define PWR_SV_E 0x200 /* Power Save Enable */ #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ +#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */ +#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */ +#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */ +#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */ +#ifdef RSI_BLKSZ +#define CARD_TYPE_MASK 0xe000 /* Card type mask */ +#define CARD_TYPE_OFFSET 13 /* Card type offset */ +#define CARD_TYPE_SDIO 0 +#define CARD_TYPE_eMMC 1 +#define CARD_TYPE_SD 2 +#define CARD_TYPE_CEATA 3 +#endif /* Bit masks for SDH_RESP_CMD */ #define RESP_CMD 0x3f /* Response Command */ @@ -33,7 +50,13 @@ #define DTX_DIR 0x2 /* Data Transfer Direction */ #define DTX_MODE 0x4 /* Data Transfer Mode */ #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#ifndef RSI_BLKSZ #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ +#else + +/* Bit masks for SDH_BLK_SIZE */ +#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */ +#endif /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ @@ -102,10 +125,13 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ #define SD_CARD_DET 0x10 /* SD Card Detect */ +#define SD_CARD_BUSYMODE 0x80000000 /* Card is in Busy mode */ +#define SD_CARD_SLPMODE 0x40000000 /* Card in Sleep Mode */ +#define SD_CARD_READY 0x00020000 /* Card Ready */ /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define SCD_MSK 0x40 /* Mask Card Detect */ +#define SCD_MSK 0x10 /* Mask Card Detect */ /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ @@ -114,7 +140,15 @@ #define SD_RST 0x10 /* SDMMC Reset */ #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#ifndef RSI_BLKSZ #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ +#else +#define PWR_ON 0x600 /* Power On */ +#define SD_CMD_OD 0x800 /* Open Drain Output */ +#define BOOT_EN 0x1000 /* Boot Enable */ +#define BOOT_MODE 0x2000 /* Alternate Boot Mode */ +#define BOOT_ACK_EN 0x4000 /* Boot ACK is expected */ +#endif /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ diff --git a/arch/blackfin/include/asm/mach-common/bits/spi6xx.h b/arch/blackfin/include/asm/mach-common/bits/spi6xx.h new file mode 100644 index 0000000..3368712 --- /dev/null +++ b/arch/blackfin/include/asm/mach-common/bits/spi6xx.h @@ -0,0 +1,240 @@ +/* + * Analog Devices bfin_spi3 controller driver + * + * Copyright (c) 2011 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _SPI_CHANNEL_H_ +#define _SPI_CHANNEL_H_ + +#include <linux/types.h> + +/* SPI_CONTROL */ +#define SPI_CTL_EN 0x00000001 /* Enable */ +#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */ +#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ +#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ +#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */ +#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ +#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ +#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in transfers */ +#define SPI_CTL_EMISO 0x00000100 /*Enable MISO */ +#define SPI_CTL_SIZE 0x00000600 /*Word Transfer Size */ +#define SPI_CTL_SIZE08 0x00000000 /*SIZE: 8 bits */ +#define SPI_CTL_SIZE16 0x00000200 /*SIZE: 16 bits */ +#define SPI_CTL_SIZE32 0x00000400 /*SIZE: 32 bits */ +#define SPI_CTL_LSBF 0x00001000 /*LSB First */ +#define SPI_CTL_FCEN 0x00002000 /*Flow-Control Enable */ +#define SPI_CTL_FCCH 0x00004000 /*Flow-Control Channel Selection */ +#define SPI_CTL_FCPL 0x00008000 /*Flow-Control Polarity */ +#define SPI_CTL_FCWM 0x00030000 /*Flow-Control Water-Mark */ +#define SPI_CTL_FIFO0 0x00000000 /*FCWM: Tx empty or Rx Full */ +#define SPI_CTL_FIFO1 0x00010000 /*FCWM: Tx empty or Rx full (>=75%) */ +#define SPI_CTL_FIFO2 0x00020000 /*FCWM: Tx empty or Rx full (>=50%) */ +#define SPI_CTL_FMODE 0x00040000 /*Fast-mode Enable */ +#define SPI_CTL_MIOM 0x00300000 /*Multiple I/O Mode */ +#define SPI_CTL_MIO_DIS 0x00000000 /*MIOM: Disable */ +#define SPI_CTL_MIO_DUAL 0x00100000 /*MIOM: Enable DIOM (Dual I/O Mode) */ +#define SPI_CTL_MIO_QUAD 0x00200000 /*MIOM: Enable QUAD (Quad SPI Mode) */ +#define SPI_CTL_SOSI 0x00400000 /*Start on MOSI */ +/* SPI_RX_CONTROL */ +#define SPI_RXCTL_REN 0x00000001 /*Receive Channel Enable */ +#define SPI_RXCTL_RTI 0x00000004 /*Receive Transfer Initiate */ +#define SPI_RXCTL_RWCEN 0x00000008 /*Receive Word Counter Enable */ +#define SPI_RXCTL_RDR 0x00000070 /*Receive Data Request */ +#define SPI_RXCTL_RDR_DIS 0x00000000 /*RDR: Disabled */ +#define SPI_RXCTL_RDR_NE 0x00000010 /*RDR: RFIFO not empty */ +#define SPI_RXCTL_RDR_25 0x00000020 /*RDR: RFIFO 25% full */ +#define SPI_RXCTL_RDR_50 0x00000030 /*RDR: RFIFO 50% full */ +#define SPI_RXCTL_RDR_75 0x00000040 /*RDR: RFIFO 75% full */ +#define SPI_RXCTL_RDR_FULL 0x00000050 /*RDR: RFIFO full */ +#define SPI_RXCTL_RDO 0x00000100 /*Receive Data Over-Run */ +#define SPI_RXCTL_RRWM 0x00003000 /*FIFO Regular Water-Mark */ +#define SPI_RXCTL_RWM_0 0x00000000 /*RRWM: RFIFO Empty */ +#define SPI_RXCTL_RWM_25 0x00001000 /*RRWM: RFIFO 25% full */ +#define SPI_RXCTL_RWM_50 0x00002000 /*RRWM: RFIFO 50% full */ +#define SPI_RXCTL_RWM_75 0x00003000 /*RRWM: RFIFO 75% full */ +#define SPI_RXCTL_RUWM 0x00070000 /*FIFO Urgent Water-Mark */ +#define SPI_RXCTL_UWM_DIS 0x00000000 /*RUWM: Disabled */ +#define SPI_RXCTL_UWM_25 0x00010000 /*RUWM: RFIFO 25% full */ +#define SPI_RXCTL_UWM_50 0x00020000 /*RUWM: RFIFO 50% full */ +#define SPI_RXCTL_UWM_75 0x00030000 /*RUWM: RFIFO 75% full */ +#define SPI_RXCTL_UWM_FULL 0x00040000 /*RUWM: RFIFO full */ +/* SPI_TX_CONTROL */ +#define SPI_TXCTL_TEN 0x00000001 /*Transmit Channel Enable */ +#define SPI_TXCTL_TTI 0x00000004 /*Transmit Transfer Initiate */ +#define SPI_TXCTL_TWCEN 0x00000008 /*Transmit Word Counter Enable */ +#define SPI_TXCTL_TDR 0x00000070 /*Transmit Data Request */ +#define SPI_TXCTL_TDR_DIS 0x00000000 /*TDR: Disabled */ +#define SPI_TXCTL_TDR_NF 0x00000010 /*TDR: TFIFO not full */ +#define SPI_TXCTL_TDR_25 0x00000020 /*TDR: TFIFO 25% empty */ +#define SPI_TXCTL_TDR_50 0x00000030 /*TDR: TFIFO 50% empty */ +#define SPI_TXCTL_TDR_75 0x00000040 /*TDR: TFIFO 75% empty */ +#define SPI_TXCTL_TDR_EMPTY 0x00000050 /*TDR: TFIFO empty */ +#define SPI_TXCTL_TDU 0x00000100 /*Transmit Data Under-Run */ +#define SPI_TXCTL_TRWM 0x00003000 /*FIFO Regular Water-Mark */ +#define SPI_TXCTL_RWM_FULL 0x00000000 /*TRWM: TFIFO full */ +#define SPI_TXCTL_RWM_25 0x00001000 /*TRWM: TFIFO 25% empty */ +#define SPI_TXCTL_RWM_50 0x00002000 /*TRWM: TFIFO 50% empty */ +#define SPI_TXCTL_RWM_75 0x00003000 /*TRWM: TFIFO 75% empty */ +#define SPI_TXCTL_TUWM 0x00070000 /*FIFO Urgent Water-Mark */ +#define SPI_TXCTL_UWM_DIS 0x00000000 /*TUWM: Disabled */ +#define SPI_TXCTL_UWM_25 0x00010000 /*TUWM: TFIFO 25% empty */ +#define SPI_TXCTL_UWM_50 0x00020000 /*TUWM: TFIFO 50% empty */ +#define SPI_TXCTL_UWM_75 0x00030000 /*TUWM: TFIFO 75% empty */ +#define SPI_TXCTL_UWM_EMPTY 0x00040000 /*TUWM: TFIFO empty */ +/* SPI_CLOCK */ +#define SPI_CLK_BAUD 0x0000FFFF /*Baud Rate */ +/* SPI_DELAY */ +#define SPI_DLY_STOP 0x000000FF /*Transfer delay time */ +#define SPI_DLY_LEADX 0x00000100 /*Extended (1 SCK) LEAD Control */ +#define SPI_DLY_LAGX 0x00000200 /*Extended (1 SCK) LAG control */ +/* SPI_SSEL */ +#define SPI_SLVSEL_SSE1 0x00000002 /*SPISSEL1 Enable */ +#define SPI_SLVSEL_SSE2 0x00000004 /*SPISSEL2 Enable */ +#define SPI_SLVSEL_SSE3 0x00000008 /*SPISSEL3 Enable */ +#define SPI_SLVSEL_SSE4 0x00000010 /*SPISSEL4 Enable */ +#define SPI_SLVSEL_SSE5 0x00000020 /*SPISSEL5 Enable */ +#define SPI_SLVSEL_SSE6 0x00000040 /*SPISSEL6 Enable */ +#define SPI_SLVSEL_SSE7 0x00000080 /*SPISSEL7 Enable */ +#define SPI_SLVSEL_SSEL1 0x00000200 /*SPISSEL1 Value */ +#define SPI_SLVSEL_SSEL2 0x00000400 /*SPISSEL2 Value */ +#define SPI_SLVSEL_SSEL3 0x00000800 /*SPISSEL3 Value */ +#define SPI_SLVSEL_SSEL4 0x00001000 /*SPISSEL4 Value */ +#define SPI_SLVSEL_SSEL5 0x00002000 /*SPISSEL5 Value */ +#define SPI_SLVSEL_SSEL6 0x00004000 /*SPISSEL6 Value */ +#define SPI_SLVSEL_SSEL7 0x00008000 /*SPISSEL7 Value */ +/* SPI_RWC */ +#define SPI_RWC_VALUE 0x0000FFFF /*Received Word-Count */ +/* SPI_RWCR */ +#define SPI_RWCR_VALUE 0x0000FFFF /*Received Word-Count Reload */ +/* SPI_TWC */ +#define SPI_TWC_VALUE 0x0000FFFF /*Transmitted Word-Count */ +/* SPI_TWCR */ +#define SPI_TWCR_VALUE 0x0000FFFF /*Transmitted Word-Count Reload */ +/* SPI_IMASK */ +#define SPI_IMSK_RUWM 0x00000002 /*Receive Water-Mark Interrupt Mask */ +#define SPI_IMSK_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */ +#define SPI_IMSK_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */ +#define SPI_IMSK_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */ +#define SPI_IMSK_TCM 0x00000040 /*Transmit Collision Interrupt Mask */ +#define SPI_IMSK_MFM 0x00000080 /*Mode Fault Interrupt Mask */ +#define SPI_IMSK_RSM 0x00000100 /*Receive Start Interrupt Mask */ +#define SPI_IMSK_TSM 0x00000200 /*Transmit Start Interrupt Mask */ +#define SPI_IMSK_RFM 0x00000400 /*Receive Finish Interrupt Mask */ +#define SPI_IMSK_TFM 0x00000800 /*Transmit Finish Interrupt Mask */ +/* SPI_IMASKCL */ +#define SPI_IMSK_CLR_RUW 0x00000002 /*Receive Water-Mark Interrupt Mask */ +#define SPI_IMSK_CLR_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */ +#define SPI_IMSK_CLR_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */ +#define SPI_IMSK_CLR_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */ +#define SPI_IMSK_CLR_TCM 0x00000040 /*Transmit Collision Interrupt Mask */ +#define SPI_IMSK_CLR_MFM 0x00000080 /*Mode Fault Interrupt Mask */ +#define SPI_IMSK_CLR_RSM 0x00000100 /*Receive Start Interrupt Mask */ +#define SPI_IMSK_CLR_TSM 0x00000200 /*Transmit Start Interrupt Mask */ +#define SPI_IMSK_CLR_RFM 0x00000400 /*Receive Finish Interrupt Mask */ +#define SPI_IMSK_CLR_TFM 0x00000800 /*Transmit Finish Interrupt Mask */ +/* SPI_IMASKST */ +#define SPI_IMSK_SET_RUWM 0x00000002 /*Receive Water-Mark Interrupt Mask */ +#define SPI_IMSK_SET_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */ +#define SPI_IMSK_SET_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */ +#define SPI_IMSK_SET_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */ +#define SPI_IMSK_SET_TCM 0x00000040 /*Transmit Collision Interrupt Mask */ +#define SPI_IMSK_SET_MFM 0x00000080 /*Mode Fault Interrupt Mask */ +#define SPI_IMSK_SET_RSM 0x00000100 /*Receive Start Interrupt Mask */ +#define SPI_IMSK_SET_TSM 0x00000200 /*Transmit Start Interrupt Mask */ +#define SPI_IMSK_SET_RFM 0x00000400 /*Receive Finish Interrupt Mask */ +#define SPI_IMSK_SET_TFM 0x00000800 /*Transmit Finish Interrupt Mask */ +/* SPI_STATUS */ +#define SPI_STAT_SPIF 0x00000001 /*SPI Finished */ +#define SPI_STAT_RUWM 0x00000002 /*Receive Water-Mark Breached */ +#define SPI_STAT_TUWM 0x00000004 /*Transmit Water-Mark Breached */ +#define SPI_STAT_ROE 0x00000010 /*Receive Over-Run Indication */ +#define SPI_STAT_TUE 0x00000020 /*Transmit Under-Run Indication */ +#define SPI_STAT_TCE 0x00000040 /*Transmit Collision Indication */ +#define SPI_STAT_MODF 0x00000080 /*Mode Fault Indication */ +#define SPI_STAT_RS 0x00000100 /*Receive Start Indication */ +#define SPI_STAT_TS 0x00000200 /*Transmit Start Indication */ +#define SPI_STAT_RF 0x00000400 /*Receive Finish Indication */ +#define SPI_STAT_TF 0x00000800 /*Transmit Finish Indication */ +#define SPI_STAT_RFS 0x00007000 /*SPI_RFIFO status */ +#define SPI_STAT_RFIFO_EMPTY 0x00000000 /*RFS: RFIFO Empty */ +#define SPI_STAT_RFIFO_25 0x00001000 /*RFS: RFIFO 25% Full */ +#define SPI_STAT_RFIFO_50 0x00002000 /*RFS: RFIFO 50% Full */ +#define SPI_STAT_RFIFO_75 0x00003000 /*RFS: RFIFO 75% Full */ +#define SPI_STAT_RFIFO_FULL 0x00004000 /*RFS: RFIFO Full */ +#define SPI_STAT_TFS 0x00070000 /*SPI_TFIFO status */ +#define SPI_STAT_TFIFO_FULL 0x00000000 /*TFS: TFIFO full */ +#define SPI_STAT_TFIFO_25 0x00010000 /*TFS: TFIFO 25% empty */ +#define SPI_STAT_TFIFO_50 0x00020000 /*TFS: TFIFO 50% empty */ +#define SPI_STAT_TFIFO_75 0x00030000 /*TFS: TFIFO 75% empty */ +#define SPI_STAT_TFIFO_EMPTY 0x00040000 /*TFS: TFIFO empty */ +#define SPI_STAT_FCS 0x00100000 /*Flow-Control Stall Indication */ +#define SPI_STAT_RFE 0x00400000 /*SPI_RFIFO Empty */ +#define SPI_STAT_TFF 0x00800000 /*SPI_TFIFO Full */ +/* SPI_ILAT */ +#define SPI_ILAT_RUWMI 0x00000002 /*Receive Water Mark Interrupt */ +#define SPI_ILAT_TUWMI 0x00000004 /*Transmit Water Mark Interrupt */ +#define SPI_ILAT_ROI 0x00000010 /*Receive Over-Run Indication */ +#define SPI_ILAT_TUI 0x00000020 /*Transmit Under-Run Indication */ +#define SPI_ILAT_TCI 0x00000040 /*Transmit Collision Indication */ +#define SPI_ILAT_MFI 0x00000080 /*Mode Fault Indication */ +#define SPI_ILAT_RSI 0x00000100 /*Receive Start Indication */ +#define SPI_ILAT_TSI 0x00000200 /*Transmit Start Indication */ +#define SPI_ILAT_RFI 0x00000400 /*Receive Finish Indication */ +#define SPI_ILAT_TFI 0x00000800 /*Transmit Finish Indication */ +/* SPI_ILATCL */ +#define SPI_ILAT_CLR_RUWMI 0x00000002 /*Receive Water Mark Interrupt */ +#define SPI_ILAT_CLR_TUWMI 0x00000004 /*Transmit Water Mark Interrupt */ +#define SPI_ILAT_CLR_ROI 0x00000010 /*Receive Over-Run Indication */ +#define SPI_ILAT_CLR_TUI 0x00000020 /*Transmit Under-Run Indication */ +#define SPI_ILAT_CLR_TCI 0x00000040 /*Transmit Collision Indication */ +#define SPI_ILAT_CLR_MFI 0x00000080 /*Mode Fault Indication */ +#define SPI_ILAT_CLR_RSI 0x00000100 /*Receive Start Indication */ +#define SPI_ILAT_CLR_TSI 0x00000200 /*Transmit Start Indication */ +#define SPI_ILAT_CLR_RFI 0x00000400 /*Receive Finish Indication */ +#define SPI_ILAT_CLR_TFI 0x00000800 /*Transmit Finish Indication */ + +/* + * bfin spi3 registers layout + */ +struct bfin_spi_regs { + u32 revid; + u32 control; + u32 rx_control; + u32 tx_control; + u32 clock; + u32 delay; + u32 ssel; + u32 rwc; + u32 rwcr; + u32 twc; + u32 twcr; + u32 reserved0; + u32 emask; + u32 emaskcl; + u32 emaskst; + u32 reserved1; + u32 status; + u32 elat; + u32 elatcl; + u32 reserved2; + u32 rfifo; + u32 reserved3; + u32 tfifo; +}; + +#endif /* _SPI_CHANNEL_H_ */ diff --git a/arch/blackfin/include/asm/mach-common/bits/uart4.h b/arch/blackfin/include/asm/mach-common/bits/uart4.h new file mode 100644 index 0000000..37808de --- /dev/null +++ b/arch/blackfin/include/asm/mach-common/bits/uart4.h @@ -0,0 +1,66 @@ +/* + * UART4 Masks + */ + +#ifndef __BFIN_PERIPHERAL_UART4__ +#define __BFIN_PERIPHERAL_UART4__ + +/* UART_CONTROL */ +#define UEN (1 << 0) +#define LOOP_ENA (1 << 1) +#define UMOD (3 << 4) +#define UMOD_UART (0 << 4) +#define UMOD_MDB (1 << 4) +#define UMOD_IRDA (1 << 4) +#define WLS (3 << 8) +#define WLS_5 (0 << 8) +#define WLS_6 (1 << 8) +#define WLS_7 (2 << 8) +#define WLS_8 (3 << 8) +#define STB (1 << 12) +#define STBH (1 << 13) +#define PEN (1 << 14) +#define EPS (1 << 15) +#define STP (1 << 16) +#define FPE (1 << 17) +#define FFE (1 << 18) +#define SB (1 << 19) +#define FCPOL (1 << 22) +#define RPOLC (1 << 23) +#define TPOLC (1 << 24) +#define MRTS (1 << 25) +#define XOFF (1 << 26) +#define ARTS (1 << 27) +#define ACTS (1 << 28) +#define RFIT (1 << 29) +#define RFRT (1 << 30) + +/* UART_STATUS */ +#define DR (1 << 0) +#define OE (1 << 1) +#define PE (1 << 2) +#define FE (1 << 3) +#define BI (1 << 4) +#define THRE (1 << 5) +#define TEMT (1 << 7) +#define TFI (1 << 8) +#define ASTKY (1 << 9) +#define ADDR (1 << 10) +#define RO (1 << 11) +#define SCTS (1 << 12) +#define CTS (1 << 16) +#define RFCS (1 << 17) + +/* UART_EMASK */ +#define ERBFI (1 << 0) +#define ETBEI (1 << 1) +#define ELSI (1 << 2) +#define EDSSI (1 << 3) +#define EDTPTI (1 << 4) +#define ETFI (1 << 5) +#define ERFCI (1 << 6) +#define EAWI (1 << 7) +#define ERXS (1 << 8) +#define ETXS (1 << 9) + +#endif diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 9fbbea0..288dc82 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -96,6 +96,13 @@ static void display_global_data(void) #define CPLB_PAGE_SIZE (4 * 1024 * 1024) #define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) +#if defined(__ADSPBF60x__) +#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024) +#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1)) +#else +#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE +#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK +#endif void init_cplbtables(void) { volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; @@ -127,6 +134,11 @@ void init_cplbtables(void) icplb_add(0xFFA00000, L1_IMEMORY); dcplb_add(0xFF800000, L1_DMEMORY); ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + ++i; +#endif if (CONFIG_MEM_SIZE) { uint32_t mbase = CONFIG_SYS_MONITOR_BASE; @@ -150,9 +162,11 @@ void init_cplbtables(void) } } +#ifndef __ADSPBF60x__ icplb_add(0x20000000, SDRAM_INON_CHBL); dcplb_add(0x20000000, SDRAM_EBIU); ++i; +#endif /* Add entries for the rest of external RAM up to the bootrom */ extern_memory = 0; @@ -167,10 +181,11 @@ void init_cplbtables(void) ++i; #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { + while (i < 16 && extern_memory < + (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += CPLB_EX_PAGE_SIZE; ++i; } while (i < 16) { @@ -295,7 +310,13 @@ void board_init_f(ulong bootflag) printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); printf("Core: %s MHz, ", strmhz(buf, get_cclk())); +#if defined(__ADSPBF60x__) + printf("System0: %s MHz, ", strmhz(buf, get_sclk0())); + printf("System1: %s MHz, ", strmhz(buf, get_sclk1())); + printf("Dclk: %s MHz\n", strmhz(buf, get_dclk())); +#else printf("System: %s MHz\n", strmhz(buf, get_sclk())); +#endif if (CONFIG_MEM_SIZE) { printf("RAM: "); diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c index 0be395b..d852f5e 100644 --- a/arch/blackfin/lib/clocks.c +++ b/arch/blackfin/lib/clocks.c @@ -9,69 +9,139 @@ #include <common.h> #include <asm/blackfin.h> +#ifdef PLL_CTL +# include <asm/mach-common/bits/pll.h> +# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF) +#else +# include <asm/mach-common/bits/cgu.h> +# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP) +# define bfin_read_PLL_CTL() bfin_read_CGU_CTL() +# define bfin_read_PLL_DIV() bfin_read_CGU_DIV() +#endif + /* Get the voltage input multiplier */ -static u_long cached_vco_pll_ctl, cached_vco; u_long get_vco(void) { - u_long msel; + static u_long cached_vco_pll_ctl, cached_vco; + + u_long msel, pll_ctl; - u_long pll_ctl = bfin_read_PLL_CTL(); + pll_ctl = bfin_read_PLL_CTL(); if (pll_ctl == cached_vco_pll_ctl) return cached_vco; else cached_vco_pll_ctl = pll_ctl; - msel = (pll_ctl >> 9) & 0x3F; + msel = (pll_ctl & MSEL) >> MSEL_P; if (0 == msel) - msel = 64; + msel = (MSEL >> MSEL_P) + 1; cached_vco = CONFIG_CLKIN_HZ; - cached_vco >>= (1 & pll_ctl); /* DF bit */ + cached_vco >>= (pll_ctl & DF); cached_vco *= msel; return cached_vco; } /* Get the Core clock */ -static u_long cached_cclk_pll_div, cached_cclk; u_long get_cclk(void) { - u_long csel, ssel; + static u_long cached_cclk_pll_div, cached_cclk; + u_long div, csel, ssel; - if (bfin_read_PLL_STAT() & 0x1) + if (pll_is_bypassed()) return CONFIG_CLKIN_HZ; - ssel = bfin_read_PLL_DIV(); - if (ssel == cached_cclk_pll_div) + div = bfin_read_PLL_DIV(); + if (div == cached_cclk_pll_div) return cached_cclk; else - cached_cclk_pll_div = ssel; + cached_cclk_pll_div = div; - csel = ((ssel >> 4) & 0x03); - ssel &= 0xf; + csel = (div & CSEL) >> CSEL_P; +#ifndef CGU_DIV + ssel = (div & SSEL) >> SSEL_P; if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ cached_cclk = get_vco() / ssel; else cached_cclk = get_vco() >> csel; +#else + cached_cclk = get_vco() / csel; +#endif return cached_cclk; } /* Get the System clock */ +#ifdef CGU_DIV + static u_long cached_sclk_pll_div, cached_sclk; +static u_long cached_sclk0, cached_sclk1, cached_dclk; +static u_long _get_sclk(u_long *cache) +{ + u_long div, ssel; + + if (pll_is_bypassed()) + return CONFIG_CLKIN_HZ; + + div = bfin_read_PLL_DIV(); + if (div == cached_sclk_pll_div) + return *cache; + else + cached_sclk_pll_div = div; + + ssel = (div & SYSSEL) >> SYSSEL_P; + cached_sclk = get_vco() / ssel; + + ssel = (div & S0SEL) >> S0SEL_P; + cached_sclk0 = cached_sclk / ssel; + + ssel = (div & S1SEL) >> S1SEL_P; + cached_sclk1 = cached_sclk / ssel; + + ssel = (div & DSEL) >> DSEL_P; + cached_dclk = get_vco() / ssel; + + return *cache; +} + u_long get_sclk(void) { - u_long ssel; + return _get_sclk(&cached_sclk); +} + +u_long get_sclk0(void) +{ + return _get_sclk(&cached_sclk0); +} + +u_long get_sclk1(void) +{ + return _get_sclk(&cached_sclk1); +} + +u_long get_dclk(void) +{ + return _get_sclk(&cached_dclk); +} +#else + +u_long get_sclk(void) +{ + static u_long cached_sclk_pll_div, cached_sclk; + u_long div, ssel; - if (bfin_read_PLL_STAT() & 0x1) + if (pll_is_bypassed()) return CONFIG_CLKIN_HZ; - ssel = bfin_read_PLL_DIV(); - if (ssel == cached_sclk_pll_div) + div = bfin_read_PLL_DIV(); + if (div == cached_sclk_pll_div) return cached_sclk; else - cached_sclk_pll_div = ssel; - - ssel &= 0xf; + cached_sclk_pll_div = div; + ssel = (div & SSEL) >> SSEL_P; cached_sclk = get_vco() / ssel; + return cached_sclk; } + +#endif diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c index e344d3b..44d8c6d 100644 --- a/arch/blackfin/lib/string.c +++ b/arch/blackfin/lib/string.c @@ -29,7 +29,7 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/io.h> -#include <asm/mach-common/bits/dma.h> +#include <asm/dma.h> char *strcpy(char *dest, const char *src) { @@ -117,81 +117,88 @@ int strncmp(const char *cs, const char *ct, size_t count) return __res1; } -#ifdef bfin_write_MDMA1_D0_IRQ_STATUS -# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS -# define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA1_D0_START_ADDR -# define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA1_D0_X_COUNT -# define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA1_D0_X_MODIFY -# define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA1_D0_CONFIG -# define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA1_S0_START_ADDR -# define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA1_S0_X_COUNT -# define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA1_S0_X_MODIFY -# define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA1_S0_CONFIG -# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS -# define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA1_D0_IRQ_STATUS +#ifdef MDMA1_D0_NEXT_DESC_PTR +# define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR +# define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR #endif + +static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count, + unsigned long *dshift, unsigned long *bpos) +{ + unsigned long limit; + +#ifdef MSIZE + limit = 6; + *dshift = MSIZE_P; +#else + limit = 3; + *dshift = WDSIZE_P; +#endif + + *bpos = min(limit, ffs(ldst | lsrc | count)) - 1; +} + /* This version misbehaves for count values of 0 and 2^16+. * Perhaps we should detect that ? Nowhere do we actually * use dma memcpy for those types of lengths though ... */ void dma_memcpy_nocache(void *dst, const void *src, size_t count) { - uint16_t wdsize, mod; + struct dma_register *mdma_d0 = (void *)MDMA_D0_NEXT_DESC_PTR; + struct dma_register *mdma_s0 = (void *)MDMA_S0_NEXT_DESC_PTR; + unsigned long ldst = (unsigned long)dst; + unsigned long lsrc = (unsigned long)src; + unsigned long dshift, bpos; + uint32_t dsize, mod; /* Disable DMA in case it's still running (older u-boot's did not * always turn them off). Do it before the if statement below so * we can be cheap and not do a SSYNC() due to the forced abort. */ - bfin_write_MDMA_D0_CONFIG(0); - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR); + bfin_write(&mdma_d0->config, 0); + bfin_write(&mdma_s0->config, 0); + bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR); /* Scratchpad cannot be a DMA source or destination */ - if (((unsigned long)src >= L1_SRAM_SCRATCH && - (unsigned long)src < L1_SRAM_SCRATCH_END) || - ((unsigned long)dst >= L1_SRAM_SCRATCH && - (unsigned long)dst < L1_SRAM_SCRATCH_END)) + if ((lsrc >= L1_SRAM_SCRATCH && lsrc < L1_SRAM_SCRATCH_END) || + (ldst >= L1_SRAM_SCRATCH && ldst < L1_SRAM_SCRATCH_END)) hang(); - if (((unsigned long)dst | (unsigned long)src | count) & 0x1) { - wdsize = WDSIZE_8; - mod = 1; - } else if (((unsigned long)dst | (unsigned long)src | count) & 0x2) { - wdsize = WDSIZE_16; - count >>= 1; - mod = 2; - } else { - wdsize = WDSIZE_32; - count >>= 2; - mod = 4; - } + dma_calc_size(ldst, lsrc, count, &dshift, &bpos); + dsize = bpos << dshift; + count >>= bpos; + mod = 1 << bpos; + +#ifdef PSIZE + dsize |= min(3, bpos) << PSIZE_P; +#endif /* Copy sram functions from sdram to sram */ /* Setup destination start address */ - bfin_write_MDMA_D0_START_ADDR(dst); + bfin_write(&mdma_d0->start_addr, ldst); /* Setup destination xcount */ - bfin_write_MDMA_D0_X_COUNT(count); + bfin_write(&mdma_d0->x_count, count); /* Setup destination xmodify */ - bfin_write_MDMA_D0_X_MODIFY(mod); + bfin_write(&mdma_d0->x_modify, mod); /* Setup Source start address */ - bfin_write_MDMA_S0_START_ADDR(src); + bfin_write(&mdma_s0->start_addr, lsrc); /* Setup Source xcount */ - bfin_write_MDMA_S0_X_COUNT(count); + bfin_write(&mdma_s0->x_count, count); /* Setup Source xmodify */ - bfin_write_MDMA_S0_X_MODIFY(mod); + bfin_write(&mdma_s0->x_modify, mod); /* Enable source DMA */ - bfin_write_MDMA_S0_CONFIG(wdsize | DMAEN); - bfin_write_MDMA_D0_CONFIG(wdsize | DMAEN | WNR | DI_EN); + bfin_write(&mdma_s0->config, dsize | DMAEN); + bfin_write(&mdma_d0->config, dsize | DMAEN | WNR | DI_EN); SSYNC(); - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) + while (!(bfin_read(&mdma_d0->status) & DMA_DONE)) continue; - bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR); - bfin_write_MDMA_D0_CONFIG(0); - bfin_write_MDMA_S0_CONFIG(0); + bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR); + bfin_write(&mdma_d0->config, 0); + bfin_write(&mdma_s0->config, 0); } /* We should do a dcache invalidate on the destination after the dma, but since * we lack such hardware capability, we'll flush/invalidate the destination diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile new file mode 100644 index 0000000..0bb8fe6 --- /dev/null +++ b/board/bf609-ezkit/Makefile @@ -0,0 +1,55 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_BFIN_SOFT_SWITCH) += soft_switch.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c new file mode 100644 index 0000000..0388226 --- /dev/null +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -0,0 +1,67 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2008-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/blackfin.h> +#include <asm/io.h> +#include <asm/portmux.h> +#include "soft_switch.h" + +int checkboard(void) +{ + printf("Board: ADI BF609 EZ-Kit board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + return 0; +} + +int board_early_init_f(void) +{ + static const unsigned short pins[] = { + P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, + P_A22, P_A23, P_A24, P_A25, P_NORCK, 0, + }; + peripheral_request_list(pins, "smc0"); + + return 0; +} + +#ifdef CONFIG_DESIGNWARE_ETH +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + if (CONFIG_DW_PORTS & 1) { + static const unsigned short pins[] = P_RMII0; + if (!peripheral_request_list(pins, "emac0")) + ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); + } + if (CONFIG_DW_PORTS & 2) { + static const unsigned short pins[] = P_RMII1; + if (!peripheral_request_list(pins, "emac1")) + ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); + } + + return ret; +} +#endif + +#ifdef CONFIG_BFIN_SDH +int board_mmc_init(bd_t *bis) +{ + return bfin_mmc_init(bis); +} +#endif + +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + printf("other init\n"); + return setup_board_switches(); +} @@ -361,6 +361,7 @@ bf538f-ezkit blackfin blackfin bf548-ezkit blackfin blackfin bf561-acvilon blackfin blackfin bf561-ezkit blackfin blackfin +bf609-ezkit blackfin blackfin blackstamp blackfin blackfin blackvme blackfin blackfin br4 blackfin blackfin diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 08a6563..b591bd3 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -191,7 +191,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, #elif defined(CONFIG_BLACKFIN) puts("\nSystem Configuration registers\n"); - +#ifndef __ADSPBF60x__ puts("\nPLL Registers\n"); printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); @@ -227,7 +227,24 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); # endif +#else + puts("\nCGU Registers\n"); + printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n", + bfin_read_CGU_DIV(), bfin_read_CGU_CTL()); + printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n", + bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL()); + puts("\nSMC DDR Registers\n"); + printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n", + bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0()); + printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n", + bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2()); + printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n", + bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1()); + printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n", + bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT()); + printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL()); +#endif #endif /* CONFIG_BLACKFIN */ return 0; diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 8d59d46..0f98b96 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -19,9 +19,7 @@ #include <asm/mach-common/bits/sdh.h> #include <asm/mach-common/bits/dma.h> -#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) -# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL -# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL +#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__) # define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL # define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL # define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT @@ -38,10 +36,21 @@ # define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL # define bfin_read_SDH_CFG bfin_read_RSI_CONFIG # define bfin_write_SDH_CFG bfin_write_RSI_CONFIG +# if defined(__ADSPBF60x__) +# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ +# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ +# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR +# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT +# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY +# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG +# else +# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL +# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL # define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR # define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT # define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY # define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG +# endif # define PORTMUX_PINS \ { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 } #elif defined(__ADSPBF54x__) @@ -70,6 +79,9 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) sdh_cmd |= CMD_RSP; if (flags & MMC_RSP_136) sdh_cmd |= CMD_L_RSP; +#ifdef RSI_BLKSZ + sdh_cmd |= CMD_DATA0_BUSY; +#endif bfin_write_SDH_ARGUMENT(arg); bfin_write_SDH_COMMAND(sdh_cmd); @@ -104,6 +116,12 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT); +#ifdef RSI_BLKSZ + /* wait till card ready */ + while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY)) + continue; + bfin_write_RSI_ESTAT(SD_CARD_READY); +#endif return ret; } @@ -113,16 +131,19 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) { u16 data_ctl = 0; u16 dma_cfg = 0; - int ret = 0; unsigned long data_size = data->blocksize * data->blocks; /* Don't support write yet. */ if (data->flags & MMC_DATA_WRITE) return UNUSABLE_ERR; +#ifndef RSI_BLKSZ data_ctl |= ((ffs(data_size) - 1) << 4); +#else + bfin_write_SDH_BLK_SIZE(data_size); +#endif data_ctl |= DTX_DIR; bfin_write_SDH_DATA_CTL(data_ctl); - dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN; + dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN; bfin_write_SDH_DATA_TIMER(-1); @@ -137,7 +158,7 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) /* kick off transfer */ bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); - return ret; + return 0; } @@ -147,13 +168,23 @@ static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, u32 status; int ret = 0; + if (data) { + ret = sdh_setup_data(mmc, data); + if (ret) + return ret; + } + ret = sdh_send_cmd(mmc, cmd); if (ret) { + bfin_write_SDH_COMMAND(0); + bfin_write_DMA_CONFIG(0); + bfin_write_SDH_DATA_CTL(0); + SSYNC(); printf("sending CMD%d failed\n", cmd->cmdidx); return ret; } + if (data) { - ret = sdh_setup_data(mmc, data); do { udelay(1); status = bfin_read_SDH_STATUS(); @@ -208,10 +239,12 @@ static void bfin_sdh_set_ios(struct mmc *mmc) if (mmc->bus_width == 4) { cfg = bfin_read_SDH_CFG(); - cfg &= ~0x80; - cfg |= 0x40; +#ifndef RSI_BLKSZ + cfg &= ~PD_SDDAT3; +#endif + cfg |= PUP_SDDAT3; bfin_write_SDH_CFG(cfg); - clk_ctl |= WIDE_BUS; + clk_ctl |= WIDE_BUS_4; } bfin_write_SDH_CLK_CTL(clk_ctl); sdh_set_clk(mmc->clock); @@ -220,20 +253,23 @@ static void bfin_sdh_set_ios(struct mmc *mmc) static int bfin_sdh_init(struct mmc *mmc) { const unsigned short pins[] = PORTMUX_PINS; - u16 pwr_ctl = 0; + int ret; /* Initialize sdh controller */ - peripheral_request_list(pins, "bfin_sdh"); + ret = peripheral_request_list(pins, "bfin_sdh"); + if (ret < 0) + return ret; #if defined(__ADSPBF54x__) bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); #endif bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); /* Disable card detect pin */ bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60); - - pwr_ctl |= ROD_CTL; - pwr_ctl |= PWR_ON; - bfin_write_SDH_PWR_CTL(pwr_ctl); +#ifndef RSI_BLKSZ + bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL); +#else + bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON); +#endif return 0; } diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 83abcbd..b8264df 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o +COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c new file mode 100644 index 0000000..fde3447 --- /dev/null +++ b/drivers/spi/bfin_spi6xx.c @@ -0,0 +1,308 @@ +/* + * Analog Devices SPI3 controller driver + * + * Copyright (c) 2011 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> + +#include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> +#include <asm/mach-common/bits/spi6xx.h> + +struct bfin_spi_slave { + struct spi_slave slave; + u32 control, clock; + struct bfin_spi_regs *regs; + int cs_pol; +}; + +#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave) + +#define gpio_cs(cs) ((cs) - MAX_CTRL_CS) +#ifdef CONFIG_BFIN_SPI_GPIO_CS +# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS) +#else +# define is_gpio_cs(cs) 0 +#endif + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (is_gpio_cs(cs)) + return gpio_is_valid(gpio_cs(cs)); + else + return (cs >= 1 && cs <= MAX_CTRL_CS); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_set_value(cs, bss->cs_pol); + } else { + u32 ssel; + ssel = bfin_read32(&bss->regs->ssel); + ssel |= 1 << slave->cs; + if (bss->cs_pol) + ssel |= (1 << 8) << slave->cs; + else + ssel &= ~((1 << 8) << slave->cs); + bfin_write32(&bss->regs->ssel, ssel); + } + + SSYNC(); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_set_value(cs, !bss->cs_pol); + } else { + u32 ssel; + ssel = bfin_read32(&bss->regs->ssel); + if (bss->cs_pol) + ssel &= ~((1 << 8) << slave->cs); + else + ssel |= (1 << 8) << slave->cs; + /* deassert cs */ + bfin_write32(&bss->regs->ssel, ssel); + SSYNC(); + /* disable cs */ + ssel &= ~(1 << slave->cs); + bfin_write32(&bss->regs->ssel, ssel); + } + + SSYNC(); +} + +void spi_init() +{ +} + +#define SPI_PINS(n) \ + { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 } +static unsigned short pins[][5] = { +#ifdef SPI0_REGBASE + [0] = SPI_PINS(0), +#endif +#ifdef SPI1_REGBASE + [1] = SPI_PINS(1), +#endif +#ifdef SPI2_REGBASE + [2] = SPI_PINS(2), +#endif +}; + +#define SPI_CS_PINS(n) \ + { \ + P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \ + P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \ + P_SPI##n##_SSEL7, \ + } +static const unsigned short cs_pins[][7] = { +#ifdef SPI0_REGBASE + [0] = SPI_CS_PINS(0), +#endif +#ifdef SPI1_REGBASE + [1] = SPI_CS_PINS(1), +#endif +#ifdef SPI2_REGBASE + [2] = SPI_CS_PINS(2), +#endif +}; + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + ulong sclk; + u32 clock; + + sclk = get_sclk1(); + clock = sclk / hz; + if (clock) + clock--; + bss->clock = clock; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct bfin_spi_slave *bss; + u32 reg_base; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) { + debug("%s: invalid bus %u\n", __func__, bus); + return NULL; + } + switch (bus) { +#ifdef SPI0_REGBASE + case 0: + reg_base = SPI0_REGBASE; + break; +#endif +#ifdef SPI1_REGBASE + case 1: + reg_base = SPI1_REGBASE; + break; +#endif +#ifdef SPI2_REGBASE + case 2: + reg_base = SPI2_REGBASE; + break; +#endif + default: + return NULL; + } + + bss = malloc(sizeof(*bss)); + if (!bss) + return NULL; + + bss->slave.bus = bus; + bss->slave.cs = cs; + bss->regs = (struct bfin_spi_regs *)reg_base; + bss->control = SPI_CTL_EN | SPI_CTL_MSTR; + if (mode & SPI_CPHA) + bss->control |= SPI_CTL_CPHA; + if (mode & SPI_CPOL) + bss->control |= SPI_CTL_CPOL; + if (mode & SPI_LSB_FIRST) + bss->control |= SPI_CTL_LSBF; + bss->control &= ~SPI_CTL_ASSEL; + bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0; + spi_set_speed(&bss->slave, max_hz); + + return &bss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + free(bss); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_request(cs, "bfin-spi"); + gpio_direction_output(cs, !bss->cs_pol); + pins[slave->bus][0] = P_DONTCARE; + } else + pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1]; + peripheral_request_list(pins[slave->bus], "bfin-spi"); + + bfin_write32(&bss->regs->control, bss->control); + bfin_write32(&bss->regs->clock, bss->clock); + bfin_write32(&bss->regs->delay, 0x0); + bfin_write32(&bss->regs->rx_control, SPI_RXCTL_REN); + bfin_write32(&bss->regs->tx_control, SPI_TXCTL_TEN | SPI_TXCTL_TTI); + SSYNC(); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + peripheral_free_list(pins[slave->bus]); + if (is_gpio_cs(slave->cs)) + gpio_free(gpio_cs(slave->cs)); + + bfin_write32(&bss->regs->rx_control, 0x0); + bfin_write32(&bss->regs->tx_control, 0x0); + bfin_write32(&bss->regs->control, 0x0); + SSYNC(); +} + +#ifndef CONFIG_BFIN_SPI_IDLE_VAL +# define CONFIG_BFIN_SPI_IDLE_VAL 0xff +#endif + +static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx, + uint bytes) +{ + /* discard invalid rx data and empty rfifo */ + while (!(bfin_read32(&bss->regs->status) & SPI_STAT_RFE)) + bfin_read32(&bss->regs->rfifo); + + while (bytes--) { + u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL); + debug("%s: tx:%x ", __func__, value); + bfin_write32(&bss->regs->tfifo, value); + SSYNC(); + while (bfin_read32(&bss->regs->status) & SPI_STAT_RFE) + if (ctrlc()) + return -1; + value = bfin_read32(&bss->regs->rfifo); + if (rx) + *rx++ = value; + debug("rx:%x\n", value); + } + + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + const u8 *tx = dout; + u8 *rx = din; + uint bytes = bitlen / 8; + int ret = 0; + + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, bytes, flags); + + if (bitlen == 0) + goto done; + + /* we can only do 8 bit transfers */ + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto done; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + ret = spi_pio_xfer(bss, tx, rx, bytes); + + done: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h new file mode 100644 index 0000000..02149fa --- /dev/null +++ b/include/configs/bf609-ezkit.h @@ -0,0 +1,162 @@ +/* + * U-boot - Configuration file for BF609 EZ-Kit board + */ + +#ifndef __CONFIG_BF609_EZKIT_H__ +#define __CONFIG_BF609_EZKIT_H__ + +#include <asm/config-pre.h> + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf609-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* For ez-board version 1.0, else undef this */ +#define CONFIG_BFIN_BOARD_VERSION_1_0 + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV + * SCLK0 = SCLK / SCLK0_DIV + * SCLK1 = SCLK / SCLK1_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ (25000000) +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF (0) + +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-127 (where 0 means 128) */ +#define CONFIG_VCO_MULT (20) + +/* CCLK_DIV controls the core clock divider */ +/* Values can range from 0-31 (where 0 means 32) */ +#define CONFIG_CCLK_DIV (1) +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 0-31 (where 0 means 32) */ +#define CONFIG_SCLK_DIV (4) +/* Values can range from 0-7 (where 0 means 8) */ +#define CONFIG_SCLK0_DIV (1) +#define CONFIG_SCLK1_DIV (1) +/* DCLK_DIV controls the DDR clock divider */ +/* Values can range from 0-31 (where 0 means 32) */ +#define CONFIG_DCLK_DIV (2) +/* OCLK_DIV controls the output clock divider */ +/* Values can range from 0-127 (where 0 means 128) */ +#define CONFIG_OCLK_DIV (16) + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 128 + +#define CONFIG_SMC_GCTL_VAL 0x00000010 +#define CONFIG_SMC_B0CTL_VAL 0x01007011 +#define CONFIG_SMC_B0TIM_VAL 0x08170977 +#define CONFIG_SMC_B0ETIM_VAL 0x00092231 + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +#define CONFIG_HW_WATCHDOG +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI +#define CONFIG_HOSTNAME "bf609-ezkit" +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_PORTS 1 +#define CONFIG_DW_AUTONEG +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_MII + +/* i2c Settings */ +#define CONFIG_BFIN_TWI_I2C +#define CONFIG_HARD_I2C + +/* + * Flash Settings + */ +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_JFFS2 +#define CONFIG_SYS_FLASH_CFI_WIDTH 2 +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0xb0000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI6XX +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ALL + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0" + +/* + * SDH Settings + */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_BFIN_SDH + +/* + * Misc Settings + */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_CMD_MEMORY + +#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4) +#define CONFIG_BFIN_SOFT_SWITCH + +#if 0 +#define CONFIG_UART_MEM 1024 +#undef CONFIG_UART_CONSOLE +#undef CONFIG_JTAG_CONSOLE +#undef CONFIG_UART_CONSOLE_IS_JTAG +#endif + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> +#endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index ccdec0d..d3ae3a7 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -10,7 +10,7 @@ */ #ifndef _CONFIG_CMD_DEFAULT_H # include <config_cmd_default.h> -# if ADI_CMDS_NETWORK +# ifdef ADI_CMDS_NETWORK # define CONFIG_CMD_DHCP # define CONFIG_BOOTP_SUBNETMASK # define CONFIG_BOOTP_GATEWAY @@ -58,7 +58,7 @@ # endif # ifdef CONFIG_RTC_BFIN # define CONFIG_CMD_DATE -# if ADI_CMDS_NETWORK +# ifdef ADI_CMDS_NETWORK # define CONFIG_CMD_SNTP # endif # endif @@ -193,10 +193,12 @@ "nand erase 0 0x40000;" \ "nand write $(loadaddr) 0 0x40000" # else -# define UBOOT_ENV_UPDATE \ +# ifndef UBOOT_ENV_UPDATE +# define UBOOT_ENV_UPDATE \ "protect off 0x20000000 +$(filesize);" \ "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" +# endif # endif # ifdef CONFIG_NETCONSOLE # define NETCONSOLE_ENV \ |