diff options
| -rw-r--r-- | arch/nds32/cpu/n1213/ag102/asm-offsets.c | 54 | ||||
| -rw-r--r-- | arch/nds32/include/asm/arch-ag102/ag102.h | 97 | ||||
| -rw-r--r-- | arch/nds32/include/asm/mach-types.h | 14 |
3 files changed, 165 insertions, 0 deletions
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c new file mode 100644 index 0000000..4769a95 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c @@ -0,0 +1,54 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <common.h> + +#include <linux/kbuild.h> + +int main(void) +{ +#ifdef CONFIG_FTSMC020 + OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); + OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); +#endif + BLANK(); +#ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); + OFFSET(FTAHBC020S_CR, ftahbc02s, cr); +#endif + BLANK(); +#ifdef CONFIG_ANDES_PCU + OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ +#endif + BLANK(); +#ifdef CONFIG_DWCDDR21MCTL + OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ + OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ + OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ + OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ + OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ + OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ + OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ + OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ + OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ + OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ + OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ + OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ + OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ + OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ + OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ + OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ + OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ +#endif + return 0; +} diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h new file mode 100644 index 0000000..a12a8c5 --- /dev/null +++ b/arch/nds32/include/asm/arch-ag102/ag102.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __AG102_H +#define __AG102_H + +/* + * Hardware register bases + */ + +/* PCI Controller */ +#define CONFIG_FTPCI100_BASE 0x90000000 +/* LPC Controller */ +#define CONFIG_LPC_IO_BASE 0x90100000 +/* LPC Controller */ +#define CONFIG_LPC_BASE 0x90200000 + +/* NDS32 Data Local Memory 01 */ +#define CONFIG_NDS_DLM1_BASE 0x90300000 +/* NDS32 Data Local Memory 02 */ +#define CONFIG_NDS_DLM2_BASE 0x90400000 + +/* Synopsys DWC DDR2/1 Controller */ +#define CONFIG_DWCDDR21MCTL_BASE 0x90500000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0x90600000 +/* FTIDE020_S IDE (ATA) Controller */ +#define CONFIG_FTIDE020S_BASE 0x90700000 +/* USB OTG Controller */ +#define CONFIG_FZOTG266HD0A_BASE 0x90800000 +/* Andes L2 Cache Controller */ +#define CONFIG_NCEL2C100_BASE 0x90900000 +/* XGI XG22 GPU */ +#define CONFIG_XGI_XG22_BASE 0x90A00000 +/* GMAC Ethernet Controller */ +#define CONFIG_FTGMAC100_BASE 0x90B00000 +/* AHB Controller */ +#define CONFIG_FTAHBC020S_BASE 0x90C00000 +/* AHB-to-APB Bridge Controller */ +#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 +/* External AHB2AHB Controller */ +#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 +/* Andes Multi-core Interrupt Controller */ +#define CONFIG_NCEMIC100_BASE 0x90F00000 + +/* + * APB Device definitions + */ +/* Compat Flash Controller */ +#define CONFIG_FTCFC010_BASE 0x94000000 +/* APB - SSP (SPI) (without AC97) Controller */ +#define CONFIG_FTSSP010_01_BASE 0x94100000 +/* UART1 - APB STUART Controller (UART0 in Linux) */ +#define CONFIG_FTUART010_01_BASE 0x94200000 +/* FTSDC010 SD Controller */ +#define CONFIG_FTSDC010_BASE 0x94400000 +/* APB - SSP with HDA/AC97 Controller */ +#define CONFIG_FTSSP010_02_BASE 0x94500000 +/* UART2 - APB STUART Controller (UART1 in Linux) */ +#define CONFIG_FTUART010_02_BASE 0x94600000 +/* PCU Controller */ +#define CONFIG_ANDES_PCU_BASE 0x94800000 +/* FTTMR010 Timer */ +#define CONFIG_FTTMR010_BASE 0x94900000 +/* Watch Dog Controller */ +#define CONFIG_FTWDT010_BASE 0x94A00000 +/* FTRTC010 Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0x98B00000 +/* GPIO Controller */ +#define CONFIG_FTGPIO010_BASE 0x94C00000 +/* I2C Controller */ +#define CONFIG_FTIIC010_BASE 0x94E00000 +/* PWM - Pulse Width Modulator Controller */ +#define CONFIG_FTPWM010_BASE 0x94F00000 + +/* Debug LED */ +#define CONFIG_DEBUG_LED 0x902FFFFC +/* Power Management Unit */ +#define CONFIG_FTPMU010_BASE 0x98100000 + +#endif /* __AG102_H */ diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index 7b52b98..259e4e7 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -40,4 +40,18 @@ extern unsigned int __machine_arch_type; # define machine_is_adpag101p() (1) #endif +#define MACH_TYPE_ADPAG102 2 + +#ifdef CONFIG_ARCH_ADPAG102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG102 +# endif +# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102) +#else +# define machine_is_adpag102() (2) +#endif + #endif /* __ASM_NDS32_MACH_TYPE_H */ |