diff options
| -rwxr-xr-x | MAKEALL | 1 | ||||
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | board/amcc/canyonlands/Makefile | 2 | ||||
| -rw-r--r-- | board/amcc/canyonlands/bootstrap.c | 23 | ||||
| -rw-r--r-- | board/amcc/canyonlands/canyonlands.c | 27 | ||||
| -rw-r--r-- | board/amcc/canyonlands/init.S | 7 | ||||
| -rw-r--r-- | board/amcc/canyonlands/u-boot-nand.lds | 137 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 8 | ||||
| -rw-r--r-- | include/configs/canyonlands.h | 89 | ||||
| -rw-r--r-- | nand_spl/board/amcc/canyonlands/Makefile | 105 | ||||
| -rw-r--r-- | nand_spl/board/amcc/canyonlands/config.mk | 49 | ||||
| -rw-r--r-- | nand_spl/board/amcc/canyonlands/ddr2_fixed.c | 96 | ||||
| -rw-r--r-- | nand_spl/board/amcc/canyonlands/u-boot.lds | 65 |
13 files changed, 591 insertions, 26 deletions
@@ -166,6 +166,7 @@ LIST_4xx=" \ bubinga \ CANBT \ canyonlands \ + canyonlands_nand \ CMS700 \ CPCI2DP \ CPCI405 \ @@ -1173,6 +1173,14 @@ CANBT_config: unconfig canyonlands_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc +canyonlands_nand_config: unconfig + @mkdir -p $(obj)include $(obj)board/amcc/canyonlands + @mkdir -p $(obj)nand_spl/board/amcc/canyonlands + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc + @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + CATcenter_config \ CATcenter_25_config \ CATcenter_33_config: unconfig diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile index 02281ae..7a2eaa5 100644 --- a/board/amcc/canyonlands/Makefile +++ b/board/amcc/canyonlands/Makefile @@ -34,7 +34,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c index 3f5822e..37fa1c9 100644 --- a/board/amcc/canyonlands/bootstrap.c +++ b/board/amcc/canyonlands/bootstrap.c @@ -28,7 +28,7 @@ #include <asm/io.h> /* - * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The + * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The * values are independent of the rest of the clock settings. */ @@ -45,14 +45,14 @@ static char *config_labels[] = { static u8 boot_configs[][17] = { { - (NOR_COMPATIBLE), + (NAND_COMPATIBLE | NOR_COMPATIBLE), 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, - 0x23, 0x50, 0x0d, 0x95, 0x00, 0x00 + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 }, { - (NOR_COMPATIBLE), + (NAND_COMPATIBLE | NOR_COMPATIBLE), 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08, - 0x23, 0x50, 0x0d, 0x95, 0x00, 0x00 + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 }, { 0, @@ -61,10 +61,10 @@ static u8 boot_configs[][17] = { }; /* - * Bytes 6,8,9,11 change for NAND boot + * Bytes 5,6,8,9,11 change for NAND boot */ static u8 nand_boot[] = { - 0xd0, 0xa0, 0x68, 0x58 + 0x90, 0x01, 0xa0, 0x68, 0x58 }; static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -146,10 +146,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) buf = &boot_configs[x][1]; if (b_nand) { - buf[6] = nand_boot[0]; - buf[8] = nand_boot[1]; - buf[9] = nand_boot[2]; - buf[11] = nand_boot[3]; + buf[5] = nand_boot[0]; + buf[6] = nand_boot[1]; + buf[8] = nand_boot[2]; + buf[9] = nand_boot[3]; + buf[11] = nand_boot[4]; } if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 8292d2d..3551429 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -134,6 +134,18 @@ u32 ddr_clktr(u32 default_val) { return (SDRAM_CLKTR_CLKP_90_DEG_ADV); } +#if defined(CONFIG_NAND_U_BOOT) +/* + * NAND booting U-Boot version uses a fixed initialization, since the whole + * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot + * code. + */ +long int initdram(int board_type) +{ + return CFG_MBYTES_SDRAM << 20; +} +#endif + #if defined(CFG_DRAM_TEST) int testdram(void) { @@ -308,14 +320,14 @@ int board_early_init_r (void) * EBC address which accepts bigger regions: * * 0xfc00.0000 -> 4.cc00.0000 - * - * For this we have to remap the CS0 and re-relocate the envrironment, - * since the original FLASH location which was needed upon startup is - * now not correct anymore. */ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000); +#else mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000); +#endif /* Remove TLB entry of boot EBC mapping */ remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20); @@ -329,6 +341,13 @@ int board_early_init_r (void) * 0xfc00.0000 is possible */ + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + return 0; } diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 5d48847..b7cac23 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -46,7 +46,12 @@ tlbtab: * use the speed up boot process. It is patched after relocation to * enable SA_I */ +#ifndef CONFIG_NAND_SPL tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ +#else + tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) +#endif /* * TLB entries for SDRAM are not needed on this platform. @@ -78,7 +83,7 @@ tlbtab: tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) /* TLB-entry for OCM */ - tlbentry(CFG_OCM_BASE, SZ_4K, 0x00040000, 4, AC_R|AC_W|AC_X) + tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) /* TLB-entry for Local Configuration registers => peripherals */ tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds new file mode 100644 index 0000000..12a5dcf --- /dev/null +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index cdfc943..8d2777d 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -403,7 +403,8 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ 2: #if defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) /* * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) */ @@ -415,6 +416,11 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ mfdcr r1,isram0_pmeg and r1,r1,r2 /* Disable pwr mgmt */ mtdcr isram0_pmeg,r1 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1,0x4000 /* BAS = 8000_0000 */ + ori r1,r1,0x4580 /* 16k */ + mtdcr isram0_sb0cr,r1 +#endif #endif #if defined(CONFIG_440EP) /* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index e244c87..b1b4709 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -114,6 +114,65 @@ #else #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#endif + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */ + /* this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) #endif /*----------------------------------------------------------------------- @@ -154,10 +213,18 @@ /*------------------------------------------------------------------------------ * DDR SDRAM *----------------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) +/* + * NAND booting U-Boot version uses a fixed initialization, since the whole + * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot + * code. + */ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ +#endif +#define CFG_MBYTES_SDRAM 256 /* 256MB */ /*----------------------------------------------------------------------- * I2C @@ -367,23 +434,29 @@ * EBC address which accepts bigger regions: * * 0xfc00.0000 -> 4.cc00.0000 - * - * For this we have to remap the CS0 and re-relocate the envrironment, - * since the original FLASH location which was needed upon startup is - * now not correct anymore. */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +/* Memory Bank 3 (NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x10055e00 +#define CFG_EBC_PB3CR (CFG_BOOT_BASE_ADDR | 0x9a000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ +#else /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x10055e00 #define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000) -/* Memory Bank 2 (CPLD) initialization */ -#define CFG_EBC_PB2AP 0x00804240 -#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */ - /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ +#endif + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x00804240 +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */ #define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */ diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile new file mode 100644 index 0000000..1ec1112 --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -0,0 +1,105 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS := start.o +SOBJS += init.o resetvec.o +SOBJS += resetvec.o +COBJS := ddr2_fixed.o +COBJS += nand_boot.o +COBJS += nand_ecc.o +COBJS += ndfc.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)ndfc.c: + @rm -f $(obj)ndfc.c + ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + +# from board directory +$(obj)init.S: + @rm -f $(obj)init.S + ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S + +# from nand_spl directory +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + +# from drivers/mtd/nand directory +$(obj)nand_ecc.c: + @rm -f $(obj)nand_ecc.c + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk new file mode 100644 index 0000000..6dad876 --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/config.mk @@ -0,0 +1,49 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 460EX Reference Platform (Canyonlands) board +# + +# +# TEXT_BASE for SPL: +# +# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff, +# in the last 4kBytes of memory space in cache. +# We will copy this SPL into internal SRAM in start.S. So we set +# TEXT_BASE to starting address in internal SRAM here. +# +TEXT_BASE = 0xE3003000 + +# PAD_TO used to generate a 16kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x4000 +PAD_TO = 0xE3007000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c new file mode 100644 index 0000000..48708a8 --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/io.h> +#include <asm/processor.h> + +static void wait_init_complete(void) +{ + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while (!(val & 0x80000000)); +} + +long int initdram(int board_type) +{ + /* + * Reset the DDR-SDRAM controller. + */ + mtsdr(SDR0_SRST, (0x80000000 >> 10)); + mtsdr(SDR0_SRST, 0x00000000); + + /* + * These values are cloned from a running NOR booting + * Canyonlands with SPD-DDR2 detection and calibration + * enabled. This will only work for the same memory + * configuration as used here: + * + * Crucial CT3264AC53E.4FD - 256MB SO-DIMM + * + */ + mtsdram(SDRAM_MCOPT2, 0x00000000); + mtsdram(SDRAM_MCOPT1, 0x05122000); + mtsdram(SDRAM_MODT0, 0x01000000); + mtsdram(SDRAM_CODT, 0x00800021); + mtsdram(SDRAM_WRDTR, 0x82000823); + mtsdram(SDRAM_CLKTR, 0x40000000); + mtsdram(SDRAM_MB0CF, 0x00000201); + mtsdram(SDRAM_RTR, 0x06180000); + mtsdram(SDRAM_SDTR1, 0x80201000); + mtsdram(SDRAM_SDTR2, 0x42103243); + mtsdram(SDRAM_SDTR3, 0x0A0D0D16); + mtsdram(SDRAM_MMODE, 0x00000632); + mtsdram(SDRAM_MEMODE, 0x00000040); + mtsdram(SDRAM_INITPLR0, 0xB5380000); + mtsdram(SDRAM_INITPLR1, 0x82100400); + mtsdram(SDRAM_INITPLR2, 0x80820000); + mtsdram(SDRAM_INITPLR3, 0x80830000); + mtsdram(SDRAM_INITPLR4, 0x80810040); + mtsdram(SDRAM_INITPLR5, 0x80800532); + mtsdram(SDRAM_INITPLR6, 0x82100400); + mtsdram(SDRAM_INITPLR7, 0x8A080000); + mtsdram(SDRAM_INITPLR8, 0x8A080000); + mtsdram(SDRAM_INITPLR9, 0x8A080000); + mtsdram(SDRAM_INITPLR10, 0x8A080000); + mtsdram(SDRAM_INITPLR11, 0x80000432); + mtsdram(SDRAM_INITPLR12, 0x808103C0); + mtsdram(SDRAM_INITPLR13, 0x80810040); + mtsdram(SDRAM_INITPLR14, 0x00000000); + mtsdram(SDRAM_INITPLR15, 0x00000000); + + mtsdram(SDRAM_MCOPT2, 0x28000000); + + wait_init_complete(); + + mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ + + mtsdram(SDRAM_RDCC, 0x40000000); + mtsdram(SDRAM_RQDC, 0x80000038); + mtsdram(SDRAM_RFDC, 0x00000257); + + return CFG_MBYTES_SDRAM << 20; +} diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds new file mode 100644 index 0000000..5bffb5b --- /dev/null +++ b/nand_spl/board/amcc/canyonlands/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc:common) +SECTIONS +{ + .resetvec 0xE3003FFC : + { + *(.resetvec) + } = 0xffff + + .text : + { + start.o (.text) + init.o (.text) + nand_boot.o (.text) + ddr2_fixed.o (.text) + ndfc.o (.text) + + *(.text) + *(.fixup) + } + _etext = .; + + .data : + { + *(.rodata*) + *(.data*) + *(.sdata*) + __got2_start = .; + *(.got2) + __got2_end = .; + } + + _edata = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) + *(.bss) + } + + _end = . ; +} |