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-rw-r--r--CHANGELOG3
-rw-r--r--cpu/ppc4xx/start.S8
-rw-r--r--include/configs/yucca.h2
3 files changed, 7 insertions, 6 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 3ec7c2e..de02125 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
+* Fix timer problems on AMCC yucca board.
+ Set Timer Clock Select to use CPU clock as a timer input source.
+
* Bring yucca config more in line with other AMCC boards.
* Add AMCC bamboo board to MAKEALL build script.
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 17d3aa3..0a6f81d 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -158,7 +158,7 @@ _start_440:
/*----------------------------------------------------------------+
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
- addi r0,r0,0x0000
+ li r0,0
mtspr esr,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
@@ -217,17 +217,15 @@ _start_440:
| g. FCOM: Normal operation
| h. MMUPEI: Record even parity. Normal operation.
| i. FFF: Flush only as much data as necessary.
- | j. TCS: Timebase increments from externally supplied clock
+ | j. TCS: Timebase increments from CPU clock.
+-----------------------------------------------------------------*/
- addis r0, r0, 0x0000
- ori r0, r0, 0x0080
+ li r0,0
mtspr ccr1, r0
/*----------------------------------------------------------------+
| Reset the timebase.
| The previous write to CCR1 sets the timebase source.
+-----------------------------------------------------------------*/
- addi r0, r0, 0x0000
mtspr tbl, r0
mtspr tbu, r0
#endif
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index ee5a448..0e58e7e 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -243,7 +243,7 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* FLASH related