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-rw-r--r--board/tqc/tqm85xx/law.c12
-rw-r--r--board/tqc/tqm85xx/sdram.c56
-rw-r--r--board/tqc/tqm85xx/tlb.c98
-rw-r--r--board/tqc/tqm85xx/tqm85xx.c330
-rw-r--r--include/configs/TQM85xx.h88
5 files changed, 293 insertions, 291 deletions
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index 224af6c..d937700 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -44,11 +44,11 @@
*/
struct law_entry law_table[] = {
- SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
- SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
- SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+ SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
-int num_law_entries = ARRAY_SIZE(law_table);
+int num_law_entries = ARRAY_SIZE (law_table);
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 788a48c..413567e 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -21,7 +21,6 @@
* MA 02111-1307 USA
*/
-
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
@@ -39,12 +38,12 @@ sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
- {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
+ {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
};
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
-int cas_latency(void);
+int cas_latency (void);
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
@@ -53,7 +52,7 @@ int cas_latency(void);
* so this should be extended for other future boards
* using this routine!
*/
-long int sdram_setup(int casl)
+long int sdram_setup (int casl)
{
int i;
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
@@ -92,17 +91,18 @@ long int sdram_setup(int casl)
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
ddr->err_disable = 0x0000000D;
- asm ("sync;isync;msync");
- udelay(1000);
+ asm ("sync; isync; msync");
+ udelay (1000);
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
asm ("sync; isync; msync");
- udelay(1000);
+ udelay (1000);
- for (i=0; i<N_DDR_CS_CONF; i++) {
+ for (i = 0; i < N_DDR_CS_CONF; i++) {
ddr->cs0_config = ddr_cs_conf[i].reg;
- if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
+ if (get_ram_size (0, ddr_cs_conf[i].size) ==
+ ddr_cs_conf[i].size) {
/*
* OK, size detected -> all done
*/
@@ -110,30 +110,30 @@ long int sdram_setup(int casl)
}
}
- return 0; /* nothing found ! */
+ return 0; /* nothing found ! */
}
-void board_add_ram_info(int use_default)
+void board_add_ram_info (int use_default)
{
int casl;
if (use_default)
casl = CONFIG_DDR_DEFAULT_CL;
else
- casl = cas_latency();
+ casl = cas_latency ();
- puts(" (CL=");
+ puts (" (CL=");
switch (casl) {
case 20:
- puts("2)");
+ puts ("2)");
break;
case 25:
- puts("2.5)");
+ puts ("2.5)");
break;
case 30:
- puts("3)");
+ puts ("3)");
break;
}
}
@@ -149,7 +149,7 @@ long int initdram (int board_type)
*/
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- int i,x;
+ int i, x;
x = 10;
@@ -157,32 +157,32 @@ long int initdram (int board_type)
* Work around to stabilize DDR DLL
*/
gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
+ asm ("sync; isync; msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
- asm("sync;isync;msync");
- for (i=0; i<x; i++)
+ asm ("sync; isync; msync");
+ for (i = 0; i < x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm("sync;isync;msync");
+ asm ("sync; isync; msync");
x++;
}
}
#endif
- casl = cas_latency();
- dram_size = sdram_setup(casl);
+ casl = cas_latency ();
+ dram_size = sdram_setup (casl);
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
/*
* Try again with default CAS latency
*/
- puts("Problem with CAS lantency");
- board_add_ram_info(1);
- puts(", using default CL!\n");
+ puts ("Problem with CAS lantency");
+ board_add_ram_info (1);
+ puts (", using default CL!\n");
casl = CONFIG_DDR_DEFAULT_CL;
- dram_size = sdram_setup(casl);
- puts(" ");
+ dram_size = sdram_setup (casl);
+ puts (" ");
}
return dram_size;
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index ad26cae..3e29062 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -28,87 +28,93 @@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
+ SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
+ CFG_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
+ CFG_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
+ CFG_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 1, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
+ CFG_FLASH_BASE + 0x4000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
+ CFG_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
+ CFG_RIO_MEM_BASE + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
/*
- * TLB 6: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
+ * TLB 6: 64M Non-cacheable, guarded
+ * 0xe0000000 1M CCSRBAR
+ * 0xe2000000 16M PCI1 IO
*/
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
- * 0x00000000 512M DDR System memory
+ * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
+ * 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
+ CFG_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
};
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+int num_tlb_entries = ARRAY_SIZE (tlb_table);
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 8fa0162..31364d3 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -42,7 +42,7 @@ void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
+void ps2mult_early_init (void);
#endif
#ifdef CONFIG_CPM2
@@ -55,149 +55,149 @@ void ps2mult_early_init(void);
const iop_conf_t iop_conf_tab[4][32] = {
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
+ /* Port A: conf, ppar, psor, pdir, podr, pdat */
+ {
+ {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
+ {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
+ {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
+ {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
+ {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
+ {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
+ {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
+ {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
+ {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
+ {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
+ {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
+ {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
+ {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
+ {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
+ {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
+ {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
+ {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
+ {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
+ {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
+ {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
+ {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
+ {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
+ {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
+ {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
+ {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
+ {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
+ {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
+ {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
+ {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
+ {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
+ {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
+ {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
+ },
+
+ /* Port B: conf, ppar, psor, pdir, podr, pdat */
+ {
+ {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
+ {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
+ {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
+ {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
+ {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
+ {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
+ {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
+ {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
+ {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
+ {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
+ {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
+ {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
+ {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
+ {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
+ {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
+ {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
+ {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
+ {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
+ {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
+ {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
+ {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
+ {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
+ {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
+ {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
+ {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
+ {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
+ {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
+ {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
+ {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
+ {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
+ {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
+ {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
+ },
+
+ /* Port C: conf, ppar, psor, pdir, podr, pdat */
+ {
+ {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
+ {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
+ {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
+ {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
+ {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
+ {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
+ {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
+ {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
+ {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
+ {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
+ {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
+ {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
+ {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
+ {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
+ {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
+ {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
+ {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
+ {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
+ {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
+ {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
+ {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
+ {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
+ {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
+ {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
+ {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
+ {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
+ {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
+ {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
+ {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
+ {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
+ {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
+ {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
+ },
+
+ /* Port D: conf, ppar, psor, pdir, podr, pdat */
+ {
+ {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
+ {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
+ {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
+ {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
+ {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
+ {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
+ {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
+ {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
+ {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
+ {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
+ {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
+ {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
+ {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
+ {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
+ {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
+ {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
+ {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
+ {0, 0, 0, 1, 0, 0}, /* PD14: LED */
+ {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
+ {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
+ {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
+ {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
+ {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
+ {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
+ {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
+ {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
+ {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
+ {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
+ {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
+ {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
+ {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
+ {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
+ }
};
#endif /* CONFIG_CPM2 */
@@ -207,9 +207,9 @@ const iop_conf_t iop_conf_tab[4][32] = {
static const int casl_table[] = { 20, 25, 30 };
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
-int cas_latency(void)
+int cas_latency (void)
{
- char *s = getenv("serial#");
+ char *s = getenv ("serial#");
int casl;
int val;
int i;
@@ -217,11 +217,11 @@ int cas_latency(void)
casl = CONFIG_DDR_DEFAULT_CL;
if (s != NULL) {
- if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
- strlen(CASL_STRING2)) == 0) {
- val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
+ if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
+ CASL_STRING2, strlen (CASL_STRING2)) == 0) {
+ val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
- for (i=0; i<N_CASL; ++i) {
+ for (i = 0; i < N_CASL; ++i) {
if (val == casl_table[i]) {
return val;
}
@@ -234,14 +234,14 @@ int cas_latency(void)
int checkboard (void)
{
- char *s = getenv("serial#");
+ char *s = getenv ("serial#");
- printf("Board: %s", CONFIG_BOARDNAME);
+ printf ("Board: %s", CONFIG_BOARDNAME);
if (s != NULL) {
- puts(", serial# ");
- puts(s);
+ puts (", serial# ");
+ puts (s);
}
- putc('\n');
+ putc ('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
@@ -272,13 +272,15 @@ int misc_init_r (void)
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
- memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
- memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
+ memctl->or0 =
+ gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
+ memctl->br0 =
+ gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
* Re-check to get correct base address
*/
- flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+ flash_get_size (gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
/*
@@ -297,7 +299,8 @@ int misc_init_r (void)
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
@@ -385,22 +388,19 @@ static struct pci_config_table pci_mpc85xxads_config_table[] = {
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
{}
};
#endif
-
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc85xxads_config_table,
+ config_table:pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
-
void pci_init_board (void)
{
#ifdef CONFIG_PCI
@@ -412,7 +412,7 @@ void pci_init_board (void)
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
- ps2mult_early_init();
+ ps2mult_early_init ();
#endif /* CONFIG_PS2MULT */
return (0);
}
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index fca5f74..f0e7318 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -50,7 +50,7 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#endif
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
@@ -102,11 +102,11 @@
/* TQM8540 & 8560 need DLL-override */
#define CONFIG_DDR_DLL /* DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
-#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
+#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
-#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
+#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */
/*
* Flash on the Local Bus
@@ -116,51 +116,51 @@
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
-#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
+#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
-#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CFG_FLASH_CFI /* flash is CFI compat. */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
-#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
-#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#if defined(CONFIG_TQM8560)
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#else /* ! TQM8560 */
+#else /* !CONFIG_TQM8560 */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@@ -173,20 +173,18 @@
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* PS/2 Keyboard */
-#if !defined(CONFIG_TQM8560)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R 1
-#endif /* !CONFIG_TQM8560 */
#endif /* CONFIG_TQM8560 */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
@@ -194,11 +192,10 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
@@ -219,7 +216,7 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
@@ -242,7 +239,7 @@
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
@@ -254,8 +251,7 @@
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-#endif /* CONFIG_PCI */
-
+#endif /* CONFIG_PCI */
#define CONFIG_NET_MULTI 1
@@ -305,7 +301,7 @@
* FCC2: a - c (X50.2 - 1)
*/
#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
+#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_TQM8560)
@@ -321,12 +317,13 @@
* FCC3: a - d (X50.2 - 3)
*/
#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
+#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
#define CONFIG_ETHER_ON_FCC1
-#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
+ CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@@ -334,7 +331,8 @@
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
#define CONFIG_ETHER_ON_FCC2
-#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
+ CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@@ -342,7 +340,8 @@
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
#define CONFIG_ETHER_ON_FCC3
-#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
+ CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@@ -353,7 +352,7 @@
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
-#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
@@ -361,8 +360,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_TIMESTAMP /* Print image info with ts */
-
+#define CONFIG_TIMESTAMP /* Print image info with ts */
/*
* BOOTP options
@@ -372,7 +370,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -389,10 +386,9 @@
#define CONFIG_CMD_MII
#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
@@ -403,12 +399,13 @@
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
+#define CFG_PBSIZE (CFG_CBSIZE + \
+ sizeof(CFG_PROMPT) + 16) /* Print Buf Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
@@ -433,7 +430,6 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
@@ -467,10 +463,10 @@
"ramdisk_addr=FE180000\0" \
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
+ "cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
generated by cgit v1.1 at 2024-11-06 00:30:45 +0000