diff options
| -rw-r--r-- | board/davinci/common/misc.c | 13 | ||||
| -rw-r--r-- | board/davinci/common/misc.h | 1 | ||||
| -rw-r--r-- | board/davinci/dvevm/dvevm.c | 2 | ||||
| -rw-r--r-- | board/davinci/schmoogie/schmoogie.c | 2 | ||||
| -rw-r--r-- | board/davinci/sffsdr/sffsdr.c | 2 | ||||
| -rw-r--r-- | board/davinci/sonata/sonata.c | 2 | ||||
| -rw-r--r-- | cpu/arm926ejs/davinci/Makefile | 2 | ||||
| -rw-r--r-- | cpu/arm926ejs/davinci/cpu.c | 131 | ||||
| -rw-r--r-- | include/asm-arm/arch-davinci/hardware.h | 5 | ||||
| -rw-r--r-- | include/configs/davinci_dvevm.h | 1 | ||||
| -rw-r--r-- | include/configs/davinci_schmoogie.h | 1 | ||||
| -rw-r--r-- | include/configs/davinci_sffsdr.h | 4 | ||||
| -rw-r--r-- | include/configs/davinci_sonata.h | 1 |
13 files changed, 138 insertions, 29 deletions
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index cfab729..ffdc20b 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -28,6 +28,7 @@ #include <net.h> #include <asm/arch/hardware.h> + DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -38,18 +39,6 @@ int dram_init(void) return(0); } -static int dv_get_pllm_output(uint32_t pllm) -{ - return (pllm + 1) * (CONFIG_SYS_HZ_CLOCK / 1000000); -} - -void dv_display_clk_infos(void) -{ - printf("ARM Clock: %dMHz\n", dv_get_pllm_output(REG(PLL1_PLLM)) / 2); - printf("DDR Clock: %dMHz\n", dv_get_pllm_output(REG(PLL2_PLLM)) / - ((REG(PLL2_DIV2) & 0x1f) + 1) / 2); -} - #ifdef CONFIG_DRIVER_TI_EMAC /* Read ethernet MAC address from EEPROM for DVEVM compatible boards. diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h index 5d29784..316159a 100644 --- a/board/davinci/common/misc.h +++ b/board/davinci/common/misc.h @@ -24,7 +24,6 @@ extern int eth_hw_init(void); -void dv_display_clk_infos(void); int dvevm_read_mac_address(uint8_t *buf); void dv_configure_mac_address(uint8_t *rom_enetaddr); diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 162a5dc..8f38633 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -69,8 +69,6 @@ int misc_init_r(void) uint8_t video_mode; uint8_t eeprom_enetaddr[6]; - dv_display_clk_infos(); - /* Read Ethernet MAC address from EEPROM if available. */ if (dvevm_read_mac_address(eeprom_enetaddr)) dv_configure_mac_address(eeprom_enetaddr); diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index d6dfef5..6e0f591 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -104,8 +104,6 @@ int misc_init_r(void) 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 }; - dv_display_clk_infos(); - /* Set serial number from UID chip */ if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) { printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR); diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index 7d855fb..7f4ee36 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -131,8 +131,6 @@ int misc_init_r(void) /* EMIF-A CS3 configuration for FPGA. */ REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; - dv_display_clk_infos(); - /* Configure I2C switch (PCA9543) to enable channel 0. */ i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0; if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0, diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index 155fb54..a0bea05 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -66,8 +66,6 @@ int misc_init_r(void) { uint8_t eeprom_enetaddr[6]; - dv_display_clk_infos(); - /* Read Ethernet MAC address from EEPROM if available. */ if (dvevm_read_mac_address(eeprom_enetaddr)) dv_configure_mac_address(eeprom_enetaddr); diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 480f19f..6eaa89c 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS-y += timer.o psc.o +COBJS-y += cpu.o timer.o psc.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c new file mode 100644 index 0000000..29aead6 --- /dev/null +++ b/cpu/arm926ejs/davinci/cpu.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2004 Texas Instruments. + * Copyright (C) 2009 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/hardware.h> + + +/* offsets from PLL controller base */ +#define PLLC_PLLCTL 0x100 +#define PLLC_PLLM 0x110 +#define PLLC_PREDIV 0x114 +#define PLLC_PLLDIV1 0x118 +#define PLLC_PLLDIV2 0x11c +#define PLLC_PLLDIV3 0x120 +#define PLLC_POSTDIV 0x128 +#define PLLC_BPDIV 0x12c +#define PLLC_PLLDIV4 0x160 +#define PLLC_PLLDIV5 0x164 +#define PLLC_PLLDIV6 0x168 +#define PLLC_PLLDIV8 0x170 +#define PLLC_PLLDIV9 0x174 + +#define BIT(x) (1 << (x)) + +/* SOC-specific pll info */ +#ifdef CONFIG_SOC_DM355 +#define ARM_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + +#ifdef CONFIG_SOC_DM644X +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DSP_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV2 +#endif + +#ifdef CONFIG_SOC_DM6447 +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DSP_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + + +#ifdef CONFIG_DISPLAY_CPUINFO + +static unsigned pll_div(volatile void *pllbase, unsigned offset) +{ + u32 div; + + div = REG(pllbase + offset); + return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; +} + +static inline unsigned pll_prediv(volatile void *pllbase) +{ +#ifdef CONFIG_SOC_DM355 + /* this register read seems to fail on pll0 */ + if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) + return 8; + else + return pll_div(pllbase, PLLC_PREDIV); +#endif + return 1; +} + +static inline unsigned pll_postdiv(volatile void *pllbase) +{ +#ifdef CONFIG_SOC_DM355 + return pll_div(pllbase, PLLC_POSTDIV); +#elif defined(CONFIG_SOC_DM6446) + if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) + return pll_div(pllbase, PLLC_POSTDIV); +#endif + return 1; +} + +static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) +{ + volatile void *pllbase = (volatile void *) pll_addr; + unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; + + /* the PLL might be bypassed */ + if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { + base /= pll_prediv(pllbase); + base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); + base /= pll_postdiv(pllbase); + } + return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); +} + +int print_cpuinfo(void) +{ + /* REVISIT fetch and display CPU ID and revision information + * too ... that will matter as more revisions appear. + */ + printf("Cores: ARM %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); + +#ifdef DSP_PLLDIV + printf(", DSP %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); +#endif + + printf("\nDDR: %d MHz\n", + /* DDR PHY uses an x2 input clock */ + pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) + / 2); + return 0; +} + +#endif + diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index a28cfb4..99324e4 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -175,11 +175,6 @@ void davinci_errata_workarounds(void); #define PSC_SILVER_BULLET (0x01c41a20) -/* Some PLL defines */ -#define PLL1_PLLM (0x01c40910) -#define PLL2_PLLM (0x01c40d10) -#define PLL2_DIV2 (0x01c40d1c) - /* Miscellania... */ #define VBPR (0x20000020) diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 9be10f7..e936ba8 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -52,6 +52,7 @@ #define DV_EVM #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR +#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index d5e77f8..6612cb3 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -27,6 +27,7 @@ #define SCHMOOGIE #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND +#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 4be5b7e..6c1dc11 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -28,8 +28,8 @@ #define SFFSDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_USE_DSPLINK /* This is to prevent U-Boot from - * powering ON the DSP. */ +#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ +#define CONFIG_DISPLAY_CPUINFO /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index a6bf825..893729c 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -52,6 +52,7 @@ #define SONATA_BOARD #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR +#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ |