diff options
| -rw-r--r-- | board/freescale/mpc8536ds/mpc8536ds.c | 42 | ||||
| -rw-r--r-- | include/configs/MPC8536DS.h | 3 |
2 files changed, 45 insertions, 0 deletions
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 5b252d1..ce77bb9 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -35,8 +35,11 @@ #include <libfdt.h> #include <spd_sdram.h> #include <fdt_support.h> +#include <tsec.h> +#include <netdev.h> #include "../common/pixis.h" +#include "../common/sgmii_riser.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -618,6 +621,45 @@ int is_sata_supported(void) return 1; } +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_TSEC_ENET + struct tsec_info_struct tsec_info[2]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + uint sdrs2_io_sel = + (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { + tsec_info[num].phyaddr = 0; + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (sdrs2_io_sel == 4) { + tsec_info[num].phyaddr = 1; + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) + fsl_sgmii_riser_init(tsec_info, num); + + tsec_eth_init(bis, tsec_info, num); +#endif + return pci_eth_init(bis); +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 29ab2c4..38be10d 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -427,6 +427,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1c + #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ |