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-rw-r--r--board/cds/common/ft_board.c30
-rw-r--r--board/cds/mpc8548cds/mpc8548cds.c32
-rw-r--r--drivers/tsec.c73
-rw-r--r--drivers/tsec.h17
-rw-r--r--include/configs/MPC8540ADS.h10
-rw-r--r--include/configs/MPC8541CDS.h9
-rw-r--r--include/configs/MPC8548CDS.h17
-rw-r--r--include/configs/MPC8555CDS.h9
8 files changed, 168 insertions, 29 deletions
diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c
index 77d1d85..a897d04 100644
--- a/board/cds/common/ft_board.c
+++ b/board/cds/common/ft_board.c
@@ -24,9 +24,35 @@
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
+#include "cadmus.h"
+
extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
+static void cds_pci_fixup(void *blob)
+{
+ int len;
+ u32 *map;
+ int slot;
+ int i;
+
+ map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
+
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ int j;
+
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+
+ map+=7;
+ }
+}
+#endif
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
@@ -45,5 +71,7 @@ ft_board_setup(void *blob, bd_t *bd)
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+
+ cds_pci_fixup(blob);
}
#endif
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index 6eedb4a..66219e3 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -27,6 +27,7 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
+#include <miiphy.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
@@ -327,3 +328,34 @@ pci_init_board(void)
pci_mpc85xx_init(&hose);
#endif
}
+
+int last_stage_init(void)
+{
+ unsigned int temp;
+
+ /* Change the resistors for the PHY */
+ /* This is needed to get the RGMII working for the 1.3+
+ * CDS cards */
+ if (get_board_version() == 0x13) {
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 18);
+
+ miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, &temp);
+
+ temp = (temp & 0xf03f);
+ temp |= 2 << 9; /* 36 ohm */
+ temp |= 2 << 6; /* 39 ohm */
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, temp);
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 3);
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, 0x8000);
+ }
+
+ return 0;
+}
diff --git a/drivers/tsec.c b/drivers/tsec.c
index a8a2ba2..0fb3ca2 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -45,9 +45,7 @@ struct tsec_info_struct {
/* The tsec_info structure contains 3 values which the
* driver uses to determine how to operate a given ethernet
- * device. For now, the structure is initialized with the
- * knowledge that all current implementations have 2 TSEC
- * devices, and one FEC. The information needed is:
+ * device. The information needed is:
* phyaddr - The address of the PHY which is attached to
* the given device.
*
@@ -57,18 +55,16 @@ struct tsec_info_struct {
*
* phyregidx - This variable specifies which ethernet device
* controls the MII Management registers which are connected
- * to the PHY. For 8540/8560, only TSEC1 (index 0) has
+ * to the PHY. For now, only TSEC1 (index 0) has
* access to the PHYs, so all of the entries have "0".
*
* The values specified in the table are taken from the board's
* config file in include/configs/. When implementing a new
* board with ethernet capability, it is necessary to define:
- * TSEC1_PHY_ADDR
- * TSEC1_PHYIDX
- * TSEC2_PHY_ADDR
- * TSEC2_PHYIDX
+ * TSECn_PHY_ADDR
+ * TSECn_PHYIDX
*
- * and for 8560:
+ * for n = 1,2,3, etc. And for FEC:
* FEC_PHY_ADDR
* FEC_PHYIDX
*/
@@ -95,10 +91,8 @@ static struct tsec_info_struct tsec_info[] = {
#else
{ 0, 0, 0},
#endif
-#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
- {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
-#elif defined(CONFIG_MPC86XX_TSEC4)
- {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
+ {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
#else
{ 0, 0, 0},
#endif
@@ -838,6 +832,58 @@ struct phy_info phy_info_M88E1111S = {
},
};
+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
+{
+ unsigned int temp;
+ uint mii_data = read_phy_reg(priv, mii_reg);
+
+
+ /* Setting MIIM_88E1145_PHY_EXT_CR */
+ if (priv->flags & TSEC_REDUCED)
+ return mii_data |
+ MIIM_M88E1145_RGMII_RX_DELAY |
+ MIIM_M88E1145_RGMII_TX_DELAY;
+ else
+ return mii_data;
+}
+
+static struct phy_info phy_info_M88E1145 = {
+ 0x01410cd,
+ "Marvell 88E1145",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ /* Errata E0, E1 */
+ {29, 0x001b, NULL},
+ {30, 0x418f, NULL},
+ {29, 0x0016, NULL},
+ {30, 0xa2da, NULL},
+
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
+ {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
+ /* Read the Status */
+ {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
+
+
struct phy_info phy_info_cis8204 = {
0x3f11,
"Cicada Cis8204",
@@ -1055,6 +1101,7 @@ struct phy_info *phy_info[] = {
&phy_info_cis8204,
&phy_info_M88E1011S,
&phy_info_M88E1111S,
+ &phy_info_M88E1145,
&phy_info_dm9161,
&phy_info_lxt971,
&phy_info_VSC8244,
diff --git a/drivers/tsec.h b/drivers/tsec.h
index 31f1867..4aa331c 100644
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -160,6 +160,23 @@
#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1011_PHYSTAT_LINK 0x0400
+#define MIIM_88E1011_PHY_SCR 0x10
+#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL 24
+#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
+
+#define MIIM_88E1145_PHY_PAGE 29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+
/* DM9161 Control register values */
#define MIIM_DM9161_CR_STOP 0x0400
#define MIIM_DM9161_CR_RSTAN 0x1200
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 8e4d2c9..31ffbaf 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -517,8 +517,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -526,13 +528,15 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index f73caf0..2b87f1b 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 37b518c..03ab976 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
+#define CONFIG_MPC85XX_TSEC4 1
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
@@ -389,13 +389,11 @@ extern unsigned long get_clock_freq(void);
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC4_PHY_ADDR 3
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
-#define FEC_PHYIDX 0
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
@@ -483,6 +481,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
@@ -505,8 +505,11 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
+
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -514,7 +517,9 @@ extern unsigned long get_clock_freq(void);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index b94e38a..771a9d3 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
generated by cgit v1.1 at 2024-11-28 00:15:15 +0000