diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | board/freescale/mx50_rdp/mx50_rdp.c | 70 | ||||
| -rw-r--r-- | include/configs/mx50_rd3.h | 293 | ||||
| -rw-r--r-- | include/configs/mx50_rd3_mfg.h | 240 |
4 files changed, 595 insertions, 10 deletions
@@ -3254,6 +3254,8 @@ mx50_arm2_iram_config \ mx50_arm2_config \ mx50_arm2_mfg_config \ mx50_rdp_iram_config \ +mx50_rd3_config \ +mx50_rd3_mfg_config \ mx50_rdp_mfg_config \ mx50_rdp_android_config \ mx50_rdp_config : unconfig diff --git a/board/freescale/mx50_rdp/mx50_rdp.c b/board/freescale/mx50_rdp/mx50_rdp.c index 6450373..554bdae 100644 --- a/board/freescale/mx50_rdp/mx50_rdp.c +++ b/board/freescale/mx50_rdp/mx50_rdp.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> * - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -129,11 +129,29 @@ static inline void setup_soc_rev(void) } } -static inline void setup_board_rev(int rev) +static inline void set_board_rev(int rev) { system_rev |= (rev & 0xF) << 8; } +static inline void setup_board_rev(void) +{ +#if defined(CONFIG_MX50_RD3) + set_board_rev(0x3); +#endif +} + +static inline void setup_arch_id(void) +{ +#if defined(CONFIG_MX50_RDP) || defined(CONFIG_MX50_RD3) + gd->bd->bi_arch_number = MACH_TYPE_MX50_RDP; +#elif defined(CONFIG_MX50_ARM2) + gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2; +#else +# error "Unsupported board!" +#endif +} + inline int is_soc_rev(int rev) { return (system_rev & 0xFF) - rev; @@ -214,7 +232,21 @@ int dram_init(void) static void setup_uart(void) { + unsigned int reg; + +#if defined(CONFIG_MX50_RD3) + /* UART3 TXD */ + mxc_request_iomux(MX50_PIN_UART3_TXD, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX50_PIN_UART3_TXD, 0x1E4); + /* Enable UART1 */ + reg = readl(GPIO6_BASE_ADDR + 0x0); + reg |= (1 << 14); + writel(reg, GPIO6_BASE_ADDR + 0x0); + reg = readl(GPIO6_BASE_ADDR + 0x4); + reg |= (1 << 14); + writel(reg, GPIO6_BASE_ADDR + 0x4); +#endif /* UART1 RXD */ mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4); @@ -599,6 +631,18 @@ static void setup_fec(void) reg = readl(GPIO6_BASE_ADDR + 0x4); reg |= (1 << 23); writel(reg, GPIO6_BASE_ADDR + 0x4); + +#elif defined(CONFIG_MX50_RD3) + /* FEC_EN: gpio4-15 set to 0 to enable FEC */ + mxc_request_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT1); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= (1 << 15); + writel(reg, GPIO4_BASE_ADDR + 0x0); + + reg = readl(GPIO4_BASE_ADDR + 0x4); + reg |= (1 << 15); + writel(reg, GPIO4_BASE_ADDR + 0x4); #endif /*FEC_MDIO*/ @@ -647,7 +691,7 @@ static void setup_fec(void) mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0); mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0); -#if defined(CONFIG_MX50_RDP) +#if defined(CONFIG_MX50_RDP) || defined(CONFIG_MX50_RD3) /* FEC_RESET_B: gpio4-12 */ mxc_request_iomux(MX50_PIN_ECSPI1_SCLK, IOMUX_CONFIG_ALT1); @@ -1065,6 +1109,12 @@ static void setup_power(void) /* Enable VGEN1 to enable ethernet */ slave = spi_pmic_probe(); +#if defined(CONFIG_MX50_RD3) + /* Set global reset time to 0s*/ + val = pmic_reg(slave, 15, 0, 0); + val &= ~(0x300); + pmic_reg(slave, 15, val, 1); +#else val = pmic_reg(slave, 30, 0, 0); val |= 0x3; pmic_reg(slave, 30, val, 1); @@ -1077,6 +1127,7 @@ static void setup_power(void) val = pmic_reg(slave, 33, 0, 0); val |= 0x40; pmic_reg(slave, 33, val, 1); +#endif spi_pmic_free(slave); } @@ -1109,14 +1160,11 @@ int board_init(void) /* soc rev */ setup_soc_rev(); + /* board rev */ + setup_board_rev(); + /* arch id for linux */ -#if defined(CONFIG_MX50_RDP) - gd->bd->bi_arch_number = MACH_TYPE_MX50_RDP; -#elif defined(CONFIG_MX50_ARM2) - gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2; -#else -# error "Unsupported board!" -#endif + setup_arch_id(); /* boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -1152,6 +1200,8 @@ int checkboard(void) { #if defined(CONFIG_MX50_RDP) printf("Board: MX50 RDP board\n"); +#elif defined(CONFIG_MX50_RD3) + printf("Board: MX50 RD3 board\n"); #elif defined(CONFIG_MX50_ARM2) printf("Board: MX50 ARM2 board\n"); #else diff --git a/include/configs/mx50_rd3.h b/include/configs/mx50_rd3.h new file mode 100644 index 0000000..62c0b97 --- /dev/null +++ b/include/configs/mx50_rd3.h @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX50-RDP Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx50.h> + + /* High Level Configuration Options */ +#define CONFIG_MXC +#define CONFIG_MX50 +#define CONFIG_MX50_RD3 +#define CONFIG_LPDDR2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU +*/ + +#define CONFIG_MX50_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +/*#define CONFIG_CMD */ +#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX50_RD3 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * DDR ZQ calibration + */ +#define CONFIG_ZQ_CALIB + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 + +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0xfe +#endif + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_M25PXX 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_CSPI +#define IMX_CSPI_VER_0_7 1 +#define MAX_SPI_BYTES (8 * 4) +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 3 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS + #define CONFIG_EMMC_DDR_MODE + + /* Indicate to esdhc driver which ports support 8-bit data */ + #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */ +#endif + +/* + * GPMI Nand Configs + */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#endif + +/* + * APBH DMA Configs + */ +#define CONFIG_APBH_DMA + +#ifdef CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx50_rd3_mfg.h b/include/configs/mx50_rd3_mfg.h new file mode 100644 index 0000000..4c13fc9 --- /dev/null +++ b/include/configs/mx50_rd3_mfg.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX50-RDP Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx50.h> + + /* High Level Configuration Options */ +#define CONFIG_MFG +#define CONFIG_MXC +#define CONFIG_MX50 +#define CONFIG_MX50_RD3 +#define CONFIG_LPDDR2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX50_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +/* #define CONFIG_CMD_MMC */ +/* #define CONFIG_CMD_ENV */ + +/*#define CONFIG_CMD */ +#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\ + "rdinit=/linuxrc" +#define CONFIG_BOOTCOMMAND "bootm 0x70800000 0x70B00000" +#define CONFIG_ENV_IS_EMBEDDED +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX50_RD3 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_M25PXX 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_CSPI +#define IMX_CSPI_VER_0_7 1 +#define MAX_SPI_BYTES (8 * 4) +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 3 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1 or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS + +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_MMC */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ |