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-rwxr-xr-xMAKEALL1
-rw-r--r--Makefile3
-rw-r--r--board/amcc/canyonlands/canyonlands.c140
-rw-r--r--board/amcc/canyonlands/init.S17
-rw-r--r--include/configs/amcc-common.h17
-rw-r--r--include/configs/canyonlands.h222
-rw-r--r--include/ppc440.h3
7 files changed, 384 insertions, 19 deletions
diff --git a/MAKEALL b/MAKEALL
index 9ccb9ac..847c1fa 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -161,6 +161,7 @@ LIST_4xx=" \
alpr \
AP1000 \
AR405 \
+ arches \
ASH405 \
bamboo \
bamboo_nand \
diff --git a/Makefile b/Makefile
index 9a132f7..e831061 100644
--- a/Makefile
+++ b/Makefile
@@ -1208,7 +1208,8 @@ bubinga_config: unconfig
CANBT_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
-# Canyonlands & Glacier use different U-Boot images
+# Arches, Canyonlands & Glacier use different U-Boot images
+arches_config \
canyonlands_config \
glacier_config: unconfig
@mkdir -p $(obj)include
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index e9186f8..2b74689 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -38,11 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
#define BOARD_GLACIER 3
+#define BOARD_ARCHES 4
+
+#if defined(CONFIG_ARCHES)
+/*
+ * FPGA read/write helper macros
+ */
+static inline int board_fpga_read(int offset)
+{
+ int data;
+
+ data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
+
+ return data;
+}
+
+static inline void board_fpga_write(int offset, int data)
+{
+ out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
+}
+
+/*
+ * CPLD read/write helper macros
+ */
+static inline int board_cpld_read(int offset)
+{
+ int data;
+
+ out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+ data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
+
+ return data;
+}
+
+static inline void board_cpld_write(int offset, int data)
+{
+ out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+ out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
+}
+#endif /* defined(CONFIG_ARCHES) */
int board_early_init_f(void)
{
+#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
u32 pvr = get_pvr();
+#endif
/*
* Setup the interrupt controller polarities, triggers, etc.
@@ -79,6 +120,7 @@ int board_early_init_f(void)
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
+#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
@@ -88,6 +130,7 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_BAC_ENCODE(3) |
(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
+#endif
/*
* Configure PFC (Pin Function Control) registers
@@ -98,6 +141,7 @@ int board_early_init_f(void)
/* Enable PCI host functionality in SDR0_PCI0 */
mtsdr(SDR0_PCI0, 0xe0000000);
+#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
@@ -123,10 +167,12 @@ int board_early_init_f(void)
gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
}
+#endif
return 0;
}
+#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
u32 reg;
@@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type)
SDR_WRITE(SDR0_SRST1, 0x00000000);
}
}
+#endif /* !defined(CONFIG_ARCHES) */
+
+int get_cpu_num(void)
+{
+ int cpu = NA_OR_UNKNOWN_CPU;
+
+#if defined(CONFIG_ARCHES)
+ int cpu_num;
+
+ cpu_num = board_fpga_read(0x3);
+
+ /* sanity check; assume cpu numbering starts and increments from 0 */
+ if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
+ cpu = cpu_num;
+#endif
+
+ return cpu;
+}
+#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
char *s = getenv("serial#");
@@ -188,6 +253,39 @@ int checkboard(void)
return (0);
}
+#else /* defined(CONFIG_ARCHES) */
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
+ printf(" Revision %02x.%02x ",
+ board_fpga_read(0x0), board_fpga_read(0x1));
+
+ gd->board_type = BOARD_ARCHES;
+
+ /* Only CPU0 has access to CPLD registers */
+ if (get_cpu_num() == 0) {
+ u8 cfg_sw = board_cpld_read(0x1);
+ printf("(FPGA=%02x, CPLD=%02x)\n",
+ board_fpga_read(0x2), board_cpld_read(0x0));
+ printf(" Configuration Switch %d%d%d%d\n",
+ ((cfg_sw >> 3) & 0x01),
+ ((cfg_sw >> 2) & 0x01),
+ ((cfg_sw >> 1) & 0x01),
+ ((cfg_sw >> 0) & 0x01));
+ } else
+ printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
+
+
+ if (s != NULL)
+ printf(" Serial# %s\n", s);
+
+ return 0;
+}
+#endif /* !defined(CONFIG_ARCHES) */
+
/*
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
@@ -389,6 +487,7 @@ int board_early_init_r (void)
return 0;
}
+#if !defined(CONFIG_ARCHES)
int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
@@ -434,6 +533,47 @@ int misc_init_r(void)
return 0;
}
+#else /* defined(CONFIG_ARCHES) */
+
+int misc_init_r(void)
+{
+ u32 eth_cfg = 0;
+ u32 eth_pll;
+ u32 reg;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+
+ /* enable SGMII mode */
+ eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII2_ENABLE);
+
+ /* Set EMAC for MDIO */
+ eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
+
+ /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
+ eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /* reset all SGMII interfaces */
+ mfsdr(SDR0_SRST1, reg);
+ reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
+ mtsdr(SDR0_SRST1, reg);
+ mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
+ mtsdr(SDR0_SRST1, 0x00000000);
+
+ do {
+ mfsdr(SDR0_ETH_PLL, eth_pll);
+ } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
+
+ return 0;
+}
+#endif /* !defined(CONFIG_ARCHES) */
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 179dd32..694cc89 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -77,11 +77,16 @@ tlbtab:
/* PCIe UTL register */
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+#if !defined(CONFIG_ARCHES)
/* TLB-entry for NAND */
tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry for CPLD */
tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+#else
+ /* TLB-entry for FPGA */
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+#endif
/* TLB-entry for OCM */
tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
@@ -92,6 +97,18 @@ tlbtab:
/* AHB: Internal USB Peripherals (USB, SATA) */
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+#if defined(CONFIG_RAPIDIO)
+ /* TLB-entries for RapidIO (SRIO) */
+ tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
+ 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
+ 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
+ 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
+ 0x4, AC_R|AC_W|SA_G|SA_I)
+#endif
+
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index fba96e1..8516571 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -160,6 +160,13 @@
#endif
/*
+ * Only very few boards have default netdev not set to eth0 (like Arches)
+ */
+#if !defined(CONFIG_USE_NETDEV)
+#define CONFIG_USE_NETDEV eth0
+#endif
+
+/*
* Only some 4xx PPC's are equipped with an FPU
*/
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
@@ -184,7 +191,7 @@
* General common environment variables shared on all AMCC eval boards
*/
#define CONFIG_AMCC_DEF_ENV \
- "netdev=eth0\0" \
+ "netdev=" xstr(CONFIG_USE_NETDEV) "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -197,8 +204,10 @@
"initrd_high=30000000\0" \
"kernel_addr_r=400000\0" \
"fdt_addr_r=800000\0" \
+ "ramdisk_addr_r=C00000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
CONFIG_AMCC_DEF_ENV_ROOTPATH
/*
@@ -214,6 +223,12 @@
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdt_file};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=run net_self_load;" \
+ "run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
/*
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 771ee69..ec08ba7 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -27,14 +27,24 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
-#ifndef CONFIG_CANYONLANDS
+/*
+ * This config file is used for Canyonlands (460EX) Glacier (460GT)
+ * and Arches dual (460GT)
+ */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_460EX 1 /* Specific PPC460EX */
+#define CONFIG_HOSTNAME canyonlands
+#else
#define CONFIG_460GT 1 /* Specific PPC460GT */
+#ifdef CONFIG_GLACIER
#define CONFIG_HOSTNAME glacier
#else
-#define CONFIG_460EX 1 /* Specific PPC460EX */
-#define CONFIG_HOSTNAME canyonlands
+#define CONFIG_HOSTNAME arches
+#define CONFIG_USE_NETDEV eth1
+#define CONFIG_BD_NUM_CPUS 2
#endif
+#endif
+
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
@@ -73,15 +83,24 @@
#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
/* EBC stuff */
-#define CONFIG_SYS_NAND_ADDR 0xE0000000
+#if !defined(CONFIG_ARCHES)
#define CONFIG_SYS_BCSR_BASE 0xE1000000
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
+#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
+#define CONFIG_SYS_FLASH_SIZE (64 << 20)
+#else
+#define CONFIG_SYS_FPGA_BASE 0xE1000000
+#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
+#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
+#define CONFIG_SYS_FLASH_SIZE (32 << 20)
+#endif
+
+#define CONFIG_SYS_NAND_ADDR 0xE0000000
+#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
- (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-#define CONFIG_SYS_FLASH_SIZE (64 << 20)
+#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
+ (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 16k */
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
@@ -223,6 +242,7 @@
* DDR SDRAM
*----------------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT)
+#if !defined(CONFIG_ARCHES)
/*
* NAND booting U-Boot version uses a fixed initialization, since the whole
* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
@@ -232,7 +252,70 @@
#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
#define CONFIG_DDR_ECC 1 /* with ECC support */
#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
-#endif
+
+#else /* defined(CONFIG_ARCHES) */
+
+#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
+#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
+#define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
+#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
+
+/* SDRAM Controller */
+#define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
+#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
+#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0 0x01000000
+#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
+#define CONFIG_SYS_SDRAM0_CODT 0x00800021
+#define CONFIG_SYS_SDRAM0_RTR 0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
+#define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
+#define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
+#define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
+#define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
+#define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
+#define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
+#define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
+#define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
+#define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
+#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
+#define CONFIG_SYS_SDRAM0_DLCR 0x03000091
+#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
+#define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
+#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
+#define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
+#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
+#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
+#endif /* !defined(CONFIG_ARCHES) */
+#endif /* !defined(CONFIG_NAND_U_BOOT) */
+
#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
/*-----------------------------------------------------------------------
@@ -254,18 +337,27 @@
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
+#if defined(CONFIG_ARCHES)
+#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
+#endif
+
+#if !defined(CONFIG_ARCHES)
/* RTC configuration */
#define CONFIG_RTC_M41T62 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#endif
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 1
+
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
+
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 1
/* Only Glacier (460GT) has 4 EMAC interfaces */
#ifdef CONFIG_460GT
#define CONFIG_PHY2_ADDR 2
@@ -274,6 +366,30 @@
#define CONFIG_HAS_ETH3
#endif
+#else /* defined(CONFIG_ARCHES) */
+
+#define CONFIG_FIXED_PHY 0xFFFFFFFF
+#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
+#define CONFIG_PHY1_ADDR 0
+#define CONFIG_PHY2_ADDR 1
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+ {devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+ CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
+
+#define CONFIG_M88E1112_PHY
+
+/*
+ * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
+ * used by CONFIG_PHYx_ADDR
+ */
+#define CONFIG_GPCS_PHY_ADDR 0xA
+#define CONFIG_GPCS_PHY1_ADDR 0xB
+#define CONFIG_GPCS_PHY2_ADDR 0xC
+#endif /* !defined(CONFIG_ARCHES) */
+
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_DYNAMIC_ANEG 1
@@ -296,7 +412,8 @@
/*
* Default environment variables
*/
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
@@ -307,20 +424,46 @@
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
""
+#else /* defined(CONFIG_ARCHES) */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fe000000\0" \
+ "fdt_addr=fe1e0000\0" \
+ "ramdisk_addr=fe200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ "ethprime=ppc_4xx_eth1\0" \
+ ""
+#endif /* !defined(CONFIG_ARCHES) */
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#if defined(CONFIG_ARCHES)
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#elif defined(CONFIG_CANYONLANDS)
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
-#ifdef CONFIG_460EX
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
+#elif defined(CONFIG_GLACIER)
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#else
+#error "board type not defined"
#endif
/* Partitions */
@@ -344,6 +487,36 @@
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#ifdef CONFIG_460GT
+#if defined(CONFIG_ARCHES)
+/*-----------------------------------------------------------------------
+ * RapidIO I/O and Registers
+ *----------------------------------------------------------------------*/
+#define CONFIG_RAPIDIO
+#define CONFIG_SYS_460GT_SRIO_ERRATA_1
+
+#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
+#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
+#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
+#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
+#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
+
+#define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
+#define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
+#define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
+#define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
+
+#define CONFIG_SYS_I2ODMA_BASE 0xCF000000
+#define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
+
+#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
+#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
+#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
+#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
+#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
+#endif /* CONFIG_ARCHES */
+#endif /* CONFIG_460GT */
+
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
@@ -356,6 +529,11 @@
* EBC address which accepts bigger regions:
*
* 0xfc00.0000 -> 4.cc00.0000
+ *
+ * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
+ * remapped to:
+ *
+ * 0xfe00.0000 -> 4.ce00.0000
*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
@@ -371,15 +549,25 @@
#define CONFIG_SYS_EBC_PB0AP 0x10055e00
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
+#if !defined(CONFIG_ARCHES)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x018003c0
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
#endif
+#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+#if !defined(CONFIG_ARCHES)
/* Memory Bank 2 (CPLD) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x00804240
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
+#else /* defined(CONFIG_ARCHES) */
+
+/* Memory Bank 1 (FPGA) initialization */
+#define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
+#endif /* !defined(CONFIG_ARCHES) */
+
#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
/*
diff --git a/include/ppc440.h b/include/ppc440.h
index 664f802..ea0ac86 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1349,6 +1349,9 @@
#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
+/* Ethernet Status Register */
+#define SDR0_ETH_STS 0x4104
+
/* Miscealleneaous Function Reg. (SDR0_MFR) */
#define SDR0_MFR 0x4300
#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
generated by cgit v1.1 at 2024-11-25 21:40:20 +0000