diff options
| -rw-r--r-- | CHANGELOG | 7 | ||||
| -rw-r--r-- | MAINTAINERS | 6 | ||||
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | board/dave/PPChameleonEVB/PPChameleonEVB.c | 8 | ||||
| -rw-r--r-- | board/mpc8540ads/init.S | 46 | ||||
| -rw-r--r-- | board/mpc8540ads/mpc8540ads.c | 247 | ||||
| -rw-r--r-- | board/mpc8560ads/init.S | 46 | ||||
| -rw-r--r-- | board/mpc8560ads/mpc8560ads.c | 241 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 10 | ||||
| -rw-r--r-- | cpu/mpc85xx/pci.c | 126 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 46 | ||||
| -rw-r--r-- | doc/README.mpc85xxads | 106 | ||||
| -rw-r--r-- | include/asm-ppc/mmu.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 41 | ||||
| -rw-r--r-- | include/common.h | 4 | ||||
| -rw-r--r-- | include/configs/MPC8540ADS.h | 491 | ||||
| -rw-r--r-- | include/configs/MPC8560ADS.h | 533 | ||||
| -rw-r--r-- | include/mpc85xx.h | 24 | ||||
| -rw-r--r-- | lib_ppc/board.c | 8 | ||||
| -rw-r--r-- | net/eth.c | 12 |
20 files changed, 1260 insertions, 750 deletions
@@ -2,6 +2,13 @@ Changes since U-Boot 1.1.1: ====================================================================== +* Patch by Jon Loeliger, 17 June 2004: + Completion of the 8540ADS/8560ADS updates: + Fix some PCI and Rapid I/O memory maps, + Initialize both TSEC 1 and 2, + Initialize SDRAM + Update MAINTAINER for 85xx boards and README.mpc85xxads + * Patch by Yuli Barcohen, 16 Jun 2004: Remove obsolete AdderII port which was superseded by unified AdderII/Adder87x port diff --git a/MAINTAINERS b/MAINTAINERS index e96697d..6ffdead 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -184,7 +184,7 @@ Eran Man <eran@nbase.co.il> Andrea "llandre" Marson <andrea.marson@dave-tech.it> PPChameleonEVB PPC405EP - + Reinhard Meyer <r.meyer@emk-elektronik.de> TOP860 MPC860T @@ -270,7 +270,7 @@ John Zhan <zhanz@sinovee.com> svm_sc8xx MPC8xx -Xianghua Xiao <x.xiao@motorola.com> +Jon Loeliger <jdl@freescale.com> MPC8540ADS MPC8540 MPC8560ADS MPC8560 @@ -376,7 +376,7 @@ Robert Schwebel <r.schwebel@pengutronix.de> Andrea Scian <andrea.scian@dave-tech.it> B2 ARM7TDMI (S3C44B0X) - + Alex Züpke <azu@sysgo.de> lart SA1100 @@ -1001,13 +1001,13 @@ M5282EVB_config : unconfig ## MPC85xx Systems ######################################################################### -MPC8540ADS_config: unconfig +MPC8540ADS_config: unconfig @./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads -MPC8560ADS_config: unconfig +MPC8560ADS_config: unconfig @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads -stxgp3_config: unconfig +stxgp3_config: unconfig @./mkconfig $(@:_config=) ppc mpc85xx stxgp3 ######################################################################### diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 2b12f97..ffa53f8 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -29,15 +29,11 @@ #include <command.h> #include <malloc.h> - /* ------------------------------------------------------------------------- */ - - /* Prototypes */ int gunzip(void *, int, unsigned char *, int *); - int board_early_init_f (void) { out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */ @@ -71,11 +67,9 @@ int board_early_init_f (void) #else mtebc (epcr, 0x28400000); /* ebc in high-z */ #endif - return 0; } - /* ------------------------------------------------------------------------- */ int misc_init_f (void) @@ -168,7 +162,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ - #endif #if 0 @@ -186,7 +179,6 @@ int misc_init_r (void) return (0); } - /* * Check Board Identity: */ diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S index 486fdc8..99c4d79 100644 --- a/board/mpc8540ads/init.S +++ b/board/mpc8540ads/init.S @@ -45,7 +45,8 @@ tlb1_entry: entry_start - .long 0x0a /* the following data table uses a few of 16 TLB entries */ + /* Number of entries in the following table */ + .long 0x0c .long TLB1_MAS0(1,1,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) @@ -116,40 +117,57 @@ tlb1_entry: .long TLB1_MAS0(1,8,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(1,9,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * RapidIO MMU for 512M + * Two entries, 10 and 11 + */ + .long TLB1_MAS0(1,10,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,11,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .long TLB1_MAS0(1,15,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #else +#else .long TLB1_MAS0(1,15,0) .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif +#endif entry_end /* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI IO 16M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M * - * Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. */ #if !defined(CONFIG_SPD_EEPROM) @@ -160,7 +178,7 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #endif -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* @@ -174,14 +192,14 @@ tlb1_entry: #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #endif -#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff) +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) /* * Rapid IO at 0xc000_0000 for 512 M */ -#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) .section .bootpg, "ax" diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 2694d62..a994d16 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002,2003, Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -24,75 +25,69 @@ */ -extern long int spd_sdram (void); - #include <common.h> #include <asm/processor.h> #include <asm/immap_85xx.h> #include <spd.h> -long int fixed_sdram (void); - #if defined(CONFIG_DDR_ECC) -void dma_init(void); -uint dma_check(void); -int dma_xfer(void *dest, uint count, void *src); +extern void ddr_enable_ecc(unsigned int dram_size); #endif +extern long int spd_sdram(void); + +void sdram_init(void); +long int fixed_sdram(void); -/* MPC8540ADS Board Status & Control Registers */ -#if 0 -typedef struct bscr_ { - unsigned long bcsr0; - unsigned long bcsr1; - unsigned long bcsr2; - unsigned long bcsr3; - unsigned long bcsr4; - unsigned long bcsr5; - unsigned long bcsr6; - unsigned long bcsr7; -} bcsr_t; -#endif int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; - pci->peer &= 0xffffffdf; /* disable master abort */ + pci->peer &= 0xffffffdf; /* disable master abort */ #endif + return 0; } int checkboard (void) { puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + return 0; } -long int initdram (int board_type) +long int +initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); volatile immap_t *immap = (immap_t *)CFG_IMMR; -#if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; + puts("Initializing\n"); - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } #endif #if defined(CONFIG_SPD_EEPROM) @@ -101,98 +96,120 @@ long int initdram (int board_type) dram_size = fixed_sdram (); #endif -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; +#if defined(CONFIG_DDR_ECC) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init (void) +{ +#if !defined(CONFIG_RAM_AS_FLASH) + sys_info_t sysinfo; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + + puts (" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * LocalBus SDRAM is not emulating flash. + */ + + /* + * Fix Local Bus clock glitch. Errata LBC11. + * + * If localbus freq is less than 66Mhz, use bypass mode, + * otherwise use DLL. + * lcrr is the local-bus clock ratio register. + */ + get_sys_info (&sysinfo); + if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000; + } else { - uint pvr = get_pvr(); + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + volatile ccsr_gur_t *gur = &immap->im_gur; + uint pvr = get_pvr (); + uint temp_lbcdll = 0; if (pvr == PVR_85xx_REV1) { - /* - * Need change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 - * temporarily. - */ - lbc->lcrr = 0x10000004; + lbc->lcrr = 0x10000004; } + + /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; - udelay(200); + udelay (200); temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000; + asm ("sync;isync;msync"); } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; lbc->br2 = CFG_BR2_PRELIM; lbc->lbcr = CFG_LBC_LBCR; + asm ("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm ("sync"); + + /* + * Configure the SDRAM controller. + */ lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); + lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); + lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); -#endif + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } #endif - - return dram_size; } @@ -262,6 +279,6 @@ long int fixed_sdram (void) asm("sync; isync; msync"); udelay(500); #endif - return (CFG_SDRAM_SIZE * 1024 * 1024); + return CFG_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S index 486fdc8..99c4d79 100644 --- a/board/mpc8560ads/init.S +++ b/board/mpc8560ads/init.S @@ -45,7 +45,8 @@ tlb1_entry: entry_start - .long 0x0a /* the following data table uses a few of 16 TLB entries */ + /* Number of entries in the following table */ + .long 0x0c .long TLB1_MAS0(1,1,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) @@ -116,40 +117,57 @@ tlb1_entry: .long TLB1_MAS0(1,8,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(1,9,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * RapidIO MMU for 512M + * Two entries, 10 and 11 + */ + .long TLB1_MAS0(1,10,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,11,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .long TLB1_MAS0(1,15,0) .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #else +#else .long TLB1_MAS0(1,15,0) .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif +#endif entry_end /* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI IO 16M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M * - * Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. */ #if !defined(CONFIG_SPD_EEPROM) @@ -160,7 +178,7 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #endif -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* @@ -174,14 +192,14 @@ tlb1_entry: #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #endif -#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff) +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) /* * Rapid IO at 0xc000_0000 for 512 M */ -#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) .section .bootpg, "ax" diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 2fa96e0..a0f6b97 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -25,8 +25,6 @@ */ -extern long int spd_sdram (void); - #include <common.h> #include <asm/processor.h> #include <asm/immap_85xx.h> @@ -34,7 +32,15 @@ extern long int spd_sdram (void); #include <spd.h> #include <miiphy.h> -long int fixed_sdram (void); +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void sdram_init(void); +long int fixed_sdram(void); + /* * I/O Port configuration table @@ -190,8 +196,11 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -/* MPC8560ADS Board Status & Control Registers */ -typedef struct bscr_ { + +/* + * MPC8560ADS Board Status & Control Registers + */ +typedef struct bcsr_ { volatile unsigned char bcsr0; volatile unsigned char bcsr1; volatile unsigned char bcsr2; @@ -203,11 +212,12 @@ typedef struct bscr_ { int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; - pci->peer &= 0xfffffffdf; /* disable master abort */ + pci->peer &= 0xffffffdf; /* disable master abort */ #endif + return 0; } @@ -237,35 +247,41 @@ void reset_phy (void) #endif /* CONFIG_MII */ } - int checkboard (void) { puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif return 0; } -long int initdram (int board_type) +long int +initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); volatile immap_t *immap = (immap_t *)CFG_IMMR; -#if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; + puts("Initializing\n"); - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } #endif #if defined(CONFIG_SPD_EEPROM) @@ -274,98 +290,120 @@ long int initdram (int board_type) dram_size = fixed_sdram (); #endif -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; +#if defined(CONFIG_DDR_ECC) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init (void) +{ +#if !defined(CONFIG_RAM_AS_FLASH) + sys_info_t sysinfo; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + + puts (" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * LocalBus SDRAM is not emulating flash. + */ + + /* + * Fix Local Bus clock glitch. Errata LBC11. + * + * If localbus freq is less than 66Mhz, use bypass mode, + * otherwise use DLL. + * lcrr is the local-bus clock ratio register. + */ + get_sys_info (&sysinfo); + if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000; + } else { - uint pvr = get_pvr(); + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + volatile ccsr_gur_t *gur = &immap->im_gur; + uint pvr = get_pvr (); + uint temp_lbcdll = 0; if (pvr == PVR_85xx_REV1) { - /* - * Need change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 - * temporarily. - */ - lbc->lcrr = 0x10000004; + lbc->lcrr = 0x10000004; } + + /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; - udelay(200); + udelay (200); temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000; + asm ("sync;isync;msync"); } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; lbc->br2 = CFG_BR2_PRELIM; lbc->lbcr = CFG_LBC_LBCR; + asm ("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm ("sync"); + + /* + * Configure the SDRAM controller. + */ lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); + lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); + lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); -#endif + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm ("sync"); + *sdram_addr = 0xff; + ppcDcbf ((unsigned long) sdram_addr); + udelay (100); - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } #endif - - return dram_size; } @@ -403,6 +441,7 @@ int testdram (void) } #endif + #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. @@ -434,6 +473,6 @@ long int fixed_sdram (void) asm("sync; isync; msync"); udelay(500); #endif - return ( CFG_SDRAM_SIZE * 1024 * 1024); + return CFG_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 55593d9..8eb9317 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -174,16 +174,6 @@ reset_85xx_watchdog(void) #endif /* CONFIG_WATCHDOG */ #if defined(CONFIG_DDR_ECC) -__inline__ void dcbz(const void* addr) -{ - __asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr)); -} - -__inline__ void dcbf(const void* addr) -{ - __asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr)); -} - void dma_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 5732c29..11f0c3e 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * Copyright (C) 2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) * @@ -28,17 +29,23 @@ #include <asm/cpm_85xx.h> #include <pci.h> + #if defined(CONFIG_PCI) + + /* * Initialize PCI Devices, report devices found. */ + #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + {} }; #endif @@ -48,60 +55,61 @@ struct pci_controller local_hose = { #endif }; -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; - volatile ccsr_pcix_t *pcix = &immap->im_pcix; - - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - (CFG_PCI_MEM_SIZE/2), - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - (CFG_PCI_MEM_BASE+0x08000000), - (CFG_PCI_MEM_PHYS+0x08000000), - 0x1000000, /* 16M */ - PCI_REGION_IO); - - hose->region_count = 2; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - - pcix->potar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff; - pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff; - pcix->powbear1 = 0x00000000; - pcix->powar1 = 0x8004401a; /* 128M MEM space */ - pcix->potar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) & 0x000fffff; - pcix->potear2 = 0x00000000; - pcix->powbar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) && 0x000fffff; - pcix->powbear2 = 0x00000000; - pcix->powar2 = 0x80088017; /* 16M IO space */ - pcix->pitar1 = 0x00000000; - pcix->piwbar1 = 0x00000000; - pcix->piwar1 = 0xa0F5501f; +void pci_init_board (void) +{ + struct pci_controller *hose = (struct pci_controller *) &local_hose; + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_pcix_t *pcix = &immap->im_pcix; + + u16 reg16; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region (hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + + pci_set_region (hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + hose->region_count = 2; + + pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); + + pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff); + pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80); + + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potear1 = 0x00000000; + pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->powbear1 = 0x00000000; + pcix->powar1 = 0x8004401c; /* 512M MEM space */ + + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potear2 = 0x00000000; + pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->powbear2 = 0x00000000; + pcix->powar2 = 0x80088017; /* 16M IO space */ + + pcix->pitar1 = 0x00000000; + pcix->piwbar1 = 0x00000000; + pcix->piwar1 = 0xa0F5501f; + + /* + * Hose scan. + */ + pci_register_hose (hose); + hose->last_busno = pci_hose_scan (hose); } + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 040b88d..885f1ab 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -130,7 +130,6 @@ _start_e500: /* disable d-cache */ li r0,0x0 mtspr L1CSR0,r0 - isync /* invalidate i-cache */ mfspr r0,L1CSR1 @@ -144,7 +143,6 @@ _start_e500: isync /* clear registers */ - sync li r0,0 mtspr SRR0,r0 mtspr SRR1,r0 @@ -158,11 +156,8 @@ _start_e500: mtspr DEAR,r0 mtspr DBCR0,r0 - isync mtspr DBCR1,r0 - isync mtspr DBCR2,r0 - isync mtspr IAC1,r0 mtspr IAC2,r0 mtspr DAC1,r0 @@ -171,26 +166,13 @@ _start_e500: mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ - isync mtspr PID0,r0 - isync mtspr PID1,r0 - isync mtspr PID2,r0 - isync - mtspr TCR,r0 mtspr BUCSR,r0 /* disable branch prediction */ - isync - - mtspr HID0,r0 - isync - mtspr HID1,r0 - isync - mtspr MAS4,r0 - isync mtspr MAS6,r0 isync @@ -376,9 +358,9 @@ _start: isync /* Enable Time Base and Select Time Base Clock */ - li r0,0x4000 /* time base is processor clock */ + lis r0,HID0_EMCP@h /* Enable machine check */ + ori r0,r0,0x4000 /* time base is processor clock */ mtspr HID0,r0 - isync #if defined(CONFIG_ADDR_STREAMING) li r0,0x3000 @@ -386,31 +368,26 @@ _start: li r0,0x1000 #endif mtspr HID1,r0 - isync /* Enable Branch Prediction */ #if defined(CONFIG_BTB) li r0,0x201 /* BBFI = 1, BPEN = 1 */ mtspr BUCSR,r0 - isync #endif #if defined(CFG_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff - mtspr dbsr,r1 /* Clear all status bits */ + mtspr DBSR,r1 /* Clear all status bits */ lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ ori r0,r0,CFG_INIT_DBCR@l - mtspr dbcr0,r0 - isync + mtspr DBCR0,r0 #endif /* L1 DCache is used for initial RAM */ mfspr r2, L1CSR0 ori r2, r2, 0x0003 oris r2, r2, 0x0001 - msync - isync mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ isync @@ -457,8 +434,7 @@ in_flash: bl cpu_init_f bl icache_enable bl board_init_f - sync - + isync /* --FIXME-- machine check with MCSRRn and rfmci */ @@ -922,6 +898,18 @@ ppcDcbi: dcbi r0,r3 blr +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + /*------------------------------------------------------------------------------- */ /* Function: ppcSync */ /* Description: Processor Synchronize */ diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index c49b2a8..1bbaa54 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -15,7 +15,7 @@ http://ftp.gnu.org/gnu/binutils. shipped with your board. Then apply the following changes: SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used) SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560) - SW11[2]='OFF for 8560, ON for 8540' (single switch to toggle 8540.8560 mode) + SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode) SW11[7]='ON' (rev2), 'OFF' (rev1) SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector) SW22[1-4]="OFF OFF ON OFF" @@ -26,7 +26,8 @@ http://ftp.gnu.org/gnu/binutils. have to change the system clock from the default 66Mhz to 33Mhz by setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need double your platform clock(SW6) because the system clock is now only - half of its original value. + half of its original value. For example, if at 66MHz your system + clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10. 1.3 SW6 is a very important switch, it decides your platform clock and CPU clock based on the on-board system clock(default 66MHz). Check the @@ -42,7 +43,7 @@ http://ftp.gnu.org/gnu/binutils. 0x0000_0000 0x7fff_ffff DDR 2G 0x8000_0000 0x9fff_ffff PCI MEM 512M 0xc000_0000 0xdfff_ffff Rapid IO 512M - 0xe000_0000 0xe000_ffff CCSR 1M + 0xe000_0000 0xe00f_ffff CCSR 1M 0xe200_0000 0xe2ff_ffff PCI IO 16M 0xf000_0000 0xf7ff_ffff SDRAM 128M 0xf800_0000 0xf80f_ffff BCSR 1M @@ -56,11 +57,12 @@ http://ftp.gnu.org/gnu/binutils. arch/ppc/configs/mpc8540_ads_defconfig arch/ppc/configs/mpc8560_ads_defconfig - 3. DEFINITIONS AND COMPILATION -3.1 Explanation on NEW definitions in include/configs/MPC8540ADS.h and include/ - configs/MPC8560ADS.h +3.1 Explanation on NEW definitions in: + include/configs/MPC8540ADS.h + include/configs/MPC8560ADS.h + CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc) CONFIG_E500 BOOKE e500 family(Motorola) CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives @@ -69,49 +71,63 @@ http://ftp.gnu.org/gnu/binutils. CONFIG_MPC8540ADS MPC8540ADS board specific CONFIG_MPC8560ADS MPC8560ADS board specific CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking - CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can also - manual config the DDR after undef this definition. + CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can + also manual config the DDR after undef this + definition. CONFIG_DDR_ECC only for ECC DDR module - CONFIG_DDR_DLL DLL fix on some ADS boards needed for more stability. - CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into localbus - SDRAM and treat localbus SDRAM as a flash. We use this - memory based U-Boot before flash is working while Metrowerks - and Windriver are still working on their flash/JTAG tools. - if you can program the flash directly, undef this. - Other than the above definitions, the rest in the config files are straightforward. + CONFIG_DDR_DLL DLL fix on some ADS boards needed for more + stability. + CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into + localbus SDRAM and treat localbus SDRAM as a + flash. We use this memory based U-Boot + before flash is working while Metrowerks and + Windriver are still working on their + flash/JTAG tools. if you can program the + flash directly, undef this. + +Other than the above definitions, the rest in the config files are +straightforward. + 3.2 Compilation - export CROSS_COMPILE=your-cross-compile-prefix(assuming you're using BASH shell) - cd u-boot - make distclean - make MPC8560ADS_config (or make MPC8540ADS_config) - make + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC8560ADS_config (or make MPC8540ADS_config) + make 4. Notes: 4.1 When connecting with kermit, the following commands must be present.in - your .kermrc file. These are especially important when booting as - MPC8560, as the serial console will not work without them: - -set speed 115200 -set carrier-watch off -set handshake none -set flow-control none -robust - -4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC ethernet. If that - happens, you can try the following steps to make network work: - MPC8560ADS>tftp 1000000 pImage - (if it hangs, use Ctrl-C to quit) - MPC8560ADS>nm fdf24524 - >0 - >1 - >. (to quit this memory operation) - MPC8560ADS>tftp 1000000 pImage - -4.3 If you're one of the early developers using the Rev1 8540/8560 chips, please use U-Boot - 1.0.0, as the newer silicon will only support Rev2 and future revisions of 8540/8560. + your .kermrc file. These are especially important when booting as + MPC8560, as the serial console will not work without them: + + set speed 115200 + set carrier-watch off + set handshake none + set flow-control none + robust + + +4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC + ethernet. If that happens, you can try the following steps to make + network work: + + MPC8560ADS>tftp 1000000 pImage + (if it hangs, use Ctrl-C to quit) + MPC8560ADS>nm fdf24524 + >0 + >1 + >. (to quit this memory operation) + MPC8560ADS>tftp 1000000 pImage + +4.3 If you're one of the early developers using the Rev1 8540/8560 chips, + please use U-Boot 1.0.0, as the newer silicon will only support Rev2 + and future revisions of 8540/8560. + 4.4 Reflash U-boot Image using U-boot @@ -121,8 +137,14 @@ robust => cp.b 0 fff80000 80000 -5. Screen dump: +4.5 Reflash U-Boot with a BDI-2000 + BDI> erase 0xFFF80000 0x2000 0x40 + BDI> prog 0xfff80000 u-boot.bin.8560ads + BDI> verify + + +5. Screen dump: 5.1 MPC8540ADS board U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 98de51b..2606b79 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -440,7 +440,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 +#define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 +#define LAWAR_TRGT_IF_PCI2 0x00100000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_RIO 0x00c00000 diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 5b3ff75..f7d90f4 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -280,7 +280,6 @@ #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ -#define SPRN_SVR 0x11E /* System-On-Chip Version Register */ #define SPRN_PVR 0x11F /* Processor Version Register */ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ @@ -297,6 +296,11 @@ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#ifdef CONFIG_BOOKE +#define SPRN_SVR 0x3FF /* System Version Register */ +#else +#define SPRN_SVR 0x11E /* System Version Register */ +#endif #define SPRN_TBHI 0x3DC /* Time Base High */ #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ #define SPRN_TBLO 0x3DD /* Time Base Low */ @@ -511,6 +515,7 @@ #define SPRG3 SPRN_SPRG3 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define SVR SPRN_SVR /* System Version Register */ #define TBRL SPRN_TBRL /* Time Base Read Lower Register */ #define TBRU SPRN_TBRU /* Time Base Read Upper Register */ #define TBWL SPRN_TBWL /* Time Base Write Lower Register */ @@ -731,8 +736,11 @@ #define PVR_7400 0x000C0000 #define PVR_7410 0x800C0000 #define PVR_7450 0x80000000 -#define PVR_8540 0x80200010 -#define PVR_8560 0x80200010 + +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) + /* * For the 8xx processors, all of them report the same PVR family for @@ -757,6 +765,33 @@ #define PVR_8260_HIP7 0x80822011 #define PVR_8260_HIP7R1 0x80822013 + +/* + * System Version Register + */ + +/* System Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ + +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ + + +/* + * SVR_VER() Version Values + */ + +#define SVR_8540 0x8030 +#define SVR_8560 0x8070 +#define SVR_8555 0x8079 +#define SVR_8541 0x807A + + /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single * generic 8xx as well. The boards containing these processors are either diff --git a/include/common.h b/include/common.h index 71dd1d9..8ab8432 100644 --- a/include/common.h +++ b/include/common.h @@ -342,7 +342,8 @@ void trap_init (ulong); defined (CONFIG_74xx_7xx) || \ defined (CONFIG_74x) || \ defined (CONFIG_75x) || \ - defined (CONFIG_74xx) + defined (CONFIG_74xx) || \ + defined(CONFIG_MPC85xx) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); unsigned short in16(unsigned int); @@ -356,6 +357,7 @@ void out32r(unsigned int, unsigned long value); void ppcDcbf(unsigned long value); void ppcDcbi(unsigned long value); void ppcSync(void); +void ppcDcbz(unsigned long value); #endif /* $(CPU)/cpu.c */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 2f1bb48..b967b1e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao <X.Xiao@motorola.com> * @@ -21,209 +22,346 @@ * MA 02111-1307 USA */ -/* mpc8540ads board configuration file */ -/* please refer to doc/README.mpc85xxads for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * mpc8540ads board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. */ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1 Chip */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific*/ - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC8540 1 /* MPC8540 specific */ +#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#if defined(CONFIG_MPC85xx_REV1) -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. +/* + * Use Localbus SDRAM to emulate flash before we can program the flash. + * Normally you need a flash-boot image(u-boot.bin). + * If unsure #undef this. */ #undef CONFIG_RAM_AS_FLASH -#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */ -#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ -#else -#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here. The board, however, can run and + * defaults to 66Mhz. In any event, this value must match the settings + * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well. + * + * SW17[8] ------+ SW6 + * SW15[1] ----+ | [0:1] + * V V V V + * 33MHz 1 1 1 0 + * 66MHz 0 0 0 1 + */ + +#define CONFIG_SYS_CLK_FREQ 66000000 -#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */ -#define CONFIG_DDR_SETTING + +#if !defined(CONFIG_SPD_EEPROM) +#define CONFIG_DDR_SETTING /* manually set up DDR parameters */ #endif -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 -#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) -#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." -#endif /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 128 /* DDR is now 128MB */ +#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ +/* + * SDRAM on the Local Bus + */ #if defined(CONFIG_RAM_AS_FLASH) #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ #else -#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ #if defined(CONFIG_RAM_AS_FLASH) -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ #else /* Boot from real Flash */ -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ #endif -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#undef CONFIG_CLOCKS_IN_MHZ + #if defined(CONFIG_DDR_SETTING) -#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ +#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ #define CFG_DDR_CS0_CONFIG 0x80000002 #define CFG_DDR_TIMING_1 0x37344321 -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/ -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/ -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/ +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ #endif -#undef CONFIG_CLOCKS_IN_MHZ -/* local bus definitions */ -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ +/* + * Local Bus Definitions + */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR5 \ + | CFG_LBC_LSDMR_PRETOACT3 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC2 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/ +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/ +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/ + #if defined(CONFIG_RAM_AS_FLASH) -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ #else -#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */ +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ #endif #define CFG_OR4_PRELIM 0xffffe1f1 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ -/* General PCI */ -#define CFG_PCI_MEM_BASE 0xe0000000 -#define CFG_PCI_MEM_PHYS 0xe0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 #if defined(CONFIG_PCI) + #define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + #undef CONFIG_EEPRO100 -#define CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ - #endif -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 8 */ - #define CFG_PCI_SUBSYS_DEVICEID 0x0003 -#else - #define CFG_PCI_SUBSYS_DEVICEID 0x0008 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif -#elif defined(CONFIG_TSEC_ENET) -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 8 /* PHY address */ + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 #endif -/* Environment */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_FEC 1 +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define FEC_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define FEC_PHYIDX 0 +#define CONFIG_ETHPRIME "MOTO ENET0" + +#endif /* CONFIG_TSEC_ENET */ + + +/* + * Environment + */ #ifndef CFG_RAMBOOT #if defined(CONFIG_RAM_AS_FLASH) #define CFG_ENV_IS_NOWHERE @@ -232,72 +370,83 @@ #else #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #endif #define CFG_ENV_SIZE 0x2000 #else -#define CFG_NO_FLASH 1 /* Flash is not usable now */ -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CFG_NO_FLASH 1 /* Flash is not usable now */ +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000 #endif -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff300000 0xff700000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS )) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) #endif #else #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C ) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) #endif #endif + #include <cmd_confdefs.h> -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "MPC8540ADS=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif + #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 +#define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif /* @@ -306,26 +455,62 @@ * Boot Flags */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -/* NOTE: change below for your network setting!!! */ +/*****************************/ +/* Environment Configuration */ +/*****************************/ + +/* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:01:af:07:9b:8a -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #endif -#define CONFIG_SERVERIP 163.12.64.52 -#define CONFIG_IPADDR 10.82.0.105 -#define CONFIG_GATEWAYIP 10.82.1.254 -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003 -#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx -#define CONFIG_BOOTFILE pImage +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 44b128f..f681b50 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao <X.Xiao@motorola.com> * @@ -21,226 +22,363 @@ * MA 02111-1307 USA */ -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * mpc8560ads board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. */ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ -#define CONFIG_MPC8560 1 /* MPC8560 specific */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC8560 1 /* MPC8560 specific */ +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#if defined(CONFIG_MPC85xx_REV1) -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. +/* + * Use Localbus SDRAM to emulate flash before we can program the flash. + * Normally you need a flash-boot image(u-boot.bin). + * If unsure #undef this. */ #undef CONFIG_RAM_AS_FLASH -#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */ -#define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else -#define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here. The board, however, can run and + * defaults to 66Mhz. In any event, this value must match the settings + * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well. + * + * SW17[8] ------+ SW6 + * SW15[1] ----+ | [0:1] + * V V V V + * 33MHz 1 1 1 0 + * 66MHz 0 0 0 1 + */ + +#define CONFIG_SYS_CLK_FREQ 66000000 -#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */ -#define CONFIG_DDR_SETTING + +#if !defined(CONFIG_SPD_EEPROM) +#define CONFIG_DDR_SETTING /* manually set up DDR parameters */ #endif -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ +#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ +/* + * SDRAM on the Local Bus + */ #if defined(CONFIG_RAM_AS_FLASH) #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ #else -#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ #if defined(CONFIG_RAM_AS_FLASH) -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ #else /* Boot from real Flash */ -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ #endif -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#undef CONFIG_CLOCKS_IN_MHZ #if defined(CONFIG_DDR_SETTING) #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ #define CFG_DDR_CS0_CONFIG 0x80000002 #define CFG_DDR_TIMING_1 0x37344321 -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/ -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/ -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/ +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ #endif -#undef CONFIG_CLOCKS_IN_MHZ -/* local bus definitions */ -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ +/* + * Local Bus Definitions + */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR5 \ + | CFG_LBC_LSDMR_PRETOACT3 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC2 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/ +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/ +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/ + #if defined(CONFIG_RAM_AS_FLASH) -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ #else -#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */ +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ #endif #define CFG_OR4_PRELIM 0xffffe1f1 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_PCI_MEM_BASE 0xe0000000 -#define CFG_PCI_MEM_PHYS 0xe0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) -#if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ - #endif -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */ - #define CFG_PCI_SUBSYS_DEVICEID 0x0003 -#else - #define CFG_PCI_SUBSYS_DEVICEID 0x0009 + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif -#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 8 /* PHY address */ + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC2 1 +#undef CONFIG_MPC85XX_FEC +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define CONFIG_ETHPRIME "MOTO ENET0" + #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - #if (CONFIG_ETHER_INDEX == 2) + +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + +#if (CONFIG_ETHER_INDEX == 2) /* * - Rx-CLK is CLK13 * - Tx-CLK is CLK14 * - Select bus for bd/buffers * - Full duplex */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) #define FETH2_RST 0x01 - #elif (CONFIG_ETHER_INDEX == 3) +#elif (CONFIG_ETHER_INDEX == 3) /* need more definitions here for FE3 */ #define FETH3_RST 0x80 - #endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_INDEX */ + #define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + /* * GPIO pins used for bit-banged MII communications */ @@ -256,9 +394,13 @@ else iop->pdat &= ~0x00200000 #define MIIDELAY udelay(1) + #endif -/* Environment */ + +/* + * Environment + */ #ifndef CFG_RAMBOOT #if defined(CONFIG_RAM_AS_FLASH) #define CFG_ENV_IS_NOWHERE @@ -267,83 +409,92 @@ #else #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #endif #define CFG_ENV_SIZE 0x2000 #else -#define CFG_NO_FLASH 1 /* Flash is not usable now */ -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CFG_NO_FLASH 1 /* Flash is not usable now */ +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000 #endif -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff400000 0xff700000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_ENV)) #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_ENV)) #endif #else #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_I2C) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) #endif #endif + #include <cmd_confdefs.h> -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "MPC8560ADS=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif + #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif /* @@ -352,26 +503,58 @@ * Boot Flags */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -/*Note: change below for your network setting!!! */ +/* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_ETHADDR 00:01:af:07:9b:8a -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #endif -#define CONFIG_SERVERIP 163.12.64.52 -#define CONFIG_IPADDR 10.82.0.105 -#define CONFIG_GATEWAYIP 10.82.1.254 -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003 -#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx -#define CONFIG_BOOTFILE pImage +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4f5c61..60b6c61 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -1,4 +1,5 @@ /* + * Copyright 2004 Freescale Semiconductor. * Copyright(c) 2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) */ @@ -6,27 +7,22 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ #if defined(CONFIG_E500) #include <e500.h> #endif -#if defined(CONFIG_DDR_ECC) -void dma_init(void); -uint dma_check(void); -int dma_xfer(void *dest, uint count, void *src); -#endif -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 +/* + * SCCR - System Clock Control Register, 9-8 */ -#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ -#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ +#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ #define SCCR_DFBRG_SHIFT 0 -#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ -#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ -#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ -#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ +#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ #endif /* __MPC85xx_H__ */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 7560a42..42b4671 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -775,7 +775,8 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \ - defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX) + defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8555CDS) || \ + defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX) /* handle the 2nd ethernet address */ s = getenv ("eth1addr"); @@ -786,8 +787,9 @@ void board_init_r (gd_t *id, ulong dest_addr) s = (*e) ? e + 1 : e; } #endif -#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || \ - defined(CONFIG_440_GX) +#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || \ + defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8560ADS) || \ + defined(CONFIG_440_GX) /* handle the 3rd ethernet address */ s = getenv ("eth2addr"); @@ -51,7 +51,7 @@ extern int rtl8139_initialize(bd_t*); extern int rtl8169_initialize(bd_t*); extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); -extern int tsec_initialize(bd_t*); +extern int tsec_initialize(bd_t*, int); static struct eth_device *eth_devices, *eth_current; @@ -147,8 +147,14 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_SK98) skge_initialize(bis); #endif -#ifdef CONFIG_TSEC_ENET - tsec_initialize(bis); +#if defined(CONFIG_MPC85XX_TSEC1) + tsec_initialize(bis, 0); +#endif +#if defined(CONFIG_MPC85XX_TSEC2) + tsec_initialize(bis, 1); +#endif +#if defined(CONFIG_MPC85XX_FEC) + tsec_initialize(bis, 2); #endif #if defined(CONFIG_AU1X00) au1x00_enet_initialize(bis); |