diff options
| -rw-r--r-- | board/mgcoge/mgcoge.c | 25 | ||||
| -rw-r--r-- | include/configs/mgcoge.h | 35 |
2 files changed, 53 insertions, 7 deletions
diff --git a/board/mgcoge/mgcoge.c b/board/mgcoge/mgcoge.c index 0207a3a..e7c3fa0 100644 --- a/board/mgcoge/mgcoge.c +++ b/board/mgcoge/mgcoge.c @@ -278,6 +278,17 @@ int checkboard(void) return 0; } +/* + * Early board initalization. + */ +int board_early_init_r(void) +{ + /* setup the UPIOx */ + *(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0; + *(char *)(CFG_PIGGY_BASE + 0x03) = 0x15; + return 0; +} + #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) /* * update "memory" property in the blob @@ -286,7 +297,7 @@ void ft_blob_update(void *blob, bd_t *bd) { int ret, nodeoffset = 0; ulong memory_data[2] = {0}; - ulong flash_data[4] = {0}; + ulong flash_data[8] = {0}; memory_data[0] = cpu_to_be32(bd->bi_memstart); memory_data[1] = cpu_to_be32(bd->bi_memsize); @@ -304,9 +315,13 @@ void ft_blob_update(void *blob, bd_t *bd) printf("ft_blob_update(): cannot find /memory node " "err:%s\n", fdt_strerror(nodeoffset)); } - /* update Flash size */ - flash_data[2] = cpu_to_be32(bd->bi_flashstart); - flash_data[3] = cpu_to_be32(bd->bi_flashsize); + /* update Flash addr, size */ + flash_data[2] = cpu_to_be32(CFG_FLASH_BASE); + flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE); + flash_data[4] = cpu_to_be32(1); + flash_data[5] = cpu_to_be32(0); + flash_data[6] = cpu_to_be32(CFG_FLASH_BASE_1); + flash_data[7] = cpu_to_be32(CFG_FLASH_SIZE_1); nodeoffset = fdt_path_offset (blob, "/localbus"); if (nodeoffset >= 0) { ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, @@ -331,7 +346,7 @@ void ft_blob_update(void *blob, bd_t *bd) } else { /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /localbus node " + printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " "err:%s\n", fdt_strerror(nodeoffset)); } diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index f4a1cc0..98facf2 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -35,6 +35,9 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ +/* Do boardspecific init */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + /* * Select serial console configuration * @@ -152,8 +155,13 @@ #define CFG_FLASH_SIZE 32 #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ + +#define CFG_FLASH_BASE_1 0x50000000 +#define CFG_FLASH_SIZE_1 64 + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 } #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) @@ -246,6 +254,8 @@ * ---- --- ------- ------ ------ * 0 60x GPCM 8 bit FLASH * 1 60x SDRAM 32 bit SDRAM + * 3 60x GPCM 8 bit GPIO/PIGGY + * 5 60x GPCM 16 bit CFG-Flash * */ /* Bank 0 - FLASH @@ -301,6 +311,27 @@ PSDMR_WRC_1C |\ PSDMR_CL_2) +/* GPIO/PIGGY on CS3 initialization values +*/ +#define CFG_PIGGY_BASE 0x30000000 +#define CFG_PIGGY_SIZE 128 + +#define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX ) + +/* CFG-Flash on CS5 initialization values +*/ +#define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\ + BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) + +#define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK | ORxG_TRLX ) + #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ /* pass open firmware flat tree */ |