diff options
| -rw-r--r-- | CHANGELOG | 4 | ||||
| -rw-r--r-- | board/tqm8xx/tqm8xx.c | 33 | ||||
| -rw-r--r-- | doc/README.m68k | 3 | ||||
| -rw-r--r-- | include/configs/NSCU.h | 42 |
4 files changed, 40 insertions, 42 deletions
@@ -5,6 +5,10 @@ Changes since U-Boot 1.1.1: * Patch by Stefan Roese, 15 Jul 2004: cpu/ppc4xx/sdram.c rewritten now using get_ram_size() +* Fix NSCU config; add ethernet wakeup code. + +* Add link for preloader for Motorola Coldfire to RAEDME.m68k + * Patch by Michael Bendzick, 12 Jul 2004: fix output formatting in drivers/cfi_flash.c diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index b90f5e7..a7a6f2a 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -445,12 +445,14 @@ int board_early_init_r (void) #endif /* CONFIG_PS2MULT */ -/* ------------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------------- */ +/* HMI10 specific stuff */ +/* ---------------------------------------------------------------------------- */ #ifdef CONFIG_HMI10 int misc_init_r (void) { -#ifdef CONFIG_IDE_LED +# ifdef CONFIG_IDE_LED volatile immap_t *immap = (immap_t *) CFG_IMMR; /* Configure PA15 as output port */ @@ -458,11 +460,11 @@ int misc_init_r (void) immap->im_ioport.iop_paodr |= 0x0001; immap->im_ioport.iop_papar &= ~0x0001; immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ -#endif +# endif return (0); } -#ifdef CONFIG_IDE_LED +# ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) { volatile immap_t *immap = (immap_t *) CFG_IMMR; @@ -474,7 +476,26 @@ void ide_led (uchar led, uchar status) immap->im_ioport.iop_padat &= ~0x0001; } } -#endif +# endif +#endif /* CONFIG_HMI10 */ + +/* ---------------------------------------------------------------------------- */ +/* NSCU specific stuff */ +/* ---------------------------------------------------------------------------- */ +#ifdef CONFIG_NSCU + +int misc_init_r (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* wake up ethernet module */ + immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ + immr->im_ioport.iop_pcdir |= 0x0004; /* output */ + immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ + immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ + + return (0); +} +#endif /* CONFIG_NSCU */ -#endif /* CONFIG_HMI10 */ /* ------------------------------------------------------------------------- */ diff --git a/doc/README.m68k b/doc/README.m68k index 9385f44..d5accdd 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -37,6 +37,9 @@ At the moment the code isn't fully implemented and still needs a pre-loader! The preloader must initialize the processor and then start u-boot. The board must be configured for a pre-loader (see 4.1) +For the preloader, please see +http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html + U-boot is configured to run at 0x20000 at default. This can be configured by change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in include/configs/M5282EVB.h. diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 930a5be..f13cb34 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -45,8 +45,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ - #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ @@ -75,6 +73,8 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_MISC_INIT_R 1 + #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -252,15 +252,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -269,17 +262,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -355,19 +340,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -437,13 +411,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us |