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-rw-r--r--board/freescale/mx28/mx28.c119
-rw-r--r--board/freescale/mx28/u-boot.lds2
-rw-r--r--cpu/arm926ejs/mx28/Makefile2
-rw-r--r--cpu/arm926ejs/mx28/generic.c136
-rw-r--r--cpu/arm926ejs/mx28/mmcops.c579
-rw-r--r--cpu/arm926ejs/mx28/pinctrl.c133
-rw-r--r--cpu/arm926ejs/mx28/reset.S5
-rw-r--r--cpu/arm926ejs/mx28/serial.c108
-rw-r--r--cpu/arm926ejs/mx28/timer.c74
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/imx_ssp_mmc.c371
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/mxc_enet.c742
l---------include/asm-arm/arch1
-rw-r--r--include/asm-arm/arch-mx28/mx28.h94
-rw-r--r--include/asm-arm/arch-mx28/pinctrl.h222
-rw-r--r--include/asm-arm/arch-mx28/regs-clkctrl.h635
-rw-r--r--include/asm-arm/arch-mx28/regs-enet.h3562
-rw-r--r--include/asm-arm/arch-mx28/regs-pinctrl.h2674
-rw-r--r--include/asm-arm/arch-mx28/regs-ssp.h471
-rw-r--r--include/asm-arm/arch-mx28/regs-timrot.h293
-rw-r--r--include/asm-arm/arch-mx28/regs-uartdbg.h301
-rw-r--r--include/configs/mx28.h110
23 files changed, 10505 insertions, 131 deletions
diff --git a/board/freescale/mx28/mx28.c b/board/freescale/mx28/mx28.c
index fa53e82..1d22de0 100644
--- a/board/freescale/mx28/mx28.c
+++ b/board/freescale/mx28/mx28.c
@@ -1,8 +1,5 @@
/*
- *
- * (c) 2008 Embedded Alley Solutions, Inc.
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,25 +20,67 @@
* MA 02111-1307 USA
*/
-
#include <common.h>
#include <asm/arch/mx28.h>
-#include <asm/arch/clkctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/spi.h>
+#include <asm/arch/regs-pinctrl.h>
+#include <asm/arch/pinctrl.h>
+
+/* This should be removed after it's added into mach-types.h */
+#ifndef MACH_TYPE_MX28EVK
+#define MACH_TYPE_MX28EVK 2531
+#endif
DECLARE_GLOBAL_DATA_PTR;
-#define KHz 1000
-#define MHz (1000 * KHz)
+/* MMC pins */
+static struct pin_desc mmc_pins_desc[] = {
+ { PINID_SSP0_DATA0, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA1, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA2, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA3, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA4, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA5, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA6, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DATA7, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_CMD, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_DETECT, PIN_FUN1, PAD_12MA, PAD_3V3, 1 },
+ { PINID_SSP0_SCK, PIN_FUN1, PAD_12MA, PAD_3V3, 1 }
+};
+
+static struct pin_group mmc_pins = {
+ .pins = mmc_pins_desc,
+ .nr_pins = ARRAY_SIZE(mmc_pins_desc)
+};
+
+/* ENET pins */
+static struct pin_desc enet_pins_desc[] = {
+ { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+ { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
+};
+
+static struct pin_group enet_pins = {
+ .pins = enet_pins_desc,
+ .nr_pins = ARRAY_SIZE(enet_pins_desc)
+};
-static void set_pinmux(void)
+/*
+ * Functions
+ */
+int board_init(void)
{
-}
+ /* Will change it for MX28 EVK later */
+ gd->bd->bi_arch_number = MACH_TYPE_MX28EVK;
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-#define IO_DIVIDER 18
-static void set_clocks(void)
-{
+ return 0;
}
int dram_init(void)
@@ -52,31 +91,43 @@ int dram_init(void)
return 0;
}
-int board_init(void)
+u32 ssp_mmc_is_wp(void)
{
- /* arch number of Freescale STMP 378x development board */
- /* gd->bd->bi_arch_number = MACH_TYPE_MX28_EVK; */
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- set_clocks();
+ return pin_gpio_get(PINID_SSP1_SCK);
+}
- set_pinmux();
+void ssp_mmc_board_init(void)
+{
+ /* Set up MMC pins */
+ pin_set_group(&mmc_pins);
- /* Configure SPI on SSP1 or SSP2 */
- spi_init();
+ /* Power on the card slot */
+ pin_set_type(PINID_PWM3, PIN_GPIO);
+ pin_gpio_direction(PINID_PWM3, 1);
+ pin_gpio_set(PINID_PWM3, 0);
- return 0;
-}
+ /* Wait 10 ms for card ramping up */
+ udelay(10000);
-int misc_init_r(void)
-{
- return 0;
+ /* Set up WP pin */
+ pin_set_type(PINID_SSP1_SCK, PIN_GPIO);
+ pin_gpio_direction(PINID_SSP1_SCK, 0);
}
-int checkboard(void)
+void enet_board_init(void)
{
- printf("Board: MX28 EVK \n");
- return 0;
+ /* Set up ENET pins */
+ pin_set_group(&enet_pins);
+
+ /* Power on the external phy */
+ pin_set_type(PINID_SSP1_DATA3, PIN_GPIO);
+ pin_gpio_direction(PINID_SSP1_DATA3, 1);
+ pin_gpio_set(PINID_SSP1_DATA3, 0);
+
+ /* Reset the external phy */
+ pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
+ pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
+ pin_gpio_set(PINID_ENET0_RX_CLK, 0);
+ udelay(200);
+ pin_gpio_set(PINID_ENET0_RX_CLK, 1);
}
diff --git a/board/freescale/mx28/u-boot.lds b/board/freescale/mx28/u-boot.lds
index 82cb8e3..b7efe6d 100644
--- a/board/freescale/mx28/u-boot.lds
+++ b/board/freescale/mx28/u-boot.lds
@@ -30,7 +30,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- cpu/arm926ejs/start.o (.text)
+ cpu/arm926ejs/start.o (.text)
*(.text)
}
.rodata : { *(.rodata) }
diff --git a/cpu/arm926ejs/mx28/Makefile b/cpu/arm926ejs/mx28/Makefile
index 3b23886..9f2d5e5 100644
--- a/cpu/arm926ejs/mx28/Makefile
+++ b/cpu/arm926ejs/mx28/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
-COBJS = timer.o spi.o
+COBJS = timer.o serial.o generic.o pinctrl.o mmcops.o
SOBJS = reset.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm926ejs/mx28/generic.c b/cpu/arm926ejs/mx28/generic.c
new file mode 100644
index 0000000..6ac75e0
--- /dev/null
+++ b/cpu/arm926ejs/mx28/generic.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/mx28.h>
+#include <asm/arch/regs-clkctrl.h>
+
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+ icache_enable();
+ dcache_enable();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ const u32 xtal = 24, ref = 480;
+ u32 cpu, bus, emi;
+ u32 clkfrac, clkdeq, clkctrl;
+ u32 frac, div;
+
+ clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
+ clkdeq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
+
+ /* CPU */
+ clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CPU);
+ if (clkctrl & (BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN |
+ BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
+ /* No support of fractional divider calculation */
+ cpu = 0;
+ } else {
+ if (clkdeq & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) {
+ /* xtal path */
+ div = (clkctrl & BM_CLKCTRL_CPU_DIV_XTAL) >>
+ BP_CLKCTRL_CPU_DIV_XTAL;
+ cpu = xtal / div;
+ } else {
+ /* ref path */
+ frac = (clkfrac & BM_CLKCTRL_FRAC0_CPUFRAC) >>
+ BP_CLKCTRL_FRAC0_CPUFRAC;
+ div = (clkctrl & BM_CLKCTRL_CPU_DIV_CPU) >>
+ BP_CLKCTRL_CPU_DIV_CPU;
+ cpu = (ref * 18 / frac) / div;
+ }
+ }
+
+ /* BUS */
+ clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_HBUS);
+ if (clkctrl & BM_CLKCTRL_HBUS_DIV_FRAC_EN) {
+ /* No support of fractional divider calculation */
+ bus = 0;
+ } else {
+ div = (clkctrl & BM_CLKCTRL_HBUS_DIV) >>
+ BP_CLKCTRL_HBUS_DIV;
+ bus = cpu / div;
+ }
+
+ /* EMI */
+ clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_EMI);
+ if (clkdeq & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) {
+ /* xtal path */
+ div = (clkctrl & BM_CLKCTRL_EMI_DIV_XTAL) >>
+ BP_CLKCTRL_EMI_DIV_XTAL;
+ emi = xtal / div;
+ } else {
+ /* ref path */
+ frac = (clkfrac & BM_CLKCTRL_FRAC0_EMIFRAC) >>
+ BP_CLKCTRL_FRAC0_EMIFRAC;
+ div = (clkctrl & BM_CLKCTRL_EMI_DIV_EMI) >>
+ BP_CLKCTRL_EMI_DIV_EMI;
+ emi = (ref * 18 / frac) / div;
+ }
+
+ /* Print */
+ printf("Freescale i.MX28 family\n");
+ printf("CPU: %d MHz\n", cpu);
+ printf("BUS: %d MHz\n", bus);
+ printf("EMI: %d MHz\n", emi);
+
+ return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip MMC controllers.
+ */
+#if defined(CONFIG_MXC_ENET)
+int imx_ssp_mmc_initialize(bd_t *bis);
+#endif
+int cpu_mmc_init(bd_t *bis)
+{
+ int rc = ENODEV;
+#ifdef CONFIG_IMX_SSP_MMC
+ rc = imx_ssp_mmc_initialize(bis);
+#endif
+ return rc;
+}
+
+/*
+ * Initializes on-chip ethernet controllers.
+ */
+#if defined(CONFIG_MXC_ENET)
+int mxc_enet_initialize(bd_t *bis);
+#endif
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = ENODEV;
+#if defined(CONFIG_MXC_ENET)
+ rc = mxc_enet_initialize(bis);
+#endif
+ return rc;
+}
+
diff --git a/cpu/arm926ejs/mx28/mmcops.c b/cpu/arm926ejs/mx28/mmcops.c
new file mode 100644
index 0000000..eed2046
--- /dev/null
+++ b/cpu/arm926ejs/mx28/mmcops.c
@@ -0,0 +1,579 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <exports.h>
+#include <mmc.h>
+
+#if defined(CONFIG_GENERIC_MMC) && defined(CONFIG_CUSTOMIZE_MMCOPS)
+#define MMCOPS_DEBUG
+
+#define MBR_SIGNATURE 0xaa55
+#define MBR_SECTOR_COUNT (CONFIG_ENV_OFFSET >> 9)
+/* 1. RSV partition (env and uImage) */
+#define RSVPART_SECTOR_OFFSET (MBR_SECTOR_COUNT)
+#define RSVPART_SECTOR_COUNT 0x3ffe /* 8 MB */
+/* 2. FAT partition */
+#define FATPART_FILESYS 0xb
+#define FATPART_SECTOR_OFFSET (RSVPART_SECTOR_OFFSET + RSVPART_SECTOR_COUNT)
+#define FATPART_SECTOR_COUNT 0x10000 /* 32 MB (minimal) */
+/* 3. EXT partition */
+#define EXTPART_FILESYS 0x83
+#define EXTPART_SECTOR_COUNT 0xc0000 /* 384 MB */
+/* 4. SB partition (uboot.sb or linux.sb) */
+#define SBPART_FILESYS 'S'
+#define SBPART_SECTOR_COUNT 0x4000 /* 8 MB */
+#define CB_SIGNATURE 0x00112233
+#define CB_SECTOR_COUNT 2
+
+#define MAX_CYLINDERS 1024
+#define MAX_HEADS 256
+#define MAX_SECTORS 63
+
+struct partition {
+ u8 boot_flag;
+ u8 start_head;
+ u8 start_sector;
+ u8 start_cylinder;
+ u8 file_system;
+ u8 end_head;
+ u8 end_sector;
+ u8 end_cylinder;
+ u32 sector_offset;
+ u32 sector_count;
+} __attribute__ ((__packed__));
+
+struct partition_table {
+ u8 reserved[446];
+ struct partition partitions[4];
+ u16 signature;
+};
+
+struct drive_info {
+ u32 chip_num;
+ u32 drive_type;
+ u32 drive_tag;
+ u32 sector_offset;
+ u32 sector_count;
+};
+
+struct config_block {
+ u32 signature;
+ u32 primary_tag;
+ u32 secondary_tag;
+ u32 num_copies;
+ struct drive_info drive_info[2];
+};
+
+static int mmc_format(int dev)
+{
+ int rc = 0;
+ u8 *buf = 0;
+ u32 i, cnt, total_sectors;
+ u32 offset[4];
+ struct config_block *cb;
+ struct partition_table *mbr;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ /* Warning */
+ printf("WARN: Data on card will get lost with format.\n"
+ "Continue?(y/n)");
+ char ch = getc();
+ printf("\n");
+ if (ch != 'y') {
+ rc = -1;
+ goto out;
+ }
+
+ /* Allocate sector buffer */
+ buf = malloc(mmc->read_bl_len);
+ if (!buf) {
+ printf("%s[%d]: malloc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ memset(buf, 0, mmc->read_bl_len);
+
+ /* Erase the first sector of each partition */
+ cnt = mmc->block_dev.block_read(dev, 0, 1, buf);
+ if (cnt != 1) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ mbr = (struct partition_table *)buf;
+ if (mbr->signature == MBR_SIGNATURE) {
+ /* Get sector offset of each partition */
+ for (i = 0; i < 4; i++)
+ offset[i] = mbr->partitions[i].sector_offset;
+ /* Erase */
+ memset(buf, 0, mmc->read_bl_len);
+ for (i = 0; i < 4; i++) {
+ if (offset[i] > 0) {
+ cnt = mmc->block_dev.block_write(dev,
+ offset[i], 1, buf);
+ if (cnt != 1) {
+ printf("%s[%d]: write mmc error\n",
+ __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ }
+ }
+ }
+
+ /* Get total sectors */
+ total_sectors = mmc->capacity >> 9;
+ if (RSVPART_SECTOR_COUNT + SBPART_SECTOR_COUNT > total_sectors) {
+ printf("Card capacity is too low to format\n");
+ rc = -1;
+ goto out;
+ }
+
+ /* Write config block */
+ cb = (struct config_block *)buf;
+ cb->signature = CB_SIGNATURE;
+ cb->num_copies = 2;
+ cb->primary_tag = 0x1;
+ cb->secondary_tag = 0x2;
+ cb->drive_info[0].chip_num = 0;
+ cb->drive_info[0].drive_type = 0;
+ cb->drive_info[0].drive_tag = 0x1;
+ cb->drive_info[0].sector_count = SBPART_SECTOR_COUNT - CB_SECTOR_COUNT;
+ cb->drive_info[0].sector_offset =
+ total_sectors - cb->drive_info[0].sector_count;
+ cb->drive_info[1].chip_num = 0;
+ cb->drive_info[1].drive_type = 0;
+ cb->drive_info[1].drive_tag = 0x2;
+ cb->drive_info[1].sector_count = SBPART_SECTOR_COUNT - CB_SECTOR_COUNT;
+ cb->drive_info[1].sector_offset =
+ total_sectors - cb->drive_info[1].sector_count;
+
+ cnt = mmc->block_dev.block_write(dev,
+ total_sectors - SBPART_SECTOR_COUNT, 1, (void *)cb);
+ if (cnt != 1) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+
+ /* Prepare for MBR */
+ memset(buf, 0, mmc->read_bl_len);
+ mbr = (struct partition_table *)buf;
+
+ /* RSV partition */
+ mbr->partitions[0].sector_offset = RSVPART_SECTOR_OFFSET;
+ mbr->partitions[0].sector_count = RSVPART_SECTOR_COUNT;
+
+ /* SB partition */
+ mbr->partitions[3].file_system = SBPART_FILESYS;
+ mbr->partitions[3].sector_offset = total_sectors - SBPART_SECTOR_COUNT;
+ mbr->partitions[3].sector_count = SBPART_SECTOR_COUNT;
+
+ /* EXT partition */
+ if (EXTPART_SECTOR_COUNT + SBPART_SECTOR_COUNT +
+ RSVPART_SECTOR_COUNT > total_sectors) {
+#ifdef MMCOPS_DEBUG
+ printf("No room for EXT partition\n");
+#endif
+ } else {
+ mbr->partitions[2].file_system = EXTPART_FILESYS;
+ mbr->partitions[2].sector_offset = total_sectors -
+ SBPART_SECTOR_COUNT - EXTPART_SECTOR_COUNT;
+ mbr->partitions[2].sector_count = EXTPART_SECTOR_COUNT;
+ }
+
+ /* FAT partition */
+ if (FATPART_SECTOR_COUNT + MBR_SECTOR_COUNT +
+ mbr->partitions[0].sector_count +
+ mbr->partitions[2].sector_count +
+ mbr->partitions[3].sector_count > total_sectors) {
+#ifdef MMCOPS_DEBUG
+ printf("No room for FAT partition\n");
+#endif
+ goto out;
+ }
+ mbr->partitions[1].file_system = FATPART_FILESYS;
+ mbr->partitions[1].sector_offset = FATPART_SECTOR_OFFSET;
+ mbr->partitions[1].sector_count = total_sectors - MBR_SECTOR_COUNT -
+ mbr->partitions[0].sector_count -
+ mbr->partitions[2].sector_count -
+ mbr->partitions[3].sector_count;
+
+out:
+ if (rc == 0) {
+ /* Write MBR */
+ mbr->signature = MBR_SIGNATURE;
+ cnt = mmc->block_dev.block_write(dev, 0, 1, (void *)mbr);
+ if (cnt != 1) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ } else
+ printf("Done.\n");
+ }
+
+ if (!buf)
+ free(buf);
+ return rc;
+}
+
+static int install_sbimage(int dev, void *addr, u32 size)
+{
+ int rc = 0;
+ u8 *buf = 0;
+ u32 cnt, offset, cb_offset, sectors, not_format = 0;
+ struct config_block *cb;
+ struct partition_table *mbr;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ /* Allocate sector buffer */
+ buf = malloc(mmc->read_bl_len);
+ if (!buf) {
+ printf("%s[%d]: malloc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+
+ /* Check partition */
+ offset = 0;
+ cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
+ if (cnt != 1) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ mbr = (struct partition_table *)buf;
+ if ((mbr->signature != MBR_SIGNATURE) ||
+ (mbr->partitions[3].file_system != SBPART_FILESYS))
+ not_format = 1;
+
+ /* Check config block */
+ offset = mbr->partitions[3].sector_offset;
+ cb_offset = offset; /* Save for later use */
+ cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
+ if (cnt != 1) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ cb = (struct config_block *)buf;
+ if (cb->signature != CB_SIGNATURE)
+ not_format = 1;
+
+ /* Not formatted */
+ if (not_format) {
+ printf("Card is not formatted yet\n");
+ rc = -1;
+ goto out;
+ }
+
+ /* Calculate sectors of image */
+ sectors = size / mmc->read_bl_len;
+ if (size % mmc->read_bl_len)
+ sectors++;
+
+ /* Write image */
+ offset = cb->drive_info[0].sector_offset;
+ cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
+ if (cnt != sectors) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ /* Verify */
+ cnt = mmc->block_dev.block_read(dev, offset, sectors,
+ addr + sectors * mmc->read_bl_len);
+ if (cnt != sectors) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ if (memcmp(addr, addr + sectors * mmc->read_bl_len,
+ sectors * mmc->read_bl_len)) {
+ printf("Verifying sbImage write fails");
+ rc = -1;
+ goto out;
+ }
+
+ /* Redundant one */
+ offset += sectors;
+ cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
+ if (cnt != sectors) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ /* Verify */
+ cnt = mmc->block_dev.block_read(dev, offset, sectors,
+ addr + sectors * mmc->read_bl_len);
+ if (cnt != sectors) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ if (memcmp(addr, addr + sectors * mmc->read_bl_len,
+ sectors * mmc->read_bl_len)) {
+ printf("Verifying redundant sbImage write fails");
+ rc = -1;
+ goto out;
+ }
+
+ /* Update config block */
+ cb->drive_info[0].sector_count = sectors;
+ cb->drive_info[1].sector_count = sectors;
+ cb->drive_info[1].sector_offset = offset;
+ cnt = mmc->block_dev.block_write(dev, cb_offset, 1, (void *)cb);
+ if (cnt != 1) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+
+ /* Done */
+ printf("Done: %d (%x hex) sectors written at %d (%x hex)\n",
+ sectors, sectors, offset - sectors, offset - sectors);
+
+out:
+ if (!buf)
+ free(buf);
+ return rc;
+}
+
+static int install_uimage(int dev, void *addr, u32 size)
+{
+ int rc = 0;
+ u8 *buf = 0;
+ u32 cnt, offset, sectors;
+ struct partition_table *mbr;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ /* Calculate sectors of uImage */
+ sectors = size / mmc->read_bl_len;
+ if (size % mmc->read_bl_len)
+ sectors++;
+
+ /* Allocate sector buffer */
+ buf = malloc(mmc->read_bl_len);
+ if (!buf) {
+ printf("%s[%d]: malloc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+
+ /* Check partition */
+ offset = 0;
+ cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
+ if (cnt != 1) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ mbr = (struct partition_table *)buf;
+ if (mbr->signature != MBR_SIGNATURE) {
+ printf("No valid partition table\n");
+ rc = -1;
+ goto out;
+ }
+ if (mbr->partitions[0].sector_count < sectors) {
+ printf("No enough uImage partition room\n");
+ rc = -1;
+ goto out;
+ }
+
+ /* Write uImage */
+ offset = mbr->partitions[0].sector_offset + (CONFIG_ENV_SIZE >> 9);
+ cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
+ if (cnt != sectors) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ /* Verify */
+ cnt = mmc->block_dev.block_read(dev, offset, sectors,
+ addr + sectors * mmc->read_bl_len);
+ if (cnt != sectors) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ if (memcmp(addr, addr + sectors * mmc->read_bl_len,
+ sectors * mmc->read_bl_len)) {
+ printf("Verifying uImage write fails");
+ rc = -1;
+ goto out;
+ }
+
+ /* Done */
+ printf("Done: %d (%x hex) sectors written at %d (%x hex)\n",
+ sectors, sectors, offset, offset);
+
+out:
+ if (!buf)
+ free(buf);
+ return rc;
+}
+
+static int install_rootfs(int dev, void *addr, u32 size)
+{
+ int rc = 0;
+ u8 *buf = 0;
+ u32 cnt, offset, sectors;
+ struct partition_table *mbr;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ /* Calculate sectors of rootfs */
+ sectors = size / mmc->read_bl_len;
+ if (size % mmc->read_bl_len)
+ sectors++;
+
+ /* Allocate sector buffer */
+ buf = malloc(mmc->read_bl_len);
+ if (!buf) {
+ printf("%s[%d]: malloc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+
+ /* Check partition */
+ offset = 0;
+ cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
+ if (cnt != 1) {
+ printf("%s[%d]: read mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+ mbr = (struct partition_table *)buf;
+ if ((mbr->signature != MBR_SIGNATURE) ||
+ (mbr->partitions[2].file_system != EXTPART_FILESYS)) {
+ printf("No rootfs partition\n");
+ rc = -1;
+ goto out;
+ }
+ if (mbr->partitions[2].sector_count < sectors) {
+ printf("No enough rootfs partition room\n");
+ rc = -1;
+ goto out;
+ }
+
+ /* Write rootfs */
+ offset = mbr->partitions[2].sector_offset;
+ cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
+ if (cnt != sectors) {
+ printf("%s[%d]: write mmc error\n", __func__, __LINE__);
+ rc = -1;
+ goto out;
+ }
+
+ /* Done */
+ printf("Done: %d (%x hex) sectors written at %d (%x hex)\n",
+ sectors, sectors, offset, offset);
+
+out:
+ if (!buf)
+ free(buf);
+ return rc;
+}
+
+int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int dev = 0;
+ struct mmc *mmc;
+
+ if (argc < 2)
+ goto err_out;
+
+ if (strcmp(argv[1], "read") && strcmp(argv[1], "write") &&
+ strcmp(argv[1], "rescan") && strcmp(argv[1], "format") &&
+ strcmp(argv[1], "install") && strcmp(argv[1], "list"))
+ goto err_out;
+
+ if (argc == 2) { /* list */
+ print_mmc_devices('\n');
+ return 0;
+ }
+
+ /* Find and init mmc */
+ dev = simple_strtoul(argv[2], NULL, 10);
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("%s[%d]: find mmc error\n", __func__, __LINE__);
+ return -1;
+ }
+ if (mmc_init(mmc)) {
+ printf("%s[%d]: init mmc error\n", __func__, __LINE__);
+ return -1;
+ }
+
+ if (!strcmp(argv[1], "format"))
+ mmc_format(dev);
+ if (argc == 3) /* rescan (mmc_init) */
+ return 0;
+
+ if (argc != 6)
+ goto err_out;
+
+ if (!strcmp(argv[1], "read") || !strcmp(argv[1], "write")) {
+ void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
+ u32 blk = simple_strtoul(argv[4], NULL, 16);
+ u32 cnt = simple_strtoul(argv[5], NULL, 16);
+ u32 n;
+
+ printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
+ argv[1], dev, blk, cnt);
+
+ if (!strcmp(argv[1], "read")) {
+ n = mmc->block_dev.block_read(dev, blk, cnt, addr);
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512); /* FIXME */
+ } else /* write */
+ n = mmc->block_dev.block_write(dev, blk, cnt, addr);
+
+ printf("%d blocks %s: %s\n", n, argv[1],
+ (n == cnt) ? "OK" : "ERROR");
+ return (n == cnt) ? 0 : -1;
+ } else if (!strcmp(argv[1], "install")) {
+ void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
+ u32 size = simple_strtoul(argv[4], NULL, 16);
+
+ if (!strcmp(argv[5], "sbImage"))
+ return install_sbimage(dev, addr, size);
+ else if (!strcmp(argv[5], "uImage"))
+ return install_uimage(dev, addr, size);
+ else if (!strcmp(argv[5], "rootfs"))
+ return install_rootfs(dev, addr, size);
+ }
+
+err_out:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return -1;
+}
+
+U_BOOT_CMD(
+ mmc, 6, 1, do_mmcops,
+ "MMC sub system",
+ "mmc read <device num> addr blk# cnt\n"
+ "mmc write <device num> addr blk# cnt\n"
+ "mmc rescan <device num>\n"
+ "mmc format <device num>\n"
+ "mmc install <device num> addr size sbImage/uImage/rootfs\n"
+ "mmc list - lists available devices");
+#endif /* (CONFIG_GENERIC_MMC && CONFIG_CUSTOMIZE_MMCOPS) */
diff --git a/cpu/arm926ejs/mx28/pinctrl.c b/cpu/arm926ejs/mx28/pinctrl.c
new file mode 100644
index 0000000..88427c8
--- /dev/null
+++ b/cpu/arm926ejs/mx28/pinctrl.c
@@ -0,0 +1,133 @@
+/*
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mx28.h>
+#include <asm/arch/regs-pinctrl.h>
+#include <asm/arch/pinctrl.h>
+
+void pin_gpio_direction(u32 id, u32 output)
+{
+ u32 addr;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0;
+ addr += 0x10 * bank;
+ if (output)
+ REG_SET_ADDR(addr, 1 << pin);
+ else
+ REG_CLR_ADDR(addr, 1 << pin);
+}
+
+u32 pin_gpio_get(u32 id)
+{
+ u32 addr, val;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0;
+ addr += 0x10 * bank;
+ val = REG_RD_ADDR(addr);
+
+ return (val & (1 << pin)) >> pin;
+}
+
+void pin_gpio_set(u32 id, u32 val)
+{
+ u32 addr;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0;
+ addr += 0x10 * bank;
+ if (val)
+ REG_SET_ADDR(addr, 1 << pin);
+ else
+ REG_CLR_ADDR(addr, 1 << pin);
+}
+
+void pin_set_strength(u32 id, enum pad_strength strength)
+{
+ u32 addr;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0;
+ addr += 0x40 * bank + 0x10 * (pin >> 3);
+ pin &= 0x7;
+ REG_CLR_ADDR(addr, 0x3 << (pin * 4));
+ REG_SET_ADDR(addr, strength << (pin * 4));
+}
+
+void pin_set_voltage(u32 id, enum pad_voltage volt)
+{
+ u32 addr;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0;
+ addr += 0x40 * bank + 0x10 * (pin >> 3);
+ pin &= 0x7;
+ if (volt == PAD_1V8)
+ REG_CLR_ADDR(addr, 1 << (pin * 4 + 2));
+ else
+ REG_SET_ADDR(addr, 1 << (pin * 4 + 2));
+}
+
+void pin_set_pullup(u32 id, u32 pullup)
+{
+ u32 addr;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0;
+ addr += 0x10 * bank;
+ if (pullup)
+ REG_SET_ADDR(addr, 1 << pin);
+ else
+ REG_CLR_ADDR(addr, 1 << pin);
+}
+
+void pin_set_type(u32 id, enum pin_fun cfg)
+{
+ u32 addr;
+ u32 bank = PINID_2_BANK(id);
+ u32 pin = PINID_2_PIN(id);
+
+ addr = REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0;
+ addr += 0x20 * bank + 0x10 * (pin >> 4);
+ pin &= 0xf;
+ REG_CLR_ADDR(addr, 0x3 << (pin * 2));
+ REG_SET_ADDR(addr, cfg << (pin * 2));
+}
+
+void pin_set_group(struct pin_group *pin_group)
+{
+ u32 p;
+ struct pin_desc *pin;
+
+ for (p = 0; p < pin_group->nr_pins; p++) {
+ pin = &pin_group->pins[p];
+ pin_set_type(pin->id, pin->fun);
+ pin_set_strength(pin->id, pin->strength);
+ pin_set_voltage(pin->id, pin->voltage);
+ pin_set_pullup(pin->id, pin->pullup);
+ }
+}
+
diff --git a/cpu/arm926ejs/mx28/reset.S b/cpu/arm926ejs/mx28/reset.S
index 324c384..c8596e5 100644
--- a/cpu/arm926ejs/mx28/reset.S
+++ b/cpu/arm926ejs/mx28/reset.S
@@ -1,7 +1,8 @@
/*
- * Processor reset for Freescale MX28 SoC.
+ * Processor reset for Freescale i.MX28 SoC.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* -----------------------------------------------------
*
@@ -39,5 +40,5 @@ POWER_MINPWR:
POWER_CHARGE:
.word 0x80044030
CLKCTRL_RESET:
- .word 0x80040120
+ .word 0x800401e0
diff --git a/cpu/arm926ejs/mx28/serial.c b/cpu/arm926ejs/mx28/serial.c
new file mode 100644
index 0000000..58f7d2a
--- /dev/null
+++ b/cpu/arm926ejs/mx28/serial.c
@@ -0,0 +1,108 @@
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <asm/arch/mx28.h>
+#include <asm/arch/regs-uartdbg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Set baud rate. The settings are always 8n1:
+ * 8 data bits, no parity, 1 stop bit
+ */
+void serial_setbrg(void)
+{
+ u32 cr;
+ u32 quot;
+
+ /* Disable everything */
+ cr = REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGCR);
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
+
+ /* Calculate and set baudrate */
+ quot = (CONFIG_DBGUART_CLK * 4) / gd->baudrate;
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGFBRD, quot & 0x3f);
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIBRD, quot >> 6);
+
+ /* Set 8n1 mode, enable FIFOs */
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGLCR_H,
+ BM_UARTDBGLCR_H_WLEN | BM_UARTDBGLCR_H_FEN);
+
+ /* Enable Debug UART */
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, cr);
+}
+
+int serial_init(void)
+{
+ /* Disable UART */
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
+
+ /* Mask interrupts */
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIMSC, 0);
+
+ /* Set default baudrate */
+ serial_setbrg();
+
+ /* Enable UART */
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR,
+ BM_UARTDBGCR_TXE | BM_UARTDBGCR_RXE | BM_UARTDBGCR_UARTEN);
+
+ return 0;
+}
+
+/* Send a character */
+void serial_putc(const char c)
+{
+ /* Wait for room in TX FIFO */
+ while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_TXFF)
+ ;
+
+ /* Write the data byte */
+ REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGDR, c);
+
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
+
+/* Test whether a character is in TX buffer */
+int serial_tstc(void)
+{
+ /* Check if RX FIFO is not empty */
+ return !(REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE);
+}
+
+/* Receive character */
+int serial_getc(void)
+{
+ /* Wait while TX FIFO is empty */
+ while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE)
+ ;
+
+ /* Read data byte */
+ return REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGDR) & 0xff;
+}
+
diff --git a/cpu/arm926ejs/mx28/timer.c b/cpu/arm926ejs/mx28/timer.c
index ffad4d8..873b30c 100644
--- a/cpu/arm926ejs/mx28/timer.c
+++ b/cpu/arm926ejs/mx28/timer.c
@@ -16,7 +16,7 @@
* (C) Copyright 2004
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -39,72 +39,60 @@
#include <common.h>
#include <asm/arch/mx28.h>
-#include <asm/arch/timrot.h>
-
-#define CONFIG_USE_TIMER0
-
-#if defined(CONFIG_USE_TIMER0)
-#define TIMCTRL TIMCTRL0
-#define TIMCOUNT TIMCOUNT0
-#elif defined(CONFIG_USE_TIMER1)
-#define TIMCTRL TIMCTRL1
-#define TIMCOUNT TIMCOUNT1
-#elif defined(CONFIG_USE_TIMER2)
-#define TIMCTRL TIMCTRL2
-#define TIMCOUNT TIMCOUNT2
-#elif defined(CONFIG_USE_TIMER3)
-#define TIMCTRL TIMCTRL3
-#define TIMCOUNT TIMCOUNT3
-#else
-#error "Define which STMP378x timer to use"
-#endif
-
-#define TIMER_LOAD_VAL 0x0000ffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER ((REG_RD(TIMROT_BASE + TIMCOUNT) & 0xffff0000) >> 16)
+#include <asm/arch/regs-timrot.h>
+
+/*
+ * TIMROT gets 4 timer instances
+ * Define N as 0..3 to specify
+ */
+#define N 0
+
+/* Ticks per second */
+#define CONFIG_SYS_HZ 1000
+
+/* Maximum fixed count */
+#define TIMER_LOAD_VAL 0xffffffff
static ulong timestamp;
static ulong lastdec;
int timer_init(void)
{
- u32 val;
-
/*
* Reset Timers and Rotary Encoder module
*/
/* Clear SFTRST */
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
- while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31))
+ REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31);
+ while (REG_RD(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL) & (1 << 31))
;
/* Clear CLKGATE */
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
+ REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 30);
/* Set SFTRST and wait until CLKGATE is set */
- REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31);
- while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30)))
+ REG_SET(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31);
+ while (!(REG_RD(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL) & (1 << 30)))
;
/* Clear SFTRST and CLKGATE */
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
+ REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31);
+ REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 30);
/*
* Now initialize timer
*/
/* Set fixed_count to 0 */
- REG_WR(TIMROT_BASE + TIMCOUNT, 0);
+ REG_WR(REGS_TIMROT_BASE, HW_TIMROT_FIXED_COUNTn(N), 0);
/* set UPDATE bit and 1Khz frequency */
- REG_WR(TIMROT_BASE + TIMCTRL,
- TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ);
+ REG_WR(REGS_TIMROT_BASE, HW_TIMROT_TIMCTRLn(N),
+ BM_TIMROT_TIMCTRLn_RELOAD | BM_TIMROT_TIMCTRLn_UPDATE |
+ BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL);
/* Set fixed_count to maximal value */
- REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL);
+ REG_WR(REGS_TIMROT_BASE, HW_TIMROT_FIXED_COUNTn(N), TIMER_LOAD_VAL);
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -166,14 +154,16 @@ void udelay(unsigned long usec)
void reset_timer_masked(void)
{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
+ /* capure current decrementer value time */
+ lastdec = REG_RD(REGS_TIMROT_BASE, HW_TIMROT_RUNNING_COUNTn(N));
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0;
}
ulong get_timer_masked(void)
{
- ulong now = READ_TIMER; /* current tick value */
+ /* current tick value */
+ ulong now = REG_RD(REGS_TIMROT_BASE, HW_TIMROT_RUNNING_COUNTn(N));
if (lastdec >= now) { /* normal mode (non roll) */
/* normal mode */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2902ba5..39a8913 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS-$(CONFIG_FSL_MMC) += fsl_esdhc.o
COBJS-$(CONFIG_IMX_MMC) += imx_esdhc.o
+COBJS-$(CONFIG_IMX_SSP_MMC) += imx_ssp_mmc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mmc/imx_ssp_mmc.c b/drivers/mmc/imx_ssp_mmc.c
new file mode 100644
index 0000000..61a1d85
--- /dev/null
+++ b/drivers/mmc/imx_ssp_mmc.c
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Terry Lv
+ *
+ * Copyright 2007, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/arch/mx28.h>
+#include <asm/arch/regs-ssp.h>
+#include <asm/arch/regs-clkctrl.h>
+
+#undef IMX_SSP_MMC_DEBUG
+
+extern void ssp_mmc_board_init(void);
+extern u32 ssp_mmc_is_wp(void);
+
+static inline void mdelay(unsigned long msec)
+{
+ unsigned long i;
+ for (i = 0; i < msec; i++)
+ udelay(1000);
+}
+
+static inline void sdelay(unsigned long sec)
+{
+ unsigned long i;
+ for (i = 0; i < sec; i++)
+ mdelay(1000);
+}
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int
+ssp_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ int i;
+
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC: CMD%d\n", cmd->cmdidx);
+#endif
+
+ /* Check bus busy */
+ i = 0;
+ while (REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) & (BM_SSP_STATUS_BUSY |
+ BM_SSP_STATUS_DATA_BUSY | BM_SSP_STATUS_CMD_BUSY)) {
+ mdelay(1);
+ i++;
+ if (i == 1000) {
+ printf("MMC: Bus busy timeout!\n");
+ return TIMEOUT;
+ }
+ }
+
+ /* See if card is present */
+ if (REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) & BM_SSP_STATUS_CARD_DETECT) {
+ printf("MMC: No card detected!\n");
+ return NO_CARD_ERR;
+ }
+
+ /* Clear all control bits except bus width */
+ REG_CLR(REGS_SSP0_BASE, HW_SSP_CTRL0, 0xff3fffff);
+
+ /* Set up command */
+ if (!(cmd->resp_type & MMC_RSP_CRC))
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_IGNORE_CRC);
+ if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_GET_RESP);
+ if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_LONG_RESP);
+
+ /* Command index */
+ REG_WR(REGS_SSP0_BASE, HW_SSP_CMD0,
+ (REG_RD(REGS_SSP0_BASE, HW_SSP_CMD0) & ~BM_SSP_CMD0_CMD) |
+ (cmd->cmdidx << BP_SSP_CMD0_CMD));
+ /* Command argument */
+ REG_WR(REGS_SSP0_BASE, HW_SSP_CMD1, cmd->cmdarg);
+
+ /* Set up data */
+ if (data) {
+ /* READ or WRITE */
+ if (data->flags & MMC_DATA_READ) {
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0,
+ BM_SSP_CTRL0_READ);
+ } else if (ssp_mmc_is_wp()) {
+ printf("MMC: Can not write a locked card!\n");
+ return UNUSABLE_ERR;
+ }
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_DATA_XFER);
+ REG_WR(REGS_SSP0_BASE, HW_SSP_BLOCK_SIZE,
+ ((data->blocks - 1) <<
+ BP_SSP_BLOCK_SIZE_BLOCK_COUNT) |
+ ((ffs(data->blocksize) - 1) <<
+ BP_SSP_BLOCK_SIZE_BLOCK_SIZE));
+ REG_WR(REGS_SSP0_BASE, HW_SSP_XFER_SIZE,
+ data->blocksize * data->blocks);
+ }
+
+ /* Kick off the command */
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_WAIT_FOR_IRQ);
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_ENABLE);
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN);
+
+ /* Wait for the command to complete */
+ i = 0;
+ do {
+ mdelay(10);
+ if (i++ == 100) {
+ printf("MMC: Command %d busy\n", cmd->cmdidx);
+ break;
+ }
+ } while (REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) &
+ BM_SSP_STATUS_CMD_BUSY);
+
+ /* Check command timeout */
+ if (REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) &
+ BM_SSP_STATUS_RESP_TIMEOUT) {
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC: Command %d timeout\n", cmd->cmdidx);
+#endif
+ return TIMEOUT;
+ }
+
+ /* Check command errors */
+ if (REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) &
+ (BM_SSP_STATUS_RESP_CRC_ERR | BM_SSP_STATUS_RESP_ERR)) {
+ printf("MMC: Command %d error (status 0x%08x)!\n",
+ cmd->cmdidx, REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS));
+ return COMM_ERR;
+ }
+
+ /* Copy response to response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[3] = REG_RD(REGS_SSP0_BASE, HW_SSP_SDRESP0);
+ cmd->response[2] = REG_RD(REGS_SSP0_BASE, HW_SSP_SDRESP1);
+ cmd->response[1] = REG_RD(REGS_SSP0_BASE, HW_SSP_SDRESP2);
+ cmd->response[0] = REG_RD(REGS_SSP0_BASE, HW_SSP_SDRESP3);
+ } else
+ cmd->response[0] = REG_RD(REGS_SSP0_BASE, HW_SSP_SDRESP0);
+
+ /* Return if no data to process */
+ if (!data)
+ return 0;
+
+ /* Process the data */
+ u32 xfer_cnt = data->blocksize * data->blocks;
+ u32 *tmp_ptr;
+
+ if (data->flags & MMC_DATA_READ) {
+ tmp_ptr = (u32 *)data->dest;
+ while (xfer_cnt > 0) {
+ if ((REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) &
+ BM_SSP_STATUS_FIFO_EMPTY) == 0) {
+ *tmp_ptr++ = REG_RD(REGS_SSP0_BASE, HW_SSP_DATA);
+ xfer_cnt -= 4;
+ }
+ }
+ } else {
+ tmp_ptr = (u32 *)data->src;
+ while (xfer_cnt > 0) {
+ if ((REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) &
+ BM_SSP_STATUS_FIFO_FULL) == 0) {
+ REG_WR(REGS_SSP0_BASE, HW_SSP_DATA, *tmp_ptr++);
+ xfer_cnt -= 4;
+ }
+ }
+ }
+
+ /* Check data errors */
+ if (REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS) &
+ (BM_SSP_STATUS_TIMEOUT | BM_SSP_STATUS_DATA_CRC_ERR |
+ BM_SSP_STATUS_FIFO_OVRFLW | BM_SSP_STATUS_FIFO_UNDRFLW)) {
+ printf("MMC: Data error with command %d (status 0x%08x)!\n",
+ cmd->cmdidx, REG_RD(REGS_SSP0_BASE, HW_SSP_STATUS));
+ return COMM_ERR;
+ }
+
+ return 0;
+}
+
+static void set_bit_clock(u32 clock)
+{
+ const u32 sspclk = 480000 * 18 / 29 / 1; /* 297931 KHz */
+ u32 divide, rate, tgtclk;
+
+ /*
+ * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+ * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+ * CLOCK_RATE could be any integer from 0 to 255.
+ */
+ clock /= 1000; /* KHz */
+ for (divide = 2; divide < 254; divide += 2) {
+ rate = sspclk / clock / divide;
+ if (rate <= 256)
+ break;
+ }
+
+ tgtclk = sspclk / divide / rate;
+ while (tgtclk > clock) {
+ rate++;
+ tgtclk = sspclk / divide / rate;
+ }
+ if (rate > 256)
+ rate = 256;
+
+ /* Always set timeout the maximum */
+ REG_WR(REGS_SSP0_BASE, HW_SSP_TIMING, BM_SSP_TIMING_TIMEOUT |
+ divide << BP_SSP_TIMING_CLOCK_DIVIDE |
+ (rate - 1) << BP_SSP_TIMING_CLOCK_RATE);
+
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC: Set clock rate to %d KHz (requested %d KHz)\n",
+ tgtclk, clock);
+#endif
+}
+
+static void ssp_mmc_set_ios(struct mmc *mmc)
+{
+ u32 regval;
+
+ /* Set the clock speed */
+ if (mmc->clock)
+ set_bit_clock(mmc->clock);
+
+ /* Set the bus width */
+ regval = REG_RD(REGS_SSP0_BASE, HW_SSP_CTRL0);
+ regval &= ~BM_SSP_CTRL0_BUS_WIDTH;
+ switch (mmc->bus_width) {
+ case 1:
+ regval |= (BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT <<
+ BP_SSP_CTRL0_BUS_WIDTH);
+ break;
+ case 4:
+ regval |= (BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT <<
+ BP_SSP_CTRL0_BUS_WIDTH);
+ break;
+ case 8:
+ regval |= (BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT <<
+ BP_SSP_CTRL0_BUS_WIDTH);
+ }
+ REG_WR(REGS_SSP0_BASE, HW_SSP_CTRL0, regval);
+
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC: Set %d bits bus width\n", mmc->bus_width);
+#endif
+}
+
+static int ssp_mmc_init(struct mmc *mmc)
+{
+ u32 regval;
+
+ /* Board level init */
+ ssp_mmc_board_init();
+
+ /*
+ * Set up SSPCLK
+ */
+ /* Set REF_IO0 at 480 MHz */
+ regval = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
+ regval &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
+ REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0,
+ regval | (29 << BP_CLKCTRL_FRAC0_IO0FRAC));
+ /* Enable REF_IO0 */
+ REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0,
+ BM_CLKCTRL_FRAC0_CLKGATEIO0);
+ /* Source SSPCLK from REF_IO0 */
+ REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ,
+ BM_CLKCTRL_CLKSEQ_BYPASS_SSP0);
+ /* Turn on SSPCLK */
+ REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_SSP0,
+ REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_SSP0) &
+ ~BM_CLKCTRL_SSP0_CLKGATE);
+ /* Set SSPCLK divide 1 */
+ regval = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_SSP0);
+ regval &= ~(BM_CLKCTRL_SSP0_DIV_FRAC_EN | BM_CLKCTRL_SSP0_DIV);
+ REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_SSP0,
+ regval | (1 << BP_CLKCTRL_SSP0_DIV));
+ /* Wait for new divide ready */
+ do {
+ udelay(10);
+ } while (REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_SSP0) &
+ BM_CLKCTRL_SSP0_BUSY);
+
+ /* Prepare for software reset */
+ REG_CLR(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_SFTRST);
+ REG_CLR(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_CLKGATE);
+ /* Assert reset */
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_SFTRST);
+ /* Wait for confirmation */
+ while (!(REG_RD(REGS_SSP0_BASE, HW_SSP_CTRL0) & BM_SSP_CTRL0_CLKGATE))
+ ;
+ /* Done */
+ REG_CLR(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_SFTRST);
+ REG_CLR(REGS_SSP0_BASE, HW_SSP_CTRL0, BM_SSP_CTRL0_CLKGATE);
+
+ /* 8 bits word length in MMC mode */
+ regval = REG_RD(REGS_SSP0_BASE, HW_SSP_CTRL1);
+ regval &= ~(BM_SSP_CTRL1_SSP_MODE | BM_SSP_CTRL1_WORD_LENGTH);
+ REG_WR(REGS_SSP0_BASE, HW_SSP_CTRL1, regval |
+ (BV_SSP_CTRL1_SSP_MODE__SD_MMC << BP_SSP_CTRL1_SSP_MODE) |
+ (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS <<
+ BP_SSP_CTRL1_WORD_LENGTH));
+
+ /* Set initial bit clock 400 KHz */
+ set_bit_clock(400000);
+
+ /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
+ REG_SET(REGS_SSP0_BASE, HW_SSP_CMD0, BM_SSP_CMD0_CONT_CLKING_EN);
+ udelay(200);
+ REG_CLR(REGS_SSP0_BASE, HW_SSP_CMD0, BM_SSP_CMD0_CONT_CLKING_EN);
+
+ return 0;
+}
+
+int imx_ssp_mmc_initialize(bd_t *bis)
+{
+ struct mmc *mmc;
+
+ mmc = malloc(sizeof(struct mmc));
+
+ sprintf(mmc->name, "IMX_SSP_MMC");
+ mmc->send_cmd = ssp_mmc_send_cmd;
+ mmc->set_ios = ssp_mmc_set_ios;
+ mmc->init = ssp_mmc_init;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_30_31 |
+ MMC_VDD_29_30 | MMC_VDD_28_29 | MMC_VDD_27_28;
+
+ mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
+ MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ /*
+ * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
+ * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+ * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+ * CLOCK_RATE could be any integer from 0 to 255.
+ */
+ mmc->f_min = 400000;
+ mmc->f_max = 148000000; /* 297.731 MHz / 2 */
+
+ mmc_register(mmc);
+
+ return 0;
+}
+
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6ba00be..9318015 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
COBJS-$(CONFIG_MXC_FEC) += mxc_fec.o
+COBJS-$(CONFIG_MXC_ENET) += mxc_enet.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/mxc_enet.c b/drivers/net/mxc_enet.c
new file mode 100644
index 0000000..edfbc1a
--- /dev/null
+++ b/drivers/net/mxc_enet.c
@@ -0,0 +1,742 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/arch/mx28.h>
+#include <asm/arch/regs-enet.h>
+#include <asm/arch/regs-clkctrl.h>
+
+/*
+ * Debug message switch
+ */
+#undef MXC_ENET_DEBUG
+
+/*
+ * Buffer descriptor control/status used by Ethernet receive.
+ */
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_RO1 ((ushort)0x4000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080)
+#define BD_ENET_RX_MC ((ushort)0x0040)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_TR BD_ENET_RX_CL
+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
+/*
+ * Buffer descriptor control/status used by Ethernet transmit.
+ */
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_ABC BD_ENET_TX_DEF
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/*
+ * Buffer descriptors
+ */
+typedef struct cpm_buf_desc {
+ ushort cbd_datlen; /* Data length in buffer */
+ ushort cbd_sc; /* Status and Control */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+/* ENET private information */
+struct enet_info_s {
+ int index;
+ u32 iobase;
+ int phy_addr;
+ int dup_spd;
+ char *phy_name;
+ int phyname_init;
+ cbd_t *rxbd; /* Rx BD */
+ cbd_t *txbd; /* Tx BD */
+ uint rxIdx;
+ uint txIdx;
+ char *rxbuf;
+ char *txbuf;
+ int initialized;
+ struct enet_info_s *next;
+};
+
+/* Register read/write struct */
+typedef struct enet {
+ u32 resv0; /* 0x0000 */
+ u32 eir; /* 0x0004 */
+ u32 eimr; /* 0x0008 */
+ u32 resv1; /* 0x000c */
+ u32 rdar; /* 0x0010 */
+ u32 tdar; /* 0x0014 */
+ u32 resv2[3]; /* 0x0018 */
+ u32 ecr; /* 0x0024 */
+ u32 resv3[6]; /* 0x0028 */
+ u32 mmfr; /* 0x0040 */
+ u32 mscr; /* 0x0044 */
+ u32 resv4[7]; /* 0x0048 */
+ u32 mibc; /* 0x0064 */
+ u32 resv5[7]; /* 0x0068 */
+ u32 rcr; /* 0x0084 */
+ u32 resv6[15]; /* 0x0088 */
+ u32 tcr; /* 0x00c4 */
+ u32 resv7[7]; /* 0x00c8 */
+ u32 palr; /* 0x00e4 */
+ u32 paur; /* 0x00e8 */
+ u32 opd; /* 0x00ec */
+ u32 resv8[10]; /* 0x00f0 */
+ u32 iaur; /* 0x0118 */
+ u32 ialr; /* 0x011c */
+ u32 gaur; /* 0x0120 */
+ u32 galr; /* 0x0124 */
+ u32 resv9[7]; /* 0x0128 */
+ u32 tfwr; /* 0x0144 */
+ u32 resv10; /* 0x0148 */
+ u32 frbr; /* 0x014c */
+ u32 frsr; /* 0x0150 */
+ u32 resv11[11]; /* 0x0154 */
+ u32 erdsr; /* 0x0180 */
+ u32 etdsr; /* 0x0184 */
+ u32 emrbr; /* 0x0188 */
+ /* Unused registers ... */
+} enet_t;
+
+/*
+ * Ethernet Transmit and Receive Buffers
+ */
+#define DBUF_LENGTH 1520
+#define RX_BUF_CNT (PKTBUFSRX)
+#define TX_BUF_CNT (RX_BUF_CNT)
+#define PKT_MINBUF_SIZE 64
+#define PKT_MAXBLR_SIZE 1520
+#define LAST_RX_BUF (RX_BUF_CNT - 1)
+#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
+#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
+
+/*
+ * MII definitions
+ */
+#define ENET_MII_ST 0x40000000
+#define ENET_MII_OP_OFF 28
+#define ENET_MII_OP_MASK 0x03
+#define ENET_MII_OP_RD 0x02
+#define ENET_MII_OP_WR 0x01
+#define ENET_MII_PA_OFF 23
+#define ENET_MII_PA_MASK 0xFF
+#define ENET_MII_RA_OFF 18
+#define ENET_MII_RA_MASK 0xFF
+#define ENET_MII_TA 0x00020000
+#define ENET_MII_DATA_OFF 0
+#define ENET_MII_DATA_MASK 0x0000FFFF
+
+#define ENET_MII_FRAME \
+ (ENET_MII_ST | ENET_MII_TA)
+
+#define ENET_MII_OP(x) \
+ (((x) & ENET_MII_OP_MASK) << ENET_MII_OP_OFF)
+
+#define ENET_MII_PA(pa) \
+ (((pa) & ENET_MII_PA_MASK) << ENET_MII_PA_OFF)
+
+#define ENET_MII_RA(ra) \
+ (((ra) & ENET_MII_RA_MASK) << ENET_MII_RA_OFF)
+
+#define ENET_MII_SET_DATA(v) \
+ (((v) & ENET_MII_DATA_MASK) << ENET_MII_DATA_OFF)
+
+#define ENET_MII_GET_DATA(v) \
+ (((v) >> ENET_MII_DATA_OFF) & ENET_MII_DATA_MASK)
+
+#define ENET_MII_READ(pa, ra) \
+ ((ENET_MII_FRAME | ENET_MII_OP(ENET_MII_OP_RD)) | \
+ ENET_MII_PA(pa) | ENET_MII_RA(ra))
+
+#define ENET_MII_WRITE(pa, ra, v) \
+ (ENET_MII_FRAME | ENET_MII_OP(ENET_MII_OP_WR) | \
+ ENET_MII_PA(pa) | ENET_MII_RA(ra) | ENET_MII_SET_DATA(v))
+
+#define ENET_MII_TIMEOUT 50000
+#define ENET_MII_TICK 2
+#define ENET_MII_PHYADDR 0x0
+
+/*
+ * Misc definitions
+ */
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#define ENET_RESET_DELAY 100
+#define ENET_MAX_TIMEOUT 50000
+#define ENET_TIMEOUT_TICKET 2
+
+#define __swap_32(x) ((((unsigned long)x) << 24) | \
+ ((0x0000FF00UL & ((unsigned long)x)) << 8) | \
+ ((0x00FF0000UL & ((unsigned long)x)) >> 8) | \
+ (((unsigned long)x) >> 24))
+
+/*
+ * Functions
+ */
+extern void enet_board_init(void);
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+static struct enet_info_s enet_info[] = {
+ {
+ 0, /* index */
+ REGS_ENET_BASE, /* io base */
+#ifdef CONFIG_DISCOVER_PHY
+ -1, /* discover phy_addr */
+#else
+ ENET_MII_PHYADDR, /* phy_addr for MAC0 */
+#endif
+ 0, /* duplex and speed */
+ 0, /* phy name */
+ 0, /* phyname init */
+ 0, /* RX BD */
+ 0, /* TX BD */
+ 0, /* rx Index */
+ 0, /* tx Index */
+ 0, /* tx buffer */
+ 0 /* initialized flag */
+ }
+};
+
+static inline int __enet_mii_read(volatile enet_t *enetp, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ int waiting = ENET_MII_TIMEOUT;
+ if (enetp->eir & BM_ENET_MAC0_EIR_MII)
+ enetp->eir |= BM_ENET_MAC0_EIR_MII;
+
+ enetp->mmfr = ENET_MII_READ(addr, reg);
+ while (1) {
+ if (enetp->eir & BM_ENET_MAC0_EIR_MII) {
+ enetp->eir |= BM_ENET_MAC0_EIR_MII;
+ break;
+ }
+ if ((waiting--) <= 0)
+ return -1;
+ udelay(ENET_MII_TICK);
+ }
+ *value = ENET_MII_GET_DATA(enetp->mmfr);
+ return 0;
+}
+
+static inline int __enet_mii_write(volatile enet_t *enetp, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ int waiting = ENET_MII_TIMEOUT;
+ if (enetp->eir & BM_ENET_MAC0_EIR_MII)
+ enetp->eir |= BM_ENET_MAC0_EIR_MII;
+
+ enetp->mmfr = ENET_MII_WRITE(addr, reg, value);
+ while (1) {
+ if (enetp->eir & BM_ENET_MAC0_EIR_MII) {
+ enetp->eir |= BM_ENET_MAC0_EIR_MII;
+ break;
+ }
+ if ((waiting--) <= 0)
+ return -1;
+ udelay(ENET_MII_TICK);
+ }
+ return 0;
+}
+
+static int mxc_enet_mii_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct enet_info_s *info;
+ volatile enet_t *enetp;
+
+ if (!dev)
+ return -1;
+ info = dev->priv;
+ enetp = (enet_t *) (info->iobase);
+ return __enet_mii_read(enetp, addr, reg, value);
+}
+
+static int mxc_enet_mii_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct enet_info_s *info;
+ volatile enet_t *enetp;
+ if (!dev)
+ return -1;
+ info = dev->priv;
+ enetp = (enet_t *) (info->iobase);
+ return __enet_mii_write(enetp, addr, reg, value);
+}
+
+static void mxc_enet_mii_init(volatile enet_t *enetp)
+{
+ /* Set RMII mode */
+ enetp->rcr |= BM_ENET_MAC0_RCR_RMII_MODE;
+
+ /* The phy requires MDC clock below 2.5 MHz */
+ enetp->mscr |= (enetp->mscr & ~BM_ENET_MAC0_MSCR_MII_SPEED) |
+ (40 << BP_ENET_MAC0_MSCR_MII_SPEED);
+}
+
+#ifdef CONFIG_DISCOVER_PHY
+static inline int __enet_mii_info(volatile enet_t *enetp, unsigned char addr)
+{
+ unsigned int id = 0;
+ unsigned short val;
+
+ if (__enet_mii_read(enetp, addr, PHY_PHYIDR2, &val) != 0)
+ return -1;
+ id = val;
+ if (id == 0xffff)
+ return -1;
+
+ if (__enet_mii_read(enetp, addr, PHY_PHYIDR1, &val) != 0)
+ return -1;
+
+ if (val == 0xffff)
+ return -1;
+
+ id |= val << 16;
+
+#ifdef MXC_ENMXC_ENET_DEBUG
+ printf("PHY indentify @ 0x%x = 0x%08x\n", addr, id);
+#endif
+ return 0;
+}
+
+static int mxc_enet_mii_discover_phy(struct eth_device *dev)
+{
+ unsigned short addr, val;
+ struct enet_info_s *info = dev->priv;
+ volatile enet_t *enetp = (enet_t *) (info->iobase);
+
+ /* Dummy read with delay to get phy start working */
+ do {
+ __enet_mii_read(enetp, ENET_MII_PHYADDR, PHY_PHYIDR1, &val);
+ udelay(10000);
+#ifdef MXC_ENET_DEBUG
+ printf("Dummy read on phy\n");
+#endif
+ } while (val == 0 || val == 0xffff);
+
+ /* Read phy ID */
+ for (addr = 0; addr < 0x20; addr++) {
+ if (!__enet_mii_info(enetp, addr))
+ return addr;
+ }
+
+ return -1;
+}
+#endif
+
+static void set_duplex_speed(volatile enet_t *enetp, unsigned char addr,
+ int dup_spd)
+{
+ unsigned short val;
+ int ret;
+
+ ret = __enet_mii_read(enetp, addr, PHY_BMCR, &val);
+ switch (dup_spd >> 16) {
+ case HALF:
+ val &= (~PHY_BMCR_DPLX);
+ break;
+ case FULL:
+ val |= PHY_BMCR_DPLX;
+ break;
+ default:
+ val |= PHY_BMCR_AUTON | PHY_BMCR_RST_NEG;
+ }
+ ret |= __enet_mii_write(enetp, addr, PHY_BMCR, val);
+
+ if (!ret && (val & PHY_BMCR_AUTON)) {
+ ret = 0;
+ while (ret++ < ENET_MII_TIMEOUT) {
+ if (__enet_mii_read(enetp, addr, PHY_BMSR, &val))
+ break;
+ if (!(val & PHY_BMSR_AUTN_ABLE))
+ break;
+ if (val & PHY_BMSR_AUTN_COMP)
+ break;
+ }
+ }
+
+ if (__enet_mii_read(enetp, addr, PHY_BMSR, &val)) {
+ dup_spd = _100BASET | (FULL << 16);
+ } else {
+ if (val & (PHY_BMSR_100TXF | PHY_BMSR_100TXH | PHY_BMSR_100T4))
+ dup_spd = _100BASET;
+ else
+ dup_spd = _10BASET;
+ if (val & (PHY_BMSR_100TXF | PHY_BMSR_10TF))
+ dup_spd |= (FULL << 16);
+ else
+ dup_spd |= (HALF << 16);
+ }
+
+ if ((dup_spd >> 16) == FULL) {
+ enetp->tcr |= BM_ENET_MAC0_TCR_FEDN;
+#ifdef MXC_ENET_DEBUG
+ printf("full duplex, ");
+#endif
+ } else {
+ enetp->rcr |= BM_ENET_MAC0_RCR_DRT;
+ enetp->tcr &= ~BM_ENET_MAC0_TCR_FEDN;
+#ifdef MXC_ENET_DEBUG
+ printf("half duplex, ");
+#endif
+ }
+#ifdef MXC_ENET_DEBUG
+ if ((dup_spd & 0xffff) == _100BASET)
+ printf("100 Mbps\n");
+ else
+ printf("10 Mbps\n");
+#endif
+}
+
+static void copy_packet(char *pdst, char *psrc, int length)
+{
+ long *pldst = (long *)pdst;
+ long *plsrc = (long *)psrc;
+
+ length /= sizeof(long);
+ while (length--) {
+ *pldst = __swap_32(*plsrc);
+ pldst++;
+ plsrc++;
+ }
+}
+
+static int enet_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ struct enet_info_s *info = dev->priv;
+ volatile enet_t *enetp = (enet_t *) (info->iobase);
+ int i;
+ u16 phyStatus;
+
+ __enet_mii_read(enetp, info->phy_addr, PHY_BMSR, &phyStatus);
+
+ if (!(phyStatus & PHY_BMSR_LS)) {
+ printf("ENET: Link is down %x\n", phyStatus);
+ return -1;
+ }
+
+ /* Wait for ready */
+ i = 0;
+ while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
+ (i < ENET_MAX_TIMEOUT)) {
+ udelay(ENET_TIMEOUT_TICKET);
+ i++;
+ }
+ if (i >= ENET_MAX_TIMEOUT)
+ printf("TX buffer is NOT ready\n");
+
+ /* Manipulate the packet buffer */
+ copy_packet((char *)info->txbd[info->txIdx].cbd_bufaddr,
+ (char *)packet, length + (4 - length % 4));
+
+ /* Set up transmit Buffer Descriptor */
+ info->txbd[info->txIdx].cbd_datlen = length;
+ info->txbd[info->txIdx].cbd_sc =
+ (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_WRAP) |
+ BD_ENET_TX_TC | BD_ENET_TX_RDY_LST;
+
+ /* Activate transmit Buffer Descriptor polling */
+ enetp->tdar = 0x01000000;
+
+ /* Move Buffer Descriptor to the next */
+ info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
+
+ return length;
+}
+
+static int enet_recv(struct eth_device *dev)
+{
+ struct enet_info_s *info = dev->priv;
+ volatile enet_t *enetp = (enet_t *) (info->iobase);
+ int length;
+
+ for (;;) {
+ if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+ length = -1;
+ break; /* nothing received - leave for() loop */
+ }
+
+ length = info->rxbd[info->rxIdx].cbd_datlen;
+
+ if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
+#ifdef MXC_ENET_DEBUG
+ printf("%s[%d] err: %x\n",
+ __func__, __LINE__,
+ info->rxbd[info->rxIdx].cbd_sc);
+#endif
+ } else {
+ length -= 4;
+
+ /* Manipulate the packet buffer */
+ copy_packet((char *)NetRxPackets[info->rxIdx],
+ (char *)info->rxbd[info->rxIdx].cbd_bufaddr,
+ length + (4 - length % 4));
+
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[info->rxIdx], length);
+ }
+
+ /* Give the buffer back to the ENET */
+ info->rxbd[info->rxIdx].cbd_datlen = 0;
+
+ /* Wrap around buffer index when necessary */
+ if (info->rxIdx == LAST_RX_BUF) {
+ info->rxbd[RX_BUF_CNT - 1].cbd_sc = BD_ENET_RX_W_E;
+ info->rxIdx = 0;
+ } else {
+ info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ info->rxIdx++;
+ }
+
+ /* Try to fill Buffer Descriptors */
+ enetp->rdar = 0x01000000;
+ }
+
+ return length;
+}
+
+static void enet_reset(struct eth_device *dev)
+{
+ int i;
+ struct enet_info_s *info = dev->priv;
+ volatile enet_t *enetp = (enet_t *) (info->iobase);
+
+ enetp->ecr |= BM_ENET_MAC0_ECR_RESET;
+ for (i = 0; (enetp->ecr & BM_ENET_MAC0_ECR_RESET) && (i < ENET_RESET_DELAY); ++i)
+ udelay(1);
+
+ if (i == ENET_RESET_DELAY)
+ printf("ENET reset timeout\n");
+}
+
+static void enet_halt(struct eth_device *dev)
+{
+ struct enet_info_s *info = dev->priv;
+
+ /* Reset ENET controller to stop transmit and receive */
+ enet_reset(dev);
+
+ /* Clear buffers */
+ info->rxIdx = info->txIdx = 0;
+ memset(info->rxbd, 0, RX_BUF_CNT * sizeof(cbd_t));
+ memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
+ memset(info->rxbuf, 0, RX_BUF_CNT * DBUF_LENGTH);
+ memset(info->txbuf, 0, TX_BUF_CNT * DBUF_LENGTH);
+}
+
+static int enet_init(struct eth_device *dev, bd_t *bd)
+{
+ struct enet_info_s *info = dev->priv;
+ volatile enet_t *enetp = (enet_t *) (info->iobase);
+ int i;
+ u8 *ea = NULL;
+
+ /* Turn on ENET clocks */
+ REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET,
+ REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) &
+ ~(BM_CLKCTRL_ENET_SLEEP | BM_CLKCTRL_ENET_DISABLE));
+
+ /* Set up ENET PLL for 50 MHz */
+ REG_SET(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0,
+ BM_CLKCTRL_PLL2CTRL0_POWER); /* Power on ENET PLL */
+ udelay(10); /* Wait 10 us */
+ REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0,
+ BM_CLKCTRL_PLL2CTRL0_CLKGATE); /* Gate on ENET PLL */
+ REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET,
+ REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) |
+ BM_CLKCTRL_ENET_CLK_OUT_EN); /* Enable pad output */
+
+ /* Board level init */
+ enet_board_init();
+
+ /* Reset ENET controller */
+ enet_reset(dev);
+
+#if defined(CONFIG_CMD_MII) || defined(CONFIG_MII) || \
+ defined(CONFIG_DISCOVER_PHY)
+ mxc_enet_mii_init(enetp);
+#ifdef CONFIG_DISCOVER_PHY
+ if (info->phy_addr < 0 || info->phy_addr > 0x1f)
+ info->phy_addr = mxc_enet_mii_discover_phy(dev);
+#endif
+ set_duplex_speed(enetp, (unsigned char)info->phy_addr, info->dup_spd);
+#else
+#ifndef CONFIG_DISCOVER_PHY
+ set_duplex_speed(enetp, (unsigned char)info->phy_addr,
+ (ENETDUPLEX << 16) | ENETSPEED);
+#endif
+#endif
+ /* We use strictly polling mode only */
+ enetp->eimr = 0;
+
+ /* Clear any pending interrupt */
+ enetp->eir = 0xffffffff;
+
+ /* Disable loopback mode */
+ enetp->rcr &= ~BM_ENET_MAC0_RCR_LOOP;
+
+ /* Enable RX flow control */
+ enetp->rcr |= BM_ENET_MAC0_RCR_FCE;
+
+ /* Set station address and enable it for TX */
+ ea = dev->enetaddr;
+ enetp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ enetp->paur = (ea[4] << 24) | (ea[5] << 16);
+ enetp->tcr |= BM_ENET_MAC0_TCR_TX_ADDR_INS;
+
+ /* Clear unicast address hash table */
+ enetp->iaur = 0;
+ enetp->ialr = 0;
+
+ /* Clear multicast address hash table */
+ enetp->gaur = 0;
+ enetp->galr = 0;
+
+ /* Set maximum receive buffer size. */
+ enetp->emrbr = PKT_MAXBLR_SIZE;
+
+ /* Setup Buffers and Buffer Desriptors */
+ info->rxIdx = 0;
+ info->txIdx = 0;
+
+ /*
+ * Setup Receiver Buffer Descriptors
+ * Settings:
+ * Empty, Wrap
+ */
+ for (i = 0; i < RX_BUF_CNT; i++) {
+ info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+ info->rxbd[i].cbd_datlen = 0; /* Reset */
+ info->rxbd[i].cbd_bufaddr =
+ (uint) (&info->rxbuf[0] + i * DBUF_LENGTH);
+ }
+ info->rxbd[RX_BUF_CNT - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+ /*
+ * Setup Transmitter Buffer Descriptors
+ * Settings:
+ * Last, Tx CRC
+ */
+ for (i = 0; i < TX_BUF_CNT; i++) {
+ info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
+ info->txbd[i].cbd_datlen = 0; /* Reset */
+ info->txbd[i].cbd_bufaddr =
+ (uint) (&info->txbuf[0] + i * DBUF_LENGTH);
+ }
+ info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+ /* Set receive and transmit descriptor base */
+ enetp->erdsr = (unsigned int)(&info->rxbd[0]);
+ enetp->etdsr = (unsigned int)(&info->txbd[0]);
+
+ /* Now enable the transmit and receive processing */
+ enetp->ecr |= BM_ENET_MAC0_ECR_ETHER_EN;
+
+ /* And last, try to fill Rx Buffer Descriptors */
+ enetp->rdar = 0x01000000;
+
+ return 0;
+}
+
+int mxc_enet_initialize(bd_t *bis)
+{
+ struct eth_device *dev;
+ int i;
+
+ for (i = 0; i < sizeof(enet_info) / sizeof(enet_info[0]); i++) {
+ dev = (struct eth_device *) memalign(CONFIG_SYS_CACHELINE_SIZE,
+ sizeof(*dev));
+ if (dev == NULL)
+ hang();
+
+ memset(dev, 0, sizeof(*dev));
+
+ /* Regiester device */
+ sprintf(dev->name, "ENET%d", enet_info[i].index);
+ dev->priv = &enet_info[i];
+ dev->init = enet_init;
+ dev->halt = enet_halt;
+ dev->send = enet_send;
+ dev->recv = enet_recv;
+ eth_register(dev);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name, mxc_enet_mii_read, mxc_enet_mii_write);
+#endif
+ /* Setup Receive and Transmit buffer descriptor */
+ enet_info[i].rxbd =
+ (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
+ RX_BUF_CNT * sizeof(cbd_t));
+ enet_info[i].rxbuf =
+ (char *) memalign(CONFIG_SYS_CACHELINE_SIZE,
+ RX_BUF_CNT * DBUF_LENGTH);
+ enet_info[i].txbd =
+ (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
+ TX_BUF_CNT * sizeof(cbd_t));
+ enet_info[i].txbuf =
+ (char *) memalign(CONFIG_SYS_CACHELINE_SIZE,
+ TX_BUF_CNT * DBUF_LENGTH);
+ enet_info[i].phy_name =
+ (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
+#ifdef MXC_ENET_DEBUG
+ printf("%s: rxbd %x txbd %x ->%x\n", dev->name,
+ (int)enet_info[i].rxbd, (int)enet_info[i].txbd,
+ (int)enet_info[i].txbuf);
+#endif
+ }
+
+ return 1;
+}
+
+#endif /* defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) */
diff --git a/include/asm-arm/arch b/include/asm-arm/arch
deleted file mode 120000
index cd1d867..0000000
--- a/include/asm-arm/arch
+++ /dev/null
@@ -1 +0,0 @@
-arch-mx35 \ No newline at end of file
diff --git a/include/asm-arm/arch-mx28/mx28.h b/include/asm-arm/arch-mx28/mx28.h
index b6343f3..c050fdf 100644
--- a/include/asm-arm/arch-mx28/mx28.h
+++ b/include/asm-arm/arch-mx28/mx28.h
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2008 Embedded Alley Solutions Inc.
*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,24 +17,92 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifndef MX28_H
-#define MX28_H
+#ifndef __MX28_H
+#define __MX28_H
/*
- * Most of MX28 SoC registers are associated with four addresses
+ * Most of i.MX28 SoC registers are associated with four addresses
* used for different operations - read/write, set, clear and toggle bits.
*
* Some of registers do not implement such feature and, thus, should be
* accessed/manipulated via single address in common way.
*/
-#define REG_RD(x) (*(volatile unsigned int *)(x))
-#define REG_WR(x, v) ((*(volatile unsigned int *)(x)) = (v))
-#define REG_SET(x, v) ((*(volatile unsigned int *)((x) + 0x04)) = (v))
-#define REG_CLR(x, v) ((*(volatile unsigned int *)((x) + 0x08)) = (v))
-#define REG_TOG(x, v) ((*(volatile unsigned int *)((x) + 0x0c)) = (v))
+#define REG_RD(base, reg) \
+ (*(volatile unsigned int *)((base) + (reg)))
+#define REG_WR(base, reg, value) \
+ ((*(volatile unsigned int *)((base) + (reg))) = (value))
+#define REG_SET(base, reg, value) \
+ ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value))
+#define REG_CLR(base, reg, value) \
+ ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value))
+#define REG_TOG(base, reg, value) \
+ ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value))
-#define MX28_OCRAM_BASE 0x00000000
-#define MX28_SDRAM_BASE 0x40000000
-#define MX28_REGS_BASE 0x80000000
+#define REG_RD_ADDR(addr) \
+ (*(volatile unsigned int *)((addr)))
+#define REG_WR_ADDR(addr, value) \
+ ((*(volatile unsigned int *)((addr))) = (value))
+#define REG_SET_ADDR(addr, value) \
+ ((*(volatile unsigned int *)((addr) + 0x4)) = (value))
+#define REG_CLR_ADDR(addr, value) \
+ ((*(volatile unsigned int *)((addr) + 0x8)) = (value))
+#define REG_TOG_ADDR(addr, value) \
+ ((*(volatile unsigned int *)((addr) + 0xc)) = (value))
-#endif /* MX28_H */
+/*
+ * Register base address
+ */
+#define REGS_ICOL_BASE (0x80000000)
+#define REGS_HSADC_BASE (0x80002000)
+#define REGS_APBH_BASE (0x80004000)
+#define REGS_PERFMON_BASE (0x80006000)
+#define REGS_BCH_BASE (0x8000A000)
+#define REGS_GPMI_BASE (0x8000C000)
+#define REGS_SSP0_BASE (0x80010000)
+#define REGS_SSP1_BASE (0x80012000)
+#define REGS_SSP2_BASE (0x80014000)
+#define REGS_SSP3_BASE (0x80016000)
+#define REGS_PINCTRL_BASE (0x80018000)
+#define REGS_DIGCTL_BASE (0x8001C000)
+#define REGS_ETM_BASE (0x80022000)
+#define REGS_APBX_BASE (0x80024000)
+#define REGS_DCP_BASE (0x80028000)
+#define REGS_PXP_BASE (0x8002A000)
+#define REGS_OCOTP_BASE (0x8002C000)
+#define REGS_AXI_AHB0_BASE (0x8002E000)
+#define REGS_LCDIF_BASE (0x80030000)
+#define REGS_CAN0_BASE (0x80032000)
+#define REGS_CAN1_BASE (0x80034000)
+#define REGS_SIMDBG_BASE (0x8003C000)
+#define REGS_SIMGPMISEL_BASE (0x8003C200)
+#define REGS_SIMSSPSEL_BASE (0x8003C300)
+#define REGS_SIMMEMSEL_BASE (0x8003C400)
+#define REGS_GPIOMON_BASE (0x8003C500)
+#define REGS_SIMENET_BASE (0x8003C700)
+#define REGS_ARMJTAG_BASE (0x8003C800)
+#define REGS_CLKCTRL_BASE (0x80040000)
+#define REGS_SAIF0_BASE (0x80042000)
+#define REGS_POWER_BASE (0x80044000)
+#define REGS_SAIF1_BASE (0x80046000)
+#define REGS_LRADC_BASE (0x80050000)
+#define REGS_SPDIF_BASE (0x80054000)
+#define REGS_RTC_BASE (0x80056000)
+#define REGS_I2C0_BASE (0x80058000)
+#define REGS_I2C1_BASE (0x8005A000)
+#define REGS_PWM_BASE (0x80064000)
+#define REGS_TIMROT_BASE (0x80068000)
+#define REGS_UARTAPP0_BASE (0x8006A000)
+#define REGS_UARTAPP1_BASE (0x8006C000)
+#define REGS_UARTAPP2_BASE (0x8006E000)
+#define REGS_UARTAPP3_BASE (0x80070000)
+#define REGS_UARTAPP4_BASE (0x80072000)
+#define REGS_UARTDBG_BASE (0x80074000)
+#define REGS_USBPHY0_BASE (0x8007C000)
+#define REGS_USBPHY1_BASE (0x8007E000)
+#define REGS_USBCTRL0_BASE (0x80080000)
+#define REGS_USBCTRL1_BASE (0x80090000)
+#define REGS_DFLPT_BASE (0x800C0000)
+#define REGS_DRAM_BASE (0x800E0000)
+#define REGS_ENET_BASE (0x800F0000)
+
+#endif /* __MX28_H */
diff --git a/include/asm-arm/arch-mx28/pinctrl.h b/include/asm-arm/arch-mx28/pinctrl.h
new file mode 100644
index 0000000..25a2e64
--- /dev/null
+++ b/include/asm-arm/arch-mx28/pinctrl.h
@@ -0,0 +1,222 @@
+/*
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __PINCTRL_H
+#define __PINCTRL_H
+
+#define PIN_BITS (5)
+#define PINS_PER_BANK (1 << PIN_BITS)
+#define PINID_2_BANK(id) ((id) >> PIN_BITS)
+#define PINID_2_PIN(id) ((id) & (PINS_PER_BANK - 1))
+#define PINID_ENCODE(bank, pin) (((bank) << PIN_BITS) + (pin))
+
+/*
+ * Each pin may be routed up to four different HW interfaces
+ * including GPIO
+ */
+enum pin_fun {
+ PIN_FUN1 = 0,
+ PIN_FUN2,
+ PIN_FUN3,
+ PIN_GPIO
+};
+
+/*
+ * Each pin may have different output drive strength in range from
+ * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
+ */
+enum pad_strength {
+ PAD_4MA = 0,
+ PAD_8MA,
+ PAD_12MA,
+ PAD_RESV
+};
+
+/*
+ * Each pin can be programmed for 1.8V or 3.3V
+ */
+enum pad_voltage {
+ PAD_1V8 = 0,
+ PAD_3V3
+};
+
+/*
+ * Structure to define a group of pins and their parameters
+ */
+struct pin_desc {
+ u32 id;
+ enum pin_fun fun;
+ enum pad_strength strength;
+ enum pad_voltage voltage;
+ u32 pullup:1;
+};
+
+struct pin_group {
+ struct pin_desc *pins;
+ int nr_pins;
+};
+
+extern void pin_gpio_direction(u32 id, u32 output);
+extern u32 pin_gpio_get(u32 id);
+extern void pin_gpio_set(u32 id, u32 val);
+extern void pin_set_type(u32 id, enum pin_fun cfg);
+extern void pin_set_strength(u32 id, enum pad_strength strength);
+extern void pin_set_voltage(u32 id, enum pad_voltage volt);
+extern void pin_set_pullup(u32 id, u32 pullup);
+extern void pin_set_group(struct pin_group *pin_group);
+
+/*
+ * Definitions of all i.MX28 pins
+ */
+/* Bank 0 */
+#define PINID_GPMI_D00 PINID_ENCODE(0, 0)
+#define PINID_GPMI_D01 PINID_ENCODE(0, 1)
+#define PINID_GPMI_D02 PINID_ENCODE(0, 2)
+#define PINID_GPMI_D03 PINID_ENCODE(0, 3)
+#define PINID_GPMI_D04 PINID_ENCODE(0, 4)
+#define PINID_GPMI_D05 PINID_ENCODE(0, 5)
+#define PINID_GPMI_D06 PINID_ENCODE(0, 6)
+#define PINID_GPMI_D07 PINID_ENCODE(0, 7)
+#define PINID_GPMI_CE0N PINID_ENCODE(0, 16)
+#define PINID_GPMI_CE1N PINID_ENCODE(0, 17)
+#define PINID_GPMI_CE2N PINID_ENCODE(0, 18)
+#define PINID_GPMI_CE3N PINID_ENCODE(0, 19)
+#define PINID_GPMI_RDY0 PINID_ENCODE(0, 20)
+#define PINID_GPMI_RDY1 PINID_ENCODE(0, 21)
+#define PINID_GPMI_RDY2 PINID_ENCODE(0, 22)
+#define PINID_GPMI_RDY3 PINID_ENCODE(0, 23)
+#define PINID_GPMI_RDN PINID_ENCODE(0, 24)
+#define PINID_GPMI_WRN PINID_ENCODE(0, 25)
+#define PINID_GPMI_ALE PINID_ENCODE(0, 26)
+#define PINID_GPMI_CLE PINID_ENCODE(0, 27)
+#define PINID_GPMI_RESETN PINID_ENCODE(0, 28)
+
+/* Bank 1 */
+#define PINID_LCD_D00 PINID_ENCODE(1, 0)
+#define PINID_LCD_D01 PINID_ENCODE(1, 1)
+#define PINID_LCD_D02 PINID_ENCODE(1, 2)
+#define PINID_LCD_D03 PINID_ENCODE(1, 3)
+#define PINID_LCD_D04 PINID_ENCODE(1, 4)
+#define PINID_LCD_D05 PINID_ENCODE(1, 5)
+#define PINID_LCD_D06 PINID_ENCODE(1, 6)
+#define PINID_LCD_D07 PINID_ENCODE(1, 7)
+#define PINID_LCD_D08 PINID_ENCODE(1, 8)
+#define PINID_LCD_D09 PINID_ENCODE(1, 9)
+#define PINID_LCD_D10 PINID_ENCODE(1, 10)
+#define PINID_LCD_D11 PINID_ENCODE(1, 11)
+#define PINID_LCD_D12 PINID_ENCODE(1, 12)
+#define PINID_LCD_D13 PINID_ENCODE(1, 13)
+#define PINID_LCD_D14 PINID_ENCODE(1, 14)
+#define PINID_LCD_D15 PINID_ENCODE(1, 15)
+#define PINID_LCD_D16 PINID_ENCODE(1, 16)
+#define PINID_LCD_D17 PINID_ENCODE(1, 17)
+#define PINID_LCD_D18 PINID_ENCODE(1, 18)
+#define PINID_LCD_D19 PINID_ENCODE(1, 19)
+#define PINID_LCD_D20 PINID_ENCODE(1, 20)
+#define PINID_LCD_D21 PINID_ENCODE(1, 21)
+#define PINID_LCD_D22 PINID_ENCODE(1, 22)
+#define PINID_LCD_D23 PINID_ENCODE(1, 23)
+#define PINID_LCD_RD_E PINID_ENCODE(1, 24)
+#define PINID_LCD_WR_RWN PINID_ENCODE(1, 25)
+#define PINID_LCD_RS PINID_ENCODE(1, 26)
+#define PINID_LCD_CS PINID_ENCODE(1, 27)
+#define PINID_LCD_VSYNC PINID_ENCODE(1, 28)
+#define PINID_LCD_HSYNC PINID_ENCODE(1, 29)
+#define PINID_LCD_DOTCK PINID_ENCODE(1, 30)
+#define PINID_LCD_ENABLE PINID_ENCODE(1, 31)
+
+/* Bank 2 */
+#define PINID_SSP0_DATA0 PINID_ENCODE(2, 0)
+#define PINID_SSP0_DATA1 PINID_ENCODE(2, 1)
+#define PINID_SSP0_DATA2 PINID_ENCODE(2, 2)
+#define PINID_SSP0_DATA3 PINID_ENCODE(2, 3)
+#define PINID_SSP0_DATA4 PINID_ENCODE(2, 4)
+#define PINID_SSP0_DATA5 PINID_ENCODE(2, 5)
+#define PINID_SSP0_DATA6 PINID_ENCODE(2, 6)
+#define PINID_SSP0_DATA7 PINID_ENCODE(2, 7)
+#define PINID_SSP0_CMD PINID_ENCODE(2, 8)
+#define PINID_SSP0_DETECT PINID_ENCODE(2, 9)
+#define PINID_SSP0_SCK PINID_ENCODE(2, 10)
+#define PINID_SSP1_SCK PINID_ENCODE(2, 12)
+#define PINID_SSP1_CMD PINID_ENCODE(2, 13)
+#define PINID_SSP1_DATA0 PINID_ENCODE(2, 14)
+#define PINID_SSP1_DATA3 PINID_ENCODE(2, 15)
+#define PINID_SSP2_SCK PINID_ENCODE(2, 16)
+#define PINID_SSP2_MOSI PINID_ENCODE(2, 17)
+#define PINID_SSP2_MISO PINID_ENCODE(2, 18)
+#define PINID_SSP2_SS0 PINID_ENCODE(2, 19)
+#define PINID_SSP2_SS1 PINID_ENCODE(2, 20)
+#define PINID_SSP2_SS2 PINID_ENCODE(2, 21)
+#define PINID_SSP3_SCK PINID_ENCODE(2, 24)
+#define PINID_SSP3_MOSI PINID_ENCODE(2, 25)
+#define PINID_SSP3_MISO PINID_ENCODE(2, 26)
+#define PINID_SSP3_SS0 PINID_ENCODE(2, 27)
+
+/* Bank 3 */
+#define PINID_AUART0_RX PINID_ENCODE(3, 0)
+#define PINID_AUART0_TX PINID_ENCODE(3, 1)
+#define PINID_AUART0_CTS PINID_ENCODE(3, 2)
+#define PINID_AUART0_RTS PINID_ENCODE(3, 3)
+#define PINID_AUART1_RX PINID_ENCODE(3, 4)
+#define PINID_AUART1_TX PINID_ENCODE(3, 5)
+#define PINID_AUART1_CTS PINID_ENCODE(3, 6)
+#define PINID_AUART1_RTS PINID_ENCODE(3, 7)
+#define PINID_AUART2_RX PINID_ENCODE(3, 8)
+#define PINID_AUART2_TX PINID_ENCODE(3, 9)
+#define PINID_AUART2_CTS PINID_ENCODE(3, 10)
+#define PINID_AUART2_RTS PINID_ENCODE(3, 11)
+#define PINID_AUART3_RX PINID_ENCODE(3, 12)
+#define PINID_AUART3_TX PINID_ENCODE(3, 13)
+#define PINID_AUART3_CTS PINID_ENCODE(3, 14)
+#define PINID_AUART3_RTS PINID_ENCODE(3, 15)
+#define PINID_PWM0 PINID_ENCODE(3, 16)
+#define PINID_PWM1 PINID_ENCODE(3, 17)
+#define PINID_PWM2 PINID_ENCODE(3, 18)
+#define PINID_SAIF0_MCLK PINID_ENCODE(3, 20)
+#define PINID_SAIF0_LRCLK PINID_ENCODE(3, 21)
+#define PINID_SAIF0_BITCLK PINID_ENCODE(3, 22)
+#define PINID_SAIF0_SDATA0 PINID_ENCODE(3, 23)
+#define PINID_I2C0_SCL PINID_ENCODE(3, 24)
+#define PINID_I2C0_SDA PINID_ENCODE(3, 25)
+#define PINID_SAIF1_SDATA0 PINID_ENCODE(3, 26)
+#define PINID_SPDIF PINID_ENCODE(3, 27)
+#define PINID_PWM3 PINID_ENCODE(3, 28)
+#define PINID_PWM4 PINID_ENCODE(3, 29)
+#define PINID_LCD_RESET PINID_ENCODE(3, 30)
+
+/* Bank 4 */
+#define PINID_ENET0_MDC PINID_ENCODE(4, 0)
+#define PINID_ENET0_MDIO PINID_ENCODE(4, 1)
+#define PINID_ENET0_RX_EN PINID_ENCODE(4, 2)
+#define PINID_ENET0_RXD0 PINID_ENCODE(4, 3)
+#define PINID_ENET0_RXD1 PINID_ENCODE(4, 4)
+#define PINID_ENET0_TX_CLK PINID_ENCODE(4, 5)
+#define PINID_ENET0_TX_EN PINID_ENCODE(4, 6)
+#define PINID_ENET0_TXD0 PINID_ENCODE(4, 7)
+#define PINID_ENET0_TXD1 PINID_ENCODE(4, 8)
+#define PINID_ENET0_RXD2 PINID_ENCODE(4, 9)
+#define PINID_ENET0_RXD3 PINID_ENCODE(4, 10)
+#define PINID_ENET0_TXD2 PINID_ENCODE(4, 11)
+#define PINID_ENET0_TXD3 PINID_ENCODE(4, 12)
+#define PINID_ENET0_RX_CLK PINID_ENCODE(4, 13)
+#define PINID_ENET0_COL PINID_ENCODE(4, 14)
+#define PINID_ENET0_CRS PINID_ENCODE(4, 15)
+#define PINID_ENET_CLK PINID_ENCODE(4, 16)
+#define PINID_JTAG_RTCK PINID_ENCODE(4, 20)
+
+#endif
diff --git a/include/asm-arm/arch-mx28/regs-clkctrl.h b/include/asm-arm/arch-mx28/regs-clkctrl.h
new file mode 100644
index 0000000..8fae885
--- /dev/null
+++ b/include/asm-arm/arch-mx28/regs-clkctrl.h
@@ -0,0 +1,635 @@
+/*
+ * Freescale CLKCTRL Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___CLKCTRL_H
+#define __ARCH_ARM___CLKCTRL_H
+
+
+#define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
+#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
+#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
+#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
+
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
+ (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
+#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
+#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
+#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
+ (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
+ (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
+#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
+#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
+#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
+ (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
+ (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
+#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
+#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
+#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
+ (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
+#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
+#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
+
+#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
+
+#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
+#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
+#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
+#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
+ (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
+#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
+ (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
+#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
+#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
+#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
+
+#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
+#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
+#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
+#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
+ (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
+ (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
+#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
+#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
+#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
+ (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
+ (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
+#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
+#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
+#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
+ (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
+#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
+#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
+
+#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
+
+#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
+#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
+#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
+#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
+ (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
+#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
+ (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
+#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
+#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
+#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
+
+#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
+#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
+#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
+#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
+ (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
+#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
+#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
+#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
+#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
+ (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
+#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
+#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
+#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
+
+#define HW_CLKCTRL_CPU (0x00000050)
+#define HW_CLKCTRL_CPU_SET (0x00000054)
+#define HW_CLKCTRL_CPU_CLR (0x00000058)
+#define HW_CLKCTRL_CPU_TOG (0x0000005c)
+
+#define BP_CLKCTRL_CPU_RSRVD5 30
+#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+ (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL 16
+#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
+ (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3 13
+#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v) \
+ (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1 6
+#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v) \
+ (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU 0
+#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v) \
+ (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
+
+#define HW_CLKCTRL_HBUS (0x00000060)
+#define HW_CLKCTRL_HBUS_SET (0x00000064)
+#define HW_CLKCTRL_HBUS_CLR (0x00000068)
+#define HW_CLKCTRL_HBUS_TOG (0x0000006c)
+
+#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
+#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
+#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
+#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
+#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
+#define BP_CLKCTRL_HBUS_SLOW_DIV 16
+#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
+ (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1 6
+#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v) \
+ (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
+#define BP_CLKCTRL_HBUS_DIV 0
+#define BM_CLKCTRL_HBUS_DIV 0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+
+#define HW_CLKCTRL_XBUS (0x00000070)
+
+#define BM_CLKCTRL_XBUS_BUSY 0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1 12
+#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
+#define BF_CLKCTRL_XBUS_RSRVD1(v) \
+ (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
+#define BP_CLKCTRL_XBUS_DIV 0
+#define BM_CLKCTRL_XBUS_DIV 0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+
+#define HW_CLKCTRL_XTAL (0x00000080)
+#define HW_CLKCTRL_XTAL_SET (0x00000084)
+#define HW_CLKCTRL_XTAL_CLR (0x00000088)
+#define HW_CLKCTRL_XTAL_TOG (0x0000008c)
+
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
+#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
+#define BP_CLKCTRL_XTAL_RSRVD2 27
+#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
+#define BF_CLKCTRL_XTAL_RSRVD2(v) \
+ (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1 2
+#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v) \
+ (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART 0
+#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v) \
+ (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+
+#define HW_CLKCTRL_SSP0 (0x00000090)
+
+#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
+#define BM_CLKCTRL_SSP0_BUSY 0x20000000
+#define BP_CLKCTRL_SSP0_RSRVD1 10
+#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
+#define BF_CLKCTRL_SSP0_RSRVD1(v) \
+ (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
+#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
+#define BP_CLKCTRL_SSP0_DIV 0
+#define BM_CLKCTRL_SSP0_DIV 0x000001FF
+#define BF_CLKCTRL_SSP0_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
+
+#define HW_CLKCTRL_SSP1 (0x000000a0)
+
+#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
+#define BM_CLKCTRL_SSP1_BUSY 0x20000000
+#define BP_CLKCTRL_SSP1_RSRVD1 10
+#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
+#define BF_CLKCTRL_SSP1_RSRVD1(v) \
+ (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
+#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
+#define BP_CLKCTRL_SSP1_DIV 0
+#define BM_CLKCTRL_SSP1_DIV 0x000001FF
+#define BF_CLKCTRL_SSP1_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
+
+#define HW_CLKCTRL_SSP2 (0x000000b0)
+
+#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
+#define BM_CLKCTRL_SSP2_BUSY 0x20000000
+#define BP_CLKCTRL_SSP2_RSRVD1 10
+#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
+#define BF_CLKCTRL_SSP2_RSRVD1(v) \
+ (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
+#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
+#define BP_CLKCTRL_SSP2_DIV 0
+#define BM_CLKCTRL_SSP2_DIV 0x000001FF
+#define BF_CLKCTRL_SSP2_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
+
+#define HW_CLKCTRL_SSP3 (0x000000c0)
+
+#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
+#define BM_CLKCTRL_SSP3_BUSY 0x20000000
+#define BP_CLKCTRL_SSP3_RSRVD1 10
+#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
+#define BF_CLKCTRL_SSP3_RSRVD1(v) \
+ (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
+#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
+#define BP_CLKCTRL_SSP3_DIV 0
+#define BM_CLKCTRL_SSP3_DIV 0x000001FF
+#define BF_CLKCTRL_SSP3_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
+
+#define HW_CLKCTRL_GPMI (0x000000d0)
+
+#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
+#define BM_CLKCTRL_GPMI_BUSY 0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1 11
+#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v) \
+ (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
+#define BP_CLKCTRL_GPMI_DIV 0
+#define BM_CLKCTRL_GPMI_DIV 0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
+
+#define HW_CLKCTRL_SPDIF (0x000000e0)
+
+#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD 0
+#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v) \
+ (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
+
+#define HW_CLKCTRL_EMI (0x000000f0)
+
+#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3 18
+#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v) \
+ (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2 12
+#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v) \
+ (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL 8
+#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
+ (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1 6
+#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v) \
+ (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI 0
+#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v) \
+ (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
+
+#define HW_CLKCTRL_SAIF0 (0x00000100)
+
+#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
+#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
+#define BP_CLKCTRL_SAIF0_RSRVD1 17
+#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
+ (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
+#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
+#define BP_CLKCTRL_SAIF0_DIV 0
+#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
+#define BF_CLKCTRL_SAIF0_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
+
+#define HW_CLKCTRL_SAIF1 (0x00000110)
+
+#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
+#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
+#define BP_CLKCTRL_SAIF1_RSRVD1 17
+#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
+ (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
+#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
+#define BP_CLKCTRL_SAIF1_DIV 0
+#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
+#define BF_CLKCTRL_SAIF1_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
+
+#define HW_CLKCTRL_DIS_LCDIF (0x00000120)
+
+#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
+#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
+#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
+#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
+#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
+#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
+ (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
+#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
+#define BP_CLKCTRL_DIS_LCDIF_DIV 0
+#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
+#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
+
+#define HW_CLKCTRL_ETM (0x00000130)
+
+#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
+#define BM_CLKCTRL_ETM_BUSY 0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1 8
+#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
+#define BF_CLKCTRL_ETM_RSRVD1(v) \
+ (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
+#define BP_CLKCTRL_ETM_DIV 0
+#define BM_CLKCTRL_ETM_DIV 0x0000007F
+#define BF_CLKCTRL_ETM_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_ETM_DIV)
+
+#define HW_CLKCTRL_ENET (0x00000140)
+
+#define BM_CLKCTRL_ENET_SLEEP 0x80000000
+#define BM_CLKCTRL_ENET_DISABLE 0x40000000
+#define BM_CLKCTRL_ENET_STATUS 0x20000000
+#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
+#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
+#define BP_CLKCTRL_ENET_DIV_TIME 21
+#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
+#define BF_CLKCTRL_ENET_DIV_TIME(v) \
+ (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
+#define BP_CLKCTRL_ENET_TIME_SEL 19
+#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
+#define BF_CLKCTRL_ENET_TIME_SEL(v) \
+ (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
+#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
+#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
+#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
+#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
+#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
+#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
+#define BP_CLKCTRL_ENET_RSRVD0 0
+#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
+#define BF_CLKCTRL_ENET_RSRVD0(v) \
+ (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
+
+#define HW_CLKCTRL_HSADC (0x00000150)
+
+#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
+#define BM_CLKCTRL_HSADC_RESETB 0x40000000
+#define BP_CLKCTRL_HSADC_FREQDIV 28
+#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
+#define BF_CLKCTRL_HSADC_FREQDIV(v) \
+ (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
+#define BP_CLKCTRL_HSADC_RSRVD1 0
+#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
+#define BF_CLKCTRL_HSADC_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
+
+#define HW_CLKCTRL_FLEXCAN (0x00000160)
+
+#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
+#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
+#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
+#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
+#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
+#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
+#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
+#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
+
+#define HW_CLKCTRL_FRAC0 (0x000001b0)
+#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
+#define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
+#define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
+
+#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
+#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
+#define BP_CLKCTRL_FRAC0_IO0FRAC 24
+#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
+#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
+ (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
+#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
+#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
+#define BP_CLKCTRL_FRAC0_IO1FRAC 16
+#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
+#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
+ (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
+#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
+#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
+#define BP_CLKCTRL_FRAC0_EMIFRAC 8
+#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
+#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
+ (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
+#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
+#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
+#define BP_CLKCTRL_FRAC0_CPUFRAC 0
+#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
+#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
+ (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
+
+#define HW_CLKCTRL_FRAC1 (0x000001c0)
+#define HW_CLKCTRL_FRAC1_SET (0x000001c4)
+#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
+#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
+
+#define BP_CLKCTRL_FRAC1_RSRVD2 24
+#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
+#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
+ (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
+#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
+#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
+#define BP_CLKCTRL_FRAC1_GPMIFRAC 16
+#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
+#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
+ (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
+#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
+#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
+#define BP_CLKCTRL_FRAC1_HSADCFRAC 8
+#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
+#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
+ (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
+#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
+#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
+#define BP_CLKCTRL_FRAC1_PIXFRAC 0
+#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
+#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
+ (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
+
+#define HW_CLKCTRL_CLKSEQ (0x000001d0)
+#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
+#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
+#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
+
+#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
+#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
+#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
+ (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
+#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
+#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
+ (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
+#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
+#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
+#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
+#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
+#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
+ (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
+
+#define HW_CLKCTRL_RESET (0x000001e0)
+
+#define BP_CLKCTRL_RESET_RSRVD 6
+#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+ (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
+#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
+#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
+#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
+#define BM_CLKCTRL_RESET_CHIP 0x00000002
+#define BM_CLKCTRL_RESET_DIG 0x00000001
+
+#define HW_CLKCTRL_STATUS (0x000001f0)
+
+#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+ (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD 0
+#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v) \
+ (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+
+#define HW_CLKCTRL_VERSION (0x00000200)
+
+#define BP_CLKCTRL_VERSION_MAJOR 24
+#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR 16
+#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v) \
+ (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP 0
+#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v) \
+ (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+#endif /* __ARCH_ARM___CLKCTRL_H */
diff --git a/include/asm-arm/arch-mx28/regs-enet.h b/include/asm-arm/arch-mx28/regs-enet.h
new file mode 100644
index 0000000..91aefe1
--- /dev/null
+++ b/include/asm-arm/arch-mx28/regs-enet.h
@@ -0,0 +1,3562 @@
+/*
+ * Freescale ENET Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.32
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___ENET_H
+#define __ARCH_ARM___ENET_H
+
+
+#define HW_ENET_MAC0_EIR (0x00000000)
+
+#define BM_ENET_MAC0_EIR_RSRVD0 0x80000000
+#define BM_ENET_MAC0_EIR_BABR 0x40000000
+#define BM_ENET_MAC0_EIR_BABT 0x20000000
+#define BM_ENET_MAC0_EIR_GRA 0x10000000
+#define BM_ENET_MAC0_EIR_TXF 0x08000000
+#define BM_ENET_MAC0_EIR_TXB 0x04000000
+#define BM_ENET_MAC0_EIR_RXF 0x02000000
+#define BM_ENET_MAC0_EIR_RXB 0x01000000
+#define BM_ENET_MAC0_EIR_MII 0x00800000
+#define BM_ENET_MAC0_EIR_EBERR 0x00400000
+#define BM_ENET_MAC0_EIR_LC 0x00200000
+#define BM_ENET_MAC0_EIR_RL 0x00100000
+#define BM_ENET_MAC0_EIR_UN 0x00080000
+#define BM_ENET_MAC0_EIR_PLR 0x00040000
+#define BM_ENET_MAC0_EIR_WAKEUP 0x00020000
+#define BM_ENET_MAC0_EIR_TS_AVAIL 0x00010000
+#define BM_ENET_MAC0_EIR_TS_TIMER 0x00008000
+#define BP_ENET_MAC0_EIR_RSRVD1 0
+#define BM_ENET_MAC0_EIR_RSRVD1 0x00007FFF
+#define BF_ENET_MAC0_EIR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC0_EIR_RSRVD1)
+
+#define HW_ENET_MAC0_EIMR (0x00000004)
+
+#define BP_ENET_MAC0_EIMR_EIMR 0
+#define BM_ENET_MAC0_EIMR_EIMR 0xFFFFFFFF
+#define BF_ENET_MAC0_EIMR_EIMR(v) (v)
+
+#define HW_ENET_MAC0_RDAR (0x0000000c)
+
+#define BP_ENET_MAC0_RDAR_RSRVD0 25
+#define BM_ENET_MAC0_RDAR_RSRVD0 0xFE000000
+#define BF_ENET_MAC0_RDAR_RSRVD0(v) \
+ (((v) << 25) & BM_ENET_MAC0_RDAR_RSRVD0)
+#define BM_ENET_MAC0_RDAR_RDAR 0x01000000
+#define BP_ENET_MAC0_RDAR_RSRVD1 0
+#define BM_ENET_MAC0_RDAR_RSRVD1 0x00FFFFFF
+#define BF_ENET_MAC0_RDAR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC0_RDAR_RSRVD1)
+
+#define HW_ENET_MAC0_TDAR (0x00000010)
+
+#define BP_ENET_MAC0_TDAR_RSRVD0 25
+#define BM_ENET_MAC0_TDAR_RSRVD0 0xFE000000
+#define BF_ENET_MAC0_TDAR_RSRVD0(v) \
+ (((v) << 25) & BM_ENET_MAC0_TDAR_RSRVD0)
+#define BM_ENET_MAC0_TDAR_TDAR 0x01000000
+#define BP_ENET_MAC0_TDAR_RSRVD1 0
+#define BM_ENET_MAC0_TDAR_RSRVD1 0x00FFFFFF
+#define BF_ENET_MAC0_TDAR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC0_TDAR_RSRVD1)
+
+#define HW_ENET_MAC0_ECR (0x00000020)
+
+#define BP_ENET_MAC0_ECR_RSRVD0 7
+#define BM_ENET_MAC0_ECR_RSRVD0 0xFFFFFF80
+#define BF_ENET_MAC0_ECR_RSRVD0(v) \
+ (((v) << 7) & BM_ENET_MAC0_ECR_RSRVD0)
+#define BM_ENET_MAC0_ECR_DBG_EN 0x00000040
+#define BM_ENET_MAC0_ECR_ETH_SPEED 0x00000020
+#define BM_ENET_MAC0_ECR_ENA_1588 0x00000010
+#define BM_ENET_MAC0_ECR_SLEEP 0x00000008
+#define BM_ENET_MAC0_ECR_MAGIC_ENA 0x00000004
+#define BM_ENET_MAC0_ECR_ETHER_EN 0x00000002
+#define BM_ENET_MAC0_ECR_RESET 0x00000001
+
+#define HW_ENET_MAC0_MMFR (0x0000003c)
+
+#define BP_ENET_MAC0_MMFR_ST 30
+#define BM_ENET_MAC0_MMFR_ST 0xC0000000
+#define BF_ENET_MAC0_MMFR_ST(v) \
+ (((v) << 30) & BM_ENET_MAC0_MMFR_ST)
+#define BP_ENET_MAC0_MMFR_OP 28
+#define BM_ENET_MAC0_MMFR_OP 0x30000000
+#define BF_ENET_MAC0_MMFR_OP(v) \
+ (((v) << 28) & BM_ENET_MAC0_MMFR_OP)
+#define BP_ENET_MAC0_MMFR_PA 23
+#define BM_ENET_MAC0_MMFR_PA 0x0F800000
+#define BF_ENET_MAC0_MMFR_PA(v) \
+ (((v) << 23) & BM_ENET_MAC0_MMFR_PA)
+#define BP_ENET_MAC0_MMFR_RA 18
+#define BM_ENET_MAC0_MMFR_RA 0x007C0000
+#define BF_ENET_MAC0_MMFR_RA(v) \
+ (((v) << 18) & BM_ENET_MAC0_MMFR_RA)
+#define BP_ENET_MAC0_MMFR_TA 16
+#define BM_ENET_MAC0_MMFR_TA 0x00030000
+#define BF_ENET_MAC0_MMFR_TA(v) \
+ (((v) << 16) & BM_ENET_MAC0_MMFR_TA)
+#define BP_ENET_MAC0_MMFR_DATA 0
+#define BM_ENET_MAC0_MMFR_DATA 0x0000FFFF
+#define BF_ENET_MAC0_MMFR_DATA(v) \
+ (((v) << 0) & BM_ENET_MAC0_MMFR_DATA)
+
+#define HW_ENET_MAC0_MSCR (0x00000040)
+
+#define BP_ENET_MAC0_MSCR_RSRVD0 11
+#define BM_ENET_MAC0_MSCR_RSRVD0 0xFFFFF800
+#define BF_ENET_MAC0_MSCR_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_MAC0_MSCR_RSRVD0)
+#define BP_ENET_MAC0_MSCR_HOLDTIME 8
+#define BM_ENET_MAC0_MSCR_HOLDTIME 0x00000700
+#define BF_ENET_MAC0_MSCR_HOLDTIME(v) \
+ (((v) << 8) & BM_ENET_MAC0_MSCR_HOLDTIME)
+#define BM_ENET_MAC0_MSCR_DIS_PRE 0x00000080
+#define BP_ENET_MAC0_MSCR_MII_SPEED 1
+#define BM_ENET_MAC0_MSCR_MII_SPEED 0x0000007E
+#define BF_ENET_MAC0_MSCR_MII_SPEED(v) \
+ (((v) << 1) & BM_ENET_MAC0_MSCR_MII_SPEED)
+#define BM_ENET_MAC0_MSCR_RSRVD1 0x00000001
+
+#define HW_ENET_MAC0_MIBC (0x00000060)
+
+#define BM_ENET_MAC0_MIBC_MIB_DIS 0x80000000
+#define BM_ENET_MAC0_MIBC_MIB_IDLE 0x40000000
+#define BM_ENET_MAC0_MIBC_MIB_CLEAR 0x20000000
+#define BP_ENET_MAC0_MIBC_RSRVD0 0
+#define BM_ENET_MAC0_MIBC_RSRVD0 0x1FFFFFFF
+#define BF_ENET_MAC0_MIBC_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_MAC0_MIBC_RSRVD0)
+
+#define HW_ENET_MAC0_RCR (0x00000080)
+
+#define BM_ENET_MAC0_RCR_GRS 0x80000000
+#define BM_ENET_MAC0_RCR_NO_LGTH_CHECK 0x40000000
+#define BP_ENET_MAC0_RCR_MAX_FL 16
+#define BM_ENET_MAC0_RCR_MAX_FL 0x3FFF0000
+#define BF_ENET_MAC0_RCR_MAX_FL(v) \
+ (((v) << 16) & BM_ENET_MAC0_RCR_MAX_FL)
+#define BM_ENET_MAC0_RCR_CNTL_FRM_ENA 0x00008000
+#define BM_ENET_MAC0_RCR_CRC_FWD 0x00004000
+#define BM_ENET_MAC0_RCR_PAUSE_FWD 0x00002000
+#define BM_ENET_MAC0_RCR_PAD_EN 0x00001000
+#define BM_ENET_MAC0_RCR_RMII_ECHO 0x00000800
+#define BM_ENET_MAC0_RCR_RMII_LOOP 0x00000400
+#define BM_ENET_MAC0_RCR_RMII_10T 0x00000200
+#define BM_ENET_MAC0_RCR_RMII_MODE 0x00000100
+#define BM_ENET_MAC0_RCR_SGMII_ENA 0x00000080
+#define BM_ENET_MAC0_RCR_RGMII_ENA 0x00000040
+#define BM_ENET_MAC0_RCR_FCE 0x00000020
+#define BM_ENET_MAC0_RCR_BC_REJ 0x00000010
+#define BM_ENET_MAC0_RCR_PROM 0x00000008
+#define BM_ENET_MAC0_RCR_MII_MODE 0x00000004
+#define BM_ENET_MAC0_RCR_DRT 0x00000002
+#define BM_ENET_MAC0_RCR_LOOP 0x00000001
+
+#define HW_ENET_MAC0_TCR (0x000000c0)
+
+#define BP_ENET_MAC0_TCR_RSRVD0 10
+#define BM_ENET_MAC0_TCR_RSRVD0 0xFFFFFC00
+#define BF_ENET_MAC0_TCR_RSRVD0(v) \
+ (((v) << 10) & BM_ENET_MAC0_TCR_RSRVD0)
+#define BM_ENET_MAC0_TCR_TX_CRC_FWD 0x00000200
+#define BM_ENET_MAC0_TCR_TX_ADDR_INS 0x00000100
+#define BP_ENET_MAC0_TCR_TX_ADDR_SEL 5
+#define BM_ENET_MAC0_TCR_TX_ADDR_SEL 0x000000E0
+#define BF_ENET_MAC0_TCR_TX_ADDR_SEL(v) \
+ (((v) << 5) & BM_ENET_MAC0_TCR_TX_ADDR_SEL)
+#define BM_ENET_MAC0_TCR_RFC_PAUSE 0x00000010
+#define BM_ENET_MAC0_TCR_TFC_PAUSE 0x00000008
+#define BM_ENET_MAC0_TCR_FEDN 0x00000004
+#define BM_ENET_MAC0_TCR_HBC 0x00000002
+#define BM_ENET_MAC0_TCR_GTS 0x00000001
+
+#define HW_ENET_MAC0_PALR (0x000000e0)
+
+#define BP_ENET_MAC0_PALR_PADDR1 0
+#define BM_ENET_MAC0_PALR_PADDR1 0xFFFFFFFF
+#define BF_ENET_MAC0_PALR_PADDR1(v) (v)
+
+#define HW_ENET_MAC0_PAUR (0x000000e4)
+
+#define BP_ENET_MAC0_PAUR_PADDR2 16
+#define BM_ENET_MAC0_PAUR_PADDR2 0xFFFF0000
+#define BF_ENET_MAC0_PAUR_PADDR2(v) \
+ (((v) << 16) & BM_ENET_MAC0_PAUR_PADDR2)
+#define BP_ENET_MAC0_PAUR_TYPE 0
+#define BM_ENET_MAC0_PAUR_TYPE 0x0000FFFF
+#define BF_ENET_MAC0_PAUR_TYPE(v) \
+ (((v) << 0) & BM_ENET_MAC0_PAUR_TYPE)
+
+#define HW_ENET_MAC0_OPD (0x000000e8)
+
+#define BP_ENET_MAC0_OPD_OPCODE 16
+#define BM_ENET_MAC0_OPD_OPCODE 0xFFFF0000
+#define BF_ENET_MAC0_OPD_OPCODE(v) \
+ (((v) << 16) & BM_ENET_MAC0_OPD_OPCODE)
+#define BP_ENET_MAC0_OPD_PAUSE_DUR 0
+#define BM_ENET_MAC0_OPD_PAUSE_DUR 0x0000FFFF
+#define BF_ENET_MAC0_OPD_PAUSE_DUR(v) \
+ (((v) << 0) & BM_ENET_MAC0_OPD_PAUSE_DUR)
+
+#define HW_ENET_MAC0_IAUR (0x00000114)
+
+#define BP_ENET_MAC0_IAUR_IADDR1 0
+#define BM_ENET_MAC0_IAUR_IADDR1 0xFFFFFFFF
+#define BF_ENET_MAC0_IAUR_IADDR1(v) (v)
+
+#define HW_ENET_MAC0_IALR (0x00000118)
+
+#define BP_ENET_MAC0_IALR_IADDR2 0
+#define BM_ENET_MAC0_IALR_IADDR2 0xFFFFFFFF
+#define BF_ENET_MAC0_IALR_IADDR2(v) (v)
+
+#define HW_ENET_MAC0_GAUR (0x0000011c)
+
+#define BP_ENET_MAC0_GAUR_GADDR1 0
+#define BM_ENET_MAC0_GAUR_GADDR1 0xFFFFFFFF
+#define BF_ENET_MAC0_GAUR_GADDR1(v) (v)
+
+#define HW_ENET_MAC0_GALR (0x00000120)
+
+#define BP_ENET_MAC0_GALR_GADDR2 0
+#define BM_ENET_MAC0_GALR_GADDR2 0xFFFFFFFF
+#define BF_ENET_MAC0_GALR_GADDR2(v) (v)
+
+#define HW_ENET_MAC0_TFW_SFCR (0x00000140)
+
+#define BP_ENET_MAC0_TFW_SFCR_RSRVD0 9
+#define BM_ENET_MAC0_TFW_SFCR_RSRVD0 0xFFFFFE00
+#define BF_ENET_MAC0_TFW_SFCR_RSRVD0(v) \
+ (((v) << 9) & BM_ENET_MAC0_TFW_SFCR_RSRVD0)
+#define BM_ENET_MAC0_TFW_SFCR_STR_FWD 0x00000100
+#define BP_ENET_MAC0_TFW_SFCR_RSRVD1 6
+#define BM_ENET_MAC0_TFW_SFCR_RSRVD1 0x000000C0
+#define BF_ENET_MAC0_TFW_SFCR_RSRVD1(v) \
+ (((v) << 6) & BM_ENET_MAC0_TFW_SFCR_RSRVD1)
+#define BP_ENET_MAC0_TFW_SFCR_TFWR 0
+#define BM_ENET_MAC0_TFW_SFCR_TFWR 0x0000003F
+#define BF_ENET_MAC0_TFW_SFCR_TFWR(v) \
+ (((v) << 0) & BM_ENET_MAC0_TFW_SFCR_TFWR)
+
+#define HW_ENET_MAC0_FRBR (0x00000148)
+
+#define BP_ENET_MAC0_FRBR_RSRVD0 10
+#define BM_ENET_MAC0_FRBR_RSRVD0 0xFFFFFC00
+#define BF_ENET_MAC0_FRBR_RSRVD0(v) \
+ (((v) << 10) & BM_ENET_MAC0_FRBR_RSRVD0)
+#define BP_ENET_MAC0_FRBR_R_BOUND 2
+#define BM_ENET_MAC0_FRBR_R_BOUND 0x000003FC
+#define BF_ENET_MAC0_FRBR_R_BOUND(v) \
+ (((v) << 2) & BM_ENET_MAC0_FRBR_R_BOUND)
+#define BP_ENET_MAC0_FRBR_RSRVD1 0
+#define BM_ENET_MAC0_FRBR_RSRVD1 0x00000003
+#define BF_ENET_MAC0_FRBR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC0_FRBR_RSRVD1)
+
+#define HW_ENET_MAC0_FRSR (0x0000014c)
+
+#define BP_ENET_MAC0_FRSR_RSRVD0 11
+#define BM_ENET_MAC0_FRSR_RSRVD0 0xFFFFF800
+#define BF_ENET_MAC0_FRSR_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_MAC0_FRSR_RSRVD0)
+#define BM_ENET_MAC0_FRSR_RSRVD1 0x00000400
+#define BP_ENET_MAC0_FRSR_R_FSTART 2
+#define BM_ENET_MAC0_FRSR_R_FSTART 0x000003FC
+#define BF_ENET_MAC0_FRSR_R_FSTART(v) \
+ (((v) << 2) & BM_ENET_MAC0_FRSR_R_FSTART)
+#define BP_ENET_MAC0_FRSR_RSRVD2 0
+#define BM_ENET_MAC0_FRSR_RSRVD2 0x00000003
+#define BF_ENET_MAC0_FRSR_RSRVD2(v) \
+ (((v) << 0) & BM_ENET_MAC0_FRSR_RSRVD2)
+
+#define HW_ENET_MAC0_ERDSR (0x0000017c)
+
+#define BP_ENET_MAC0_ERDSR_R_DES_START 2
+#define BM_ENET_MAC0_ERDSR_R_DES_START 0xFFFFFFFC
+#define BF_ENET_MAC0_ERDSR_R_DES_START(v) \
+ (((v) << 2) & BM_ENET_MAC0_ERDSR_R_DES_START)
+#define BP_ENET_MAC0_ERDSR_RSRVD0 0
+#define BM_ENET_MAC0_ERDSR_RSRVD0 0x00000003
+#define BF_ENET_MAC0_ERDSR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_MAC0_ERDSR_RSRVD0)
+
+#define HW_ENET_MAC0_ETDSR (0x00000180)
+
+#define BP_ENET_MAC0_ETDSR_X_DES_START 2
+#define BM_ENET_MAC0_ETDSR_X_DES_START 0xFFFFFFFC
+#define BF_ENET_MAC0_ETDSR_X_DES_START(v) \
+ (((v) << 2) & BM_ENET_MAC0_ETDSR_X_DES_START)
+#define BP_ENET_MAC0_ETDSR_RSRVD0 0
+#define BM_ENET_MAC0_ETDSR_RSRVD0 0x00000003
+#define BF_ENET_MAC0_ETDSR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_MAC0_ETDSR_RSRVD0)
+
+#define HW_ENET_MAC0_EMRBR (0x00000184)
+
+#define BP_ENET_MAC0_EMRBR_RSRVD0 11
+#define BM_ENET_MAC0_EMRBR_RSRVD0 0xFFFFF800
+#define BF_ENET_MAC0_EMRBR_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_MAC0_EMRBR_RSRVD0)
+#define BP_ENET_MAC0_EMRBR_R_BUF_SIZE 4
+#define BM_ENET_MAC0_EMRBR_R_BUF_SIZE 0x000007F0
+#define BF_ENET_MAC0_EMRBR_R_BUF_SIZE(v) \
+ (((v) << 4) & BM_ENET_MAC0_EMRBR_R_BUF_SIZE)
+#define BP_ENET_MAC0_EMRBR_RSRVD1 0
+#define BM_ENET_MAC0_EMRBR_RSRVD1 0x0000000F
+#define BF_ENET_MAC0_EMRBR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC0_EMRBR_RSRVD1)
+
+#define HW_ENET_MAC0_RX_SECTION_FULL (0x0000018c)
+
+#define BP_ENET_MAC0_RX_SECTION_FULL_RSRVD0 8
+#define BM_ENET_MAC0_RX_SECTION_FULL_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_RX_SECTION_FULL_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_RX_SECTION_FULL_RSRVD0)
+#define BP_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL 0
+#define BM_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL 0x000000FF
+#define BF_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL(v) \
+ (((v) << 0) & BM_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL)
+
+#define HW_ENET_MAC0_RX_SECTION_EMPTY (0x00000190)
+
+#define BP_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0 8
+#define BM_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0)
+#define BP_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0
+#define BM_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0x000000FF
+#define BF_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY)
+
+#define HW_ENET_MAC0_RX_ALMOST_EMPTY (0x00000194)
+
+#define BP_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0 8
+#define BM_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0)
+#define BP_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0
+#define BM_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0x000000FF
+#define BF_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY)
+
+#define HW_ENET_MAC0_RX_ALMOST_FULL (0x00000198)
+
+#define BP_ENET_MAC0_RX_ALMOST_FULL_RSRVD0 8
+#define BM_ENET_MAC0_RX_ALMOST_FULL_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_RX_ALMOST_FULL_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_RX_ALMOST_FULL_RSRVD0)
+#define BP_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL 0
+#define BM_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL 0x000000FF
+#define BF_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL(v) \
+ (((v) << 0) & BM_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL)
+
+#define HW_ENET_MAC0_TX_SECTION_EMPTY (0x0000019c)
+
+#define BP_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0 8
+#define BM_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0)
+#define BP_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0
+#define BM_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0x000000FF
+#define BF_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY)
+
+#define HW_ENET_MAC0_TX_ALMOST_EMPTY (0x000001a0)
+
+#define BP_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0 8
+#define BM_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0)
+#define BP_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0
+#define BM_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0x000000FF
+#define BF_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY)
+
+#define HW_ENET_MAC0_TX_ALMOST_FULL (0x000001a4)
+
+#define BP_ENET_MAC0_TX_ALMOST_FULL_RSRVD0 8
+#define BM_ENET_MAC0_TX_ALMOST_FULL_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_TX_ALMOST_FULL_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_TX_ALMOST_FULL_RSRVD0)
+#define BP_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL 0
+#define BM_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL 0x000000FF
+#define BF_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL(v) \
+ (((v) << 0) & BM_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL)
+
+#define HW_ENET_MAC0_TX_IPG_LENGTH (0x000001a8)
+
+#define BP_ENET_MAC0_TX_IPG_LENGTH_RSRVD0 5
+#define BM_ENET_MAC0_TX_IPG_LENGTH_RSRVD0 0xFFFFFFE0
+#define BF_ENET_MAC0_TX_IPG_LENGTH_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_MAC0_TX_IPG_LENGTH_RSRVD0)
+#define BP_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH 0
+#define BM_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH 0x0000001F
+#define BF_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH(v) \
+ (((v) << 0) & BM_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH)
+
+#define HW_ENET_MAC0_TRUNC_FL (0x000001ac)
+
+#define BP_ENET_MAC0_TRUNC_FL_RSRVD0 14
+#define BM_ENET_MAC0_TRUNC_FL_RSRVD0 0xFFFFC000
+#define BF_ENET_MAC0_TRUNC_FL_RSRVD0(v) \
+ (((v) << 14) & BM_ENET_MAC0_TRUNC_FL_RSRVD0)
+#define BP_ENET_MAC0_TRUNC_FL_TRUNC_FL 0
+#define BM_ENET_MAC0_TRUNC_FL_TRUNC_FL 0x00003FFF
+#define BF_ENET_MAC0_TRUNC_FL_TRUNC_FL(v) \
+ (((v) << 0) & BM_ENET_MAC0_TRUNC_FL_TRUNC_FL)
+
+#define HW_ENET_MAC0_IPACCTXCONF (0x000001bc)
+
+#define BP_ENET_MAC0_IPACCTXCONF_RSRVD0 5
+#define BM_ENET_MAC0_IPACCTXCONF_RSRVD0 0xFFFFFFE0
+#define BF_ENET_MAC0_IPACCTXCONF_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_MAC0_IPACCTXCONF_RSRVD0)
+#define BM_ENET_MAC0_IPACCTXCONF_TX_PROTCHK_INS 0x00000010
+#define BM_ENET_MAC0_IPACCTXCONF_TX_IPCHK_INS 0x00000008
+#define BP_ENET_MAC0_IPACCTXCONF_RSRVD1 1
+#define BM_ENET_MAC0_IPACCTXCONF_RSRVD1 0x00000006
+#define BF_ENET_MAC0_IPACCTXCONF_RSRVD1(v) \
+ (((v) << 1) & BM_ENET_MAC0_IPACCTXCONF_RSRVD1)
+#define BM_ENET_MAC0_IPACCTXCONF_SHIFT16 0x00000001
+
+#define HW_ENET_MAC0_IPACCRXCONF (0x000001c0)
+
+#define BP_ENET_MAC0_IPACCRXCONF_RSRVD0 8
+#define BM_ENET_MAC0_IPACCRXCONF_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC0_IPACCRXCONF_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC0_IPACCRXCONF_RSRVD0)
+#define BM_ENET_MAC0_IPACCRXCONF_SHIFT16 0x00000080
+#define BM_ENET_MAC0_IPACCRXCONF_RX_LINEERR_DISC 0x00000040
+#define BP_ENET_MAC0_IPACCRXCONF_RSRVD1 3
+#define BM_ENET_MAC0_IPACCRXCONF_RSRVD1 0x00000038
+#define BF_ENET_MAC0_IPACCRXCONF_RSRVD1(v) \
+ (((v) << 3) & BM_ENET_MAC0_IPACCRXCONF_RSRVD1)
+#define BM_ENET_MAC0_IPACCRXCONF_RX_PROTERR_DISCARD 0x00000004
+#define BM_ENET_MAC0_IPACCRXCONF_RX_IPERR_DISCARD 0x00000002
+#define BM_ENET_MAC0_IPACCRXCONF_RX_IP_PAD_REMOVE 0x00000001
+
+#define HW_ENET_MAC0_RMON_T_DROP (0x000001fc)
+
+#define BP_ENET_MAC0_RMON_T_DROP_RMON_T_DROP 0
+#define BM_ENET_MAC0_RMON_T_DROP_RMON_T_DROP 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_DROP_RMON_T_DROP(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_PACKETS (0x00000200)
+
+#define BP_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS 0
+#define BM_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_BC_PKT (0x00000204)
+
+#define BP_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT 0
+#define BM_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_MC_PKT (0x00000208)
+
+#define BP_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT 0
+#define BM_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_CRC_ALIGN (0x0000020c)
+
+#define BP_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0
+#define BM_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_UNDERSIZE (0x00000210)
+
+#define BP_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0
+#define BM_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_OVERSIZE (0x00000214)
+
+#define BP_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0
+#define BM_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_FRAG (0x00000218)
+
+#define BP_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG 0
+#define BM_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_JAB (0x0000021c)
+
+#define BP_ENET_MAC0_RMON_T_JAB_RMON_T_JAB 0
+#define BM_ENET_MAC0_RMON_T_JAB_RMON_T_JAB 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_JAB_RMON_T_JAB(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_COL (0x00000220)
+
+#define BP_ENET_MAC0_RMON_T_COL_RMON_T_COL 0
+#define BM_ENET_MAC0_RMON_T_COL_RMON_T_COL 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_COL_RMON_T_COL(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P64 (0x00000224)
+
+#define BP_ENET_MAC0_RMON_T_P64_RMON_T_P64 0
+#define BM_ENET_MAC0_RMON_T_P64_RMON_T_P64 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P64_RMON_T_P64(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P65TO127N (0x00000228)
+
+#define BP_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N 0
+#define BM_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P128TO255N (0x0000022c)
+
+#define BP_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N 0
+#define BM_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P256TO511 (0x00000230)
+
+#define BP_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511 0
+#define BM_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P512TO1023 (0x00000234)
+
+#define BP_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023 0
+#define BM_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P1024TO2047 (0x00000238)
+
+#define BP_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0
+#define BM_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_P_GTE2048 (0x0000023c)
+
+#define BP_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0
+#define BM_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048(v) (v)
+
+#define HW_ENET_MAC0_RMON_T_OCTETS (0x00000240)
+
+#define BP_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS 0
+#define BM_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_DROP (0x00000244)
+
+#define BP_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP 0
+#define BM_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_FRAME_OK (0x00000248)
+
+#define BP_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0
+#define BM_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_1COL (0x0000024c)
+
+#define BP_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL 0
+#define BM_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_MCOL (0x00000250)
+
+#define BP_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL 0
+#define BM_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_DEF (0x00000254)
+
+#define BP_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF 0
+#define BM_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_LCOL (0x00000258)
+
+#define BP_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL 0
+#define BM_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_EXCOL (0x0000025c)
+
+#define BP_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL 0
+#define BM_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_MACERR (0x00000260)
+
+#define BP_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR 0
+#define BM_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_CSERR (0x00000264)
+
+#define BP_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR 0
+#define BM_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_SQE (0x00000268)
+
+#define BP_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE 0
+#define BM_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_FDXFC (0x0000026c)
+
+#define BP_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC 0
+#define BM_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC(v) (v)
+
+#define HW_ENET_MAC0_IEEE_T_OCTETS_OK (0x00000270)
+
+#define BP_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0
+#define BM_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_PACKETS (0x00000280)
+
+#define BP_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS 0
+#define BM_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_BC_PKT (0x00000284)
+
+#define BP_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT 0
+#define BM_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_MC_PKT (0x00000288)
+
+#define BP_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT 0
+#define BM_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_CRC_ALIGN (0x0000028c)
+
+#define BP_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0
+#define BM_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_UNDERSIZE (0x00000290)
+
+#define BP_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0
+#define BM_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_OVERSIZE (0x00000294)
+
+#define BP_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0
+#define BM_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_FRAG (0x00000298)
+
+#define BP_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG 0
+#define BM_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_JAB (0x0000029c)
+
+#define BP_ENET_MAC0_RMON_R_JAB_RMON_R_JAB 0
+#define BM_ENET_MAC0_RMON_R_JAB_RMON_R_JAB 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_JAB_RMON_R_JAB(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P64 (0x000002a4)
+
+#define BP_ENET_MAC0_RMON_R_P64_RMON_R_P64 0
+#define BM_ENET_MAC0_RMON_R_P64_RMON_R_P64 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P64_RMON_R_P64(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P65TO127 (0x000002a8)
+
+#define BP_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127 0
+#define BM_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P128TO255 (0x000002ac)
+
+#define BP_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255 0
+#define BM_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P256TO511 (0x000002b0)
+
+#define BP_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511 0
+#define BM_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P512TO1023 (0x000002b4)
+
+#define BP_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023 0
+#define BM_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P1024TO2047 (0x000002b8)
+
+#define BP_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0
+#define BM_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_P_GTE2048 (0x000002bc)
+
+#define BP_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0
+#define BM_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048(v) (v)
+
+#define HW_ENET_MAC0_RMON_R_OCTETS (0x000002c0)
+
+#define BP_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS 0
+#define BM_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS 0xFFFFFFFF
+#define BF_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_DROP (0x000002c4)
+
+#define BP_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP 0
+#define BM_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_FRAME_OK (0x000002c8)
+
+#define BP_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0
+#define BM_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_CRC (0x000002cc)
+
+#define BP_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC 0
+#define BM_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_ALIGN (0x000002d0)
+
+#define BP_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN 0
+#define BM_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_MACERR (0x000002d4)
+
+#define BP_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR 0
+#define BM_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_FDXFC (0x000002d8)
+
+#define BP_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC 0
+#define BM_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC(v) (v)
+
+#define HW_ENET_MAC0_IEEE_R_OCTETS_OK (0x000002dc)
+
+#define BP_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0
+#define BM_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0xFFFFFFFF
+#define BF_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK(v) (v)
+
+#define HW_ENET_MAC0_ATIME_CTRL (0x000003fc)
+
+#define BP_ENET_MAC0_ATIME_CTRL_RSRVD0 14
+#define BM_ENET_MAC0_ATIME_CTRL_RSRVD0 0xFFFFC000
+#define BF_ENET_MAC0_ATIME_CTRL_RSRVD0(v) \
+ (((v) << 14) & BM_ENET_MAC0_ATIME_CTRL_RSRVD0)
+#define BM_ENET_MAC0_ATIME_CTRL_FRC_SLAVE 0x00002000
+#define BM_ENET_MAC0_ATIME_CTRL_RSRVD1 0x00001000
+#define BM_ENET_MAC0_ATIME_CTRL_CAPTURE 0x00000800
+#define BM_ENET_MAC0_ATIME_CTRL_RSRVD2 0x00000400
+#define BM_ENET_MAC0_ATIME_CTRL_RESTART 0x00000200
+#define BM_ENET_MAC0_ATIME_CTRL_RSRVD3 0x00000100
+#define BM_ENET_MAC0_ATIME_CTRL_PIN_PERIOD_ENA 0x00000080
+#define BM_ENET_MAC0_ATIME_CTRL_RSRVD4 0x00000040
+#define BM_ENET_MAC0_ATIME_CTRL_EVT_PERIOD_RST 0x00000020
+#define BM_ENET_MAC0_ATIME_CTRL_EVT_PERIOD_ENA 0x00000010
+#define BM_ENET_MAC0_ATIME_CTRL_EVT_OFFSET_RST 0x00000008
+#define BM_ENET_MAC0_ATIME_CTRL_EVT_OFFSET_ENA 0x00000004
+#define BM_ENET_MAC0_ATIME_CTRL_ONE_SHOT 0x00000002
+#define BM_ENET_MAC0_ATIME_CTRL_ENABLE 0x00000001
+
+#define HW_ENET_MAC0_ATIME (0x00000400)
+
+#define BP_ENET_MAC0_ATIME_ATIME 0
+#define BM_ENET_MAC0_ATIME_ATIME 0xFFFFFFFF
+#define BF_ENET_MAC0_ATIME_ATIME(v) (v)
+
+#define HW_ENET_MAC0_ATIME_EVT_OFFSET (0x00000404)
+
+#define BP_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0
+#define BM_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0xFFFFFFFF
+#define BF_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET(v) (v)
+
+#define HW_ENET_MAC0_ATIME_EVT_PERIOD (0x00000408)
+
+#define BP_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0
+#define BM_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0xFFFFFFFF
+#define BF_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD(v) (v)
+
+#define HW_ENET_MAC0_ATIME_CORR (0x0000040c)
+
+#define BM_ENET_MAC0_ATIME_CORR_RSRVD0 0x80000000
+#define BP_ENET_MAC0_ATIME_CORR_ATIME_CORR 0
+#define BM_ENET_MAC0_ATIME_CORR_ATIME_CORR 0x7FFFFFFF
+#define BF_ENET_MAC0_ATIME_CORR_ATIME_CORR(v) \
+ (((v) << 0) & BM_ENET_MAC0_ATIME_CORR_ATIME_CORR)
+
+#define HW_ENET_MAC0_ATIME_INC (0x00000410)
+
+#define BP_ENET_MAC0_ATIME_INC_RSRVD0 15
+#define BM_ENET_MAC0_ATIME_INC_RSRVD0 0xFFFF8000
+#define BF_ENET_MAC0_ATIME_INC_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_MAC0_ATIME_INC_RSRVD0)
+#define BP_ENET_MAC0_ATIME_INC_ATIME_INC_CORR 8
+#define BM_ENET_MAC0_ATIME_INC_ATIME_INC_CORR 0x00007F00
+#define BF_ENET_MAC0_ATIME_INC_ATIME_INC_CORR(v) \
+ (((v) << 8) & BM_ENET_MAC0_ATIME_INC_ATIME_INC_CORR)
+#define BM_ENET_MAC0_ATIME_INC_RSRVD1 0x00000080
+#define BP_ENET_MAC0_ATIME_INC_ATIME_INC 0
+#define BM_ENET_MAC0_ATIME_INC_ATIME_INC 0x0000007F
+#define BF_ENET_MAC0_ATIME_INC_ATIME_INC(v) \
+ (((v) << 0) & BM_ENET_MAC0_ATIME_INC_ATIME_INC)
+
+#define HW_ENET_MAC0_TS_TIMESTAMP (0x00000414)
+
+#define BP_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP 0
+#define BM_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP 0xFFFFFFFF
+#define BF_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP(v) (v)
+
+#define HW_ENET_MAC0_SMAC_0_0 (0x000004fc)
+
+#define BP_ENET_MAC0_SMAC_0_0_SMAC_0_0 0
+#define BM_ENET_MAC0_SMAC_0_0_SMAC_0_0 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_0_0_SMAC_0_0(v) (v)
+
+#define HW_ENET_MAC0_SMAC_0_1 (0x00000500)
+
+#define BP_ENET_MAC0_SMAC_0_1_SMAC_0_1 0
+#define BM_ENET_MAC0_SMAC_0_1_SMAC_0_1 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_0_1_SMAC_0_1(v) (v)
+
+#define HW_ENET_MAC0_SMAC_1_0 (0x00000504)
+
+#define BP_ENET_MAC0_SMAC_1_0_SMAC_1_0 0
+#define BM_ENET_MAC0_SMAC_1_0_SMAC_1_0 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_1_0_SMAC_1_0(v) (v)
+
+#define HW_ENET_MAC0_SMAC_1_1 (0x00000508)
+
+#define BP_ENET_MAC0_SMAC_1_1_SMAC_1_1 0
+#define BM_ENET_MAC0_SMAC_1_1_SMAC_1_1 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_1_1_SMAC_1_1(v) (v)
+
+#define HW_ENET_MAC0_SMAC_2_0 (0x0000050c)
+
+#define BP_ENET_MAC0_SMAC_2_0_SMAC_2_0 0
+#define BM_ENET_MAC0_SMAC_2_0_SMAC_2_0 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_2_0_SMAC_2_0(v) (v)
+
+#define HW_ENET_MAC0_SMAC_2_1 (0x00000510)
+
+#define BP_ENET_MAC0_SMAC_2_1_SMAC_2_1 0
+#define BM_ENET_MAC0_SMAC_2_1_SMAC_2_1 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_2_1_SMAC_2_1(v) (v)
+
+#define HW_ENET_MAC0_SMAC_3_0 (0x00000514)
+
+#define BP_ENET_MAC0_SMAC_3_0_SMAC_3_0 0
+#define BM_ENET_MAC0_SMAC_3_0_SMAC_3_0 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_3_0_SMAC_3_0(v) (v)
+
+#define HW_ENET_MAC0_SMAC_3_1 (0x00000518)
+
+#define BP_ENET_MAC0_SMAC_3_1_SMAC_3_1 0
+#define BM_ENET_MAC0_SMAC_3_1_SMAC_3_1 0xFFFFFFFF
+#define BF_ENET_MAC0_SMAC_3_1_SMAC_3_1(v) (v)
+
+#define HW_ENET_MAC0_COMP_REG_0 (0x000005fc)
+
+#define BP_ENET_MAC0_COMP_REG_0_COMP_REG_0 0
+#define BM_ENET_MAC0_COMP_REG_0_COMP_REG_0 0xFFFFFFFF
+#define BF_ENET_MAC0_COMP_REG_0_COMP_REG_0(v) (v)
+
+#define HW_ENET_MAC0_COMP_REG_1 (0x00000600)
+
+#define BP_ENET_MAC0_COMP_REG_1_COMP_REG_1 0
+#define BM_ENET_MAC0_COMP_REG_1_COMP_REG_1 0xFFFFFFFF
+#define BF_ENET_MAC0_COMP_REG_1_COMP_REG_1(v) (v)
+
+#define HW_ENET_MAC0_COMP_REG_2 (0x00000604)
+
+#define BP_ENET_MAC0_COMP_REG_2_COMP_REG_2 0
+#define BM_ENET_MAC0_COMP_REG_2_COMP_REG_2 0xFFFFFFFF
+#define BF_ENET_MAC0_COMP_REG_2_COMP_REG_2(v) (v)
+
+#define HW_ENET_MAC0_COMP_REG_3 (0x00000608)
+
+#define BP_ENET_MAC0_COMP_REG_3_COMP_REG_3 0
+#define BM_ENET_MAC0_COMP_REG_3_COMP_REG_3 0xFFFFFFFF
+#define BF_ENET_MAC0_COMP_REG_3_COMP_REG_3(v) (v)
+
+#define HW_ENET_MAC0_CAPT_REG_0 (0x0000063c)
+
+#define BP_ENET_MAC0_CAPT_REG_0_CAPT_REG_0 0
+#define BM_ENET_MAC0_CAPT_REG_0_CAPT_REG_0 0xFFFFFFFF
+#define BF_ENET_MAC0_CAPT_REG_0_CAPT_REG_0(v) (v)
+
+#define HW_ENET_MAC0_CAPT_REG_1 (0x00000640)
+
+#define BP_ENET_MAC0_CAPT_REG_1_CAPT_REG_1 0
+#define BM_ENET_MAC0_CAPT_REG_1_CAPT_REG_1 0xFFFFFFFF
+#define BF_ENET_MAC0_CAPT_REG_1_CAPT_REG_1(v) (v)
+
+#define HW_ENET_MAC0_CAPT_REG_2 (0x00000644)
+
+#define BP_ENET_MAC0_CAPT_REG_2_CAPT_REG_2 0
+#define BM_ENET_MAC0_CAPT_REG_2_CAPT_REG_2 0xFFFFFFFF
+#define BF_ENET_MAC0_CAPT_REG_2_CAPT_REG_2(v) (v)
+
+#define HW_ENET_MAC0_CAPT_REG_3 (0x00000648)
+
+#define BP_ENET_MAC0_CAPT_REG_3_CAPT_REG_3 0
+#define BM_ENET_MAC0_CAPT_REG_3_CAPT_REG_3 0xFFFFFFFF
+#define BF_ENET_MAC0_CAPT_REG_3_CAPT_REG_3(v) (v)
+
+#define HW_ENET_MAC0_CCB_INT (0x0000067c)
+
+#define BP_ENET_MAC0_CCB_INT_RSRVD0 20
+#define BM_ENET_MAC0_CCB_INT_RSRVD0 0xFFF00000
+#define BF_ENET_MAC0_CCB_INT_RSRVD0(v) \
+ (((v) << 20) & BM_ENET_MAC0_CCB_INT_RSRVD0)
+#define BM_ENET_MAC0_CCB_INT_COMPARE3 0x00080000
+#define BM_ENET_MAC0_CCB_INT_COMPARE2 0x00040000
+#define BM_ENET_MAC0_CCB_INT_COMPARE1 0x00020000
+#define BM_ENET_MAC0_CCB_INT_COMPARE0 0x00010000
+#define BP_ENET_MAC0_CCB_INT_RSRVD1 4
+#define BM_ENET_MAC0_CCB_INT_RSRVD1 0x0000FFF0
+#define BF_ENET_MAC0_CCB_INT_RSRVD1(v) \
+ (((v) << 4) & BM_ENET_MAC0_CCB_INT_RSRVD1)
+#define BM_ENET_MAC0_CCB_INT_CAPTURE3 0x00000008
+#define BM_ENET_MAC0_CCB_INT_CAPTURE2 0x00000004
+#define BM_ENET_MAC0_CCB_INT_CAPTURE1 0x00000002
+#define BM_ENET_MAC0_CCB_INT_CAPTURE0 0x00000001
+
+#define HW_ENET_MAC0_CCB_INT_MASK (0x00000680)
+
+#define BP_ENET_MAC0_CCB_INT_MASK_RSRVD0 20
+#define BM_ENET_MAC0_CCB_INT_MASK_RSRVD0 0xFFF00000
+#define BF_ENET_MAC0_CCB_INT_MASK_RSRVD0(v) \
+ (((v) << 20) & BM_ENET_MAC0_CCB_INT_MASK_RSRVD0)
+#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE3 0x00080000
+#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE2 0x00040000
+#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE1 0x00020000
+#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE0 0x00010000
+#define BP_ENET_MAC0_CCB_INT_MASK_RSRVD1 4
+#define BM_ENET_MAC0_CCB_INT_MASK_RSRVD1 0x0000FFF0
+#define BF_ENET_MAC0_CCB_INT_MASK_RSRVD1(v) \
+ (((v) << 4) & BM_ENET_MAC0_CCB_INT_MASK_RSRVD1)
+#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE3 0x00000008
+#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE2 0x00000004
+#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE1 0x00000002
+#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE0 0x00000001
+
+#define HW_ENET_MAC1_EIR (0x00004000)
+
+#define BM_ENET_MAC1_EIR_RSRVD0 0x80000000
+#define BM_ENET_MAC1_EIR_BABR 0x40000000
+#define BM_ENET_MAC1_EIR_BABT 0x20000000
+#define BM_ENET_MAC1_EIR_GRA 0x10000000
+#define BM_ENET_MAC1_EIR_TXF 0x08000000
+#define BM_ENET_MAC1_EIR_TXB 0x04000000
+#define BM_ENET_MAC1_EIR_RXF 0x02000000
+#define BM_ENET_MAC1_EIR_RXB 0x01000000
+#define BM_ENET_MAC1_EIR_MII 0x00800000
+#define BM_ENET_MAC1_EIR_EBERR 0x00400000
+#define BM_ENET_MAC1_EIR_LC 0x00200000
+#define BM_ENET_MAC1_EIR_RL 0x00100000
+#define BM_ENET_MAC1_EIR_UN 0x00080000
+#define BM_ENET_MAC1_EIR_PLR 0x00040000
+#define BM_ENET_MAC1_EIR_WAKEUP 0x00020000
+#define BM_ENET_MAC1_EIR_TS_AVAIL 0x00010000
+#define BM_ENET_MAC1_EIR_TS_TIMER 0x00008000
+#define BP_ENET_MAC1_EIR_RSRVD1 0
+#define BM_ENET_MAC1_EIR_RSRVD1 0x00007FFF
+#define BF_ENET_MAC1_EIR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC1_EIR_RSRVD1)
+
+#define HW_ENET_MAC1_EIMR (0x00004004)
+
+#define BP_ENET_MAC1_EIMR_EIMR 0
+#define BM_ENET_MAC1_EIMR_EIMR 0xFFFFFFFF
+#define BF_ENET_MAC1_EIMR_EIMR(v) (v)
+
+#define HW_ENET_MAC1_RDAR (0x0000400c)
+
+#define BP_ENET_MAC1_RDAR_RSRVD0 25
+#define BM_ENET_MAC1_RDAR_RSRVD0 0xFE000000
+#define BF_ENET_MAC1_RDAR_RSRVD0(v) \
+ (((v) << 25) & BM_ENET_MAC1_RDAR_RSRVD0)
+#define BM_ENET_MAC1_RDAR_RDAR 0x01000000
+#define BP_ENET_MAC1_RDAR_RSRVD1 0
+#define BM_ENET_MAC1_RDAR_RSRVD1 0x00FFFFFF
+#define BF_ENET_MAC1_RDAR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC1_RDAR_RSRVD1)
+
+#define HW_ENET_MAC1_TDAR (0x00004010)
+
+#define BP_ENET_MAC1_TDAR_RSRVD0 25
+#define BM_ENET_MAC1_TDAR_RSRVD0 0xFE000000
+#define BF_ENET_MAC1_TDAR_RSRVD0(v) \
+ (((v) << 25) & BM_ENET_MAC1_TDAR_RSRVD0)
+#define BM_ENET_MAC1_TDAR_TDAR 0x01000000
+#define BP_ENET_MAC1_TDAR_RSRVD1 0
+#define BM_ENET_MAC1_TDAR_RSRVD1 0x00FFFFFF
+#define BF_ENET_MAC1_TDAR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC1_TDAR_RSRVD1)
+
+#define HW_ENET_MAC1_ECR (0x00004020)
+
+#define BP_ENET_MAC1_ECR_RSRVD0 7
+#define BM_ENET_MAC1_ECR_RSRVD0 0xFFFFFF80
+#define BF_ENET_MAC1_ECR_RSRVD0(v) \
+ (((v) << 7) & BM_ENET_MAC1_ECR_RSRVD0)
+#define BM_ENET_MAC1_ECR_DBG_EN 0x00000040
+#define BM_ENET_MAC1_ECR_ETH_SPEED 0x00000020
+#define BM_ENET_MAC1_ECR_ENA_1588 0x00000010
+#define BM_ENET_MAC1_ECR_SLEEP 0x00000008
+#define BM_ENET_MAC1_ECR_MAGIC_ENA 0x00000004
+#define BM_ENET_MAC1_ECR_ETHER_EN 0x00000002
+#define BM_ENET_MAC1_ECR_RESET 0x00000001
+
+#define HW_ENET_MAC1_MMFR (0x0000403c)
+
+#define BP_ENET_MAC1_MMFR_ST 30
+#define BM_ENET_MAC1_MMFR_ST 0xC0000000
+#define BF_ENET_MAC1_MMFR_ST(v) \
+ (((v) << 30) & BM_ENET_MAC1_MMFR_ST)
+#define BP_ENET_MAC1_MMFR_OP 28
+#define BM_ENET_MAC1_MMFR_OP 0x30000000
+#define BF_ENET_MAC1_MMFR_OP(v) \
+ (((v) << 28) & BM_ENET_MAC1_MMFR_OP)
+#define BP_ENET_MAC1_MMFR_PA 23
+#define BM_ENET_MAC1_MMFR_PA 0x0F800000
+#define BF_ENET_MAC1_MMFR_PA(v) \
+ (((v) << 23) & BM_ENET_MAC1_MMFR_PA)
+#define BP_ENET_MAC1_MMFR_RA 18
+#define BM_ENET_MAC1_MMFR_RA 0x007C0000
+#define BF_ENET_MAC1_MMFR_RA(v) \
+ (((v) << 18) & BM_ENET_MAC1_MMFR_RA)
+#define BP_ENET_MAC1_MMFR_TA 16
+#define BM_ENET_MAC1_MMFR_TA 0x00030000
+#define BF_ENET_MAC1_MMFR_TA(v) \
+ (((v) << 16) & BM_ENET_MAC1_MMFR_TA)
+#define BP_ENET_MAC1_MMFR_DATA 0
+#define BM_ENET_MAC1_MMFR_DATA 0x0000FFFF
+#define BF_ENET_MAC1_MMFR_DATA(v) \
+ (((v) << 0) & BM_ENET_MAC1_MMFR_DATA)
+
+#define HW_ENET_MAC1_MSCR (0x00004040)
+
+#define BP_ENET_MAC1_MSCR_RSRVD0 11
+#define BM_ENET_MAC1_MSCR_RSRVD0 0xFFFFF800
+#define BF_ENET_MAC1_MSCR_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_MAC1_MSCR_RSRVD0)
+#define BP_ENET_MAC1_MSCR_HOLDTIME 8
+#define BM_ENET_MAC1_MSCR_HOLDTIME 0x00000700
+#define BF_ENET_MAC1_MSCR_HOLDTIME(v) \
+ (((v) << 8) & BM_ENET_MAC1_MSCR_HOLDTIME)
+#define BM_ENET_MAC1_MSCR_DIS_PRE 0x00000080
+#define BP_ENET_MAC1_MSCR_MII_SPEED 1
+#define BM_ENET_MAC1_MSCR_MII_SPEED 0x0000007E
+#define BF_ENET_MAC1_MSCR_MII_SPEED(v) \
+ (((v) << 1) & BM_ENET_MAC1_MSCR_MII_SPEED)
+#define BM_ENET_MAC1_MSCR_RSRVD1 0x00000001
+
+#define HW_ENET_MAC1_MIBC (0x00004060)
+
+#define BM_ENET_MAC1_MIBC_MIB_DIS 0x80000000
+#define BM_ENET_MAC1_MIBC_MIB_IDLE 0x40000000
+#define BM_ENET_MAC1_MIBC_MIB_CLEAR 0x20000000
+#define BP_ENET_MAC1_MIBC_RSRVD0 0
+#define BM_ENET_MAC1_MIBC_RSRVD0 0x1FFFFFFF
+#define BF_ENET_MAC1_MIBC_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_MAC1_MIBC_RSRVD0)
+
+#define HW_ENET_MAC1_RCR (0x00004080)
+
+#define BM_ENET_MAC1_RCR_GRS 0x80000000
+#define BM_ENET_MAC1_RCR_NO_LGTH_CHECK 0x40000000
+#define BP_ENET_MAC1_RCR_MAX_FL 16
+#define BM_ENET_MAC1_RCR_MAX_FL 0x3FFF0000
+#define BF_ENET_MAC1_RCR_MAX_FL(v) \
+ (((v) << 16) & BM_ENET_MAC1_RCR_MAX_FL)
+#define BM_ENET_MAC1_RCR_CNTL_FRM_ENA 0x00008000
+#define BM_ENET_MAC1_RCR_CRC_FWD 0x00004000
+#define BM_ENET_MAC1_RCR_PAUSE_FWD 0x00002000
+#define BM_ENET_MAC1_RCR_PAD_EN 0x00001000
+#define BM_ENET_MAC1_RCR_RMII_ECHO 0x00000800
+#define BM_ENET_MAC1_RCR_RMII_LOOP 0x00000400
+#define BM_ENET_MAC1_RCR_RMII_10T 0x00000200
+#define BM_ENET_MAC1_RCR_RMII_MODE 0x00000100
+#define BM_ENET_MAC1_RCR_SGMII_ENA 0x00000080
+#define BM_ENET_MAC1_RCR_RGMII_ENA 0x00000040
+#define BM_ENET_MAC1_RCR_FCE 0x00000020
+#define BM_ENET_MAC1_RCR_BC_REJ 0x00000010
+#define BM_ENET_MAC1_RCR_PROM 0x00000008
+#define BM_ENET_MAC1_RCR_MII_MODE 0x00000004
+#define BM_ENET_MAC1_RCR_DRT 0x00000002
+#define BM_ENET_MAC1_RCR_LOOP 0x00000001
+
+#define HW_ENET_MAC1_TCR (0x000040c0)
+
+#define BP_ENET_MAC1_TCR_RSRVD0 10
+#define BM_ENET_MAC1_TCR_RSRVD0 0xFFFFFC00
+#define BF_ENET_MAC1_TCR_RSRVD0(v) \
+ (((v) << 10) & BM_ENET_MAC1_TCR_RSRVD0)
+#define BM_ENET_MAC1_TCR_TX_CRC_FWD 0x00000200
+#define BM_ENET_MAC1_TCR_TX_ADDR_INS 0x00000100
+#define BP_ENET_MAC1_TCR_TX_ADDR_SEL 5
+#define BM_ENET_MAC1_TCR_TX_ADDR_SEL 0x000000E0
+#define BF_ENET_MAC1_TCR_TX_ADDR_SEL(v) \
+ (((v) << 5) & BM_ENET_MAC1_TCR_TX_ADDR_SEL)
+#define BM_ENET_MAC1_TCR_RFC_PAUSE 0x00000010
+#define BM_ENET_MAC1_TCR_TFC_PAUSE 0x00000008
+#define BM_ENET_MAC1_TCR_FEDN 0x00000004
+#define BM_ENET_MAC1_TCR_HBC 0x00000002
+#define BM_ENET_MAC1_TCR_GTS 0x00000001
+
+#define HW_ENET_MAC1_PALR (0x000040e0)
+
+#define BP_ENET_MAC1_PALR_PADDR1 0
+#define BM_ENET_MAC1_PALR_PADDR1 0xFFFFFFFF
+#define BF_ENET_MAC1_PALR_PADDR1(v) (v)
+
+#define HW_ENET_MAC1_PAUR (0x000040e4)
+
+#define BP_ENET_MAC1_PAUR_PADDR2 16
+#define BM_ENET_MAC1_PAUR_PADDR2 0xFFFF0000
+#define BF_ENET_MAC1_PAUR_PADDR2(v) \
+ (((v) << 16) & BM_ENET_MAC1_PAUR_PADDR2)
+#define BP_ENET_MAC1_PAUR_TYPE 0
+#define BM_ENET_MAC1_PAUR_TYPE 0x0000FFFF
+#define BF_ENET_MAC1_PAUR_TYPE(v) \
+ (((v) << 0) & BM_ENET_MAC1_PAUR_TYPE)
+
+#define HW_ENET_MAC1_OPD (0x000040e8)
+
+#define BP_ENET_MAC1_OPD_OPCODE 16
+#define BM_ENET_MAC1_OPD_OPCODE 0xFFFF0000
+#define BF_ENET_MAC1_OPD_OPCODE(v) \
+ (((v) << 16) & BM_ENET_MAC1_OPD_OPCODE)
+#define BP_ENET_MAC1_OPD_PAUSE_DUR 0
+#define BM_ENET_MAC1_OPD_PAUSE_DUR 0x0000FFFF
+#define BF_ENET_MAC1_OPD_PAUSE_DUR(v) \
+ (((v) << 0) & BM_ENET_MAC1_OPD_PAUSE_DUR)
+
+#define HW_ENET_MAC1_IAUR (0x00004114)
+
+#define BP_ENET_MAC1_IAUR_IADDR1 0
+#define BM_ENET_MAC1_IAUR_IADDR1 0xFFFFFFFF
+#define BF_ENET_MAC1_IAUR_IADDR1(v) (v)
+
+#define HW_ENET_MAC1_IALR (0x00004118)
+
+#define BP_ENET_MAC1_IALR_IADDR2 0
+#define BM_ENET_MAC1_IALR_IADDR2 0xFFFFFFFF
+#define BF_ENET_MAC1_IALR_IADDR2(v) (v)
+
+#define HW_ENET_MAC1_GAUR (0x0000411c)
+
+#define BP_ENET_MAC1_GAUR_GADDR1 0
+#define BM_ENET_MAC1_GAUR_GADDR1 0xFFFFFFFF
+#define BF_ENET_MAC1_GAUR_GADDR1(v) (v)
+
+#define HW_ENET_MAC1_GALR (0x00004120)
+
+#define BP_ENET_MAC1_GALR_GADDR2 0
+#define BM_ENET_MAC1_GALR_GADDR2 0xFFFFFFFF
+#define BF_ENET_MAC1_GALR_GADDR2(v) (v)
+
+#define HW_ENET_MAC1_TFW_SFCR (0x00004140)
+
+#define BP_ENET_MAC1_TFW_SFCR_RSRVD0 9
+#define BM_ENET_MAC1_TFW_SFCR_RSRVD0 0xFFFFFE00
+#define BF_ENET_MAC1_TFW_SFCR_RSRVD0(v) \
+ (((v) << 9) & BM_ENET_MAC1_TFW_SFCR_RSRVD0)
+#define BM_ENET_MAC1_TFW_SFCR_STR_FWD 0x00000100
+#define BP_ENET_MAC1_TFW_SFCR_RSRVD1 6
+#define BM_ENET_MAC1_TFW_SFCR_RSRVD1 0x000000C0
+#define BF_ENET_MAC1_TFW_SFCR_RSRVD1(v) \
+ (((v) << 6) & BM_ENET_MAC1_TFW_SFCR_RSRVD1)
+#define BP_ENET_MAC1_TFW_SFCR_TFWR 0
+#define BM_ENET_MAC1_TFW_SFCR_TFWR 0x0000003F
+#define BF_ENET_MAC1_TFW_SFCR_TFWR(v) \
+ (((v) << 0) & BM_ENET_MAC1_TFW_SFCR_TFWR)
+
+#define HW_ENET_MAC1_FRBR (0x00004148)
+
+#define BP_ENET_MAC1_FRBR_RSRVD0 10
+#define BM_ENET_MAC1_FRBR_RSRVD0 0xFFFFFC00
+#define BF_ENET_MAC1_FRBR_RSRVD0(v) \
+ (((v) << 10) & BM_ENET_MAC1_FRBR_RSRVD0)
+#define BP_ENET_MAC1_FRBR_R_BOUND 2
+#define BM_ENET_MAC1_FRBR_R_BOUND 0x000003FC
+#define BF_ENET_MAC1_FRBR_R_BOUND(v) \
+ (((v) << 2) & BM_ENET_MAC1_FRBR_R_BOUND)
+#define BP_ENET_MAC1_FRBR_RSRVD1 0
+#define BM_ENET_MAC1_FRBR_RSRVD1 0x00000003
+#define BF_ENET_MAC1_FRBR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC1_FRBR_RSRVD1)
+
+#define HW_ENET_MAC1_FRSR (0x0000414c)
+
+#define BP_ENET_MAC1_FRSR_RSRVD0 11
+#define BM_ENET_MAC1_FRSR_RSRVD0 0xFFFFF800
+#define BF_ENET_MAC1_FRSR_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_MAC1_FRSR_RSRVD0)
+#define BM_ENET_MAC1_FRSR_RSRVD1 0x00000400
+#define BP_ENET_MAC1_FRSR_R_FSTART 2
+#define BM_ENET_MAC1_FRSR_R_FSTART 0x000003FC
+#define BF_ENET_MAC1_FRSR_R_FSTART(v) \
+ (((v) << 2) & BM_ENET_MAC1_FRSR_R_FSTART)
+#define BP_ENET_MAC1_FRSR_RSRVD2 0
+#define BM_ENET_MAC1_FRSR_RSRVD2 0x00000003
+#define BF_ENET_MAC1_FRSR_RSRVD2(v) \
+ (((v) << 0) & BM_ENET_MAC1_FRSR_RSRVD2)
+
+#define HW_ENET_MAC1_ERDSR (0x0000417c)
+
+#define BP_ENET_MAC1_ERDSR_R_DES_START 2
+#define BM_ENET_MAC1_ERDSR_R_DES_START 0xFFFFFFFC
+#define BF_ENET_MAC1_ERDSR_R_DES_START(v) \
+ (((v) << 2) & BM_ENET_MAC1_ERDSR_R_DES_START)
+#define BP_ENET_MAC1_ERDSR_RSRVD0 0
+#define BM_ENET_MAC1_ERDSR_RSRVD0 0x00000003
+#define BF_ENET_MAC1_ERDSR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_MAC1_ERDSR_RSRVD0)
+
+#define HW_ENET_MAC1_ETDSR (0x00004180)
+
+#define BP_ENET_MAC1_ETDSR_X_DES_START 2
+#define BM_ENET_MAC1_ETDSR_X_DES_START 0xFFFFFFFC
+#define BF_ENET_MAC1_ETDSR_X_DES_START(v) \
+ (((v) << 2) & BM_ENET_MAC1_ETDSR_X_DES_START)
+#define BP_ENET_MAC1_ETDSR_RSRVD0 0
+#define BM_ENET_MAC1_ETDSR_RSRVD0 0x00000003
+#define BF_ENET_MAC1_ETDSR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_MAC1_ETDSR_RSRVD0)
+
+#define HW_ENET_MAC1_EMRBR (0x00004184)
+
+#define BP_ENET_MAC1_EMRBR_RSRVD0 11
+#define BM_ENET_MAC1_EMRBR_RSRVD0 0xFFFFF800
+#define BF_ENET_MAC1_EMRBR_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_MAC1_EMRBR_RSRVD0)
+#define BP_ENET_MAC1_EMRBR_R_BUF_SIZE 4
+#define BM_ENET_MAC1_EMRBR_R_BUF_SIZE 0x000007F0
+#define BF_ENET_MAC1_EMRBR_R_BUF_SIZE(v) \
+ (((v) << 4) & BM_ENET_MAC1_EMRBR_R_BUF_SIZE)
+#define BP_ENET_MAC1_EMRBR_RSRVD1 0
+#define BM_ENET_MAC1_EMRBR_RSRVD1 0x0000000F
+#define BF_ENET_MAC1_EMRBR_RSRVD1(v) \
+ (((v) << 0) & BM_ENET_MAC1_EMRBR_RSRVD1)
+
+#define HW_ENET_MAC1_RX_SECTION_FULL (0x0000418c)
+
+#define BP_ENET_MAC1_RX_SECTION_FULL_RSRVD0 8
+#define BM_ENET_MAC1_RX_SECTION_FULL_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_RX_SECTION_FULL_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_RX_SECTION_FULL_RSRVD0)
+#define BP_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL 0
+#define BM_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL 0x000000FF
+#define BF_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL(v) \
+ (((v) << 0) & BM_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL)
+
+#define HW_ENET_MAC1_RX_SECTION_EMPTY (0x00004190)
+
+#define BP_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0 8
+#define BM_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0)
+#define BP_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0
+#define BM_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0x000000FF
+#define BF_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY)
+
+#define HW_ENET_MAC1_RX_ALMOST_EMPTY (0x00004194)
+
+#define BP_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0 8
+#define BM_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0)
+#define BP_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0
+#define BM_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0x000000FF
+#define BF_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY)
+
+#define HW_ENET_MAC1_RX_ALMOST_FULL (0x00004198)
+
+#define BP_ENET_MAC1_RX_ALMOST_FULL_RSRVD0 8
+#define BM_ENET_MAC1_RX_ALMOST_FULL_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_RX_ALMOST_FULL_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_RX_ALMOST_FULL_RSRVD0)
+#define BP_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL 0
+#define BM_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL 0x000000FF
+#define BF_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL(v) \
+ (((v) << 0) & BM_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL)
+
+#define HW_ENET_MAC1_TX_SECTION_EMPTY (0x0000419c)
+
+#define BP_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0 8
+#define BM_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0)
+#define BP_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0
+#define BM_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0x000000FF
+#define BF_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY)
+
+#define HW_ENET_MAC1_TX_ALMOST_EMPTY (0x000041a0)
+
+#define BP_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0 8
+#define BM_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0)
+#define BP_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0
+#define BM_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0x000000FF
+#define BF_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY(v) \
+ (((v) << 0) & BM_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY)
+
+#define HW_ENET_MAC1_TX_ALMOST_FULL (0x000041a4)
+
+#define BP_ENET_MAC1_TX_ALMOST_FULL_RSRVD0 8
+#define BM_ENET_MAC1_TX_ALMOST_FULL_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_TX_ALMOST_FULL_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_TX_ALMOST_FULL_RSRVD0)
+#define BP_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL 0
+#define BM_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL 0x000000FF
+#define BF_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL(v) \
+ (((v) << 0) & BM_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL)
+
+#define HW_ENET_MAC1_TX_IPG_LENGTH (0x000041a8)
+
+#define BP_ENET_MAC1_TX_IPG_LENGTH_RSRVD0 5
+#define BM_ENET_MAC1_TX_IPG_LENGTH_RSRVD0 0xFFFFFFE0
+#define BF_ENET_MAC1_TX_IPG_LENGTH_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_MAC1_TX_IPG_LENGTH_RSRVD0)
+#define BP_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH 0
+#define BM_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH 0x0000001F
+#define BF_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH(v) \
+ (((v) << 0) & BM_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH)
+
+#define HW_ENET_MAC1_TRUNC_FL (0x000041ac)
+
+#define BP_ENET_MAC1_TRUNC_FL_RSRVD0 14
+#define BM_ENET_MAC1_TRUNC_FL_RSRVD0 0xFFFFC000
+#define BF_ENET_MAC1_TRUNC_FL_RSRVD0(v) \
+ (((v) << 14) & BM_ENET_MAC1_TRUNC_FL_RSRVD0)
+#define BP_ENET_MAC1_TRUNC_FL_TRUNC_FL 0
+#define BM_ENET_MAC1_TRUNC_FL_TRUNC_FL 0x00003FFF
+#define BF_ENET_MAC1_TRUNC_FL_TRUNC_FL(v) \
+ (((v) << 0) & BM_ENET_MAC1_TRUNC_FL_TRUNC_FL)
+
+#define HW_ENET_MAC1_IPACCTXCONF (0x000041bc)
+
+#define BP_ENET_MAC1_IPACCTXCONF_RSRVD0 5
+#define BM_ENET_MAC1_IPACCTXCONF_RSRVD0 0xFFFFFFE0
+#define BF_ENET_MAC1_IPACCTXCONF_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_MAC1_IPACCTXCONF_RSRVD0)
+#define BM_ENET_MAC1_IPACCTXCONF_TX_PROTCHK_INS 0x00000010
+#define BM_ENET_MAC1_IPACCTXCONF_TX_IPCHK_INS 0x00000008
+#define BP_ENET_MAC1_IPACCTXCONF_RSRVD1 1
+#define BM_ENET_MAC1_IPACCTXCONF_RSRVD1 0x00000006
+#define BF_ENET_MAC1_IPACCTXCONF_RSRVD1(v) \
+ (((v) << 1) & BM_ENET_MAC1_IPACCTXCONF_RSRVD1)
+#define BM_ENET_MAC1_IPACCTXCONF_SHIFT16 0x00000001
+
+#define HW_ENET_MAC1_IPACCRXCONF (0x000041c0)
+
+#define BP_ENET_MAC1_IPACCRXCONF_RSRVD0 8
+#define BM_ENET_MAC1_IPACCRXCONF_RSRVD0 0xFFFFFF00
+#define BF_ENET_MAC1_IPACCRXCONF_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_MAC1_IPACCRXCONF_RSRVD0)
+#define BM_ENET_MAC1_IPACCRXCONF_SHIFT16 0x00000080
+#define BM_ENET_MAC1_IPACCRXCONF_RX_LINEERR_DISC 0x00000040
+#define BP_ENET_MAC1_IPACCRXCONF_RSRVD1 3
+#define BM_ENET_MAC1_IPACCRXCONF_RSRVD1 0x00000038
+#define BF_ENET_MAC1_IPACCRXCONF_RSRVD1(v) \
+ (((v) << 3) & BM_ENET_MAC1_IPACCRXCONF_RSRVD1)
+#define BM_ENET_MAC1_IPACCRXCONF_RX_PROTERR_DISCARD 0x00000004
+#define BM_ENET_MAC1_IPACCRXCONF_RX_IPERR_DISCARD 0x00000002
+#define BM_ENET_MAC1_IPACCRXCONF_RX_IP_PAD_REMOVE 0x00000001
+
+#define HW_ENET_MAC1_RMON_T_DROP (0x000041fc)
+
+#define BP_ENET_MAC1_RMON_T_DROP_RMON_T_DROP 0
+#define BM_ENET_MAC1_RMON_T_DROP_RMON_T_DROP 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_DROP_RMON_T_DROP(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_PACKETS (0x00004200)
+
+#define BP_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS 0
+#define BM_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_BC_PKT (0x00004204)
+
+#define BP_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT 0
+#define BM_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_MC_PKT (0x00004208)
+
+#define BP_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT 0
+#define BM_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_CRC_ALIGN (0x0000420c)
+
+#define BP_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0
+#define BM_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_UNDERSIZE (0x00004210)
+
+#define BP_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0
+#define BM_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_OVERSIZE (0x00004214)
+
+#define BP_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0
+#define BM_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_FRAG (0x00004218)
+
+#define BP_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG 0
+#define BM_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_JAB (0x0000421c)
+
+#define BP_ENET_MAC1_RMON_T_JAB_RMON_T_JAB 0
+#define BM_ENET_MAC1_RMON_T_JAB_RMON_T_JAB 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_JAB_RMON_T_JAB(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_COL (0x00004220)
+
+#define BP_ENET_MAC1_RMON_T_COL_RMON_T_COL 0
+#define BM_ENET_MAC1_RMON_T_COL_RMON_T_COL 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_COL_RMON_T_COL(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P64 (0x00004224)
+
+#define BP_ENET_MAC1_RMON_T_P64_RMON_T_P64 0
+#define BM_ENET_MAC1_RMON_T_P64_RMON_T_P64 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P64_RMON_T_P64(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P65TO127N (0x00004228)
+
+#define BP_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N 0
+#define BM_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P128TO255N (0x0000422c)
+
+#define BP_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N 0
+#define BM_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P256TO511 (0x00004230)
+
+#define BP_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511 0
+#define BM_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P512TO1023 (0x00004234)
+
+#define BP_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023 0
+#define BM_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P1024TO2047 (0x00004238)
+
+#define BP_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0
+#define BM_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_P_GTE2048 (0x0000423c)
+
+#define BP_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0
+#define BM_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048(v) (v)
+
+#define HW_ENET_MAC1_RMON_T_OCTETS (0x00004240)
+
+#define BP_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS 0
+#define BM_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_DROP (0x00004244)
+
+#define BP_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP 0
+#define BM_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_FRAME_OK (0x00004248)
+
+#define BP_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0
+#define BM_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_1COL (0x0000424c)
+
+#define BP_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL 0
+#define BM_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_MCOL (0x00004250)
+
+#define BP_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL 0
+#define BM_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_DEF (0x00004254)
+
+#define BP_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF 0
+#define BM_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_LCOL (0x00004258)
+
+#define BP_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL 0
+#define BM_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_EXCOL (0x0000425c)
+
+#define BP_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL 0
+#define BM_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_MACERR (0x00004260)
+
+#define BP_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR 0
+#define BM_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_CSERR (0x00004264)
+
+#define BP_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR 0
+#define BM_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_SQE (0x00004268)
+
+#define BP_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE 0
+#define BM_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_FDXFC (0x0000426c)
+
+#define BP_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC 0
+#define BM_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC(v) (v)
+
+#define HW_ENET_MAC1_IEEE_T_OCTETS_OK (0x00004270)
+
+#define BP_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0
+#define BM_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_PACKETS (0x00004280)
+
+#define BP_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS 0
+#define BM_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_BC_PKT (0x00004284)
+
+#define BP_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT 0
+#define BM_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_MC_PKT (0x00004288)
+
+#define BP_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT 0
+#define BM_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_CRC_ALIGN (0x0000428c)
+
+#define BP_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0
+#define BM_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_UNDERSIZE (0x00004290)
+
+#define BP_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0
+#define BM_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_OVERSIZE (0x00004294)
+
+#define BP_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0
+#define BM_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_FRAG (0x00004298)
+
+#define BP_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG 0
+#define BM_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_JAB (0x0000429c)
+
+#define BP_ENET_MAC1_RMON_R_JAB_RMON_R_JAB 0
+#define BM_ENET_MAC1_RMON_R_JAB_RMON_R_JAB 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_JAB_RMON_R_JAB(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P64 (0x000042a4)
+
+#define BP_ENET_MAC1_RMON_R_P64_RMON_R_P64 0
+#define BM_ENET_MAC1_RMON_R_P64_RMON_R_P64 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P64_RMON_R_P64(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P65TO127 (0x000042a8)
+
+#define BP_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127 0
+#define BM_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P128TO255 (0x000042ac)
+
+#define BP_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255 0
+#define BM_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P256TO511 (0x000042b0)
+
+#define BP_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511 0
+#define BM_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P512TO1023 (0x000042b4)
+
+#define BP_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023 0
+#define BM_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P1024TO2047 (0x000042b8)
+
+#define BP_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0
+#define BM_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_P_GTE2048 (0x000042bc)
+
+#define BP_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0
+#define BM_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048(v) (v)
+
+#define HW_ENET_MAC1_RMON_R_OCTETS (0x000042c0)
+
+#define BP_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS 0
+#define BM_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS 0xFFFFFFFF
+#define BF_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_DROP (0x000042c4)
+
+#define BP_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP 0
+#define BM_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_FRAME_OK (0x000042c8)
+
+#define BP_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0
+#define BM_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_CRC (0x000042cc)
+
+#define BP_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC 0
+#define BM_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_ALIGN (0x000042d0)
+
+#define BP_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN 0
+#define BM_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_MACERR (0x000042d4)
+
+#define BP_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR 0
+#define BM_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_FDXFC (0x000042d8)
+
+#define BP_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC 0
+#define BM_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC(v) (v)
+
+#define HW_ENET_MAC1_IEEE_R_OCTETS_OK (0x000042dc)
+
+#define BP_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0
+#define BM_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0xFFFFFFFF
+#define BF_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK(v) (v)
+
+#define HW_ENET_MAC1_ATIME_CTRL (0x000043fc)
+
+#define BP_ENET_MAC1_ATIME_CTRL_RSRVD0 14
+#define BM_ENET_MAC1_ATIME_CTRL_RSRVD0 0xFFFFC000
+#define BF_ENET_MAC1_ATIME_CTRL_RSRVD0(v) \
+ (((v) << 14) & BM_ENET_MAC1_ATIME_CTRL_RSRVD0)
+#define BM_ENET_MAC1_ATIME_CTRL_FRC_SLAVE 0x00002000
+#define BM_ENET_MAC1_ATIME_CTRL_RSRVD1 0x00001000
+#define BM_ENET_MAC1_ATIME_CTRL_CAPTURE 0x00000800
+#define BM_ENET_MAC1_ATIME_CTRL_RSRVD2 0x00000400
+#define BM_ENET_MAC1_ATIME_CTRL_RESTART 0x00000200
+#define BM_ENET_MAC1_ATIME_CTRL_RSRVD3 0x00000100
+#define BM_ENET_MAC1_ATIME_CTRL_PIN_PERIOD_ENA 0x00000080
+#define BM_ENET_MAC1_ATIME_CTRL_RSRVD4 0x00000040
+#define BM_ENET_MAC1_ATIME_CTRL_EVT_PERIOD_RST 0x00000020
+#define BM_ENET_MAC1_ATIME_CTRL_EVT_PERIOD_ENA 0x00000010
+#define BM_ENET_MAC1_ATIME_CTRL_EVT_OFFSET_RST 0x00000008
+#define BM_ENET_MAC1_ATIME_CTRL_EVT_OFFSET_ENA 0x00000004
+#define BM_ENET_MAC1_ATIME_CTRL_ONE_SHOT 0x00000002
+#define BM_ENET_MAC1_ATIME_CTRL_ENABLE 0x00000001
+
+#define HW_ENET_MAC1_ATIME (0x00004400)
+
+#define BP_ENET_MAC1_ATIME_ATIME 0
+#define BM_ENET_MAC1_ATIME_ATIME 0xFFFFFFFF
+#define BF_ENET_MAC1_ATIME_ATIME(v) (v)
+
+#define HW_ENET_MAC1_ATIME_EVT_OFFSET (0x00004404)
+
+#define BP_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0
+#define BM_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0xFFFFFFFF
+#define BF_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET(v) (v)
+
+#define HW_ENET_MAC1_ATIME_EVT_PERIOD (0x00004408)
+
+#define BP_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0
+#define BM_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0xFFFFFFFF
+#define BF_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD(v) (v)
+
+#define HW_ENET_MAC1_ATIME_CORR (0x0000440c)
+
+#define BM_ENET_MAC1_ATIME_CORR_RSRVD0 0x80000000
+#define BP_ENET_MAC1_ATIME_CORR_ATIME_CORR 0
+#define BM_ENET_MAC1_ATIME_CORR_ATIME_CORR 0x7FFFFFFF
+#define BF_ENET_MAC1_ATIME_CORR_ATIME_CORR(v) \
+ (((v) << 0) & BM_ENET_MAC1_ATIME_CORR_ATIME_CORR)
+
+#define HW_ENET_MAC1_ATIME_INC (0x00004410)
+
+#define BP_ENET_MAC1_ATIME_INC_RSRVD0 15
+#define BM_ENET_MAC1_ATIME_INC_RSRVD0 0xFFFF8000
+#define BF_ENET_MAC1_ATIME_INC_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_MAC1_ATIME_INC_RSRVD0)
+#define BP_ENET_MAC1_ATIME_INC_ATIME_INC_CORR 8
+#define BM_ENET_MAC1_ATIME_INC_ATIME_INC_CORR 0x00007F00
+#define BF_ENET_MAC1_ATIME_INC_ATIME_INC_CORR(v) \
+ (((v) << 8) & BM_ENET_MAC1_ATIME_INC_ATIME_INC_CORR)
+#define BM_ENET_MAC1_ATIME_INC_RSRVD1 0x00000080
+#define BP_ENET_MAC1_ATIME_INC_ATIME_INC 0
+#define BM_ENET_MAC1_ATIME_INC_ATIME_INC 0x0000007F
+#define BF_ENET_MAC1_ATIME_INC_ATIME_INC(v) \
+ (((v) << 0) & BM_ENET_MAC1_ATIME_INC_ATIME_INC)
+
+#define HW_ENET_MAC1_TS_TIMESTAMP (0x00004414)
+
+#define BP_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP 0
+#define BM_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP 0xFFFFFFFF
+#define BF_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP(v) (v)
+
+#define HW_ENET_MAC1_SMAC_0_0 (0x000044fc)
+
+#define BP_ENET_MAC1_SMAC_0_0_SMAC_0_0 0
+#define BM_ENET_MAC1_SMAC_0_0_SMAC_0_0 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_0_0_SMAC_0_0(v) (v)
+
+#define HW_ENET_MAC1_SMAC_0_1 (0x00004500)
+
+#define BP_ENET_MAC1_SMAC_0_1_SMAC_0_1 0
+#define BM_ENET_MAC1_SMAC_0_1_SMAC_0_1 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_0_1_SMAC_0_1(v) (v)
+
+#define HW_ENET_MAC1_SMAC_1_0 (0x00004504)
+
+#define BP_ENET_MAC1_SMAC_1_0_SMAC_1_0 0
+#define BM_ENET_MAC1_SMAC_1_0_SMAC_1_0 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_1_0_SMAC_1_0(v) (v)
+
+#define HW_ENET_MAC1_SMAC_1_1 (0x00004508)
+
+#define BP_ENET_MAC1_SMAC_1_1_SMAC_1_1 0
+#define BM_ENET_MAC1_SMAC_1_1_SMAC_1_1 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_1_1_SMAC_1_1(v) (v)
+
+#define HW_ENET_MAC1_SMAC_2_0 (0x0000450c)
+
+#define BP_ENET_MAC1_SMAC_2_0_SMAC_2_0 0
+#define BM_ENET_MAC1_SMAC_2_0_SMAC_2_0 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_2_0_SMAC_2_0(v) (v)
+
+#define HW_ENET_MAC1_SMAC_2_1 (0x00004510)
+
+#define BP_ENET_MAC1_SMAC_2_1_SMAC_2_1 0
+#define BM_ENET_MAC1_SMAC_2_1_SMAC_2_1 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_2_1_SMAC_2_1(v) (v)
+
+#define HW_ENET_MAC1_SMAC_3_0 (0x00004514)
+
+#define BP_ENET_MAC1_SMAC_3_0_SMAC_3_0 0
+#define BM_ENET_MAC1_SMAC_3_0_SMAC_3_0 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_3_0_SMAC_3_0(v) (v)
+
+#define HW_ENET_MAC1_SMAC_3_1 (0x00004518)
+
+#define BP_ENET_MAC1_SMAC_3_1_SMAC_3_1 0
+#define BM_ENET_MAC1_SMAC_3_1_SMAC_3_1 0xFFFFFFFF
+#define BF_ENET_MAC1_SMAC_3_1_SMAC_3_1(v) (v)
+
+#define HW_ENET_MAC1_COMP_REG_0 (0x000045fc)
+
+#define BP_ENET_MAC1_COMP_REG_0_COMP_REG_0 0
+#define BM_ENET_MAC1_COMP_REG_0_COMP_REG_0 0xFFFFFFFF
+#define BF_ENET_MAC1_COMP_REG_0_COMP_REG_0(v) (v)
+
+#define HW_ENET_MAC1_COMP_REG_1 (0x00004600)
+
+#define BP_ENET_MAC1_COMP_REG_1_COMP_REG_1 0
+#define BM_ENET_MAC1_COMP_REG_1_COMP_REG_1 0xFFFFFFFF
+#define BF_ENET_MAC1_COMP_REG_1_COMP_REG_1(v) (v)
+
+#define HW_ENET_MAC1_COMP_REG_2 (0x00004604)
+
+#define BP_ENET_MAC1_COMP_REG_2_COMP_REG_2 0
+#define BM_ENET_MAC1_COMP_REG_2_COMP_REG_2 0xFFFFFFFF
+#define BF_ENET_MAC1_COMP_REG_2_COMP_REG_2(v) (v)
+
+#define HW_ENET_MAC1_COMP_REG_3 (0x00004608)
+
+#define BP_ENET_MAC1_COMP_REG_3_COMP_REG_3 0
+#define BM_ENET_MAC1_COMP_REG_3_COMP_REG_3 0xFFFFFFFF
+#define BF_ENET_MAC1_COMP_REG_3_COMP_REG_3(v) (v)
+
+#define HW_ENET_MAC1_CAPT_REG_0 (0x0000463c)
+
+#define BP_ENET_MAC1_CAPT_REG_0_CAPT_REG_0 0
+#define BM_ENET_MAC1_CAPT_REG_0_CAPT_REG_0 0xFFFFFFFF
+#define BF_ENET_MAC1_CAPT_REG_0_CAPT_REG_0(v) (v)
+
+#define HW_ENET_MAC1_CAPT_REG_1 (0x00004640)
+
+#define BP_ENET_MAC1_CAPT_REG_1_CAPT_REG_1 0
+#define BM_ENET_MAC1_CAPT_REG_1_CAPT_REG_1 0xFFFFFFFF
+#define BF_ENET_MAC1_CAPT_REG_1_CAPT_REG_1(v) (v)
+
+#define HW_ENET_MAC1_CAPT_REG_2 (0x00004644)
+
+#define BP_ENET_MAC1_CAPT_REG_2_CAPT_REG_2 0
+#define BM_ENET_MAC1_CAPT_REG_2_CAPT_REG_2 0xFFFFFFFF
+#define BF_ENET_MAC1_CAPT_REG_2_CAPT_REG_2(v) (v)
+
+#define HW_ENET_MAC1_CAPT_REG_3 (0x00004648)
+
+#define BP_ENET_MAC1_CAPT_REG_3_CAPT_REG_3 0
+#define BM_ENET_MAC1_CAPT_REG_3_CAPT_REG_3 0xFFFFFFFF
+#define BF_ENET_MAC1_CAPT_REG_3_CAPT_REG_3(v) (v)
+
+#define HW_ENET_MAC1_CCB_INT (0x0000467c)
+
+#define BP_ENET_MAC1_CCB_INT_RSRVD0 20
+#define BM_ENET_MAC1_CCB_INT_RSRVD0 0xFFF00000
+#define BF_ENET_MAC1_CCB_INT_RSRVD0(v) \
+ (((v) << 20) & BM_ENET_MAC1_CCB_INT_RSRVD0)
+#define BM_ENET_MAC1_CCB_INT_COMPARE3 0x00080000
+#define BM_ENET_MAC1_CCB_INT_COMPARE2 0x00040000
+#define BM_ENET_MAC1_CCB_INT_COMPARE1 0x00020000
+#define BM_ENET_MAC1_CCB_INT_COMPARE0 0x00010000
+#define BP_ENET_MAC1_CCB_INT_RSRVD1 4
+#define BM_ENET_MAC1_CCB_INT_RSRVD1 0x0000FFF0
+#define BF_ENET_MAC1_CCB_INT_RSRVD1(v) \
+ (((v) << 4) & BM_ENET_MAC1_CCB_INT_RSRVD1)
+#define BM_ENET_MAC1_CCB_INT_CAPTURE3 0x00000008
+#define BM_ENET_MAC1_CCB_INT_CAPTURE2 0x00000004
+#define BM_ENET_MAC1_CCB_INT_CAPTURE1 0x00000002
+#define BM_ENET_MAC1_CCB_INT_CAPTURE0 0x00000001
+
+#define HW_ENET_MAC1_CCB_INT_MASK (0x00004680)
+
+#define BP_ENET_MAC1_CCB_INT_MASK_RSRVD0 20
+#define BM_ENET_MAC1_CCB_INT_MASK_RSRVD0 0xFFF00000
+#define BF_ENET_MAC1_CCB_INT_MASK_RSRVD0(v) \
+ (((v) << 20) & BM_ENET_MAC1_CCB_INT_MASK_RSRVD0)
+#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE3 0x00080000
+#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE2 0x00040000
+#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE1 0x00020000
+#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE0 0x00010000
+#define BP_ENET_MAC1_CCB_INT_MASK_RSRVD1 4
+#define BM_ENET_MAC1_CCB_INT_MASK_RSRVD1 0x0000FFF0
+#define BF_ENET_MAC1_CCB_INT_MASK_RSRVD1(v) \
+ (((v) << 4) & BM_ENET_MAC1_CCB_INT_MASK_RSRVD1)
+#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE3 0x00000008
+#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE2 0x00000004
+#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE1 0x00000002
+#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE0 0x00000001
+
+#define HW_ENET_SWI_REVISION (0x00007ffc)
+
+#define BP_ENET_SWI_REVISION_CUSTOMER_REVISION 16
+#define BM_ENET_SWI_REVISION_CUSTOMER_REVISION 0xFFFF0000
+#define BF_ENET_SWI_REVISION_CUSTOMER_REVISION(v) \
+ (((v) << 16) & BM_ENET_SWI_REVISION_CUSTOMER_REVISION)
+#define BP_ENET_SWI_REVISION_CORE_REVISION 0
+#define BM_ENET_SWI_REVISION_CORE_REVISION 0x0000FFFF
+#define BF_ENET_SWI_REVISION_CORE_REVISION(v) \
+ (((v) << 0) & BM_ENET_SWI_REVISION_CORE_REVISION)
+
+#define HW_ENET_SWI_SCRATCH (0x00008000)
+
+#define BP_ENET_SWI_SCRATCH_COMPARE0 0
+#define BM_ENET_SWI_SCRATCH_COMPARE0 0xFFFFFFFF
+#define BF_ENET_SWI_SCRATCH_COMPARE0(v) (v)
+
+#define HW_ENET_SWI_PORT_ENA (0x00008004)
+
+#define BP_ENET_SWI_PORT_ENA_RSRVD1 19
+#define BM_ENET_SWI_PORT_ENA_RSRVD1 0xFFF80000
+#define BF_ENET_SWI_PORT_ENA_RSRVD1(v) \
+ (((v) << 19) & BM_ENET_SWI_PORT_ENA_RSRVD1)
+#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_2 0x00040000
+#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_1 0x00020000
+#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_0 0x00010000
+#define BP_ENET_SWI_PORT_ENA_RSRVD0 3
+#define BM_ENET_SWI_PORT_ENA_RSRVD0 0x0000FFF8
+#define BF_ENET_SWI_PORT_ENA_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_PORT_ENA_RSRVD0)
+#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_2 0x00000004
+#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_1 0x00000002
+#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_VERIFY (0x0000800c)
+
+#define BP_ENET_SWI_VLAN_VERIFY_RSRVD1 19
+#define BM_ENET_SWI_VLAN_VERIFY_RSRVD1 0xFFF80000
+#define BF_ENET_SWI_VLAN_VERIFY_RSRVD1(v) \
+ (((v) << 19) & BM_ENET_SWI_VLAN_VERIFY_RSRVD1)
+#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P2 0x00040000
+#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P1 0x00020000
+#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P0 0x00010000
+#define BP_ENET_SWI_VLAN_VERIFY_RSRVD0 3
+#define BM_ENET_SWI_VLAN_VERIFY_RSRVD0 0x0000FFF8
+#define BF_ENET_SWI_VLAN_VERIFY_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_VERIFY_RSRVD0)
+#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_2 0x00000004
+#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_1 0x00000002
+#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_0 0x00000001
+
+#define HW_ENET_SWI_BCAST_DEFAULT_MASK (0x00008010)
+
+#define BP_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0 3
+#define BM_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0 0xFFFFFFF8
+#define BF_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0)
+#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_2 0x00000004
+#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_1 0x00000002
+#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_0 0x00000001
+
+#define HW_ENET_SWI_MCAST_DEFAULT_MASK (0x00008014)
+
+#define BP_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0 3
+#define BM_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0 0xFFFFFFF8
+#define BF_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0)
+#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_2 0x00000004
+#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_1 0x00000002
+#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_0 0x00000001
+
+#define HW_ENET_SWI_INPUT_LEARN_BLOCK (0x00008018)
+
+#define BP_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1 19
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1 0xFFF80000
+#define BF_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1(v) \
+ (((v) << 19) & BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1)
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DIS_P2 0x00040000
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DI_P1 0x00020000
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DI_P0 0x00010000
+#define BP_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0 3
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0 0x0000FFF8
+#define BF_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0)
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P2 0x00000004
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P1 0x00000002
+#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P0 0x00000001
+
+#define HW_ENET_SWI_MGMT_CONFIG (0x0000801c)
+
+#define BP_ENET_SWI_MGMT_CONFIG_RSRVD2 19
+#define BM_ENET_SWI_MGMT_CONFIG_RSRVD2 0xFFF80000
+#define BF_ENET_SWI_MGMT_CONFIG_RSRVD2(v) \
+ (((v) << 19) & BM_ENET_SWI_MGMT_CONFIG_RSRVD2)
+#define BP_ENET_SWI_MGMT_CONFIG_PORTMASK 16
+#define BM_ENET_SWI_MGMT_CONFIG_PORTMASK 0x00070000
+#define BF_ENET_SWI_MGMT_CONFIG_PORTMASK(v) \
+ (((v) << 16) & BM_ENET_SWI_MGMT_CONFIG_PORTMASK)
+#define BP_ENET_SWI_MGMT_CONFIG_PRIORITY 13
+#define BM_ENET_SWI_MGMT_CONFIG_PRIORITY 0x0000E000
+#define BF_ENET_SWI_MGMT_CONFIG_PRIORITY(v) \
+ (((v) << 13) & BM_ENET_SWI_MGMT_CONFIG_PRIORITY)
+#define BP_ENET_SWI_MGMT_CONFIG_RSRVD1 8
+#define BM_ENET_SWI_MGMT_CONFIG_RSRVD1 0x00001F00
+#define BF_ENET_SWI_MGMT_CONFIG_RSRVD1(v) \
+ (((v) << 8) & BM_ENET_SWI_MGMT_CONFIG_RSRVD1)
+#define BM_ENET_SWI_MGMT_CONFIG_DISCARD 0x00000080
+#define BM_ENET_SWI_MGMT_CONFIG_ENABLE 0x00000040
+#define BM_ENET_SWI_MGMT_CONFIG_MESSAGE_TRANSMITTED 0x00000020
+#define BM_ENET_SWI_MGMT_CONFIG_RSRVD0 0x00000010
+#define BP_ENET_SWI_MGMT_CONFIG_PORT 0
+#define BM_ENET_SWI_MGMT_CONFIG_PORT 0x0000000F
+#define BF_ENET_SWI_MGMT_CONFIG_PORT(v) \
+ (((v) << 0) & BM_ENET_SWI_MGMT_CONFIG_PORT)
+
+#define HW_ENET_SWI_MODE_CONFIG (0x00008020)
+
+#define BM_ENET_SWI_MODE_CONFIG_STATSRESET 0x80000000
+#define BP_ENET_SWI_MODE_CONFIG_RSRVD1 10
+#define BM_ENET_SWI_MODE_CONFIG_RSRVD1 0x7FFFFC00
+#define BF_ENET_SWI_MODE_CONFIG_RSRVD1(v) \
+ (((v) << 10) & BM_ENET_SWI_MODE_CONFIG_RSRVD1)
+#define BM_ENET_SWI_MODE_CONFIG_P0BUF_CUT_THROUGH 0x00000200
+#define BM_ENET_SWI_MODE_CONFIG_CRC_TRANSPARENT 0x00000100
+#define BM_ENET_SWI_MODE_CONFIG_STOP_EN 0x00000080
+#define BP_ENET_SWI_MODE_CONFIG_RSRVD0 2
+#define BM_ENET_SWI_MODE_CONFIG_RSRVD0 0x0000007C
+#define BF_ENET_SWI_MODE_CONFIG_RSRVD0(v) \
+ (((v) << 2) & BM_ENET_SWI_MODE_CONFIG_RSRVD0)
+#define BM_ENET_SWI_MODE_CONFIG_SWITCH_EN 0x00000002
+#define BM_ENET_SWI_MODE_CONFIG_SWITCH_RESET 0x00000001
+
+#define HW_ENET_SWI_VLAN_IN_MODE (0x00008024)
+
+#define BP_ENET_SWI_VLAN_IN_MODE_RSRVD0 6
+#define BM_ENET_SWI_VLAN_IN_MODE_RSRVD0 0xFFFFFFC0
+#define BF_ENET_SWI_VLAN_IN_MODE_RSRVD0(v) \
+ (((v) << 6) & BM_ENET_SWI_VLAN_IN_MODE_RSRVD0)
+#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2 4
+#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2 0x00000030
+#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2(v) \
+ (((v) << 4) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2)
+#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1 2
+#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1 0x0000000C
+#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1(v) \
+ (((v) << 2) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1)
+#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0 0
+#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0 0x00000003
+#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0(v) \
+ (((v) << 0) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0)
+
+#define HW_ENET_SWI_VLAN_OUT_MODE (0x00008028)
+
+#define BP_ENET_SWI_VLAN_OUT_MODE_RSRVD0 6
+#define BM_ENET_SWI_VLAN_OUT_MODE_RSRVD0 0xFFFFFFC0
+#define BF_ENET_SWI_VLAN_OUT_MODE_RSRVD0(v) \
+ (((v) << 6) & BM_ENET_SWI_VLAN_OUT_MODE_RSRVD0)
+#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2 4
+#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2 0x00000030
+#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2(v) \
+ (((v) << 4) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2)
+#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1 2
+#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1 0x0000000C
+#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1(v) \
+ (((v) << 2) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1)
+#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0 0
+#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0 0x00000003
+#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0(v) \
+ (((v) << 0) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0)
+
+#define HW_ENET_SWI_VLAN_IN_MODE_ENA (0x0000802c)
+
+#define BP_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0 3
+#define BM_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0 0xFFFFFFF8
+#define BF_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0)
+#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_2 0x00000004
+#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_1 0x00000002
+#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_TAG_ID (0x00008030)
+
+#define BP_ENET_SWI_VLAN_TAG_ID_RSRVD0 16
+#define BM_ENET_SWI_VLAN_TAG_ID_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_VLAN_TAG_ID_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_VLAN_TAG_ID_RSRVD0)
+#define BP_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID 0
+#define BM_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID 0x0000FFFF
+#define BF_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID(v) \
+ (((v) << 0) & BM_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID)
+
+#define HW_ENET_SWI_MIRROR_CONTROL (0x0000803c)
+
+#define BP_ENET_SWI_MIRROR_CONTROL_RSRVD0 11
+#define BM_ENET_SWI_MIRROR_CONTROL_RSRVD0 0xFFFFF800
+#define BF_ENET_SWI_MIRROR_CONTROL_RSRVD0(v) \
+ (((v) << 11) & BM_ENET_SWI_MIRROR_CONTROL_RSRVD0)
+#define BM_ENET_SWI_MIRROR_CONTROL_EG_DA_MATCH 0x00000400
+#define BM_ENET_SWI_MIRROR_CONTROL_EG_SA_MATCH 0x00000200
+#define BM_ENET_SWI_MIRROR_CONTROL_ING_DA_MATCH 0x00000100
+#define BM_ENET_SWI_MIRROR_CONTROL_ING_SA_MATCH 0x00000080
+#define BM_ENET_SWI_MIRROR_CONTROL_EG_MAP_ENABLE 0x00000040
+#define BM_ENET_SWI_MIRROR_CONTROL_ING_MAP_ENABLE 0x00000020
+#define BM_ENET_SWI_MIRROR_CONTROL_MIRROR_ENABLE 0x00000010
+#define BP_ENET_SWI_MIRROR_CONTROL_PORTX 0
+#define BM_ENET_SWI_MIRROR_CONTROL_PORTX 0x0000000F
+#define BF_ENET_SWI_MIRROR_CONTROL_PORTX(v) \
+ (((v) << 0) & BM_ENET_SWI_MIRROR_CONTROL_PORTX)
+
+#define HW_ENET_SWI_MIRROR_EG_MAP (0x00008040)
+
+#define BP_ENET_SWI_MIRROR_EG_MAP_RSRVD0 3
+#define BM_ENET_SWI_MIRROR_EG_MAP_RSRVD0 0xFFFFFFF8
+#define BF_ENET_SWI_MIRROR_EG_MAP_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_MIRROR_EG_MAP_RSRVD0)
+#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_2 0x00000004
+#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_1 0x00000002
+#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_0 0x00000001
+
+#define HW_ENET_SWI_MIRROR_ING_MAP (0x00008044)
+
+#define BP_ENET_SWI_MIRROR_ING_MAP_RSRVD0 3
+#define BM_ENET_SWI_MIRROR_ING_MAP_RSRVD0 0xFFFFFFF8
+#define BF_ENET_SWI_MIRROR_ING_MAP_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_MIRROR_ING_MAP_RSRVD0)
+#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_2 0x00000004
+#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_1 0x00000002
+#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_0 0x00000001
+
+#define HW_ENET_SWI_MIRROR_ISRC_0 (0x00008048)
+
+#define BP_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0 0
+#define BM_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0 0xFFFFFFFF
+#define BF_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0(v) (v)
+
+#define HW_ENET_SWI_MIRROR_ISRC_1 (0x0000804c)
+
+#define BP_ENET_SWI_MIRROR_ISRC_1_RSRVD0 16
+#define BM_ENET_SWI_MIRROR_ISRC_1_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_MIRROR_ISRC_1_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_MIRROR_ISRC_1_RSRVD0)
+#define BP_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1 0
+#define BM_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1 0x0000FFFF
+#define BF_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1(v) \
+ (((v) << 0) & BM_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1)
+
+#define HW_ENET_SWI_MIRROR_IDST_0 (0x00008050)
+
+#define BP_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0 0
+#define BM_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0 0xFFFFFFFF
+#define BF_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0(v) (v)
+
+#define HW_ENET_SWI_MIRROR_IDST_1 (0x00008054)
+
+#define BP_ENET_SWI_MIRROR_IDST_1_RSRVD0 16
+#define BM_ENET_SWI_MIRROR_IDST_1_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_MIRROR_IDST_1_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_MIRROR_IDST_1_RSRVD0)
+#define BP_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1 0
+#define BM_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1 0x0000FFFF
+#define BF_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1(v) \
+ (((v) << 0) & BM_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1)
+
+#define HW_ENET_SWI_MIRROR_ESRC_0 (0x00008058)
+
+#define BP_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0 0
+#define BM_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0 0xFFFFFFFF
+#define BF_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0(v) (v)
+
+#define HW_ENET_SWI_MIRROR_ESRC_1 (0x0000805c)
+
+#define BP_ENET_SWI_MIRROR_ESRC_1_RSRVD0 16
+#define BM_ENET_SWI_MIRROR_ESRC_1_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_MIRROR_ESRC_1_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_MIRROR_ESRC_1_RSRVD0)
+#define BP_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1 0
+#define BM_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1 0x0000FFFF
+#define BF_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1(v) \
+ (((v) << 0) & BM_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1)
+
+#define HW_ENET_SWI_MIRROR_EDST_0 (0x00008060)
+
+#define BP_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0 0
+#define BM_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0 0xFFFFFFFF
+#define BF_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0(v) (v)
+
+#define HW_ENET_SWI_MIRROR_EDST_1 (0x00008064)
+
+#define BP_ENET_SWI_MIRROR_EDST_1_RSRVD0 16
+#define BM_ENET_SWI_MIRROR_EDST_1_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_MIRROR_EDST_1_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_MIRROR_EDST_1_RSRVD0)
+#define BP_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1 0
+#define BM_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1 0x0000FFFF
+#define BF_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1(v) \
+ (((v) << 0) & BM_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1)
+
+#define HW_ENET_SWI_MIRROR_CNT (0x00008068)
+
+#define BP_ENET_SWI_MIRROR_CNT_RSRVD0 8
+#define BM_ENET_SWI_MIRROR_CNT_RSRVD0 0xFFFFFF00
+#define BF_ENET_SWI_MIRROR_CNT_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_SWI_MIRROR_CNT_RSRVD0)
+#define BP_ENET_SWI_MIRROR_CNT_MIRROR_CNT 0
+#define BM_ENET_SWI_MIRROR_CNT_MIRROR_CNT 0x000000FF
+#define BF_ENET_SWI_MIRROR_CNT_MIRROR_CNT(v) \
+ (((v) << 0) & BM_ENET_SWI_MIRROR_CNT_MIRROR_CNT)
+
+#define HW_ENET_SWI_OQMGR_STATUS (0x0000807c)
+
+#define BP_ENET_SWI_OQMGR_STATUS_RSRVD2 24
+#define BM_ENET_SWI_OQMGR_STATUS_RSRVD2 0xFF000000
+#define BF_ENET_SWI_OQMGR_STATUS_RSRVD2(v) \
+ (((v) << 24) & BM_ENET_SWI_OQMGR_STATUS_RSRVD2)
+#define BP_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE 16
+#define BM_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE 0x00FF0000
+#define BF_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE(v) \
+ (((v) << 16) & BM_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE)
+#define BP_ENET_SWI_OQMGR_STATUS_RSRVD1 7
+#define BM_ENET_SWI_OQMGR_STATUS_RSRVD1 0x0000FF80
+#define BF_ENET_SWI_OQMGR_STATUS_RSRVD1(v) \
+ (((v) << 7) & BM_ENET_SWI_OQMGR_STATUS_RSRVD1)
+#define BM_ENET_SWI_OQMGR_STATUS_DEQUEUE_GRANT 0x00000040
+#define BP_ENET_SWI_OQMGR_STATUS_RSRVD0 4
+#define BM_ENET_SWI_OQMGR_STATUS_RSRVD0 0x00000030
+#define BF_ENET_SWI_OQMGR_STATUS_RSRVD0(v) \
+ (((v) << 4) & BM_ENET_SWI_OQMGR_STATUS_RSRVD0)
+#define BM_ENET_SWI_OQMGR_STATUS_MEM_FULL_LATCH 0x00000008
+#define BM_ENET_SWI_OQMGR_STATUS_MEM_FULL 0x00000004
+#define BM_ENET_SWI_OQMGR_STATUS_NO_CELL_LATCH 0x00000002
+#define BM_ENET_SWI_OQMGR_STATUS_BUSY_INITIALIZING 0x00000001
+
+#define HW_ENET_SWI_QMGR_MINCELLS (0x00008080)
+
+#define BP_ENET_SWI_QMGR_MINCELLS_RSRVD0 8
+#define BM_ENET_SWI_QMGR_MINCELLS_RSRVD0 0xFFFFFF00
+#define BF_ENET_SWI_QMGR_MINCELLS_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_SWI_QMGR_MINCELLS_RSRVD0)
+#define BP_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS 0
+#define BM_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS 0x000000FF
+#define BF_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS(v) \
+ (((v) << 0) & BM_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS)
+
+#define HW_ENET_SWI_QMGR_ST_MINCELLS (0x00008084)
+
+#define BP_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS 0
+#define BM_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS 0xFFFFFFFF
+#define BF_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS(v) (v)
+
+#define HW_ENET_SWI_QMGR_CONGEST_STAT (0x00008088)
+
+#define BP_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0 3
+#define BM_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0 0xFFFFFFF8
+#define BF_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0)
+#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_2 0x00000004
+#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_1 0x00000002
+#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_0 0x00000001
+
+#define HW_ENET_SWI_QMGR_IFACE_STAT (0x0000808c)
+
+#define BP_ENET_SWI_QMGR_IFACE_STAT_RSRVD1 19
+#define BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD1 0xFFF80000
+#define BF_ENET_SWI_QMGR_IFACE_STAT_RSRVD1(v) \
+ (((v) << 19) & BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD1)
+#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_2 0x00040000
+#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_1 0x00020000
+#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_0 0x00010000
+#define BP_ENET_SWI_QMGR_IFACE_STAT_RSRVD0 3
+#define BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD0 0x0000FFF8
+#define BF_ENET_SWI_QMGR_IFACE_STAT_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD0)
+#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_2 0x00000004
+#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_1 0x00000002
+#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_0 0x00000001
+
+#define HW_ENET_SWI_QM_WEIGHTS (0x00008090)
+
+#define BP_ENET_SWI_QM_WEIGHTS_RSRVD3 29
+#define BM_ENET_SWI_QM_WEIGHTS_RSRVD3 0xE0000000
+#define BF_ENET_SWI_QM_WEIGHTS_RSRVD3(v) \
+ (((v) << 29) & BM_ENET_SWI_QM_WEIGHTS_RSRVD3)
+#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_3 24
+#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_3 0x1F000000
+#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_3(v) \
+ (((v) << 24) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_3)
+#define BP_ENET_SWI_QM_WEIGHTS_RSRVD2 21
+#define BM_ENET_SWI_QM_WEIGHTS_RSRVD2 0x00E00000
+#define BF_ENET_SWI_QM_WEIGHTS_RSRVD2(v) \
+ (((v) << 21) & BM_ENET_SWI_QM_WEIGHTS_RSRVD2)
+#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_2 16
+#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_2 0x001F0000
+#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_2(v) \
+ (((v) << 16) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_2)
+#define BP_ENET_SWI_QM_WEIGHTS_RSRVD1 13
+#define BM_ENET_SWI_QM_WEIGHTS_RSRVD1 0x0000E000
+#define BF_ENET_SWI_QM_WEIGHTS_RSRVD1(v) \
+ (((v) << 13) & BM_ENET_SWI_QM_WEIGHTS_RSRVD1)
+#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_1 8
+#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_1 0x00001F00
+#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_1(v) \
+ (((v) << 8) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_1)
+#define BP_ENET_SWI_QM_WEIGHTS_RSRVD0 5
+#define BM_ENET_SWI_QM_WEIGHTS_RSRVD0 0x000000E0
+#define BF_ENET_SWI_QM_WEIGHTS_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_QM_WEIGHTS_RSRVD0)
+#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_0 0
+#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_0 0x0000001F
+#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_0(v) \
+ (((v) << 0) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_0)
+
+#define HW_ENET_SWI_QMGR_MINCELLSP0 (0x00008098)
+
+#define BP_ENET_SWI_QMGR_MINCELLSP0_RSRVD0 8
+#define BM_ENET_SWI_QMGR_MINCELLSP0_RSRVD0 0xFFFFFF00
+#define BF_ENET_SWI_QMGR_MINCELLSP0_RSRVD0(v) \
+ (((v) << 8) & BM_ENET_SWI_QMGR_MINCELLSP0_RSRVD0)
+#define BP_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0 0
+#define BM_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0 0x000000FF
+#define BF_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0(v) \
+ (((v) << 0) & BM_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0)
+
+#define HW_ENET_SWI_FORCE_FWD_P0 (0x000080b8)
+
+#define BP_ENET_SWI_FORCE_FWD_P0_RSRVD1 4
+#define BM_ENET_SWI_FORCE_FWD_P0_RSRVD1 0xFFFFFFF0
+#define BF_ENET_SWI_FORCE_FWD_P0_RSRVD1(v) \
+ (((v) << 4) & BM_ENET_SWI_FORCE_FWD_P0_RSRVD1)
+#define BP_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION 2
+#define BM_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION 0x0000000C
+#define BF_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION(v) \
+ (((v) << 2) & BM_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION)
+#define BM_ENET_SWI_FORCE_FWD_P0_RSRVD0 0x00000002
+#define BM_ENET_SWI_FORCE_FWD_P0_FORCE_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP1 (0x000080bc)
+
+#define BP_ENET_SWI_PORTSNOOP1_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP1_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP1_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP1_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP1_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP1_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP1_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP1_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP1_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP1_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP1_MODE 1
+#define BM_ENET_SWI_PORTSNOOP1_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP1_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP1_MODE)
+#define BM_ENET_SWI_PORTSNOOP1_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP2 (0x000080c0)
+
+#define BP_ENET_SWI_PORTSNOOP2_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP2_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP2_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP2_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP2_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP2_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP2_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP2_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP2_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP2_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP2_MODE 1
+#define BM_ENET_SWI_PORTSNOOP2_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP2_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP2_MODE)
+#define BM_ENET_SWI_PORTSNOOP2_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP3 (0x000080c4)
+
+#define BP_ENET_SWI_PORTSNOOP3_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP3_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP3_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP3_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP3_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP3_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP3_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP3_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP3_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP3_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP3_MODE 1
+#define BM_ENET_SWI_PORTSNOOP3_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP3_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP3_MODE)
+#define BM_ENET_SWI_PORTSNOOP3_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP4 (0x000080c8)
+
+#define BP_ENET_SWI_PORTSNOOP4_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP4_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP4_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP4_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP4_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP4_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP4_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP4_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP4_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP4_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP4_MODE 1
+#define BM_ENET_SWI_PORTSNOOP4_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP4_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP4_MODE)
+#define BM_ENET_SWI_PORTSNOOP4_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP5 (0x000080cc)
+
+#define BP_ENET_SWI_PORTSNOOP5_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP5_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP5_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP5_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP5_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP5_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP5_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP5_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP5_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP5_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP5_MODE 1
+#define BM_ENET_SWI_PORTSNOOP5_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP5_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP5_MODE)
+#define BM_ENET_SWI_PORTSNOOP5_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP6 (0x000080d0)
+
+#define BP_ENET_SWI_PORTSNOOP6_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP6_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP6_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP6_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP6_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP6_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP6_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP6_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP6_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP6_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP6_MODE 1
+#define BM_ENET_SWI_PORTSNOOP6_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP6_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP6_MODE)
+#define BM_ENET_SWI_PORTSNOOP6_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP7 (0x000080d4)
+
+#define BP_ENET_SWI_PORTSNOOP7_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP7_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP7_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP7_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP7_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP7_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP7_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP7_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP7_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP7_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP7_MODE 1
+#define BM_ENET_SWI_PORTSNOOP7_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP7_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP7_MODE)
+#define BM_ENET_SWI_PORTSNOOP7_ENABLE 0x00000001
+
+#define HW_ENET_SWI_PORTSNOOP8 (0x000080d8)
+
+#define BP_ENET_SWI_PORTSNOOP8_DESTINATION_PORT 16
+#define BM_ENET_SWI_PORTSNOOP8_DESTINATION_PORT 0xFFFF0000
+#define BF_ENET_SWI_PORTSNOOP8_DESTINATION_PORT(v) \
+ (((v) << 16) & BM_ENET_SWI_PORTSNOOP8_DESTINATION_PORT)
+#define BP_ENET_SWI_PORTSNOOP8_RSRVD0 5
+#define BM_ENET_SWI_PORTSNOOP8_RSRVD0 0x0000FFE0
+#define BF_ENET_SWI_PORTSNOOP8_RSRVD0(v) \
+ (((v) << 5) & BM_ENET_SWI_PORTSNOOP8_RSRVD0)
+#define BM_ENET_SWI_PORTSNOOP8_COMPARE_SOURCE 0x00000010
+#define BM_ENET_SWI_PORTSNOOP8_COMPARE_DEST 0x00000008
+#define BP_ENET_SWI_PORTSNOOP8_MODE 1
+#define BM_ENET_SWI_PORTSNOOP8_MODE 0x00000006
+#define BF_ENET_SWI_PORTSNOOP8_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_PORTSNOOP8_MODE)
+#define BM_ENET_SWI_PORTSNOOP8_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP1 (0x000080dc)
+
+#define BP_ENET_SWI_IPSNOOP1_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP1_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP1_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP1_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP1_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP1_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP1_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP1_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP1_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP1_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP1_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP1_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP1_MODE 1
+#define BM_ENET_SWI_IPSNOOP1_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP1_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP1_MODE)
+#define BM_ENET_SWI_IPSNOOP1_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP2 (0x000080e0)
+
+#define BP_ENET_SWI_IPSNOOP2_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP2_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP2_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP2_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP2_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP2_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP2_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP2_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP2_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP2_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP2_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP2_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP2_MODE 1
+#define BM_ENET_SWI_IPSNOOP2_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP2_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP2_MODE)
+#define BM_ENET_SWI_IPSNOOP2_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP3 (0x000080e4)
+
+#define BP_ENET_SWI_IPSNOOP3_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP3_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP3_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP3_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP3_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP3_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP3_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP3_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP3_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP3_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP3_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP3_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP3_MODE 1
+#define BM_ENET_SWI_IPSNOOP3_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP3_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP3_MODE)
+#define BM_ENET_SWI_IPSNOOP3_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP4 (0x000080e8)
+
+#define BP_ENET_SWI_IPSNOOP4_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP4_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP4_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP4_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP4_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP4_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP4_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP4_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP4_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP4_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP4_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP4_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP4_MODE 1
+#define BM_ENET_SWI_IPSNOOP4_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP4_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP4_MODE)
+#define BM_ENET_SWI_IPSNOOP4_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP5 (0x000080ec)
+
+#define BP_ENET_SWI_IPSNOOP5_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP5_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP5_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP5_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP5_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP5_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP5_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP5_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP5_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP5_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP5_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP5_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP5_MODE 1
+#define BM_ENET_SWI_IPSNOOP5_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP5_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP5_MODE)
+#define BM_ENET_SWI_IPSNOOP5_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP6 (0x000080f0)
+
+#define BP_ENET_SWI_IPSNOOP6_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP6_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP6_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP6_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP6_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP6_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP6_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP6_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP6_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP6_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP6_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP6_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP6_MODE 1
+#define BM_ENET_SWI_IPSNOOP6_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP6_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP6_MODE)
+#define BM_ENET_SWI_IPSNOOP6_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP7 (0x000080f4)
+
+#define BP_ENET_SWI_IPSNOOP7_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP7_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP7_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP7_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP7_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP7_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP7_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP7_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP7_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP7_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP7_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP7_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP7_MODE 1
+#define BM_ENET_SWI_IPSNOOP7_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP7_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP7_MODE)
+#define BM_ENET_SWI_IPSNOOP7_ENABLE 0x00000001
+
+#define HW_ENET_SWI_IPSNOOP8 (0x000080f8)
+
+#define BP_ENET_SWI_IPSNOOP8_RSRVD1 16
+#define BM_ENET_SWI_IPSNOOP8_RSRVD1 0xFFFF0000
+#define BF_ENET_SWI_IPSNOOP8_RSRVD1(v) \
+ (((v) << 16) & BM_ENET_SWI_IPSNOOP8_RSRVD1)
+#define BP_ENET_SWI_IPSNOOP8_PROTOCOL 8
+#define BM_ENET_SWI_IPSNOOP8_PROTOCOL 0x0000FF00
+#define BF_ENET_SWI_IPSNOOP8_PROTOCOL(v) \
+ (((v) << 8) & BM_ENET_SWI_IPSNOOP8_PROTOCOL)
+#define BP_ENET_SWI_IPSNOOP8_RSRVD0 3
+#define BM_ENET_SWI_IPSNOOP8_RSRVD0 0x000000F8
+#define BF_ENET_SWI_IPSNOOP8_RSRVD0(v) \
+ (((v) << 3) & BM_ENET_SWI_IPSNOOP8_RSRVD0)
+#define BP_ENET_SWI_IPSNOOP8_MODE 1
+#define BM_ENET_SWI_IPSNOOP8_MODE 0x00000006
+#define BF_ENET_SWI_IPSNOOP8_MODE(v) \
+ (((v) << 1) & BM_ENET_SWI_IPSNOOP8_MODE)
+#define BM_ENET_SWI_IPSNOOP8_ENABLE 0x00000001
+
+#define HW_ENET_SWI_VLAN_PRIORITY0 (0x000080fc)
+
+#define BP_ENET_SWI_VLAN_PRIORITY0_RSRVD0 24
+#define BM_ENET_SWI_VLAN_PRIORITY0_RSRVD0 0xFF000000
+#define BF_ENET_SWI_VLAN_PRIORITY0_RSRVD0(v) \
+ (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY0_RSRVD0)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P7 21
+#define BM_ENET_SWI_VLAN_PRIORITY0_P7 0x00E00000
+#define BF_ENET_SWI_VLAN_PRIORITY0_P7(v) \
+ (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY0_P7)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P6 18
+#define BM_ENET_SWI_VLAN_PRIORITY0_P6 0x001C0000
+#define BF_ENET_SWI_VLAN_PRIORITY0_P6(v) \
+ (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY0_P6)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P5 15
+#define BM_ENET_SWI_VLAN_PRIORITY0_P5 0x00038000
+#define BF_ENET_SWI_VLAN_PRIORITY0_P5(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY0_P5)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P4 12
+#define BM_ENET_SWI_VLAN_PRIORITY0_P4 0x00007000
+#define BF_ENET_SWI_VLAN_PRIORITY0_P4(v) \
+ (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY0_P4)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P3 9
+#define BM_ENET_SWI_VLAN_PRIORITY0_P3 0x00000E00
+#define BF_ENET_SWI_VLAN_PRIORITY0_P3(v) \
+ (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY0_P3)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P2 6
+#define BM_ENET_SWI_VLAN_PRIORITY0_P2 0x000001C0
+#define BF_ENET_SWI_VLAN_PRIORITY0_P2(v) \
+ (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY0_P2)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P1 3
+#define BM_ENET_SWI_VLAN_PRIORITY0_P1 0x00000038
+#define BF_ENET_SWI_VLAN_PRIORITY0_P1(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY0_P1)
+#define BP_ENET_SWI_VLAN_PRIORITY0_P0 0
+#define BM_ENET_SWI_VLAN_PRIORITY0_P0 0x00000007
+#define BF_ENET_SWI_VLAN_PRIORITY0_P0(v) \
+ (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY0_P0)
+
+#define HW_ENET_SWI_VLAN_PRIORITY1 (0x00008100)
+
+#define BP_ENET_SWI_VLAN_PRIORITY1_RSRVD0 24
+#define BM_ENET_SWI_VLAN_PRIORITY1_RSRVD0 0xFF000000
+#define BF_ENET_SWI_VLAN_PRIORITY1_RSRVD0(v) \
+ (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY1_RSRVD0)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P7 21
+#define BM_ENET_SWI_VLAN_PRIORITY1_P7 0x00E00000
+#define BF_ENET_SWI_VLAN_PRIORITY1_P7(v) \
+ (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY1_P7)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P6 18
+#define BM_ENET_SWI_VLAN_PRIORITY1_P6 0x001C0000
+#define BF_ENET_SWI_VLAN_PRIORITY1_P6(v) \
+ (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY1_P6)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P5 15
+#define BM_ENET_SWI_VLAN_PRIORITY1_P5 0x00038000
+#define BF_ENET_SWI_VLAN_PRIORITY1_P5(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY1_P5)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P4 12
+#define BM_ENET_SWI_VLAN_PRIORITY1_P4 0x00007000
+#define BF_ENET_SWI_VLAN_PRIORITY1_P4(v) \
+ (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY1_P4)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P3 9
+#define BM_ENET_SWI_VLAN_PRIORITY1_P3 0x00000E00
+#define BF_ENET_SWI_VLAN_PRIORITY1_P3(v) \
+ (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY1_P3)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P2 6
+#define BM_ENET_SWI_VLAN_PRIORITY1_P2 0x000001C0
+#define BF_ENET_SWI_VLAN_PRIORITY1_P2(v) \
+ (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY1_P2)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P1 3
+#define BM_ENET_SWI_VLAN_PRIORITY1_P1 0x00000038
+#define BF_ENET_SWI_VLAN_PRIORITY1_P1(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY1_P1)
+#define BP_ENET_SWI_VLAN_PRIORITY1_P0 0
+#define BM_ENET_SWI_VLAN_PRIORITY1_P0 0x00000007
+#define BF_ENET_SWI_VLAN_PRIORITY1_P0(v) \
+ (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY1_P0)
+
+#define HW_ENET_SWI_VLAN_PRIORITY2 (0x00008104)
+
+#define BP_ENET_SWI_VLAN_PRIORITY2_RSRVD0 24
+#define BM_ENET_SWI_VLAN_PRIORITY2_RSRVD0 0xFF000000
+#define BF_ENET_SWI_VLAN_PRIORITY2_RSRVD0(v) \
+ (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY2_RSRVD0)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P7 21
+#define BM_ENET_SWI_VLAN_PRIORITY2_P7 0x00E00000
+#define BF_ENET_SWI_VLAN_PRIORITY2_P7(v) \
+ (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY2_P7)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P6 18
+#define BM_ENET_SWI_VLAN_PRIORITY2_P6 0x001C0000
+#define BF_ENET_SWI_VLAN_PRIORITY2_P6(v) \
+ (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY2_P6)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P5 15
+#define BM_ENET_SWI_VLAN_PRIORITY2_P5 0x00038000
+#define BF_ENET_SWI_VLAN_PRIORITY2_P5(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY2_P5)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P4 12
+#define BM_ENET_SWI_VLAN_PRIORITY2_P4 0x00007000
+#define BF_ENET_SWI_VLAN_PRIORITY2_P4(v) \
+ (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY2_P4)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P3 9
+#define BM_ENET_SWI_VLAN_PRIORITY2_P3 0x00000E00
+#define BF_ENET_SWI_VLAN_PRIORITY2_P3(v) \
+ (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY2_P3)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P2 6
+#define BM_ENET_SWI_VLAN_PRIORITY2_P2 0x000001C0
+#define BF_ENET_SWI_VLAN_PRIORITY2_P2(v) \
+ (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY2_P2)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P1 3
+#define BM_ENET_SWI_VLAN_PRIORITY2_P1 0x00000038
+#define BF_ENET_SWI_VLAN_PRIORITY2_P1(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY2_P1)
+#define BP_ENET_SWI_VLAN_PRIORITY2_P0 0
+#define BM_ENET_SWI_VLAN_PRIORITY2_P0 0x00000007
+#define BF_ENET_SWI_VLAN_PRIORITY2_P0(v) \
+ (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY2_P0)
+
+#define HW_ENET_SWI_IP_PRIORITY (0x0000813c)
+
+#define BM_ENET_SWI_IP_PRIORITY_READ 0x80000000
+#define BP_ENET_SWI_IP_PRIORITY_RSRVD0 15
+#define BM_ENET_SWI_IP_PRIORITY_RSRVD0 0x7FFF8000
+#define BF_ENET_SWI_IP_PRIORITY_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_IP_PRIORITY_RSRVD0)
+#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2 13
+#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2 0x00006000
+#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2(v) \
+ (((v) << 13) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2)
+#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1 11
+#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1 0x00001800
+#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1(v) \
+ (((v) << 11) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1)
+#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0 9
+#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0 0x00000600
+#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0(v) \
+ (((v) << 9) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0)
+#define BM_ENET_SWI_IP_PRIORITY_IPV4_SELECT 0x00000100
+#define BP_ENET_SWI_IP_PRIORITY_ADDRESS 0
+#define BM_ENET_SWI_IP_PRIORITY_ADDRESS 0x000000FF
+#define BF_ENET_SWI_IP_PRIORITY_ADDRESS(v) \
+ (((v) << 0) & BM_ENET_SWI_IP_PRIORITY_ADDRESS)
+
+#define HW_ENET_SWI_PRIORITY_CFG0 (0x0000817c)
+
+#define BP_ENET_SWI_PRIORITY_CFG0_RSRVD1 7
+#define BM_ENET_SWI_PRIORITY_CFG0_RSRVD1 0xFFFFFF80
+#define BF_ENET_SWI_PRIORITY_CFG0_RSRVD1(v) \
+ (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG0_RSRVD1)
+#define BP_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY 4
+#define BM_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY 0x00000070
+#define BF_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY(v) \
+ (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY)
+#define BM_ENET_SWI_PRIORITY_CFG0_RSRVD0 0x00000008
+#define BM_ENET_SWI_PRIORITY_CFG0_MAC_EN 0x00000004
+#define BM_ENET_SWI_PRIORITY_CFG0_IP_EN 0x00000002
+#define BM_ENET_SWI_PRIORITY_CFG0_VLAN_EN 0x00000001
+
+#define HW_ENET_SWI_PRIORITY_CFG1 (0x00008180)
+
+#define BP_ENET_SWI_PRIORITY_CFG1_RSRVD1 7
+#define BM_ENET_SWI_PRIORITY_CFG1_RSRVD1 0xFFFFFF80
+#define BF_ENET_SWI_PRIORITY_CFG1_RSRVD1(v) \
+ (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG1_RSRVD1)
+#define BP_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY 4
+#define BM_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY 0x00000070
+#define BF_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY(v) \
+ (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY)
+#define BM_ENET_SWI_PRIORITY_CFG1_RSRVD0 0x00000008
+#define BM_ENET_SWI_PRIORITY_CFG1_MAC_EN 0x00000004
+#define BM_ENET_SWI_PRIORITY_CFG1_IP_EN 0x00000002
+#define BM_ENET_SWI_PRIORITY_CFG1_VLAN_EN 0x00000001
+
+#define HW_ENET_SWI_PRIORITY_CFG2 (0x00008184)
+
+#define BP_ENET_SWI_PRIORITY_CFG2_RSRVD1 7
+#define BM_ENET_SWI_PRIORITY_CFG2_RSRVD1 0xFFFFFF80
+#define BF_ENET_SWI_PRIORITY_CFG2_RSRVD1(v) \
+ (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG2_RSRVD1)
+#define BP_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY 4
+#define BM_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY 0x00000070
+#define BF_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY(v) \
+ (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY)
+#define BM_ENET_SWI_PRIORITY_CFG2_RSRVD0 0x00000008
+#define BM_ENET_SWI_PRIORITY_CFG2_MAC_EN 0x00000004
+#define BM_ENET_SWI_PRIORITY_CFG2_IP_EN 0x00000002
+#define BM_ENET_SWI_PRIORITY_CFG2_VLAN_EN 0x00000001
+
+#define HW_ENET_SWI_SYSTEM_TAGINFO0 (0x000081fc)
+
+#define BP_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0 16
+#define BM_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0)
+#define BP_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0 0
+#define BM_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0 0x0000FFFF
+#define BF_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0(v) \
+ (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0)
+
+#define HW_ENET_SWI_SYSTEM_TAGINFO1 (0x00008200)
+
+#define BP_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0 16
+#define BM_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0)
+#define BP_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0 0
+#define BM_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0 0x0000FFFF
+#define BF_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0(v) \
+ (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0)
+
+#define HW_ENET_SWI_SYSTEM_TAGINFO2 (0x00008204)
+
+#define BP_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0 16
+#define BM_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0 0xFFFF0000
+#define BF_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0(v) \
+ (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0)
+#define BP_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0 0
+#define BM_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0 0x0000FFFF
+#define BF_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0(v) \
+ (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0)
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_0 (0x0000827c)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0)
+#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_1 (0x00008280)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1)
+#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_2 (0x00008284)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2)
+#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_3 (0x00008288)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3)
+#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_4 (0x0000828c)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4)
+#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_5 (0x00008290)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5)
+#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_6 (0x00008294)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6)
+#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_7 (0x00008298)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7)
+#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_8 (0x0000829c)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8)
+#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_9 (0x000082a0)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9)
+#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_10 (0x000082a4)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10)
+#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_11 (0x000082a8)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11)
+#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_12 (0x000082ac)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12)
+#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_13 (0x000082b0)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13)
+#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_14 (0x000082b4)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14)
+#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_15 (0x000082b8)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15)
+#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_16 (0x000082bc)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16)
+#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_17 (0x000082c0)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17)
+#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_18 (0x000082c4)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18)
+#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_19 (0x000082c8)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19)
+#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_20 (0x000082cc)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20)
+#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_21 (0x000082d0)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21)
+#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_22 (0x000082d4)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22)
+#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_23 (0x000082d8)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23)
+#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_24 (0x000082dc)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24)
+#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_25 (0x000082e0)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25)
+#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_26 (0x000082e4)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26)
+#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_27 (0x000082e8)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27)
+#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_28 (0x000082ec)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28)
+#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_29 (0x000082f0)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29)
+#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_30 (0x000082f4)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30)
+#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_0 0x00000001
+
+#define HW_ENET_SWI_VLAN_RES_TABLE_31 (0x000082f8)
+
+#define BP_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0 15
+#define BM_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0 0xFFFF8000
+#define BF_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0(v) \
+ (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0)
+#define BP_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31 3
+#define BM_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31 0x00007FF8
+#define BF_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31(v) \
+ (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31)
+#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_2 0x00000004
+#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_1 0x00000002
+#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_0 0x00000001
+
+#define HW_ENET_SWI_TOTAL_DISC (0x000082fc)
+
+#define BP_ENET_SWI_TOTAL_DISC_TOTAL_DISC 0
+#define BM_ENET_SWI_TOTAL_DISC_TOTAL_DISC 0xFFFFFFFF
+#define BF_ENET_SWI_TOTAL_DISC_TOTAL_DISC(v) (v)
+
+#define HW_ENET_SWI_TOTAL_BYT_DISC (0x00008300)
+
+#define BP_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC 0
+#define BM_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC 0xFFFFFFFF
+#define BF_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC(v) (v)
+
+#define HW_ENET_SWI_TOTAL_FRM (0x00008304)
+
+#define BP_ENET_SWI_TOTAL_FRM_TOTAL_FRM 0
+#define BM_ENET_SWI_TOTAL_FRM_TOTAL_FRM 0xFFFFFFFF
+#define BF_ENET_SWI_TOTAL_FRM_TOTAL_FRM(v) (v)
+
+#define HW_ENET_SWI_TOTAL_BYT_FRM (0x00008308)
+
+#define BP_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM 0
+#define BM_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM 0xFFFFFFFF
+#define BF_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM(v) (v)
+
+#define HW_ENET_SWI_ODISC0 (0x0000830c)
+
+#define BP_ENET_SWI_ODISC0_ODISC0 0
+#define BM_ENET_SWI_ODISC0_ODISC0 0xFFFFFFFF
+#define BF_ENET_SWI_ODISC0_ODISC0(v) (v)
+
+#define HW_ENET_SWI_IDISC_VLAN0 (0x00008310)
+
+#define BP_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0 0
+#define BM_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0(v) (v)
+
+#define HW_ENET_SWI_IDISC_UNTAGGED0 (0x00008314)
+
+#define BP_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0 0
+#define BM_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0(v) (v)
+
+#define HW_ENET_SWI_IDISC_BLOCKED0 (0x00008318)
+
+#define BP_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0 0
+#define BM_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0(v) (v)
+
+#define HW_ENET_SWI_ODISC1 (0x0000831c)
+
+#define BP_ENET_SWI_ODISC1_ODISC1 0
+#define BM_ENET_SWI_ODISC1_ODISC1 0xFFFFFFFF
+#define BF_ENET_SWI_ODISC1_ODISC1(v) (v)
+
+#define HW_ENET_SWI_IDISC_VLAN1 (0x00008320)
+
+#define BP_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1 0
+#define BM_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1(v) (v)
+
+#define HW_ENET_SWI_IDISC_UNTAGGED1 (0x00008324)
+
+#define BP_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1 0
+#define BM_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1(v) (v)
+
+#define HW_ENET_SWI_IDISC_BLOCKED1 (0x00008328)
+
+#define BP_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1 0
+#define BM_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1(v) (v)
+
+#define HW_ENET_SWI_ODISC2 (0x0000832c)
+
+#define BP_ENET_SWI_ODISC2_ODISC2 0
+#define BM_ENET_SWI_ODISC2_ODISC2 0xFFFFFFFF
+#define BF_ENET_SWI_ODISC2_ODISC2(v) (v)
+
+#define HW_ENET_SWI_IDISC_VLAN2 (0x00008330)
+
+#define BP_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2 0
+#define BM_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2(v) (v)
+
+#define HW_ENET_SWI_IDISC_UNTAGGED2 (0x00008334)
+
+#define BP_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2 0
+#define BM_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2(v) (v)
+
+#define HW_ENET_SWI_IDISC_BLOCKED2 (0x00008338)
+
+#define BP_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2 0
+#define BM_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2 0xFFFFFFFF
+#define BF_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2(v) (v)
+
+#define HW_ENET_SWI_EIR (0x000083fc)
+
+#define BP_ENET_SWI_EIR_RSRVD0 10
+#define BM_ENET_SWI_EIR_RSRVD0 0xFFFFFC00
+#define BF_ENET_SWI_EIR_RSRVD0(v) \
+ (((v) << 10) & BM_ENET_SWI_EIR_RSRVD0)
+#define BM_ENET_SWI_EIR_LRN 0x00000200
+#define BM_ENET_SWI_EIR_OD2 0x00000100
+#define BM_ENET_SWI_EIR_OD1 0x00000080
+#define BM_ENET_SWI_EIR_OD0 0x00000040
+#define BM_ENET_SWI_EIR_QM 0x00000020
+#define BM_ENET_SWI_EIR_TXF 0x00000010
+#define BM_ENET_SWI_EIR_TXB 0x00000008
+#define BM_ENET_SWI_EIR_RXF 0x00000004
+#define BM_ENET_SWI_EIR_RXB 0x00000002
+#define BM_ENET_SWI_EIR_EBERR 0x00000001
+
+#define HW_ENET_SWI_EIMR (0x00008400)
+
+#define BP_ENET_SWI_EIMR_RSRVD0 10
+#define BM_ENET_SWI_EIMR_RSRVD0 0xFFFFFC00
+#define BF_ENET_SWI_EIMR_RSRVD0(v) \
+ (((v) << 10) & BM_ENET_SWI_EIMR_RSRVD0)
+#define BM_ENET_SWI_EIMR_LRN 0x00000200
+#define BM_ENET_SWI_EIMR_OD2 0x00000100
+#define BM_ENET_SWI_EIMR_OD1 0x00000080
+#define BM_ENET_SWI_EIMR_OD0 0x00000040
+#define BM_ENET_SWI_EIMR_QM 0x00000020
+#define BM_ENET_SWI_EIMR_TXF 0x00000010
+#define BM_ENET_SWI_EIMR_TXB 0x00000008
+#define BM_ENET_SWI_EIMR_RXF 0x00000004
+#define BM_ENET_SWI_EIMR_RXB 0x00000002
+#define BM_ENET_SWI_EIMR_EBERR 0x00000001
+
+#define HW_ENET_SWI_ERDSR (0x00008404)
+
+#define BP_ENET_SWI_ERDSR_ERDSR 2
+#define BM_ENET_SWI_ERDSR_ERDSR 0xFFFFFFFC
+#define BF_ENET_SWI_ERDSR_ERDSR(v) \
+ (((v) << 2) & BM_ENET_SWI_ERDSR_ERDSR)
+#define BP_ENET_SWI_ERDSR_RSRVD0 0
+#define BM_ENET_SWI_ERDSR_RSRVD0 0x00000003
+#define BF_ENET_SWI_ERDSR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_SWI_ERDSR_RSRVD0)
+
+#define HW_ENET_SWI_ETDSR (0x00008408)
+
+#define BP_ENET_SWI_ETDSR_ETDSR 2
+#define BM_ENET_SWI_ETDSR_ETDSR 0xFFFFFFFC
+#define BF_ENET_SWI_ETDSR_ETDSR(v) \
+ (((v) << 2) & BM_ENET_SWI_ETDSR_ETDSR)
+#define BP_ENET_SWI_ETDSR_RSRVD0 0
+#define BM_ENET_SWI_ETDSR_RSRVD0 0x00000003
+#define BF_ENET_SWI_ETDSR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_SWI_ETDSR_RSRVD0)
+
+#define HW_ENET_SWI_EMRBR (0x0000840c)
+
+#define BP_ENET_SWI_EMRBR_RSRVD1 14
+#define BM_ENET_SWI_EMRBR_RSRVD1 0xFFFFC000
+#define BF_ENET_SWI_EMRBR_RSRVD1(v) \
+ (((v) << 14) & BM_ENET_SWI_EMRBR_RSRVD1)
+#define BP_ENET_SWI_EMRBR_EMRBR 4
+#define BM_ENET_SWI_EMRBR_EMRBR 0x00003FF0
+#define BF_ENET_SWI_EMRBR_EMRBR(v) \
+ (((v) << 4) & BM_ENET_SWI_EMRBR_EMRBR)
+#define BP_ENET_SWI_EMRBR_RSRVD0 0
+#define BM_ENET_SWI_EMRBR_RSRVD0 0x0000000F
+#define BF_ENET_SWI_EMRBR_RSRVD0(v) \
+ (((v) << 0) & BM_ENET_SWI_EMRBR_RSRVD0)
+
+#define HW_ENET_SWI_RDAR (0x00008410)
+
+#define BP_ENET_SWI_RDAR_RDAR 0
+#define BM_ENET_SWI_RDAR_RDAR 0xFFFFFFFF
+#define BF_ENET_SWI_RDAR_RDAR(v) (v)
+
+#define HW_ENET_SWI_TDAR (0x00008414)
+
+#define BP_ENET_SWI_TDAR_TDAR 0
+#define BM_ENET_SWI_TDAR_TDAR 0xFFFFFFFF
+#define BF_ENET_SWI_TDAR_TDAR(v) (v)
+
+#define HW_ENET_SWI_LRN_REC_0 (0x000084fc)
+
+#define BP_ENET_SWI_LRN_REC_0_LRN_REC_0 0
+#define BM_ENET_SWI_LRN_REC_0_LRN_REC_0 0xFFFFFFFF
+#define BF_ENET_SWI_LRN_REC_0_LRN_REC_0(v) (v)
+
+#define HW_ENET_SWI_LRN_REC_1 (0x00008500)
+
+#define BP_ENET_SWI_LRN_REC_1_RSRVD0 26
+#define BM_ENET_SWI_LRN_REC_1_RSRVD0 0xFC000000
+#define BF_ENET_SWI_LRN_REC_1_RSRVD0(v) \
+ (((v) << 26) & BM_ENET_SWI_LRN_REC_1_RSRVD0)
+#define BP_ENET_SWI_LRN_REC_1_SW_PORT 24
+#define BM_ENET_SWI_LRN_REC_1_SW_PORT 0x03000000
+#define BF_ENET_SWI_LRN_REC_1_SW_PORT(v) \
+ (((v) << 24) & BM_ENET_SWI_LRN_REC_1_SW_PORT)
+#define BP_ENET_SWI_LRN_REC_1_HASH 16
+#define BM_ENET_SWI_LRN_REC_1_HASH 0x00FF0000
+#define BF_ENET_SWI_LRN_REC_1_HASH(v) \
+ (((v) << 16) & BM_ENET_SWI_LRN_REC_1_HASH)
+#define BP_ENET_SWI_LRN_REC_1_MAC_ADDR1 0
+#define BM_ENET_SWI_LRN_REC_1_MAC_ADDR1 0x0000FFFF
+#define BF_ENET_SWI_LRN_REC_1_MAC_ADDR1(v) \
+ (((v) << 0) & BM_ENET_SWI_LRN_REC_1_MAC_ADDR1)
+
+#define HW_ENET_SWI_LRN_STATUS (0x00008504)
+
+#define BP_ENET_SWI_LRN_STATUS_RSRVD0 1
+#define BM_ENET_SWI_LRN_STATUS_RSRVD0 0xFFFFFFFE
+#define BF_ENET_SWI_LRN_STATUS_RSRVD0(v) \
+ (((v) << 1) & BM_ENET_SWI_LRN_STATUS_RSRVD0)
+#define BM_ENET_SWI_LRN_STATUS_LRN_STATUS 0x00000001
+
+#define HW_ENET_SWI_LOOKUP_MEMORY_START (0x0000bffc)
+
+#define BP_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA 0
+#define BM_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA 0xFFFFFFFF
+#define BF_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA(v) (v)
+
+#define HW_ENET_SWI_LOOKUP_MEMORY_END (0x0000fff8)
+
+#define BP_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA 0
+#define BM_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA 0xFFFFFFFF
+#define BF_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA(v) (v)
+#endif /* __ARCH_ARM___ENET_H */
diff --git a/include/asm-arm/arch-mx28/regs-pinctrl.h b/include/asm-arm/arch-mx28/regs-pinctrl.h
new file mode 100644
index 0000000..82046f3
--- /dev/null
+++ b/include/asm-arm/arch-mx28/regs-pinctrl.h
@@ -0,0 +1,2674 @@
+/*
+ * Freescale PINCTRL Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.19
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___PINCTRL_H
+#define __ARCH_ARM___PINCTRL_H
+
+
+#define HW_PINCTRL_CTRL (0x00000000)
+#define HW_PINCTRL_CTRL_SET (0x00000004)
+#define HW_PINCTRL_CTRL_CLR (0x00000008)
+#define HW_PINCTRL_CTRL_TOG (0x0000000c)
+
+#define BM_PINCTRL_CTRL_SFTRST 0x80000000
+#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
+#define BP_PINCTRL_CTRL_RSRVD2 25
+#define BM_PINCTRL_CTRL_RSRVD2 0x3E000000
+#define BF_PINCTRL_CTRL_RSRVD2(v) \
+ (((v) << 25) & BM_PINCTRL_CTRL_RSRVD2)
+#define BM_PINCTRL_CTRL_PRESENT4 0x01000000
+#define BM_PINCTRL_CTRL_PRESENT3 0x00800000
+#define BM_PINCTRL_CTRL_PRESENT2 0x00400000
+#define BM_PINCTRL_CTRL_PRESENT1 0x00200000
+#define BM_PINCTRL_CTRL_PRESENT0 0x00100000
+#define BP_PINCTRL_CTRL_RSRVD1 5
+#define BM_PINCTRL_CTRL_RSRVD1 0x000FFFE0
+#define BF_PINCTRL_CTRL_RSRVD1(v) \
+ (((v) << 5) & BM_PINCTRL_CTRL_RSRVD1)
+#define BM_PINCTRL_CTRL_IRQOUT4 0x00000010
+#define BM_PINCTRL_CTRL_IRQOUT3 0x00000008
+#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004
+#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002
+#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001
+
+#define HW_PINCTRL_MUXSEL0 (0x00000100)
+#define HW_PINCTRL_MUXSEL0_SET (0x00000104)
+#define HW_PINCTRL_MUXSEL0_CLR (0x00000108)
+#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c)
+
+#define BP_PINCTRL_MUXSEL0_RSRVD0 16
+#define BM_PINCTRL_MUXSEL0_RSRVD0 0xFFFF0000
+#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00)
+
+#define HW_PINCTRL_MUXSEL1 (0x00000110)
+#define HW_PINCTRL_MUXSEL1_SET (0x00000114)
+#define HW_PINCTRL_MUXSEL1_CLR (0x00000118)
+#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c)
+
+#define BP_PINCTRL_MUXSEL1_RSRVD0 26
+#define BM_PINCTRL_MUXSEL1_RSRVD0 0xFC000000
+#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16)
+
+#define HW_PINCTRL_MUXSEL2 (0x00000120)
+#define HW_PINCTRL_MUXSEL2_SET (0x00000124)
+#define HW_PINCTRL_MUXSEL2_CLR (0x00000128)
+#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c)
+
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00)
+
+#define HW_PINCTRL_MUXSEL3 (0x00000130)
+#define HW_PINCTRL_MUXSEL3_SET (0x00000134)
+#define HW_PINCTRL_MUXSEL3_CLR (0x00000138)
+#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c)
+
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN31 30
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN31 0xC0000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16)
+
+#define HW_PINCTRL_MUXSEL4 (0x00000140)
+#define HW_PINCTRL_MUXSEL4_SET (0x00000144)
+#define HW_PINCTRL_MUXSEL4_CLR (0x00000148)
+#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c)
+
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12)
+#define BP_PINCTRL_MUXSEL4_RSRVD0 22
+#define BM_PINCTRL_MUXSEL4_RSRVD0 0x00C00000
+#define BF_PINCTRL_MUXSEL4_RSRVD0(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00)
+
+#define HW_PINCTRL_MUXSEL5 (0x00000150)
+#define HW_PINCTRL_MUXSEL5_SET (0x00000154)
+#define HW_PINCTRL_MUXSEL5_CLR (0x00000158)
+#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c)
+
+#define BP_PINCTRL_MUXSEL5_RSRVD1 24
+#define BM_PINCTRL_MUXSEL5_RSRVD1 0xFF000000
+#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24)
+#define BP_PINCTRL_MUXSEL5_RSRVD0 12
+#define BM_PINCTRL_MUXSEL5_RSRVD0 0x0000F000
+#define BF_PINCTRL_MUXSEL5_RSRVD0(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16)
+
+#define HW_PINCTRL_MUXSEL6 (0x00000160)
+#define HW_PINCTRL_MUXSEL6_SET (0x00000164)
+#define HW_PINCTRL_MUXSEL6_CLR (0x00000168)
+#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c)
+
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00)
+
+#define HW_PINCTRL_MUXSEL7 (0x00000170)
+#define HW_PINCTRL_MUXSEL7_SET (0x00000174)
+#define HW_PINCTRL_MUXSEL7_CLR (0x00000178)
+#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c)
+
+#define BP_PINCTRL_MUXSEL7_RSRVD1 30
+#define BM_PINCTRL_MUXSEL7_RSRVD1 0xC0000000
+#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN30 28
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN30 0x30000000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN29 26
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN29 0x0C000000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN28 24
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN28 0x03000000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN27 22
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN26 20
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN25 18
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN24 16
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN23 14
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN22 12
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20)
+#define BP_PINCTRL_MUXSEL7_RSRVD0 6
+#define BM_PINCTRL_MUXSEL7_RSRVD0 0x000000C0
+#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16)
+
+#define HW_PINCTRL_MUXSEL8 (0x00000180)
+#define HW_PINCTRL_MUXSEL8_SET (0x00000184)
+#define HW_PINCTRL_MUXSEL8_CLR (0x00000188)
+#define HW_PINCTRL_MUXSEL8_TOG (0x0000018c)
+
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN15 30
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN14 28
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN13 26
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN12 24
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN11 22
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN10 20
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN09 18
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN08 16
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN07 14
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN06 12
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN05 10
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN04 8
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN03 6
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN02 4
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN01 2
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01)
+#define BP_PINCTRL_MUXSEL8_BANK4_PIN00 0
+#define BM_PINCTRL_MUXSEL8_BANK4_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00)
+
+#define HW_PINCTRL_MUXSEL9 (0x00000190)
+#define HW_PINCTRL_MUXSEL9_SET (0x00000194)
+#define HW_PINCTRL_MUXSEL9_CLR (0x00000198)
+#define HW_PINCTRL_MUXSEL9_TOG (0x0000019c)
+
+#define BP_PINCTRL_MUXSEL9_RSRVD1 10
+#define BM_PINCTRL_MUXSEL9_RSRVD1 0xFFFFFC00
+#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1)
+#define BP_PINCTRL_MUXSEL9_BANK4_PIN20 8
+#define BM_PINCTRL_MUXSEL9_BANK4_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20)
+#define BP_PINCTRL_MUXSEL9_RSRVD0 2
+#define BM_PINCTRL_MUXSEL9_RSRVD0 0x000000FC
+#define BF_PINCTRL_MUXSEL9_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0)
+#define BP_PINCTRL_MUXSEL9_BANK4_PIN16 0
+#define BM_PINCTRL_MUXSEL9_BANK4_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16)
+
+#define HW_PINCTRL_MUXSEL10 (0x000001a0)
+#define HW_PINCTRL_MUXSEL10_SET (0x000001a4)
+#define HW_PINCTRL_MUXSEL10_CLR (0x000001a8)
+#define HW_PINCTRL_MUXSEL10_TOG (0x000001ac)
+
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN15 30
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN14 28
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN13 26
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN12 24
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN11 22
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN10 20
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN09 18
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN08 16
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN07 14
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN06 12
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN05 10
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN04 8
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN03 6
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN02 4
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN01 2
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01)
+#define BP_PINCTRL_MUXSEL10_BANK5_PIN00 0
+#define BM_PINCTRL_MUXSEL10_BANK5_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00)
+
+#define HW_PINCTRL_MUXSEL11 (0x000001b0)
+#define HW_PINCTRL_MUXSEL11_SET (0x000001b4)
+#define HW_PINCTRL_MUXSEL11_CLR (0x000001b8)
+#define HW_PINCTRL_MUXSEL11_TOG (0x000001bc)
+
+#define BP_PINCTRL_MUXSEL11_RSRVD1 22
+#define BM_PINCTRL_MUXSEL11_RSRVD1 0xFFC00000
+#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN26 20
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26)
+#define BP_PINCTRL_MUXSEL11_RSRVD0 16
+#define BM_PINCTRL_MUXSEL11_RSRVD0 0x000F0000
+#define BF_PINCTRL_MUXSEL11_RSRVD0(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN23 14
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN22 12
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN21 10
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN20 8
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN19 6
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN18 4
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN17 2
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17)
+#define BP_PINCTRL_MUXSEL11_BANK5_PIN16 0
+#define BM_PINCTRL_MUXSEL11_BANK5_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16)
+
+#define HW_PINCTRL_MUXSEL12 (0x000001c0)
+#define HW_PINCTRL_MUXSEL12_SET (0x000001c4)
+#define HW_PINCTRL_MUXSEL12_CLR (0x000001c8)
+#define HW_PINCTRL_MUXSEL12_TOG (0x000001cc)
+
+#define BP_PINCTRL_MUXSEL12_RSRVD0 30
+#define BM_PINCTRL_MUXSEL12_RSRVD0 0xC0000000
+#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN14 28
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN13 26
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN12 24
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN11 22
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN10 20
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN09 18
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN08 16
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN07 14
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN06 12
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN05 10
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN04 8
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN03 6
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN02 4
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN01 2
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01)
+#define BP_PINCTRL_MUXSEL12_BANK6_PIN00 0
+#define BM_PINCTRL_MUXSEL12_BANK6_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00)
+
+#define HW_PINCTRL_MUXSEL13 (0x000001d0)
+#define HW_PINCTRL_MUXSEL13_SET (0x000001d4)
+#define HW_PINCTRL_MUXSEL13_CLR (0x000001d8)
+#define HW_PINCTRL_MUXSEL13_TOG (0x000001dc)
+
+#define BP_PINCTRL_MUXSEL13_RSRVD0 18
+#define BM_PINCTRL_MUXSEL13_RSRVD0 0xFFFC0000
+#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN24 16
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN23 14
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN22 12
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN21 10
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN20 8
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN19 6
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN18 4
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN17 2
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17)
+#define BP_PINCTRL_MUXSEL13_BANK6_PIN16 0
+#define BM_PINCTRL_MUXSEL13_BANK6_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16)
+
+#define HW_PINCTRL_DRIVE0 (0x00000300)
+#define HW_PINCTRL_DRIVE0_SET (0x00000304)
+#define HW_PINCTRL_DRIVE0_CLR (0x00000308)
+#define HW_PINCTRL_DRIVE0_TOG (0x0000030c)
+
+#define BM_PINCTRL_DRIVE0_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V 0x40000000
+#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28
+#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V 0x04000000
+#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24
+#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V 0x00400000
+#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20
+#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V 0x00040000
+#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16
+#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V 0x00004000
+#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12
+#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V 0x00000400
+#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8
+#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V 0x00000040
+#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4
+#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA)
+#define BM_PINCTRL_DRIVE0_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V 0x00000004
+#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0
+#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE1 (0x00000310)
+#define HW_PINCTRL_DRIVE1_SET (0x00000314)
+#define HW_PINCTRL_DRIVE1_CLR (0x00000318)
+#define HW_PINCTRL_DRIVE1_TOG (0x0000031c)
+
+#define BP_PINCTRL_DRIVE1_RSRVD0 0
+#define BM_PINCTRL_DRIVE1_RSRVD0 0xFFFFFFFF
+#define BF_PINCTRL_DRIVE1_RSRVD0(v) (v)
+
+#define HW_PINCTRL_DRIVE2 (0x00000320)
+#define HW_PINCTRL_DRIVE2_SET (0x00000324)
+#define HW_PINCTRL_DRIVE2_CLR (0x00000328)
+#define HW_PINCTRL_DRIVE2_TOG (0x0000032c)
+
+#define BM_PINCTRL_DRIVE2_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V 0x40000000
+#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28
+#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V 0x04000000
+#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24
+#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V 0x00400000
+#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20
+#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16
+#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V 0x00004000
+#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12
+#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V 0x00000400
+#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8
+#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V 0x00000040
+#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4
+#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA)
+#define BM_PINCTRL_DRIVE2_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0
+#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE3 (0x00000330)
+#define HW_PINCTRL_DRIVE3_SET (0x00000334)
+#define HW_PINCTRL_DRIVE3_CLR (0x00000338)
+#define HW_PINCTRL_DRIVE3_TOG (0x0000033c)
+
+#define BP_PINCTRL_DRIVE3_RSRVD5 20
+#define BM_PINCTRL_DRIVE3_RSRVD5 0xFFF00000
+#define BF_PINCTRL_DRIVE3_RSRVD5(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5)
+#define BM_PINCTRL_DRIVE3_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V 0x00040000
+#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16
+#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA)
+#define BM_PINCTRL_DRIVE3_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V 0x00004000
+#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12
+#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA)
+#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V 0x00000400
+#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8
+#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA)
+#define BM_PINCTRL_DRIVE3_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V 0x00000040
+#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4
+#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA)
+#define BM_PINCTRL_DRIVE3_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V 0x00000004
+#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0
+#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE4 (0x00000340)
+#define HW_PINCTRL_DRIVE4_SET (0x00000344)
+#define HW_PINCTRL_DRIVE4_CLR (0x00000348)
+#define HW_PINCTRL_DRIVE4_TOG (0x0000034c)
+
+#define BM_PINCTRL_DRIVE4_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V 0x40000000
+#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28
+#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V 0x04000000
+#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24
+#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V 0x00400000
+#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20
+#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V 0x00040000
+#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16
+#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V 0x00004000
+#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12
+#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V 0x00000400
+#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8
+#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V 0x00000040
+#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4
+#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA)
+#define BM_PINCTRL_DRIVE4_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V 0x00000004
+#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0
+#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE5 (0x00000350)
+#define HW_PINCTRL_DRIVE5_SET (0x00000354)
+#define HW_PINCTRL_DRIVE5_CLR (0x00000358)
+#define HW_PINCTRL_DRIVE5_TOG (0x0000035c)
+
+#define BM_PINCTRL_DRIVE5_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V 0x40000000
+#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28
+#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V 0x04000000
+#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24
+#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V 0x00400000
+#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20
+#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V 0x00040000
+#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16
+#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V 0x00004000
+#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12
+#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V 0x00000400
+#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8
+#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V 0x00000040
+#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4
+#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA)
+#define BM_PINCTRL_DRIVE5_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V 0x00000004
+#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0
+#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE6 (0x00000360)
+#define HW_PINCTRL_DRIVE6_SET (0x00000364)
+#define HW_PINCTRL_DRIVE6_CLR (0x00000368)
+#define HW_PINCTRL_DRIVE6_TOG (0x0000036c)
+
+#define BM_PINCTRL_DRIVE6_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V 0x40000000
+#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28
+#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V 0x04000000
+#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24
+#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V 0x00400000
+#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20
+#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16
+#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V 0x00004000
+#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12
+#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V 0x00000400
+#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8
+#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V 0x00000040
+#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4
+#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA)
+#define BM_PINCTRL_DRIVE6_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0
+#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE7 (0x00000370)
+#define HW_PINCTRL_DRIVE7_SET (0x00000374)
+#define HW_PINCTRL_DRIVE7_CLR (0x00000378)
+#define HW_PINCTRL_DRIVE7_TOG (0x0000037c)
+
+#define BM_PINCTRL_DRIVE7_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V 0x40000000
+#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA 28
+#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA 0x30000000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V 0x04000000
+#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24
+#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V 0x00400000
+#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20
+#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V 0x00040000
+#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16
+#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V 0x00004000
+#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12
+#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V 0x00000400
+#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8
+#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V 0x00000040
+#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4
+#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA)
+#define BM_PINCTRL_DRIVE7_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V 0x00000004
+#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0
+#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE8 (0x00000380)
+#define HW_PINCTRL_DRIVE8_SET (0x00000384)
+#define HW_PINCTRL_DRIVE8_CLR (0x00000388)
+#define HW_PINCTRL_DRIVE8_TOG (0x0000038c)
+
+#define BM_PINCTRL_DRIVE8_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V 0x40000000
+#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28
+#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V 0x04000000
+#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24
+#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V 0x00400000
+#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20
+#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V 0x00040000
+#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16
+#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V 0x00004000
+#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12
+#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V 0x00000400
+#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8
+#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V 0x00000040
+#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4
+#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA)
+#define BM_PINCTRL_DRIVE8_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V 0x00000004
+#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0
+#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE9 (0x00000390)
+#define HW_PINCTRL_DRIVE9_SET (0x00000394)
+#define HW_PINCTRL_DRIVE9_CLR (0x00000398)
+#define HW_PINCTRL_DRIVE9_TOG (0x0000039c)
+
+#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28
+#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24
+#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20
+#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16
+#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA)
+#define BP_PINCTRL_DRIVE9_RSRVD3 12
+#define BM_PINCTRL_DRIVE9_RSRVD3 0x0000F000
+#define BF_PINCTRL_DRIVE9_RSRVD3(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3)
+#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400
+#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8
+#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040
+#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4
+#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V 0x00000004
+#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0
+#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE10 (0x000003a0)
+#define HW_PINCTRL_DRIVE10_SET (0x000003a4)
+#define HW_PINCTRL_DRIVE10_CLR (0x000003a8)
+#define HW_PINCTRL_DRIVE10_TOG (0x000003ac)
+
+#define BP_PINCTRL_DRIVE10_RSRVD6 24
+#define BM_PINCTRL_DRIVE10_RSRVD6 0xFF000000
+#define BF_PINCTRL_DRIVE10_RSRVD6(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6)
+#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20
+#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16
+#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12
+#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400
+#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8
+#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040
+#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4
+#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0
+#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE11 (0x000003b0)
+#define HW_PINCTRL_DRIVE11_SET (0x000003b4)
+#define HW_PINCTRL_DRIVE11_CLR (0x000003b8)
+#define HW_PINCTRL_DRIVE11_TOG (0x000003bc)
+
+#define BP_PINCTRL_DRIVE11_RSRVD4 16
+#define BM_PINCTRL_DRIVE11_RSRVD4 0xFFFF0000
+#define BF_PINCTRL_DRIVE11_RSRVD4(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4)
+#define BM_PINCTRL_DRIVE11_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V 0x00004000
+#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12
+#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400
+#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8
+#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040
+#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4
+#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004
+#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0
+#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE12 (0x000003c0)
+#define HW_PINCTRL_DRIVE12_SET (0x000003c4)
+#define HW_PINCTRL_DRIVE12_CLR (0x000003c8)
+#define HW_PINCTRL_DRIVE12_TOG (0x000003cc)
+
+#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28
+#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24
+#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20
+#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16
+#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12
+#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400
+#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8
+#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040
+#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4
+#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004
+#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0
+#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE13 (0x000003d0)
+#define HW_PINCTRL_DRIVE13_SET (0x000003d4)
+#define HW_PINCTRL_DRIVE13_CLR (0x000003d8)
+#define HW_PINCTRL_DRIVE13_TOG (0x000003dc)
+
+#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28
+#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24
+#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20
+#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16
+#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12
+#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400
+#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8
+#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040
+#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4
+#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004
+#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0
+#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE14 (0x000003e0)
+#define HW_PINCTRL_DRIVE14_SET (0x000003e4)
+#define HW_PINCTRL_DRIVE14_CLR (0x000003e8)
+#define HW_PINCTRL_DRIVE14_TOG (0x000003ec)
+
+#define BM_PINCTRL_DRIVE14_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V 0x40000000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA 28
+#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA 0x30000000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V 0x04000000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA 24
+#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA 0x03000000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20
+#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16
+#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA)
+#define BP_PINCTRL_DRIVE14_RSRVD3 12
+#define BM_PINCTRL_DRIVE14_RSRVD3 0x0000F000
+#define BF_PINCTRL_DRIVE14_RSRVD3(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3)
+#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400
+#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8
+#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040
+#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4
+#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0
+#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE15 (0x000003f0)
+#define HW_PINCTRL_DRIVE15_SET (0x000003f4)
+#define HW_PINCTRL_DRIVE15_CLR (0x000003f8)
+#define HW_PINCTRL_DRIVE15_TOG (0x000003fc)
+
+#define BP_PINCTRL_DRIVE15_RSRVD7 28
+#define BM_PINCTRL_DRIVE15_RSRVD7 0xF0000000
+#define BF_PINCTRL_DRIVE15_RSRVD7(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7)
+#define BM_PINCTRL_DRIVE15_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V 0x04000000
+#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA 24
+#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA 0x03000000
+#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA)
+#define BM_PINCTRL_DRIVE15_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V 0x00400000
+#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA 20
+#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA 0x00300000
+#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA)
+#define BM_PINCTRL_DRIVE15_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V 0x00040000
+#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA 16
+#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA 0x00030000
+#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA)
+#define BM_PINCTRL_DRIVE15_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V 0x00004000
+#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA 12
+#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA)
+#define BM_PINCTRL_DRIVE15_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V 0x00000400
+#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA 8
+#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA)
+#define BM_PINCTRL_DRIVE15_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V 0x00000040
+#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA 4
+#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA)
+#define BM_PINCTRL_DRIVE15_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V 0x00000004
+#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA 0
+#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE16 (0x00000400)
+#define HW_PINCTRL_DRIVE16_SET (0x00000404)
+#define HW_PINCTRL_DRIVE16_CLR (0x00000408)
+#define HW_PINCTRL_DRIVE16_TOG (0x0000040c)
+
+#define BM_PINCTRL_DRIVE16_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V 0x40000000
+#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA 28
+#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V 0x04000000
+#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA 24
+#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V 0x00400000
+#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA 20
+#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V 0x00040000
+#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA 16
+#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V 0x00004000
+#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA 12
+#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V 0x00000400
+#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA 8
+#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V 0x00000040
+#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA 4
+#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA)
+#define BM_PINCTRL_DRIVE16_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V 0x00000004
+#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA 0
+#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE17 (0x00000410)
+#define HW_PINCTRL_DRIVE17_SET (0x00000414)
+#define HW_PINCTRL_DRIVE17_CLR (0x00000418)
+#define HW_PINCTRL_DRIVE17_TOG (0x0000041c)
+
+#define BM_PINCTRL_DRIVE17_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V 0x40000000
+#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA 28
+#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V 0x04000000
+#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA 24
+#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V 0x00400000
+#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA 20
+#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V 0x00040000
+#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA 16
+#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V 0x00004000
+#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA 12
+#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V 0x00000400
+#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA 8
+#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V 0x00000040
+#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA 4
+#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA)
+#define BM_PINCTRL_DRIVE17_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V 0x00000004
+#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA 0
+#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE18 (0x00000420)
+#define HW_PINCTRL_DRIVE18_SET (0x00000424)
+#define HW_PINCTRL_DRIVE18_CLR (0x00000428)
+#define HW_PINCTRL_DRIVE18_TOG (0x0000042c)
+
+#define BP_PINCTRL_DRIVE18_RSRVD3 20
+#define BM_PINCTRL_DRIVE18_RSRVD3 0xFFF00000
+#define BF_PINCTRL_DRIVE18_RSRVD3(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3)
+#define BM_PINCTRL_DRIVE18_RSRVD2 0x00080000
+#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA 16
+#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA)
+#define BP_PINCTRL_DRIVE18_RSRVD1 4
+#define BM_PINCTRL_DRIVE18_RSRVD1 0x0000FFF0
+#define BF_PINCTRL_DRIVE18_RSRVD1(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1)
+#define BM_PINCTRL_DRIVE18_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA 0
+#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE19 (0x00000430)
+#define HW_PINCTRL_DRIVE19_SET (0x00000434)
+#define HW_PINCTRL_DRIVE19_CLR (0x00000438)
+#define HW_PINCTRL_DRIVE19_TOG (0x0000043c)
+
+#define BP_PINCTRL_DRIVE19_RSRVD0 0
+#define BM_PINCTRL_DRIVE19_RSRVD0 0xFFFFFFFF
+#define BF_PINCTRL_DRIVE19_RSRVD0(v) (v)
+
+#define HW_PINCTRL_PULL0 (0x00000600)
+#define HW_PINCTRL_PULL0_SET (0x00000604)
+#define HW_PINCTRL_PULL0_CLR (0x00000608)
+#define HW_PINCTRL_PULL0_TOG (0x0000060c)
+
+#define BP_PINCTRL_PULL0_RSRVD1 29
+#define BM_PINCTRL_PULL0_RSRVD1 0xE0000000
+#define BF_PINCTRL_PULL0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_PULL0_RSRVD1)
+#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000
+#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000
+#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000
+#define BM_PINCTRL_PULL0_BANK0_PIN25 0x02000000
+#define BM_PINCTRL_PULL0_BANK0_PIN24 0x01000000
+#define BM_PINCTRL_PULL0_BANK0_PIN23 0x00800000
+#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000
+#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000
+#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000
+#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000
+#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000
+#define BM_PINCTRL_PULL0_BANK0_PIN17 0x00020000
+#define BM_PINCTRL_PULL0_BANK0_PIN16 0x00010000
+#define BP_PINCTRL_PULL0_RSRVD0 8
+#define BM_PINCTRL_PULL0_RSRVD0 0x0000FF00
+#define BF_PINCTRL_PULL0_RSRVD0(v) \
+ (((v) << 8) & BM_PINCTRL_PULL0_RSRVD0)
+#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080
+#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040
+#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020
+#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010
+#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008
+#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004
+#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002
+#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL1 (0x00000610)
+#define HW_PINCTRL_PULL1_SET (0x00000614)
+#define HW_PINCTRL_PULL1_CLR (0x00000618)
+#define HW_PINCTRL_PULL1_TOG (0x0000061c)
+
+#define BM_PINCTRL_PULL1_BANK1_PIN31 0x80000000
+#define BM_PINCTRL_PULL1_BANK1_PIN30 0x40000000
+#define BM_PINCTRL_PULL1_BANK1_PIN29 0x20000000
+#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000
+#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000
+#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000
+#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000
+#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000
+#define BM_PINCTRL_PULL1_BANK1_PIN23 0x00800000
+#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000
+#define BM_PINCTRL_PULL1_BANK1_PIN21 0x00200000
+#define BM_PINCTRL_PULL1_BANK1_PIN20 0x00100000
+#define BM_PINCTRL_PULL1_BANK1_PIN19 0x00080000
+#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000
+#define BM_PINCTRL_PULL1_BANK1_PIN17 0x00020000
+#define BM_PINCTRL_PULL1_BANK1_PIN16 0x00010000
+#define BM_PINCTRL_PULL1_BANK1_PIN15 0x00008000
+#define BM_PINCTRL_PULL1_BANK1_PIN14 0x00004000
+#define BM_PINCTRL_PULL1_BANK1_PIN13 0x00002000
+#define BM_PINCTRL_PULL1_BANK1_PIN12 0x00001000
+#define BM_PINCTRL_PULL1_BANK1_PIN11 0x00000800
+#define BM_PINCTRL_PULL1_BANK1_PIN10 0x00000400
+#define BM_PINCTRL_PULL1_BANK1_PIN09 0x00000200
+#define BM_PINCTRL_PULL1_BANK1_PIN08 0x00000100
+#define BM_PINCTRL_PULL1_BANK1_PIN07 0x00000080
+#define BM_PINCTRL_PULL1_BANK1_PIN06 0x00000040
+#define BM_PINCTRL_PULL1_BANK1_PIN05 0x00000020
+#define BM_PINCTRL_PULL1_BANK1_PIN04 0x00000010
+#define BM_PINCTRL_PULL1_BANK1_PIN03 0x00000008
+#define BM_PINCTRL_PULL1_BANK1_PIN02 0x00000004
+#define BM_PINCTRL_PULL1_BANK1_PIN01 0x00000002
+#define BM_PINCTRL_PULL1_BANK1_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL2 (0x00000620)
+#define HW_PINCTRL_PULL2_SET (0x00000624)
+#define HW_PINCTRL_PULL2_CLR (0x00000628)
+#define HW_PINCTRL_PULL2_TOG (0x0000062c)
+
+#define BP_PINCTRL_PULL2_RSRVD2 28
+#define BM_PINCTRL_PULL2_RSRVD2 0xF0000000
+#define BF_PINCTRL_PULL2_RSRVD2(v) \
+ (((v) << 28) & BM_PINCTRL_PULL2_RSRVD2)
+#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000
+#define BM_PINCTRL_PULL2_BANK2_PIN26 0x04000000
+#define BM_PINCTRL_PULL2_BANK2_PIN25 0x02000000
+#define BM_PINCTRL_PULL2_BANK2_PIN24 0x01000000
+#define BP_PINCTRL_PULL2_RSRVD1 22
+#define BM_PINCTRL_PULL2_RSRVD1 0x00C00000
+#define BF_PINCTRL_PULL2_RSRVD1(v) \
+ (((v) << 22) & BM_PINCTRL_PULL2_RSRVD1)
+#define BM_PINCTRL_PULL2_BANK2_PIN21 0x00200000
+#define BM_PINCTRL_PULL2_BANK2_PIN20 0x00100000
+#define BM_PINCTRL_PULL2_BANK2_PIN19 0x00080000
+#define BM_PINCTRL_PULL2_BANK2_PIN18 0x00040000
+#define BM_PINCTRL_PULL2_BANK2_PIN17 0x00020000
+#define BM_PINCTRL_PULL2_BANK2_PIN16 0x00010000
+#define BM_PINCTRL_PULL2_BANK2_PIN15 0x00008000
+#define BM_PINCTRL_PULL2_BANK2_PIN14 0x00004000
+#define BM_PINCTRL_PULL2_BANK2_PIN13 0x00002000
+#define BM_PINCTRL_PULL2_BANK2_PIN12 0x00001000
+#define BM_PINCTRL_PULL2_RSRVD0 0x00000800
+#define BM_PINCTRL_PULL2_BANK2_PIN10 0x00000400
+#define BM_PINCTRL_PULL2_BANK2_PIN09 0x00000200
+#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100
+#define BM_PINCTRL_PULL2_BANK2_PIN07 0x00000080
+#define BM_PINCTRL_PULL2_BANK2_PIN06 0x00000040
+#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020
+#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010
+#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008
+#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004
+#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002
+#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL3 (0x00000630)
+#define HW_PINCTRL_PULL3_SET (0x00000634)
+#define HW_PINCTRL_PULL3_CLR (0x00000638)
+#define HW_PINCTRL_PULL3_TOG (0x0000063c)
+
+#define BM_PINCTRL_PULL3_RSRVD1 0x80000000
+#define BM_PINCTRL_PULL3_BANK3_PIN30 0x40000000
+#define BM_PINCTRL_PULL3_BANK3_PIN29 0x20000000
+#define BM_PINCTRL_PULL3_BANK3_PIN28 0x10000000
+#define BM_PINCTRL_PULL3_BANK3_PIN27 0x08000000
+#define BM_PINCTRL_PULL3_BANK3_PIN26 0x04000000
+#define BM_PINCTRL_PULL3_BANK3_PIN25 0x02000000
+#define BM_PINCTRL_PULL3_BANK3_PIN24 0x01000000
+#define BM_PINCTRL_PULL3_BANK3_PIN23 0x00800000
+#define BM_PINCTRL_PULL3_BANK3_PIN22 0x00400000
+#define BM_PINCTRL_PULL3_BANK3_PIN21 0x00200000
+#define BM_PINCTRL_PULL3_BANK3_PIN20 0x00100000
+#define BM_PINCTRL_PULL3_RSRVD0 0x00080000
+#define BM_PINCTRL_PULL3_BANK3_PIN18 0x00040000
+#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000
+#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000
+#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000
+#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000
+#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000
+#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000
+#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800
+#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400
+#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200
+#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100
+#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080
+#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040
+#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020
+#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010
+#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008
+#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004
+#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002
+#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL4 (0x00000640)
+#define HW_PINCTRL_PULL4_SET (0x00000644)
+#define HW_PINCTRL_PULL4_CLR (0x00000648)
+#define HW_PINCTRL_PULL4_TOG (0x0000064c)
+
+#define BP_PINCTRL_PULL4_RSRVD1 21
+#define BM_PINCTRL_PULL4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_PULL4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_PULL4_RSRVD1)
+#define BM_PINCTRL_PULL4_BANK4_PIN20 0x00100000
+#define BP_PINCTRL_PULL4_RSRVD0 17
+#define BM_PINCTRL_PULL4_RSRVD0 0x000E0000
+#define BF_PINCTRL_PULL4_RSRVD0(v) \
+ (((v) << 17) & BM_PINCTRL_PULL4_RSRVD0)
+#define BM_PINCTRL_PULL4_BANK4_PIN16 0x00010000
+#define BM_PINCTRL_PULL4_BANK4_PIN15 0x00008000
+#define BM_PINCTRL_PULL4_BANK4_PIN14 0x00004000
+#define BM_PINCTRL_PULL4_BANK4_PIN13 0x00002000
+#define BM_PINCTRL_PULL4_BANK4_PIN12 0x00001000
+#define BM_PINCTRL_PULL4_BANK4_PIN11 0x00000800
+#define BM_PINCTRL_PULL4_BANK4_PIN10 0x00000400
+#define BM_PINCTRL_PULL4_BANK4_PIN09 0x00000200
+#define BM_PINCTRL_PULL4_BANK4_PIN08 0x00000100
+#define BM_PINCTRL_PULL4_BANK4_PIN07 0x00000080
+#define BM_PINCTRL_PULL4_BANK4_PIN06 0x00000040
+#define BM_PINCTRL_PULL4_BANK4_PIN05 0x00000020
+#define BM_PINCTRL_PULL4_BANK4_PIN04 0x00000010
+#define BM_PINCTRL_PULL4_BANK4_PIN03 0x00000008
+#define BM_PINCTRL_PULL4_BANK4_PIN02 0x00000004
+#define BM_PINCTRL_PULL4_BANK4_PIN01 0x00000002
+#define BM_PINCTRL_PULL4_BANK4_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL5 (0x00000650)
+#define HW_PINCTRL_PULL5_SET (0x00000654)
+#define HW_PINCTRL_PULL5_CLR (0x00000658)
+#define HW_PINCTRL_PULL5_TOG (0x0000065c)
+
+#define BP_PINCTRL_PULL5_RSRVD1 27
+#define BM_PINCTRL_PULL5_RSRVD1 0xF8000000
+#define BF_PINCTRL_PULL5_RSRVD1(v) \
+ (((v) << 27) & BM_PINCTRL_PULL5_RSRVD1)
+#define BM_PINCTRL_PULL5_BANK5_PIN26 0x04000000
+#define BP_PINCTRL_PULL5_RSRVD0 24
+#define BM_PINCTRL_PULL5_RSRVD0 0x03000000
+#define BF_PINCTRL_PULL5_RSRVD0(v) \
+ (((v) << 24) & BM_PINCTRL_PULL5_RSRVD0)
+#define BM_PINCTRL_PULL5_BANK5_PIN23 0x00800000
+#define BM_PINCTRL_PULL5_BANK5_PIN22 0x00400000
+#define BM_PINCTRL_PULL5_BANK5_PIN21 0x00200000
+#define BM_PINCTRL_PULL5_BANK5_PIN20 0x00100000
+#define BM_PINCTRL_PULL5_BANK5_PIN19 0x00080000
+#define BM_PINCTRL_PULL5_BANK5_PIN18 0x00040000
+#define BM_PINCTRL_PULL5_BANK5_PIN17 0x00020000
+#define BM_PINCTRL_PULL5_BANK5_PIN16 0x00010000
+#define BM_PINCTRL_PULL5_BANK5_PIN15 0x00008000
+#define BM_PINCTRL_PULL5_BANK5_PIN14 0x00004000
+#define BM_PINCTRL_PULL5_BANK5_PIN13 0x00002000
+#define BM_PINCTRL_PULL5_BANK5_PIN12 0x00001000
+#define BM_PINCTRL_PULL5_BANK5_PIN11 0x00000800
+#define BM_PINCTRL_PULL5_BANK5_PIN10 0x00000400
+#define BM_PINCTRL_PULL5_BANK5_PIN09 0x00000200
+#define BM_PINCTRL_PULL5_BANK5_PIN08 0x00000100
+#define BM_PINCTRL_PULL5_BANK5_PIN07 0x00000080
+#define BM_PINCTRL_PULL5_BANK5_PIN06 0x00000040
+#define BM_PINCTRL_PULL5_BANK5_PIN05 0x00000020
+#define BM_PINCTRL_PULL5_BANK5_PIN04 0x00000010
+#define BM_PINCTRL_PULL5_BANK5_PIN03 0x00000008
+#define BM_PINCTRL_PULL5_BANK5_PIN02 0x00000004
+#define BM_PINCTRL_PULL5_BANK5_PIN01 0x00000002
+#define BM_PINCTRL_PULL5_BANK5_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL6 (0x00000660)
+#define HW_PINCTRL_PULL6_SET (0x00000664)
+#define HW_PINCTRL_PULL6_CLR (0x00000668)
+#define HW_PINCTRL_PULL6_TOG (0x0000066c)
+
+#define BP_PINCTRL_PULL6_RSRVD1 25
+#define BM_PINCTRL_PULL6_RSRVD1 0xFE000000
+#define BF_PINCTRL_PULL6_RSRVD1(v) \
+ (((v) << 25) & BM_PINCTRL_PULL6_RSRVD1)
+#define BM_PINCTRL_PULL6_BANK6_PIN24 0x01000000
+#define BM_PINCTRL_PULL6_BANK6_PIN23 0x00800000
+#define BM_PINCTRL_PULL6_BANK6_PIN22 0x00400000
+#define BM_PINCTRL_PULL6_BANK6_PIN21 0x00200000
+#define BM_PINCTRL_PULL6_BANK6_PIN20 0x00100000
+#define BM_PINCTRL_PULL6_BANK6_PIN19 0x00080000
+#define BM_PINCTRL_PULL6_BANK6_PIN18 0x00040000
+#define BM_PINCTRL_PULL6_BANK6_PIN17 0x00020000
+#define BM_PINCTRL_PULL6_BANK6_PIN16 0x00010000
+#define BM_PINCTRL_PULL6_RSRVD0 0x00008000
+#define BM_PINCTRL_PULL6_BANK6_PIN14 0x00004000
+#define BM_PINCTRL_PULL6_BANK6_PIN13 0x00002000
+#define BM_PINCTRL_PULL6_BANK6_PIN12 0x00001000
+#define BM_PINCTRL_PULL6_BANK6_PIN11 0x00000800
+#define BM_PINCTRL_PULL6_BANK6_PIN10 0x00000400
+#define BM_PINCTRL_PULL6_BANK6_PIN09 0x00000200
+#define BM_PINCTRL_PULL6_BANK6_PIN08 0x00000100
+#define BM_PINCTRL_PULL6_BANK6_PIN07 0x00000080
+#define BM_PINCTRL_PULL6_BANK6_PIN06 0x00000040
+#define BM_PINCTRL_PULL6_BANK6_PIN05 0x00000020
+#define BM_PINCTRL_PULL6_BANK6_PIN04 0x00000010
+#define BM_PINCTRL_PULL6_BANK6_PIN03 0x00000008
+#define BM_PINCTRL_PULL6_BANK6_PIN02 0x00000004
+#define BM_PINCTRL_PULL6_BANK6_PIN01 0x00000002
+#define BM_PINCTRL_PULL6_BANK6_PIN00 0x00000001
+
+#define HW_PINCTRL_DOUT0 (0x00000700)
+#define HW_PINCTRL_DOUT0_SET (0x00000704)
+#define HW_PINCTRL_DOUT0_CLR (0x00000708)
+#define HW_PINCTRL_DOUT0_TOG (0x0000070c)
+
+#define BP_PINCTRL_DOUT0_RSRVD1 29
+#define BM_PINCTRL_DOUT0_RSRVD1 0xE0000000
+#define BF_PINCTRL_DOUT0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1)
+#define BP_PINCTRL_DOUT0_DOUT 0
+#define BM_PINCTRL_DOUT0_DOUT 0x1FFFFFFF
+#define BF_PINCTRL_DOUT0_DOUT(v) \
+ (((v) << 0) & BM_PINCTRL_DOUT0_DOUT)
+
+#define HW_PINCTRL_DOUT1 (0x00000710)
+#define HW_PINCTRL_DOUT1_SET (0x00000714)
+#define HW_PINCTRL_DOUT1_CLR (0x00000718)
+#define HW_PINCTRL_DOUT1_TOG (0x0000071c)
+
+#define BP_PINCTRL_DOUT1_DOUT 0
+#define BM_PINCTRL_DOUT1_DOUT 0xFFFFFFFF
+#define BF_PINCTRL_DOUT1_DOUT(v) (v)
+
+#define HW_PINCTRL_DOUT2 (0x00000720)
+#define HW_PINCTRL_DOUT2_SET (0x00000724)
+#define HW_PINCTRL_DOUT2_CLR (0x00000728)
+#define HW_PINCTRL_DOUT2_TOG (0x0000072c)
+
+#define BP_PINCTRL_DOUT2_RSRVD1 28
+#define BM_PINCTRL_DOUT2_RSRVD1 0xF0000000
+#define BF_PINCTRL_DOUT2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1)
+#define BP_PINCTRL_DOUT2_DOUT 0
+#define BM_PINCTRL_DOUT2_DOUT 0x0FFFFFFF
+#define BF_PINCTRL_DOUT2_DOUT(v) \
+ (((v) << 0) & BM_PINCTRL_DOUT2_DOUT)
+
+#define HW_PINCTRL_DOUT3 (0x00000730)
+#define HW_PINCTRL_DOUT3_SET (0x00000734)
+#define HW_PINCTRL_DOUT3_CLR (0x00000738)
+#define HW_PINCTRL_DOUT3_TOG (0x0000073c)
+
+#define BM_PINCTRL_DOUT3_RSRVD1 0x80000000
+#define BP_PINCTRL_DOUT3_DOUT 0
+#define BM_PINCTRL_DOUT3_DOUT 0x7FFFFFFF
+#define BF_PINCTRL_DOUT3_DOUT(v) \
+ (((v) << 0) & BM_PINCTRL_DOUT3_DOUT)
+
+#define HW_PINCTRL_DOUT4 (0x00000740)
+#define HW_PINCTRL_DOUT4_SET (0x00000744)
+#define HW_PINCTRL_DOUT4_CLR (0x00000748)
+#define HW_PINCTRL_DOUT4_TOG (0x0000074c)
+
+#define BP_PINCTRL_DOUT4_RSRVD1 21
+#define BM_PINCTRL_DOUT4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_DOUT4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1)
+#define BP_PINCTRL_DOUT4_DOUT 0
+#define BM_PINCTRL_DOUT4_DOUT 0x001FFFFF
+#define BF_PINCTRL_DOUT4_DOUT(v) \
+ (((v) << 0) & BM_PINCTRL_DOUT4_DOUT)
+
+#define HW_PINCTRL_DIN0 (0x00000900)
+#define HW_PINCTRL_DIN0_SET (0x00000904)
+#define HW_PINCTRL_DIN0_CLR (0x00000908)
+#define HW_PINCTRL_DIN0_TOG (0x0000090c)
+
+#define BP_PINCTRL_DIN0_RSRVD1 29
+#define BM_PINCTRL_DIN0_RSRVD1 0xE0000000
+#define BF_PINCTRL_DIN0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_DIN0_RSRVD1)
+#define BP_PINCTRL_DIN0_DIN 0
+#define BM_PINCTRL_DIN0_DIN 0x1FFFFFFF
+#define BF_PINCTRL_DIN0_DIN(v) \
+ (((v) << 0) & BM_PINCTRL_DIN0_DIN)
+
+#define HW_PINCTRL_DIN1 (0x00000910)
+#define HW_PINCTRL_DIN1_SET (0x00000914)
+#define HW_PINCTRL_DIN1_CLR (0x00000918)
+#define HW_PINCTRL_DIN1_TOG (0x0000091c)
+
+#define BP_PINCTRL_DIN1_DIN 0
+#define BM_PINCTRL_DIN1_DIN 0xFFFFFFFF
+#define BF_PINCTRL_DIN1_DIN(v) (v)
+
+#define HW_PINCTRL_DIN2 (0x00000920)
+#define HW_PINCTRL_DIN2_SET (0x00000924)
+#define HW_PINCTRL_DIN2_CLR (0x00000928)
+#define HW_PINCTRL_DIN2_TOG (0x0000092c)
+
+#define BP_PINCTRL_DIN2_RSRVD1 28
+#define BM_PINCTRL_DIN2_RSRVD1 0xF0000000
+#define BF_PINCTRL_DIN2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_DIN2_RSRVD1)
+#define BP_PINCTRL_DIN2_DIN 0
+#define BM_PINCTRL_DIN2_DIN 0x0FFFFFFF
+#define BF_PINCTRL_DIN2_DIN(v) \
+ (((v) << 0) & BM_PINCTRL_DIN2_DIN)
+
+#define HW_PINCTRL_DIN3 (0x00000930)
+#define HW_PINCTRL_DIN3_SET (0x00000934)
+#define HW_PINCTRL_DIN3_CLR (0x00000938)
+#define HW_PINCTRL_DIN3_TOG (0x0000093c)
+
+#define BM_PINCTRL_DIN3_RSRVD1 0x80000000
+#define BP_PINCTRL_DIN3_DIN 0
+#define BM_PINCTRL_DIN3_DIN 0x7FFFFFFF
+#define BF_PINCTRL_DIN3_DIN(v) \
+ (((v) << 0) & BM_PINCTRL_DIN3_DIN)
+
+#define HW_PINCTRL_DIN4 (0x00000940)
+#define HW_PINCTRL_DIN4_SET (0x00000944)
+#define HW_PINCTRL_DIN4_CLR (0x00000948)
+#define HW_PINCTRL_DIN4_TOG (0x0000094c)
+
+#define BP_PINCTRL_DIN4_RSRVD1 21
+#define BM_PINCTRL_DIN4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_DIN4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_DIN4_RSRVD1)
+#define BP_PINCTRL_DIN4_DIN 0
+#define BM_PINCTRL_DIN4_DIN 0x001FFFFF
+#define BF_PINCTRL_DIN4_DIN(v) \
+ (((v) << 0) & BM_PINCTRL_DIN4_DIN)
+
+#define HW_PINCTRL_DOE0 (0x00000b00)
+#define HW_PINCTRL_DOE0_SET (0x00000b04)
+#define HW_PINCTRL_DOE0_CLR (0x00000b08)
+#define HW_PINCTRL_DOE0_TOG (0x00000b0c)
+
+#define BP_PINCTRL_DOE0_RSRVD1 29
+#define BM_PINCTRL_DOE0_RSRVD1 0xE0000000
+#define BF_PINCTRL_DOE0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_DOE0_RSRVD1)
+#define BP_PINCTRL_DOE0_DOE 0
+#define BM_PINCTRL_DOE0_DOE 0x1FFFFFFF
+#define BF_PINCTRL_DOE0_DOE(v) \
+ (((v) << 0) & BM_PINCTRL_DOE0_DOE)
+
+#define HW_PINCTRL_DOE1 (0x00000b10)
+#define HW_PINCTRL_DOE1_SET (0x00000b14)
+#define HW_PINCTRL_DOE1_CLR (0x00000b18)
+#define HW_PINCTRL_DOE1_TOG (0x00000b1c)
+
+#define BP_PINCTRL_DOE1_DOE 0
+#define BM_PINCTRL_DOE1_DOE 0xFFFFFFFF
+#define BF_PINCTRL_DOE1_DOE(v) (v)
+
+#define HW_PINCTRL_DOE2 (0x00000b20)
+#define HW_PINCTRL_DOE2_SET (0x00000b24)
+#define HW_PINCTRL_DOE2_CLR (0x00000b28)
+#define HW_PINCTRL_DOE2_TOG (0x00000b2c)
+
+#define BP_PINCTRL_DOE2_RSRVD1 28
+#define BM_PINCTRL_DOE2_RSRVD1 0xF0000000
+#define BF_PINCTRL_DOE2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_DOE2_RSRVD1)
+#define BP_PINCTRL_DOE2_DOE 0
+#define BM_PINCTRL_DOE2_DOE 0x0FFFFFFF
+#define BF_PINCTRL_DOE2_DOE(v) \
+ (((v) << 0) & BM_PINCTRL_DOE2_DOE)
+
+#define HW_PINCTRL_DOE3 (0x00000b30)
+#define HW_PINCTRL_DOE3_SET (0x00000b34)
+#define HW_PINCTRL_DOE3_CLR (0x00000b38)
+#define HW_PINCTRL_DOE3_TOG (0x00000b3c)
+
+#define BM_PINCTRL_DOE3_RSRVD1 0x80000000
+#define BP_PINCTRL_DOE3_DOE 0
+#define BM_PINCTRL_DOE3_DOE 0x7FFFFFFF
+#define BF_PINCTRL_DOE3_DOE(v) \
+ (((v) << 0) & BM_PINCTRL_DOE3_DOE)
+
+#define HW_PINCTRL_DOE4 (0x00000b40)
+#define HW_PINCTRL_DOE4_SET (0x00000b44)
+#define HW_PINCTRL_DOE4_CLR (0x00000b48)
+#define HW_PINCTRL_DOE4_TOG (0x00000b4c)
+
+#define BP_PINCTRL_DOE4_RSRVD1 21
+#define BM_PINCTRL_DOE4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_DOE4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_DOE4_RSRVD1)
+#define BP_PINCTRL_DOE4_DOE 0
+#define BM_PINCTRL_DOE4_DOE 0x001FFFFF
+#define BF_PINCTRL_DOE4_DOE(v) \
+ (((v) << 0) & BM_PINCTRL_DOE4_DOE)
+
+#define HW_PINCTRL_PIN2IRQ0 (0x00001000)
+#define HW_PINCTRL_PIN2IRQ0_SET (0x00001004)
+#define HW_PINCTRL_PIN2IRQ0_CLR (0x00001008)
+#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000100c)
+
+#define BP_PINCTRL_PIN2IRQ0_RSRVD1 29
+#define BM_PINCTRL_PIN2IRQ0_RSRVD1 0xE0000000
+#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1)
+#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0x1FFFFFFF
+#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) \
+ (((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ)
+
+#define HW_PINCTRL_PIN2IRQ1 (0x00001010)
+#define HW_PINCTRL_PIN2IRQ1_SET (0x00001014)
+#define HW_PINCTRL_PIN2IRQ1_CLR (0x00001018)
+#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000101c)
+
+#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0xFFFFFFFF
+#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) (v)
+
+#define HW_PINCTRL_PIN2IRQ2 (0x00001020)
+#define HW_PINCTRL_PIN2IRQ2_SET (0x00001024)
+#define HW_PINCTRL_PIN2IRQ2_CLR (0x00001028)
+#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000102c)
+
+#define BP_PINCTRL_PIN2IRQ2_RSRVD1 28
+#define BM_PINCTRL_PIN2IRQ2_RSRVD1 0xF0000000
+#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1)
+#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0x0FFFFFFF
+#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) \
+ (((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ)
+
+#define HW_PINCTRL_PIN2IRQ3 (0x00001030)
+#define HW_PINCTRL_PIN2IRQ3_SET (0x00001034)
+#define HW_PINCTRL_PIN2IRQ3_CLR (0x00001038)
+#define HW_PINCTRL_PIN2IRQ3_TOG (0x0000103c)
+
+#define BM_PINCTRL_PIN2IRQ3_RSRVD1 0x80000000
+#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ 0x7FFFFFFF
+#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v) \
+ (((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ)
+
+#define HW_PINCTRL_PIN2IRQ4 (0x00001040)
+#define HW_PINCTRL_PIN2IRQ4_SET (0x00001044)
+#define HW_PINCTRL_PIN2IRQ4_CLR (0x00001048)
+#define HW_PINCTRL_PIN2IRQ4_TOG (0x0000104c)
+
+#define BP_PINCTRL_PIN2IRQ4_RSRVD1 21
+#define BM_PINCTRL_PIN2IRQ4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1)
+#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ 0x001FFFFF
+#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v) \
+ (((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ)
+
+#define HW_PINCTRL_IRQEN0 (0x00001100)
+#define HW_PINCTRL_IRQEN0_SET (0x00001104)
+#define HW_PINCTRL_IRQEN0_CLR (0x00001108)
+#define HW_PINCTRL_IRQEN0_TOG (0x0000110c)
+
+#define BP_PINCTRL_IRQEN0_RSRVD1 29
+#define BM_PINCTRL_IRQEN0_RSRVD1 0xE0000000
+#define BF_PINCTRL_IRQEN0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1)
+#define BP_PINCTRL_IRQEN0_IRQEN 0
+#define BM_PINCTRL_IRQEN0_IRQEN 0x1FFFFFFF
+#define BF_PINCTRL_IRQEN0_IRQEN(v) \
+ (((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN)
+
+#define HW_PINCTRL_IRQEN1 (0x00001110)
+#define HW_PINCTRL_IRQEN1_SET (0x00001114)
+#define HW_PINCTRL_IRQEN1_CLR (0x00001118)
+#define HW_PINCTRL_IRQEN1_TOG (0x0000111c)
+
+#define BP_PINCTRL_IRQEN1_IRQEN 0
+#define BM_PINCTRL_IRQEN1_IRQEN 0xFFFFFFFF
+#define BF_PINCTRL_IRQEN1_IRQEN(v) (v)
+
+#define HW_PINCTRL_IRQEN2 (0x00001120)
+#define HW_PINCTRL_IRQEN2_SET (0x00001124)
+#define HW_PINCTRL_IRQEN2_CLR (0x00001128)
+#define HW_PINCTRL_IRQEN2_TOG (0x0000112c)
+
+#define BP_PINCTRL_IRQEN2_RSRVD1 28
+#define BM_PINCTRL_IRQEN2_RSRVD1 0xF0000000
+#define BF_PINCTRL_IRQEN2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1)
+#define BP_PINCTRL_IRQEN2_IRQEN 0
+#define BM_PINCTRL_IRQEN2_IRQEN 0x0FFFFFFF
+#define BF_PINCTRL_IRQEN2_IRQEN(v) \
+ (((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN)
+
+#define HW_PINCTRL_IRQEN3 (0x00001130)
+#define HW_PINCTRL_IRQEN3_SET (0x00001134)
+#define HW_PINCTRL_IRQEN3_CLR (0x00001138)
+#define HW_PINCTRL_IRQEN3_TOG (0x0000113c)
+
+#define BM_PINCTRL_IRQEN3_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQEN3_IRQEN 0
+#define BM_PINCTRL_IRQEN3_IRQEN 0x7FFFFFFF
+#define BF_PINCTRL_IRQEN3_IRQEN(v) \
+ (((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN)
+
+#define HW_PINCTRL_IRQEN4 (0x00001140)
+#define HW_PINCTRL_IRQEN4_SET (0x00001144)
+#define HW_PINCTRL_IRQEN4_CLR (0x00001148)
+#define HW_PINCTRL_IRQEN4_TOG (0x0000114c)
+
+#define BP_PINCTRL_IRQEN4_RSRVD1 21
+#define BM_PINCTRL_IRQEN4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_IRQEN4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1)
+#define BP_PINCTRL_IRQEN4_IRQEN 0
+#define BM_PINCTRL_IRQEN4_IRQEN 0x001FFFFF
+#define BF_PINCTRL_IRQEN4_IRQEN(v) \
+ (((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN)
+
+#define HW_PINCTRL_IRQLEVEL0 (0x00001200)
+#define HW_PINCTRL_IRQLEVEL0_SET (0x00001204)
+#define HW_PINCTRL_IRQLEVEL0_CLR (0x00001208)
+#define HW_PINCTRL_IRQLEVEL0_TOG (0x0000120c)
+
+#define BP_PINCTRL_IRQLEVEL0_RSRVD1 29
+#define BM_PINCTRL_IRQLEVEL0_RSRVD1 0xE0000000
+#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1)
+#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0x1FFFFFFF
+#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL)
+
+#define HW_PINCTRL_IRQLEVEL1 (0x00001210)
+#define HW_PINCTRL_IRQLEVEL1_SET (0x00001214)
+#define HW_PINCTRL_IRQLEVEL1_CLR (0x00001218)
+#define HW_PINCTRL_IRQLEVEL1_TOG (0x0000121c)
+
+#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0xFFFFFFFF
+#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) (v)
+
+#define HW_PINCTRL_IRQLEVEL2 (0x00001220)
+#define HW_PINCTRL_IRQLEVEL2_SET (0x00001224)
+#define HW_PINCTRL_IRQLEVEL2_CLR (0x00001228)
+#define HW_PINCTRL_IRQLEVEL2_TOG (0x0000122c)
+
+#define BP_PINCTRL_IRQLEVEL2_RSRVD1 28
+#define BM_PINCTRL_IRQLEVEL2_RSRVD1 0xF0000000
+#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1)
+#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0x0FFFFFFF
+#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL)
+
+#define HW_PINCTRL_IRQLEVEL3 (0x00001230)
+#define HW_PINCTRL_IRQLEVEL3_SET (0x00001234)
+#define HW_PINCTRL_IRQLEVEL3_CLR (0x00001238)
+#define HW_PINCTRL_IRQLEVEL3_TOG (0x0000123c)
+
+#define BM_PINCTRL_IRQLEVEL3_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL 0x7FFFFFFF
+#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL)
+
+#define HW_PINCTRL_IRQLEVEL4 (0x00001240)
+#define HW_PINCTRL_IRQLEVEL4_SET (0x00001244)
+#define HW_PINCTRL_IRQLEVEL4_CLR (0x00001248)
+#define HW_PINCTRL_IRQLEVEL4_TOG (0x0000124c)
+
+#define BP_PINCTRL_IRQLEVEL4_RSRVD1 21
+#define BM_PINCTRL_IRQLEVEL4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1)
+#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL 0x001FFFFF
+#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL)
+
+#define HW_PINCTRL_IRQPOL0 (0x00001300)
+#define HW_PINCTRL_IRQPOL0_SET (0x00001304)
+#define HW_PINCTRL_IRQPOL0_CLR (0x00001308)
+#define HW_PINCTRL_IRQPOL0_TOG (0x0000130c)
+
+#define BP_PINCTRL_IRQPOL0_RSRVD1 29
+#define BM_PINCTRL_IRQPOL0_RSRVD1 0xE0000000
+#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1)
+#define BP_PINCTRL_IRQPOL0_IRQPOL 0
+#define BM_PINCTRL_IRQPOL0_IRQPOL 0x1FFFFFFF
+#define BF_PINCTRL_IRQPOL0_IRQPOL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL)
+
+#define HW_PINCTRL_IRQPOL1 (0x00001310)
+#define HW_PINCTRL_IRQPOL1_SET (0x00001314)
+#define HW_PINCTRL_IRQPOL1_CLR (0x00001318)
+#define HW_PINCTRL_IRQPOL1_TOG (0x0000131c)
+
+#define BP_PINCTRL_IRQPOL1_IRQPOL 0
+#define BM_PINCTRL_IRQPOL1_IRQPOL 0xFFFFFFFF
+#define BF_PINCTRL_IRQPOL1_IRQPOL(v) (v)
+
+#define HW_PINCTRL_IRQPOL2 (0x00001320)
+#define HW_PINCTRL_IRQPOL2_SET (0x00001324)
+#define HW_PINCTRL_IRQPOL2_CLR (0x00001328)
+#define HW_PINCTRL_IRQPOL2_TOG (0x0000132c)
+
+#define BP_PINCTRL_IRQPOL2_RSRVD1 28
+#define BM_PINCTRL_IRQPOL2_RSRVD1 0xF0000000
+#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1)
+#define BP_PINCTRL_IRQPOL2_IRQPOL 0
+#define BM_PINCTRL_IRQPOL2_IRQPOL 0x0FFFFFFF
+#define BF_PINCTRL_IRQPOL2_IRQPOL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL)
+
+#define HW_PINCTRL_IRQPOL3 (0x00001330)
+#define HW_PINCTRL_IRQPOL3_SET (0x00001334)
+#define HW_PINCTRL_IRQPOL3_CLR (0x00001338)
+#define HW_PINCTRL_IRQPOL3_TOG (0x0000133c)
+
+#define BM_PINCTRL_IRQPOL3_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQPOL3_IRQPOL 0
+#define BM_PINCTRL_IRQPOL3_IRQPOL 0x7FFFFFFF
+#define BF_PINCTRL_IRQPOL3_IRQPOL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL)
+
+#define HW_PINCTRL_IRQPOL4 (0x00001340)
+#define HW_PINCTRL_IRQPOL4_SET (0x00001344)
+#define HW_PINCTRL_IRQPOL4_CLR (0x00001348)
+#define HW_PINCTRL_IRQPOL4_TOG (0x0000134c)
+
+#define BP_PINCTRL_IRQPOL4_RSRVD1 21
+#define BM_PINCTRL_IRQPOL4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1)
+#define BP_PINCTRL_IRQPOL4_IRQPOL 0
+#define BM_PINCTRL_IRQPOL4_IRQPOL 0x001FFFFF
+#define BF_PINCTRL_IRQPOL4_IRQPOL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL)
+
+#define HW_PINCTRL_IRQSTAT0 (0x00001400)
+#define HW_PINCTRL_IRQSTAT0_SET (0x00001404)
+#define HW_PINCTRL_IRQSTAT0_CLR (0x00001408)
+#define HW_PINCTRL_IRQSTAT0_TOG (0x0000140c)
+
+#define BP_PINCTRL_IRQSTAT0_RSRVD1 29
+#define BM_PINCTRL_IRQSTAT0_RSRVD1 0xE0000000
+#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \
+ (((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1)
+#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0x1FFFFFFF
+#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) \
+ (((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT)
+
+#define HW_PINCTRL_IRQSTAT1 (0x00001410)
+#define HW_PINCTRL_IRQSTAT1_SET (0x00001414)
+#define HW_PINCTRL_IRQSTAT1_CLR (0x00001418)
+#define HW_PINCTRL_IRQSTAT1_TOG (0x0000141c)
+
+#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0xFFFFFFFF
+#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) (v)
+
+#define HW_PINCTRL_IRQSTAT2 (0x00001420)
+#define HW_PINCTRL_IRQSTAT2_SET (0x00001424)
+#define HW_PINCTRL_IRQSTAT2_CLR (0x00001428)
+#define HW_PINCTRL_IRQSTAT2_TOG (0x0000142c)
+
+#define BP_PINCTRL_IRQSTAT2_RSRVD1 28
+#define BM_PINCTRL_IRQSTAT2_RSRVD1 0xF0000000
+#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1)
+#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0x0FFFFFFF
+#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) \
+ (((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT)
+
+#define HW_PINCTRL_IRQSTAT3 (0x00001430)
+#define HW_PINCTRL_IRQSTAT3_SET (0x00001434)
+#define HW_PINCTRL_IRQSTAT3_CLR (0x00001438)
+#define HW_PINCTRL_IRQSTAT3_TOG (0x0000143c)
+
+#define BM_PINCTRL_IRQSTAT3_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQSTAT3_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT3_IRQSTAT 0x7FFFFFFF
+#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v) \
+ (((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT)
+
+#define HW_PINCTRL_IRQSTAT4 (0x00001440)
+#define HW_PINCTRL_IRQSTAT4_SET (0x00001444)
+#define HW_PINCTRL_IRQSTAT4_CLR (0x00001448)
+#define HW_PINCTRL_IRQSTAT4_TOG (0x0000144c)
+
+#define BP_PINCTRL_IRQSTAT4_RSRVD1 21
+#define BM_PINCTRL_IRQSTAT4_RSRVD1 0xFFE00000
+#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \
+ (((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1)
+#define BP_PINCTRL_IRQSTAT4_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT4_IRQSTAT 0x001FFFFF
+#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v) \
+ (((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT)
+
+#define HW_PINCTRL_EMI_ODT_CTRL (0x00001a40)
+#define HW_PINCTRL_EMI_ODT_CTRL_SET (0x00001a44)
+#define HW_PINCTRL_EMI_ODT_CTRL_CLR (0x00001a48)
+#define HW_PINCTRL_EMI_ODT_CTRL_TOG (0x00001a4c)
+
+#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1 28
+#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1 0xF0000000
+#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \
+ (((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1)
+#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 26
+#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 0x0C000000
+#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v) \
+ (((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 24
+#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 0x03000000
+#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v) \
+ (((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD)
+#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 22
+#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 0x00C00000
+#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v) \
+ (((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 20
+#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 0x00300000
+#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v) \
+ (((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD)
+#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 18
+#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 0x000C0000
+#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v) \
+ (((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 16
+#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 0x00030000
+#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v) \
+ (((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 14
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 0x0000C000
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v) \
+ (((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 12
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 0x00003000
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v) \
+ (((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 10
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 0x00000C00
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v) \
+ (((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 8
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 0x00000300
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v) \
+ (((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 6
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 0x000000C0
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v) \
+ (((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 4
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 0x00000030
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v) \
+ (((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 2
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 0x0000000C
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v) \
+ (((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB)
+#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0
+#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0x00000003
+#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v) \
+ (((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD)
+
+#define HW_PINCTRL_EMI_DS_CTRL (0x00001b80)
+#define HW_PINCTRL_EMI_DS_CTRL_SET (0x00001b84)
+#define HW_PINCTRL_EMI_DS_CTRL_CLR (0x00001b88)
+#define HW_PINCTRL_EMI_DS_CTRL_TOG (0x00001b8c)
+
+#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1 18
+#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1 0xFFFC0000
+#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \
+ (((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1)
+#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE 16
+#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE 0x00030000
+#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v) \
+ (((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE)
+#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR 00
+#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO 01
+#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10
+#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2 11
+#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0 14
+#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0 0x0000C000
+#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v) \
+ (((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0)
+#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 12
+#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 0x00003000
+#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v) \
+ (((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA)
+#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA 10
+#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA 0x00000C00
+#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v) \
+ (((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA)
+#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 8
+#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 0x00000300
+#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v) \
+ (((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA)
+#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA 6
+#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA 0x000000C0
+#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v) \
+ (((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA)
+#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA 4
+#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA 0x00000030
+#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v) \
+ (((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA)
+#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA 2
+#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA 0x0000000C
+#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v) \
+ (((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA)
+#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0
+#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0x00000003
+#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v) \
+ (((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA)
+#endif /* __ARCH_ARM___PINCTRL_H */
diff --git a/include/asm-arm/arch-mx28/regs-ssp.h b/include/asm-arm/arch-mx28/regs-ssp.h
new file mode 100644
index 0000000..96ee211
--- /dev/null
+++ b/include/asm-arm/arch-mx28/regs-ssp.h
@@ -0,0 +1,471 @@
+/*
+ * Freescale SSP Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 4.0
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___SSP_H
+#define __ARCH_ARM___SSP_H
+
+
+#define HW_SSP_CTRL0 (0x00000000)
+#define HW_SSP_CTRL0_SET (0x00000004)
+#define HW_SSP_CTRL0_CLR (0x00000008)
+#define HW_SSP_CTRL0_TOG (0x0000000c)
+
+#define BM_SSP_CTRL0_SFTRST 0x80000000
+#define BM_SSP_CTRL0_CLKGATE 0x40000000
+#define BM_SSP_CTRL0_RUN 0x20000000
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000
+#define BM_SSP_CTRL0_LOCK_CS 0x08000000
+#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
+#define BM_SSP_CTRL0_READ 0x02000000
+#define BM_SSP_CTRL0_DATA_XFER 0x01000000
+#define BP_SSP_CTRL0_BUS_WIDTH 22
+#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
+#define BF_SSP_CTRL0_BUS_WIDTH(v) \
+ (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH)
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1
+#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
+#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
+#define BM_SSP_CTRL0_LONG_RESP 0x00080000
+#define BM_SSP_CTRL0_CHECK_RESP 0x00040000
+#define BM_SSP_CTRL0_GET_RESP 0x00020000
+#define BM_SSP_CTRL0_ENABLE 0x00010000
+#define BP_SSP_CTRL0_RSVD0 0
+#define BM_SSP_CTRL0_RSVD0 0x0000FFFF
+#define BF_SSP_CTRL0_RSVD0(v) \
+ (((v) << 0) & BM_SSP_CTRL0_RSVD0)
+
+#define HW_SSP_CMD0 (0x00000010)
+#define HW_SSP_CMD0_SET (0x00000014)
+#define HW_SSP_CMD0_CLR (0x00000018)
+#define HW_SSP_CMD0_TOG (0x0000001c)
+
+#define BP_SSP_CMD0_RSVD0 27
+#define BM_SSP_CMD0_RSVD0 0xF8000000
+#define BF_SSP_CMD0_RSVD0(v) \
+ (((v) << 27) & BM_SSP_CMD0_RSVD0)
+#define BM_SSP_CMD0_SOFT_TERMINATE 0x04000000
+#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000
+#define BM_SSP_CMD0_PRIM_BOOT_OP_EN 0x01000000
+#define BM_SSP_CMD0_BOOT_ACK_EN 0x00800000
+#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000
+#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000
+#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
+#define BP_SSP_CMD0_RSVD1 8
+#define BM_SSP_CMD0_RSVD1 0x000FFF00
+#define BF_SSP_CMD0_RSVD1(v) \
+ (((v) << 8) & BM_SSP_CMD0_RSVD1)
+#define BP_SSP_CMD0_CMD 0
+#define BM_SSP_CMD0_CMD 0x000000FF
+#define BF_SSP_CMD0_CMD(v) \
+ (((v) << 0) & BM_SSP_CMD0_CMD)
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05
+#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03
+#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09
+#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE 0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38
+
+#define HW_SSP_CMD1 (0x00000020)
+
+#define BP_SSP_CMD1_CMD_ARG 0
+#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
+#define BF_SSP_CMD1_CMD_ARG(v) (v)
+
+#define HW_SSP_XFER_SIZE (0x00000030)
+
+#define BP_SSP_XFER_SIZE_XFER_COUNT 0
+#define BM_SSP_XFER_SIZE_XFER_COUNT 0xFFFFFFFF
+#define BF_SSP_XFER_SIZE_XFER_COUNT(v) (v)
+
+#define HW_SSP_BLOCK_SIZE (0x00000040)
+
+#define BP_SSP_BLOCK_SIZE_RSVD0 28
+#define BM_SSP_BLOCK_SIZE_RSVD0 0xF0000000
+#define BF_SSP_BLOCK_SIZE_RSVD0(v) \
+ (((v) << 28) & BM_SSP_BLOCK_SIZE_RSVD0)
+#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
+#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0FFFFFF0
+#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \
+ (((v) << 4) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT)
+#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
+#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x0000000F
+#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \
+ (((v) << 0) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE)
+
+#define HW_SSP_COMPREF (0x00000050)
+
+#define BP_SSP_COMPREF_REFERENCE 0
+#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF
+#define BF_SSP_COMPREF_REFERENCE(v) (v)
+
+#define HW_SSP_COMPMASK (0x00000060)
+
+#define BP_SSP_COMPMASK_MASK 0
+#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF
+#define BF_SSP_COMPMASK_MASK(v) (v)
+
+#define HW_SSP_TIMING (0x00000070)
+
+#define BP_SSP_TIMING_TIMEOUT 16
+#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
+#define BF_SSP_TIMING_TIMEOUT(v) \
+ (((v) << 16) & BM_SSP_TIMING_TIMEOUT)
+#define BP_SSP_TIMING_CLOCK_DIVIDE 8
+#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
+ (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
+#define BP_SSP_TIMING_CLOCK_RATE 0
+#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
+#define BF_SSP_TIMING_CLOCK_RATE(v) \
+ (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
+
+#define HW_SSP_CTRL1 (0x00000080)
+#define HW_SSP_CTRL1_SET (0x00000084)
+#define HW_SSP_CTRL1_CLR (0x00000088)
+#define HW_SSP_CTRL1_TOG (0x0000008c)
+
+#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
+#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000
+#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800
+#define BM_SSP_CTRL1_PHASE 0x00000400
+#define BM_SSP_CTRL1_POLARITY 0x00000200
+#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100
+#define BP_SSP_CTRL1_WORD_LENGTH 4
+#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
+#define BF_SSP_CTRL1_WORD_LENGTH(v) \
+ (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
+#define BP_SSP_CTRL1_SSP_MODE 0
+#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
+#define BF_SSP_CTRL1_SSP_MODE(v) \
+ (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
+#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
+
+#define HW_SSP_DATA (0x00000090)
+
+#define BP_SSP_DATA_DATA 0
+#define BM_SSP_DATA_DATA 0xFFFFFFFF
+#define BF_SSP_DATA_DATA(v) (v)
+
+#define HW_SSP_SDRESP0 (0x000000a0)
+
+#define BP_SSP_SDRESP0_RESP0 0
+#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF
+#define BF_SSP_SDRESP0_RESP0(v) (v)
+
+#define HW_SSP_SDRESP1 (0x000000b0)
+
+#define BP_SSP_SDRESP1_RESP1 0
+#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF
+#define BF_SSP_SDRESP1_RESP1(v) (v)
+
+#define HW_SSP_SDRESP2 (0x000000c0)
+
+#define BP_SSP_SDRESP2_RESP2 0
+#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF
+#define BF_SSP_SDRESP2_RESP2(v) (v)
+
+#define HW_SSP_SDRESP3 (0x000000d0)
+
+#define BP_SSP_SDRESP3_RESP3 0
+#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF
+#define BF_SSP_SDRESP3_RESP3(v) (v)
+
+#define HW_SSP_DDR_CTRL (0x000000e0)
+
+#define BP_SSP_DDR_CTRL_DMA_BURST_TYPE 30
+#define BM_SSP_DDR_CTRL_DMA_BURST_TYPE 0xC0000000
+#define BF_SSP_DDR_CTRL_DMA_BURST_TYPE(v) \
+ (((v) << 30) & BM_SSP_DDR_CTRL_DMA_BURST_TYPE)
+#define BP_SSP_DDR_CTRL_RSVD0 2
+#define BM_SSP_DDR_CTRL_RSVD0 0x3FFFFFFC
+#define BF_SSP_DDR_CTRL_RSVD0(v) \
+ (((v) << 2) & BM_SSP_DDR_CTRL_RSVD0)
+#define BM_SSP_DDR_CTRL_NIBBLE_POS 0x00000002
+#define BM_SSP_DDR_CTRL_TXCLK_DELAY_TYPE 0x00000001
+
+#define HW_SSP_DLL_CTRL (0x000000f0)
+
+#define BP_SSP_DLL_CTRL_REF_UPDATE_INT 28
+#define BM_SSP_DLL_CTRL_REF_UPDATE_INT 0xF0000000
+#define BF_SSP_DLL_CTRL_REF_UPDATE_INT(v) \
+ (((v) << 28) & BM_SSP_DLL_CTRL_REF_UPDATE_INT)
+#define BP_SSP_DLL_CTRL_SLV_UPDATE_INT 20
+#define BM_SSP_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000
+#define BF_SSP_DLL_CTRL_SLV_UPDATE_INT(v) \
+ (((v) << 20) & BM_SSP_DLL_CTRL_SLV_UPDATE_INT)
+#define BP_SSP_DLL_CTRL_RSVD1 16
+#define BM_SSP_DLL_CTRL_RSVD1 0x000F0000
+#define BF_SSP_DLL_CTRL_RSVD1(v) \
+ (((v) << 16) & BM_SSP_DLL_CTRL_RSVD1)
+#define BP_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 10
+#define BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 0x0000FC00
+#define BF_SSP_DLL_CTRL_SLV_OVERRIDE_VAL(v) \
+ (((v) << 10) & BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL)
+#define BM_SSP_DLL_CTRL_SLV_OVERRIDE 0x00000200
+#define BM_SSP_DLL_CTRL_RSVD0 0x00000100
+#define BM_SSP_DLL_CTRL_GATE_UPDATE 0x00000080
+#define BP_SSP_DLL_CTRL_SLV_DLY_TARGET 3
+#define BM_SSP_DLL_CTRL_SLV_DLY_TARGET 0x00000078
+#define BF_SSP_DLL_CTRL_SLV_DLY_TARGET(v) \
+ (((v) << 3) & BM_SSP_DLL_CTRL_SLV_DLY_TARGET)
+#define BM_SSP_DLL_CTRL_SLV_FORCE_UPD 0x00000004
+#define BM_SSP_DLL_CTRL_RESET 0x00000002
+#define BM_SSP_DLL_CTRL_ENABLE 0x00000001
+
+#define HW_SSP_STATUS (0x00000100)
+
+#define BM_SSP_STATUS_PRESENT 0x80000000
+#define BM_SSP_STATUS_MS_PRESENT 0x40000000
+#define BM_SSP_STATUS_SD_PRESENT 0x20000000
+#define BM_SSP_STATUS_CARD_DETECT 0x10000000
+#define BP_SSP_STATUS_RSVD3 23
+#define BM_SSP_STATUS_RSVD3 0x0F800000
+#define BF_SSP_STATUS_RSVD3(v) \
+ (((v) << 23) & BM_SSP_STATUS_RSVD3)
+#define BM_SSP_STATUS_DMABURST 0x00400000
+#define BM_SSP_STATUS_DMASENSE 0x00200000
+#define BM_SSP_STATUS_DMATERM 0x00100000
+#define BM_SSP_STATUS_DMAREQ 0x00080000
+#define BM_SSP_STATUS_DMAEND 0x00040000
+#define BM_SSP_STATUS_SDIO_IRQ 0x00020000
+#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
+#define BM_SSP_STATUS_RESP_ERR 0x00008000
+#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
+#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000
+#define BM_SSP_STATUS_TIMEOUT 0x00001000
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800
+#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400
+#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200
+#define BM_SSP_STATUS_FIFO_FULL 0x00000100
+#define BP_SSP_STATUS_RSVD1 6
+#define BM_SSP_STATUS_RSVD1 0x000000C0
+#define BF_SSP_STATUS_RSVD1(v) \
+ (((v) << 6) & BM_SSP_STATUS_RSVD1)
+#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
+#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010
+#define BM_SSP_STATUS_CMD_BUSY 0x00000008
+#define BM_SSP_STATUS_DATA_BUSY 0x00000004
+#define BM_SSP_STATUS_RSVD0 0x00000002
+#define BM_SSP_STATUS_BUSY 0x00000001
+
+#define HW_SSP_DLL_STS (0x00000110)
+
+#define BP_SSP_DLL_STS_RSVD0 14
+#define BM_SSP_DLL_STS_RSVD0 0xFFFFC000
+#define BF_SSP_DLL_STS_RSVD0(v) \
+ (((v) << 14) & BM_SSP_DLL_STS_RSVD0)
+#define BP_SSP_DLL_STS_REF_SEL 8
+#define BM_SSP_DLL_STS_REF_SEL 0x00003F00
+#define BF_SSP_DLL_STS_REF_SEL(v) \
+ (((v) << 8) & BM_SSP_DLL_STS_REF_SEL)
+#define BP_SSP_DLL_STS_SLV_SEL 2
+#define BM_SSP_DLL_STS_SLV_SEL 0x000000FC
+#define BF_SSP_DLL_STS_SLV_SEL(v) \
+ (((v) << 2) & BM_SSP_DLL_STS_SLV_SEL)
+#define BM_SSP_DLL_STS_REF_LOCK 0x00000002
+#define BM_SSP_DLL_STS_SLV_LOCK 0x00000001
+
+#define HW_SSP_DEBUG (0x00000120)
+
+#define BP_SSP_DEBUG_DATACRC_ERR 28
+#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v) \
+ (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR)
+#define BM_SSP_DEBUG_DATA_STALL 0x08000000
+#define BP_SSP_DEBUG_DAT_SM 24
+#define BM_SSP_DEBUG_DAT_SM 0x07000000
+#define BF_SSP_DEBUG_DAT_SM(v) \
+ (((v) << 24) & BM_SSP_DEBUG_DAT_SM)
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5
+#define BP_SSP_DEBUG_MSTK_SM 20
+#define BM_SSP_DEBUG_MSTK_SM 0x00F00000
+#define BF_SSP_DEBUG_MSTK_SM(v) \
+ (((v) << 20) & BM_SSP_DEBUG_MSTK_SM)
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE
+#define BM_SSP_DEBUG_CMD_OE 0x00080000
+#define BP_SSP_DEBUG_DMA_SM 16
+#define BM_SSP_DEBUG_DMA_SM 0x00070000
+#define BF_SSP_DEBUG_DMA_SM(v) \
+ (((v) << 16) & BM_SSP_DEBUG_DMA_SM)
+#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2
+#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3
+#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4
+#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5
+#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6
+#define BP_SSP_DEBUG_MMC_SM 12
+#define BM_SSP_DEBUG_MMC_SM 0x0000F000
+#define BF_SSP_DEBUG_MMC_SM(v) \
+ (((v) << 12) & BM_SSP_DEBUG_MMC_SM)
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7
+#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8
+#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9
+#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA
+#define BP_SSP_DEBUG_CMD_SM 10
+#define BM_SSP_DEBUG_CMD_SM 0x00000C00
+#define BF_SSP_DEBUG_CMD_SM(v) \
+ (((v) << 10) & BM_SSP_DEBUG_CMD_SM)
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3
+#define BM_SSP_DEBUG_SSP_CMD 0x00000200
+#define BM_SSP_DEBUG_SSP_RESP 0x00000100
+#define BP_SSP_DEBUG_SSP_RXD 0
+#define BM_SSP_DEBUG_SSP_RXD 0x000000FF
+#define BF_SSP_DEBUG_SSP_RXD(v) \
+ (((v) << 0) & BM_SSP_DEBUG_SSP_RXD)
+
+#define HW_SSP_VERSION (0x00000130)
+
+#define BP_SSP_VERSION_MAJOR 24
+#define BM_SSP_VERSION_MAJOR 0xFF000000
+#define BF_SSP_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_SSP_VERSION_MAJOR)
+#define BP_SSP_VERSION_MINOR 16
+#define BM_SSP_VERSION_MINOR 0x00FF0000
+#define BF_SSP_VERSION_MINOR(v) \
+ (((v) << 16) & BM_SSP_VERSION_MINOR)
+#define BP_SSP_VERSION_STEP 0
+#define BM_SSP_VERSION_STEP 0x0000FFFF
+#define BF_SSP_VERSION_STEP(v) \
+ (((v) << 0) & BM_SSP_VERSION_STEP)
+#endif /* __ARCH_ARM___SSP_H */
diff --git a/include/asm-arm/arch-mx28/regs-timrot.h b/include/asm-arm/arch-mx28/regs-timrot.h
new file mode 100644
index 0000000..125b835
--- /dev/null
+++ b/include/asm-arm/arch-mx28/regs-timrot.h
@@ -0,0 +1,293 @@
+/*
+ * Freescale TIMROT Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.40
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___TIMROT_H
+#define __ARCH_ARM___TIMROT_H
+
+
+#define HW_TIMROT_ROTCTRL (0x00000000)
+#define HW_TIMROT_ROTCTRL_SET (0x00000004)
+#define HW_TIMROT_ROTCTRL_CLR (0x00000008)
+#define HW_TIMROT_ROTCTRL_TOG (0x0000000c)
+
+#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
+#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000
+#define BP_TIMROT_ROTCTRL_STATE 22
+#define BM_TIMROT_ROTCTRL_STATE 0x01C00000
+#define BF_TIMROT_ROTCTRL_STATE(v) \
+ (((v) << 22) & BM_TIMROT_ROTCTRL_STATE)
+#define BP_TIMROT_ROTCTRL_DIVIDER 16
+#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v) \
+ (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER)
+#define BP_TIMROT_ROTCTRL_RSRVD3 13
+#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000
+#define BF_TIMROT_ROTCTRL_RSRVD3(v) \
+ (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3)
+#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \
+ (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE)
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3
+#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
+#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
+#define BP_TIMROT_ROTCTRL_SELECT_B 4
+#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0
+#define BF_TIMROT_ROTCTRL_SELECT_B(v) \
+ (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B)
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA
+#define BP_TIMROT_ROTCTRL_SELECT_A 0
+#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F
+#define BF_TIMROT_ROTCTRL_SELECT_A(v) \
+ (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A)
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA
+
+#define HW_TIMROT_ROTCOUNT (0x00000010)
+
+#define BP_TIMROT_ROTCOUNT_RSRVD1 16
+#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000
+#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \
+ (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1)
+#define BP_TIMROT_ROTCOUNT_UPDOWN 0
+#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \
+ (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN)
+
+/*
+ * multi-register-define name HW_TIMROT_TIMCTRLn
+ * base 0x00000020
+ * count 3
+ * offset 0x40
+ */
+#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40)
+#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40)
+#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40)
+#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40)
+#define BP_TIMROT_TIMCTRLn_RSRVD3 16
+#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000
+#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \
+ (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3)
+#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
+#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
+#define BP_TIMROT_TIMCTRLn_RSRVD2 12
+#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000
+#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \
+ (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2)
+#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800
+#define BP_TIMROT_TIMCTRLn_RSRVD1 9
+#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600
+#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \
+ (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1)
+#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
+#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
+#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
+#define BP_TIMROT_TIMCTRLn_PRESCALE 4
+#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \
+ (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3
+#define BP_TIMROT_TIMCTRLn_SELECT 0
+#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
+#define BF_TIMROT_TIMCTRLn_SELECT(v) \
+ (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF
+
+/*
+ * multi-register-define name HW_TIMROT_RUNNING_COUNTn
+ * base 0x00000030
+ * count 3
+ * offset 0x40
+ */
+#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40)
+#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0
+#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF
+#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v)
+
+/*
+ * multi-register-define name HW_TIMROT_FIXED_COUNTn
+ * base 0x00000040
+ * count 3
+ * offset 0x40
+ */
+#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40)
+#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0
+#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF
+#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v)
+
+/*
+ * multi-register-define name HW_TIMROT_MATCH_COUNTn
+ * base 0x00000050
+ * count 4
+ * offset 0x40
+ */
+#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40)
+#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0
+#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF
+#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v)
+
+#define HW_TIMROT_TIMCTRL3 (0x000000e0)
+#define HW_TIMROT_TIMCTRL3_SET (0x000000e4)
+#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8)
+#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec)
+
+#define BP_TIMROT_TIMCTRL3_RSRVD2 20
+#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000
+#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \
+ (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2)
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \
+ (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL)
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF
+#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000
+#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000
+#define BP_TIMROT_TIMCTRL3_RSRVD1 12
+#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000
+#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \
+ (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1)
+#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200
+#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100
+#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080
+#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040
+#define BP_TIMROT_TIMCTRL3_PRESCALE 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \
+ (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE)
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3
+#define BP_TIMROT_TIMCTRL3_SELECT 0
+#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F
+#define BF_TIMROT_TIMCTRL3_SELECT(v) \
+ (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT)
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF
+
+#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0)
+
+#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0
+#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF
+#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v)
+
+#define HW_TIMROT_FIXED_COUNT3 (0x00000100)
+
+#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0
+#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF
+#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v)
+
+#define HW_TIMROT_VERSION (0x00000120)
+
+#define BP_TIMROT_VERSION_MAJOR 24
+#define BM_TIMROT_VERSION_MAJOR 0xFF000000
+#define BF_TIMROT_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_TIMROT_VERSION_MAJOR)
+#define BP_TIMROT_VERSION_MINOR 16
+#define BM_TIMROT_VERSION_MINOR 0x00FF0000
+#define BF_TIMROT_VERSION_MINOR(v) \
+ (((v) << 16) & BM_TIMROT_VERSION_MINOR)
+#define BP_TIMROT_VERSION_STEP 0
+#define BM_TIMROT_VERSION_STEP 0x0000FFFF
+#define BF_TIMROT_VERSION_STEP(v) \
+ (((v) << 0) & BM_TIMROT_VERSION_STEP)
+#endif /* __ARCH_ARM___TIMROT_H */
diff --git a/include/asm-arm/arch-mx28/regs-uartdbg.h b/include/asm-arm/arch-mx28/regs-uartdbg.h
new file mode 100644
index 0000000..0b5932c
--- /dev/null
+++ b/include/asm-arm/arch-mx28/regs-uartdbg.h
@@ -0,0 +1,301 @@
+/*
+ * Freescale UARTDBG Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.21
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___UARTDBG_H
+#define __ARCH_ARM___UARTDBG_H
+
+
+#define HW_UARTDBGDR (0x00000000)
+
+#define BP_UARTDBGDR_UNAVAILABLE 16
+#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGDR_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
+#define BP_UARTDBGDR_RESERVED 12
+#define BM_UARTDBGDR_RESERVED 0x0000F000
+#define BF_UARTDBGDR_RESERVED(v) \
+ (((v) << 12) & BM_UARTDBGDR_RESERVED)
+#define BM_UARTDBGDR_OE 0x00000800
+#define BM_UARTDBGDR_BE 0x00000400
+#define BM_UARTDBGDR_PE 0x00000200
+#define BM_UARTDBGDR_FE 0x00000100
+#define BP_UARTDBGDR_DATA 0
+#define BM_UARTDBGDR_DATA 0x000000FF
+#define BF_UARTDBGDR_DATA(v) \
+ (((v) << 0) & BM_UARTDBGDR_DATA)
+
+#define HW_UARTDBGRSR_ECR (0x00000004)
+
+#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
+#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
+ (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
+#define BP_UARTDBGRSR_ECR_EC 4
+#define BM_UARTDBGRSR_ECR_EC 0x000000F0
+#define BF_UARTDBGRSR_ECR_EC(v) \
+ (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
+#define BM_UARTDBGRSR_ECR_OE 0x00000008
+#define BM_UARTDBGRSR_ECR_BE 0x00000004
+#define BM_UARTDBGRSR_ECR_PE 0x00000002
+#define BM_UARTDBGRSR_ECR_FE 0x00000001
+
+#define HW_UARTDBGFR (0x00000018)
+
+#define BP_UARTDBGFR_UNAVAILABLE 16
+#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGFR_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
+#define BP_UARTDBGFR_RESERVED 9
+#define BM_UARTDBGFR_RESERVED 0x0000FE00
+#define BF_UARTDBGFR_RESERVED(v) \
+ (((v) << 9) & BM_UARTDBGFR_RESERVED)
+#define BM_UARTDBGFR_RI 0x00000100
+#define BM_UARTDBGFR_TXFE 0x00000080
+#define BM_UARTDBGFR_RXFF 0x00000040
+#define BM_UARTDBGFR_TXFF 0x00000020
+#define BM_UARTDBGFR_RXFE 0x00000010
+#define BM_UARTDBGFR_BUSY 0x00000008
+#define BM_UARTDBGFR_DCD 0x00000004
+#define BM_UARTDBGFR_DSR 0x00000002
+#define BM_UARTDBGFR_CTS 0x00000001
+
+#define HW_UARTDBGILPR (0x00000020)
+
+#define BP_UARTDBGILPR_UNAVAILABLE 8
+#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGILPR_UNAVAILABLE(v) \
+ (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
+#define BP_UARTDBGILPR_ILPDVSR 0
+#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
+#define BF_UARTDBGILPR_ILPDVSR(v) \
+ (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
+
+#define HW_UARTDBGIBRD (0x00000024)
+
+#define BP_UARTDBGIBRD_UNAVAILABLE 16
+#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
+#define BP_UARTDBGIBRD_BAUD_DIVINT 0
+#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
+#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
+ (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
+
+#define HW_UARTDBGFBRD (0x00000028)
+
+#define BP_UARTDBGFBRD_UNAVAILABLE 8
+#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
+ (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
+#define BP_UARTDBGFBRD_RESERVED 6
+#define BM_UARTDBGFBRD_RESERVED 0x000000C0
+#define BF_UARTDBGFBRD_RESERVED(v) \
+ (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
+#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
+#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
+#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
+ (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
+
+#define HW_UARTDBGLCR_H (0x0000002c)
+
+#define BP_UARTDBGLCR_H_UNAVAILABLE 16
+#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
+#define BP_UARTDBGLCR_H_RESERVED 8
+#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
+#define BF_UARTDBGLCR_H_RESERVED(v) \
+ (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
+#define BM_UARTDBGLCR_H_SPS 0x00000080
+#define BP_UARTDBGLCR_H_WLEN 5
+#define BM_UARTDBGLCR_H_WLEN 0x00000060
+#define BF_UARTDBGLCR_H_WLEN(v) \
+ (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
+#define BM_UARTDBGLCR_H_FEN 0x00000010
+#define BM_UARTDBGLCR_H_STP2 0x00000008
+#define BM_UARTDBGLCR_H_EPS 0x00000004
+#define BM_UARTDBGLCR_H_PEN 0x00000002
+#define BM_UARTDBGLCR_H_BRK 0x00000001
+
+#define HW_UARTDBGCR (0x00000030)
+
+#define BP_UARTDBGCR_UNAVAILABLE 16
+#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGCR_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
+#define BM_UARTDBGCR_CTSEN 0x00008000
+#define BM_UARTDBGCR_RTSEN 0x00004000
+#define BM_UARTDBGCR_OUT2 0x00002000
+#define BM_UARTDBGCR_OUT1 0x00001000
+#define BM_UARTDBGCR_RTS 0x00000800
+#define BM_UARTDBGCR_DTR 0x00000400
+#define BM_UARTDBGCR_RXE 0x00000200
+#define BM_UARTDBGCR_TXE 0x00000100
+#define BM_UARTDBGCR_LBE 0x00000080
+#define BP_UARTDBGCR_RESERVED 3
+#define BM_UARTDBGCR_RESERVED 0x00000078
+#define BF_UARTDBGCR_RESERVED(v) \
+ (((v) << 3) & BM_UARTDBGCR_RESERVED)
+#define BM_UARTDBGCR_SIRLP 0x00000004
+#define BM_UARTDBGCR_SIREN 0x00000002
+#define BM_UARTDBGCR_UARTEN 0x00000001
+
+#define HW_UARTDBGIFLS (0x00000034)
+
+#define BP_UARTDBGIFLS_UNAVAILABLE 16
+#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
+#define BP_UARTDBGIFLS_RESERVED 6
+#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
+#define BF_UARTDBGIFLS_RESERVED(v) \
+ (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
+#define BP_UARTDBGIFLS_RXIFLSEL 3
+#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
+#define BF_UARTDBGIFLS_RXIFLSEL(v) \
+ (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_EIGHT 0x0
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
+#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
+#define BP_UARTDBGIFLS_TXIFLSEL 0
+#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
+#define BF_UARTDBGIFLS_TXIFLSEL(v) \
+ (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_EIGHT 0x0
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
+#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
+
+#define HW_UARTDBGIMSC (0x00000038)
+
+#define BP_UARTDBGIMSC_UNAVAILABLE 16
+#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
+#define BP_UARTDBGIMSC_RESERVED 11
+#define BM_UARTDBGIMSC_RESERVED 0x0000F800
+#define BF_UARTDBGIMSC_RESERVED(v) \
+ (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
+#define BM_UARTDBGIMSC_OEIM 0x00000400
+#define BM_UARTDBGIMSC_BEIM 0x00000200
+#define BM_UARTDBGIMSC_PEIM 0x00000100
+#define BM_UARTDBGIMSC_FEIM 0x00000080
+#define BM_UARTDBGIMSC_RTIM 0x00000040
+#define BM_UARTDBGIMSC_TXIM 0x00000020
+#define BM_UARTDBGIMSC_RXIM 0x00000010
+#define BM_UARTDBGIMSC_DSRMIM 0x00000008
+#define BM_UARTDBGIMSC_DCDMIM 0x00000004
+#define BM_UARTDBGIMSC_CTSMIM 0x00000002
+#define BM_UARTDBGIMSC_RIMIM 0x00000001
+
+#define HW_UARTDBGRIS (0x0000003c)
+
+#define BP_UARTDBGRIS_UNAVAILABLE 16
+#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGRIS_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
+#define BP_UARTDBGRIS_RESERVED 11
+#define BM_UARTDBGRIS_RESERVED 0x0000F800
+#define BF_UARTDBGRIS_RESERVED(v) \
+ (((v) << 11) & BM_UARTDBGRIS_RESERVED)
+#define BM_UARTDBGRIS_OERIS 0x00000400
+#define BM_UARTDBGRIS_BERIS 0x00000200
+#define BM_UARTDBGRIS_PERIS 0x00000100
+#define BM_UARTDBGRIS_FERIS 0x00000080
+#define BM_UARTDBGRIS_RTRIS 0x00000040
+#define BM_UARTDBGRIS_TXRIS 0x00000020
+#define BM_UARTDBGRIS_RXRIS 0x00000010
+#define BM_UARTDBGRIS_DSRRMIS 0x00000008
+#define BM_UARTDBGRIS_DCDRMIS 0x00000004
+#define BM_UARTDBGRIS_CTSRMIS 0x00000002
+#define BM_UARTDBGRIS_RIRMIS 0x00000001
+
+#define HW_UARTDBGMIS (0x00000040)
+
+#define BP_UARTDBGMIS_UNAVAILABLE 16
+#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGMIS_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
+#define BP_UARTDBGMIS_RESERVED 11
+#define BM_UARTDBGMIS_RESERVED 0x0000F800
+#define BF_UARTDBGMIS_RESERVED(v) \
+ (((v) << 11) & BM_UARTDBGMIS_RESERVED)
+#define BM_UARTDBGMIS_OEMIS 0x00000400
+#define BM_UARTDBGMIS_BEMIS 0x00000200
+#define BM_UARTDBGMIS_PEMIS 0x00000100
+#define BM_UARTDBGMIS_FEMIS 0x00000080
+#define BM_UARTDBGMIS_RTMIS 0x00000040
+#define BM_UARTDBGMIS_TXMIS 0x00000020
+#define BM_UARTDBGMIS_RXMIS 0x00000010
+#define BM_UARTDBGMIS_DSRMMIS 0x00000008
+#define BM_UARTDBGMIS_DCDMMIS 0x00000004
+#define BM_UARTDBGMIS_CTSMMIS 0x00000002
+#define BM_UARTDBGMIS_RIMMIS 0x00000001
+
+#define HW_UARTDBGICR (0x00000044)
+
+#define BP_UARTDBGICR_UNAVAILABLE 16
+#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGICR_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
+#define BP_UARTDBGICR_RESERVED 11
+#define BM_UARTDBGICR_RESERVED 0x0000F800
+#define BF_UARTDBGICR_RESERVED(v) \
+ (((v) << 11) & BM_UARTDBGICR_RESERVED)
+#define BM_UARTDBGICR_OEIC 0x00000400
+#define BM_UARTDBGICR_BEIC 0x00000200
+#define BM_UARTDBGICR_PEIC 0x00000100
+#define BM_UARTDBGICR_FEIC 0x00000080
+#define BM_UARTDBGICR_RTIC 0x00000040
+#define BM_UARTDBGICR_TXIC 0x00000020
+#define BM_UARTDBGICR_RXIC 0x00000010
+#define BM_UARTDBGICR_DSRMIC 0x00000008
+#define BM_UARTDBGICR_DCDMIC 0x00000004
+#define BM_UARTDBGICR_CTSMIC 0x00000002
+#define BM_UARTDBGICR_RIMIC 0x00000001
+
+#define HW_UARTDBGDMACR (0x00000048)
+
+#define BP_UARTDBGDMACR_UNAVAILABLE 16
+#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
+ (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
+#define BP_UARTDBGDMACR_RESERVED 3
+#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
+#define BF_UARTDBGDMACR_RESERVED(v) \
+ (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
+#define BM_UARTDBGDMACR_DMAONERR 0x00000004
+#define BM_UARTDBGDMACR_TXDMAE 0x00000002
+#define BM_UARTDBGDMACR_RXDMAE 0x00000001
+#endif /* __ARCH_ARM___UARTDBG_H */
diff --git a/include/configs/mx28.h b/include/configs/mx28.h
index 4af0a28..84fecc3 100644
--- a/include/configs/mx28.h
+++ b/include/configs/mx28.h
@@ -1,7 +1,6 @@
/*
* Copyright (C) 2008 Embedded Alley Solutions, Inc.
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -61,16 +60,15 @@
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x41000000 /* 16MB RAM test */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x40000000 /* mDDR Start */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* mDDR size 32MB */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* mDDR size 32MB */
/*====================*/
/* Serial Driver info */
/*====================*/
-#define CONFIG_STMP3XXX_DBGUART /* 378x debug UART */
#define CONFIG_DBGUART_CLK 24000000
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
@@ -88,28 +86,28 @@
/*=====================*/
#define CONFIG_SYS_NO_FLASH /* Flash is not supported */
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
-#define CONFIG_ENV_SIZE 0x20000
+
+
+/* ROM loads UBOOT into DRAM */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.167.10.2
-#define CONFIG_SERVERIP 192.167.10.1
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "stmp378x U-Boot > "
- /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_PROMPT "MX28 U-Boot > "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x40400000
- /* default Linux kernel load address */
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CFG_HUSH_PARSER
@@ -119,32 +117,70 @@
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
+/*
+ * Boot Linux
+ */
#define LINUX_BOOT_PARAM_ADDR 0x40000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "\
- "root=/dev/mtdblock1 rootfstype=jffs2 lcd_panel=lms350"
-#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
+#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
+#define CONFIG_BOOTCOMMAND "run bootcmd_net"
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "nfsroot=/data/rootfs_home/rootfs\0" \
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "bootcmd_net=run bootargs_nfs; dhcp; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p2 " \
+ "ip=dhcp rootfstype=ext2\0" \
+ "bootcmd_mmc=run bootargs_mmc; " \
+ "mmc read 0 ${loadaddr} 100 3000; bootm\0" \
/*=================*/
/* U-Boot commands */
/*=================*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DIAG
+#undef CONFIG_CMD_MMC /* MX28 use special mmc command*/
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * ENET Driver
+ */
+#define CONFIG_MXC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETH_PRIME
#define CONFIG_CMD_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_SAVES
-#undef CONFIG_CMD_IMLS
-
-/* Ethernet chip - select an alternative driver */
-#define CONFIG_ENC28J60_ETH
-#define CONFIG_ENC28J60_ETH_SPI_BUS 0
-#define CONFIG_ENC28J60_ETH_SPI_CS 0
+#define CONFIG_IPADDR 192.168.1.101
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_NETMASK 255.255.255.0
+
+/*
+ * MMC Driver
+ */
+#define CONFIG_IMX_SSP_MMC /* MMC driver based on SSP */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CUSTOMIZE_MMCOPS /* To customize do_mmcops() */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_MMC
+
+/*
+ * Environments on MMC
+ */
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_MMC
+/* Assoiated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET (0x400) /* 1 KB */
+#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */
#endif /* __CONFIG_H */
generated by cgit v1.1 at 2024-11-21 12:50:12 +0000