diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | board/freescale/mx6q_arm2/flash_header.S | 307 | ||||
| -rw-r--r-- | include/configs/mx6dl_arm2.h | 1 | ||||
| -rw-r--r-- | include/configs/mx6dl_arm2_lpddr2.h | 319 |
4 files changed, 627 insertions, 1 deletions
@@ -3309,6 +3309,7 @@ mx53_evk_config : unconfig mx6dl_arm2_config \ mx6dl_arm2_iram_config \ mx6dl_arm2_mfg_config \ +mx6dl_arm2_lpddr2_config \ mx6q_arm2_config \ mx6q_arm2_mfg_config \ mx6q_arm2_lpddr2_config \ diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S index 8254179..c6cb83f 100644 --- a/board/freescale/mx6q_arm2/flash_header.S +++ b/board/freescale/mx6q_arm2/flash_header.S @@ -56,7 +56,7 @@ boot_data: .word TEXT_BASE image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET plugin: .word 0x0 -#if defined CONFIG_MX6DL +#if defined CONFIG_MX6DL_DDR3 dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */ @@ -192,6 +192,311 @@ MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) +#elif defined CONFIG_MX6DL_LPDDR2 + +dcd_hdr: .word 0x408803D2 /* Tag=0xD2, Len=112*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x048403CC /* Tag=0xCC, Len=112*8 + 4, Param=0x04 */ + +# IOMUX SETTINGS +# IOMUXC_BASE_ADDR = 0x020e0000 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x4bc, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x4c0, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4c4, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4c8, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x4cc, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x4d0, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x4d4, 0x00003028) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x4d8, 0x00003028) + +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x470, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x474, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x478, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x47c, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x480, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x484, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x488, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x48c, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x464, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x490, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4ac, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4b0, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x494, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4a4, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4a8, 0x00000038) +/* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 + * DSE can be configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ +MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x4b4, 0x00000038) +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ +MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x4b8, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ +MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x764, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ +MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x770, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ +MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x778, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ +MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x77c, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ +MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x780, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ +MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x784, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ +MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x78c, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ +MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ +MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ +MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x76c, 0x00000038) +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ +MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000) +/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ +MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x754, 0x00000000) +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ +MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x760, 0x00020000) +/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ +MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x774, 0x00080000) + +/* + * DDR Controller Registers + * + * Manufacturer: Mocron + * Device Part Number: MT42L64M64D2KH-18 + * Clock Freq.: 528MHz + * MMDC channels: Both MMDC0, MMDC1 + *Density per CS in Gb: 256M + * Chip Selects used: 2 + * Number of Banks: 8 + * Row address: 14 + * Column address: 9 + * Data bus width 32 + */ + +# MMDC_P0_BASE_ADDR = 0x021b0000 +# MMDC_P1_BASE_ADDR = 0x021b4000 + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000) + +/*LPDDR2 ZQ params */ +MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff) +MXC_DCD_ITEM(44, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff) + +# Calibration setup. +/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ +MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003) + +/*ca bus abs delay */ +MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x890, 0x00400000) +/*ca bus abs delay */ +MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x890, 0x00400000) +/* values of 20,40,50,60,7f tried. no difference seen */ + +/* DDR_PHY_P1_MPWRCADL */ +MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555) + +/*frc_msr.*/ +MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) +/*frc_msr.*/ +MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) + +/* DDR_PHY_P0_MPREDQBY0DL3 */ +MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) +/* DDR_PHY_P0_MPREDQBY1DL3 */ +MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) +/* DDR_PHY_P0_MPREDQBY2DL3 */ +MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) +/* DDR_PHY_P0_MPREDQBY3DL3 */ +MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) +/* DDR_PHY_P1_MPREDQBY0DL3 */ +MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333) +/* DDR_PHY_P1_MPREDQBY1DL3 */ +MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x820, 0x33333333) +/* DDR_PHY_P1_MPREDQBY2DL3 */ +MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x824, 0x33333333) +/* DDR_PHY_P1_MPREDQBY3DL3 */ +MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x828, 0x33333333) + +/* + * Read and write data delay, per byte. + * For optimized DDR operation it is recommended to run mmdc_calibration + * on your board, and replace 4 delay register assigns with resulted values + * Note: + * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section + * should be skipped, or the write/read calibration comming after that + * will stall + * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. + */ + +MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b524f) +MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x848, 0x494f4c44) + +MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x850, 0x3c3d303c) +MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x850, 0x3c343d38) + +/*dqs gating dis */ +MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000) +MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x840, 0x0) +MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000) +MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x840, 0x0) + +/*clk delay */ +MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x858, 0xa00) +/*clk delay */ +MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x858, 0xa00) + +/*frc_msr */ +MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) +/*frc_msr */ +MXC_DCD_ITEM(70, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) +# Calibration setup end + +/* Channel0 - startng address 0x80000000 */ +/* MMDC0_MDCFG0 */ +MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x00c, 0x34386145) + +/* MMDC0_MDPDC */ +MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x004, 0x00020036) +/* MMDC0_MDCFG1 */ +MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x010, 0x00100c83) +/* MMDC0_MDCFG2 */ +MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x014, 0x000000Dc) +/* MMDC0_MDMISC */ +MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x018, 0x0000174C) +/* MMDC0_MDRWD;*/ +MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x02c, 0x0f9f26d2) +/* MMDC0_MDOR */ +MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x030, 0x0000020e) +/* MMDC0_MDCFG3LP */ +MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x038, 0x00190778) +/* MMDC0_MDOTC */ +MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x008, 0x00000000) + +/* CS0_END */ +MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x040, 0x0000005f) +/* ROC */ +MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x404, 0x0000000f) + +/* MMDC0_MDCTL */ +MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x000, 0xc3010000) + +/* Channel1 - starting address 0x10000000 */ +/* MMDC1_MDCFG0 */ +MXC_DCD_ITEM(83, MMDC_P1_BASE_ADDR + 0x00c, 0x34386145) + +/* MMDC1_MDPDC */ +MXC_DCD_ITEM(84, MMDC_P1_BASE_ADDR + 0x004, 0x00020036) +/* MMDC1_MDCFG1 */ +MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x010, 0x00100c83) +/* MMDC1_MDCFG2 */ +MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x014, 0x000000Dc) +/* MMDC1_MDMISC */ +MXC_DCD_ITEM(87, MMDC_P1_BASE_ADDR + 0x018, 0x0000174C) +/* MMDC1_MDRWD;*/ +MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x02c, 0x0f9f26d2) +/* MMDC1_MDOR */ +MXC_DCD_ITEM(89, MMDC_P1_BASE_ADDR + 0x030, 0x0000020e) +/* MMDC1_MDCFG3LP */ +MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x038, 0x00190778) +/* MMDC1_MDOTC */ +MXC_DCD_ITEM(91, MMDC_P1_BASE_ADDR + 0x008, 0x00000000) + +/* CS0_END */ +MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0x040, 0x0000003f) + +/* MMDC1_MDCTL */ +MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x000, 0xc3010000) + +/* Channel0 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +MXC_DCD_ITEM(94, MMDC_P0_BASE_ADDR + 0x01c, 0x003f8030) +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +MXC_DCD_ITEM(95, MMDC_P0_BASE_ADDR + 0x01c, 0xff0a8030) +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +MXC_DCD_ITEM(96, MMDC_P0_BASE_ADDR + 0x01c, 0xa2018030) +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +MXC_DCD_ITEM(97, MMDC_P0_BASE_ADDR + 0x01c, 0x06028030) +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +MXC_DCD_ITEM(98, MMDC_P0_BASE_ADDR + 0x01c, 0x01038030) + +/* Channel1 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x01c, 0x003f8030) +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x01c, 0xff0a8030) +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x01c, 0xa2018030) +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x01c, 0x06028030) +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +MXC_DCD_ITEM(103, MMDC_P1_BASE_ADDR + 0x01c, 0x01038030) + +/* MMDC0_MDREF */ +MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) +/* MMDC1_MDREF */ +MXC_DCD_ITEM(105, MMDC_P1_BASE_ADDR + 0x020, 0x00005800) + +/* DDR_PHY_P0_MPODTCTRL */ +MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x818, 0x0) +/* DDR_PHY_P1_MPODTCTRL */ +MXC_DCD_ITEM(107, MMDC_P1_BASE_ADDR + 0x818, 0x0) + +/* + * calibration values based on calibration compare of 0x00ffff00: + * Note, these calibration values are based on Freescale's board + * May need to run calibration on target board to fine tune these + */ + +/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ +MXC_DCD_ITEM(108, MMDC_P0_BASE_ADDR + 0x800, 0xa1310003) + +/* DDR_PHY_P0_MPMUR0, frc_msr */ +MXC_DCD_ITEM(109, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) +/* DDR_PHY_P1_MPMUR0, frc_msr */ +MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) + +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +MXC_DCD_ITEM(111, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x01c, 0x00000000) + #elif defined(CONFIG_LPDDR2) dcd_hdr: .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */ diff --git a/include/configs/mx6dl_arm2.h b/include/configs/mx6dl_arm2.h index eaa9a34..5c3ba3b 100644 --- a/include/configs/mx6dl_arm2.h +++ b/include/configs/mx6dl_arm2.h @@ -28,6 +28,7 @@ #define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ #define CONFIG_MXC #define CONFIG_MX6DL +#define CONFIG_MX6DL_DDR3 #define CONFIG_MX6Q_ARM2 #define CONFIG_DDR_32BIT /* For 32bit DDR, comment it out for 64bit */ #define CONFIG_FLASH_HEADER diff --git a/include/configs/mx6dl_arm2_lpddr2.h b/include/configs/mx6dl_arm2_lpddr2.h new file mode 100644 index 0000000..a665dbc --- /dev/null +++ b/include/configs/mx6dl_arm2_lpddr2.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX6Q Armadillo2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx6.h> + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX6DL +#define CONFIG_MX6DL_LPDDR2 +#define CONFIG_MX6Q_ARM2 +#define CONFIG_DDR_32BIT /* For 32bit DDR, comment it out for 64bit */ +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_MX6_CLK32 32768 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_ARCH_MMU /* disable MMU first */ +#define CONFIG_L2_OFF /* disable L2 cache first*/ + +#define CONFIG_MX6_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_UART_BASE_ADDR UART4_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_SPI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMXOTP + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_SF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_IMX_DOWNLOAD_MODE + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc3,115200 "\ + "nosmp enable_wait_mode=off\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p1 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; " \ + "mmc dev 3; " \ + "mmc read ${loadaddr} 0x800 0x2000; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX6SDL ARM2 LPDDR2 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10010000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_MIIBASE -1 +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_MXC_FEC +#define CONFIG_FEC0_PHY_ADDR 0 +#define CONFIG_ETH_PRIME +#define CONFIG_RMII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_IPADDR 192.168.1.103 +#define CONFIG_SERVERIP 192.168.1.101 +#define CONFIG_NETMASK 255.255.255.0 + +/* + * OCOTP Configs + */ +#ifdef CONFIG_CMD_IMXOTP + #define CONFIG_IMX_OTP + #define IMX_OTP_BASE OCOTP_BASE_ADDR + #define IMX_OTP_ADDR_MAX 0x7F + #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#endif + +/* + * I2C Configs + */ +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0x1f +#endif + +/* + * SPI Configs + */ +#ifdef CONFIG_CMD_SF + #define CONFIG_FSL_SF 1 + #define CONFIG_SPI_FLASH_IMX_M25PXX 1 + #define CONFIG_SPI_FLASH_CS 1 + #define CONFIG_IMX_ECSPI + #define IMX_CSPI_VER_2_3 1 + #define MAX_SPI_BYTES (64 * 4) +#endif + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_USDHC_NUM 4 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 2 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether SD1, 2, 3, or 4 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + /* SD3 and SD4 are 8 bit */ + #define CONFIG_MMC_8BIT_PORTS 0xC + /* Setup target delay in DDR mode for each SD port */ + #define CONFIG_GET_DDR_TARGET_DELAY +#endif + +/* + * GPMI Nand Configs + */ +/* #define CONFIG_CMD_NAND */ + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + /* NAND is the unique module invoke APBH-DMA */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR +#ifdef CONFIG_DDR_32BIT +#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) +#else +#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024) +#endif +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ + +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_SPLASH_SCREEN + /* + * Framebuffer and LCD + */ + #define CONFIG_LCD + #define CONFIG_IPU_V3H + #define CONFIG_VIDEO_MX5 + #define CONFIG_IPU_CLKRATE 260000000 + #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define LCD_BPP LCD_COLOR16 + #define CONFIG_CMD_BMP + #define CONFIG_BMP_8BPP + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SPLASH_SCREEN_ALIGN + #define CONFIG_SYS_WHITE_ON_BLACK +#endif +#endif /* __CONFIG_H */ |