diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabresd/mx6q_sabresd.c | 162 | ||||
| -rw-r--r-- | include/configs/mx6q_sabresd.h | 2 | ||||
| -rw-r--r-- | include/configs/mx6q_sabresd_android.h | 80 | ||||
| -rw-r--r-- | include/configs/mx6q_sabresd_mfg.h | 306 |
5 files changed, 551 insertions, 1 deletions
@@ -3321,6 +3321,8 @@ mx6q_arm2_iram_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_arm2 freescale mx6 mx6q_sabresd_config \ +mx6q_sabresd_android_config \ +mx6q_sabresd_mfg_config \ mx6q_sabresd_iram_config : unconfig @[ -z "$(findstring iram_,$@)" ] || \ { echo "TEXT_BASE = 0x00907000" >$(obj)board/freescale/mx6q_sabresd/config.tmp ; \ diff --git a/board/freescale/mx6q_sabresd/mx6q_sabresd.c b/board/freescale/mx6q_sabresd/mx6q_sabresd.c index db325ed..e2a080e 100644 --- a/board/freescale/mx6q_sabresd/mx6q_sabresd.c +++ b/board/freescale/mx6q_sabresd/mx6q_sabresd.c @@ -59,6 +59,16 @@ #include <asm/clock.h> #endif +#ifdef CONFIG_ANDROID_RECOVERY +#include "../common/recovery.h" +#include <part.h> +#include <ext2fs.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <ubi_uboot.h> +#include <jffs2/load_kernel.h> +#endif + DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; @@ -743,6 +753,134 @@ int board_init(void) return 0; } + +#ifdef CONFIG_ANDROID_RECOVERY +struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = { + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = NULL, + .args = NULL, + }, +}; + +int check_recovery_cmd_file(void) +{ + disk_partition_t info; + int button_pressed = 0; + ulong part_length; + int filelen = 0; + char *env; + u32 reg; + int i; + + printf("Checking for recovery command file...\n"); + switch (get_boot_device()) { + case MMC_BOOT: + case SD_BOOT: + case SPI_NOR_BOOT: + case I2C_BOOT: + { + for (i = 0; i < 3; i++) { + block_dev_desc_t *dev_desc = NULL; + struct mmc *mmc = find_mmc_device(i); + + dev_desc = get_dev("mmc", i); + + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", i); + continue; + } + + mmc_init(mmc); + + if (get_partition_info(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC, + &info)) { + printf("** Bad partition %d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + continue; + } + + part_length = ext2fs_set_blk_dev(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC); + if (part_length == 0) { + printf("** Bad partition - mmc %d:%d **\n", i, + CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + continue; + } + + if (!ext2fs_mount(part_length)) { + printf("** Bad ext2 partition or " + "disk - mmc %d:%d **\n", + i, CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + continue; + } + + filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE); + + ext2fs_close(); + break; + } + } + break; + case NAND_BOOT: + return 0; + break; + case UNKNOWN_BOOT: + default: + return 0; + break; + } + + + /* Check Recovery Combo Button press or not. */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_5__GPIO_1_5); + reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR); + reg &= ~(1<<5); + writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR); + reg = readl(GPIO1_BASE_ADDR + GPIO_PSR); + if (!(reg & (1 << 5))) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return (filelen > 0 || button_pressed); +} +#endif + int board_late_init(void) { return 0; @@ -898,3 +1036,27 @@ int checkboard(void) } return 0; } + +#ifdef CONFIG_IMX_UDC + +void udc_pins_setting(void) +{ +#define GPIO_3_22_BIT_MASK (1<<22) + u32 reg; + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_1__USBOTG_ID); + /* USB_OTG_PWR */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D22__GPIO_3_22); + + reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR); + /* set gpio_3_22 as output */ + reg |= GPIO_3_22_BIT_MASK; + writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR); + + /* set USB_OTG_PWR to 0 */ + reg = readl(GPIO3_BASE_ADDR + GPIO_DR); + reg &= ~GPIO_3_22_BIT_MASK; + writel(reg, GPIO3_BASE_ADDR + GPIO_DR); + + mxc_iomux_set_gpr_register(1, 13, 1, 1); +} +#endif diff --git a/include/configs/mx6q_sabresd.h b/include/configs/mx6q_sabresd.h index b8c7410..c5c02e6 100644 --- a/include/configs/mx6q_sabresd.h +++ b/include/configs/mx6q_sabresd.h @@ -110,7 +110,7 @@ #define CONFIG_PRIME "FEC0" #define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ -#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) +#define CONFIG_RD_LOADADDR (0x1300000) #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/mx6q_sabresd_android.h b/include/configs/mx6q_sabresd_android.h new file mode 100644 index 0000000..349ffc1 --- /dev/null +++ b/include/configs/mx6q_sabresd_android.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX6Q Sabre Lite2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MX6Q_SABRESD_ANDROID_H +#define MX6Q_SABRESD_ANDROID_H + +#include "mx6q_sabresd.h" + +/* Can't enable OTG on this board, if enable kernel will hang very + * early stage */ +#if 0 +#define CONFIG_USB_DEVICE +#define CONFIG_IMX_UDC 1 +#define CONFIG_FASTBOOT 1 +#define CONFIG_FASTBOOT_STORAGE_EMMC_SATA +#define CONFIG_FASTBOOT_VENDOR_ID 0xbb4 +#define CONFIG_FASTBOOT_PRODUCT_ID 0xc01 +#define CONFIG_FASTBOOT_BCD_DEVICE 0x311 +#define CONFIG_FASTBOOT_MANUFACTURER_STR "Freescale" +#define CONFIG_FASTBOOT_PRODUCT_NAME_STR "i.mx6q arm" +#define CONFIG_FASTBOOT_INTERFACE_STR "Android fastboot" +#define CONFIG_FASTBOOT_CONFIGURATION_STR "Android fastboot" +#define CONFIG_FASTBOOT_SERIAL_NUM "12345" +#define CONFIG_FASTBOOT_SATA_NO 0 +#define CONFIG_FASTBOOT_TRANSFER_BUF 0x30000000 +#define CONFIG_FASTBOOT_TRANSFER_BUF_SIZE 0x10000000 /* 256M byte */ +#endif /* if 0 */ + +#define CONFIG_ANDROID_RECOVERY +#define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 2 +#define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 4 +#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6 + +#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \ + "setenv bootargs ${bootargs} init=/init root=/dev/mmcblk0p4 rootfs=ext4 rootwait enable_wait_mode=off" +#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \ + "run bootargs_android_recovery; " \ + "mmc dev 3; " \ + "mmc read ${loadaddr} 0x800 0x2000;bootm" +#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command" + +#undef CONFIG_LOADADDR +#undef CONFIG_RD_LOADADDR +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR 0x11000000 + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "bootfile=uImage\0" \ + "bootargs=console=ttymxc0,115200 init=/init rw " \ + "video=mxcfb0 fbmem=10M vmalloc=400M enable_wait_mode=off\0" \ + "bootcmd_SD=mmc dev 3;" \ + "mmc read ${loadaddr} 0x800 0x2000;" \ + "mmc read ${rd_loadaddr} 0x3000 0x300\0" \ + "bootcmd=run bootcmd_SD; bootm ${loadaddr} ${rd_loadaddr}\0" \ + + +#endif diff --git a/include/configs/mx6q_sabresd_mfg.h b/include/configs/mx6q_sabresd_mfg.h new file mode 100644 index 0000000..0e27db1 --- /dev/null +++ b/include/configs/mx6q_sabresd_mfg.h @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX6Q Sabre Lite2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx6.h> + + /* High Level Configuration Options */ +#define CONFIG_MFG +#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX6Q +#define CONFIG_MX6Q_SABRESD +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_MX6_CLK32 32768 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_ARCH_MMU /* disable MMU first */ +#define CONFIG_L2_OFF /* disable L2 cache first*/ + +#define CONFIG_MX6_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_SPI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMXOTP + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_SF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ + +/* #define CONFIG_CMD_SATA */ +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR 0x10c00000 + +#define CONFIG_BOOTARGS "console=ttymxc0,115200 rdinit=/linuxrc enable_wait_mode=off" +#define CONFIG_BOOTCOMMAND "bootm 0x10800000 0x10c00000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX6Q SABRESD-MFG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10010000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_MIIBASE -1 +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_MXC_FEC +#define CONFIG_FEC0_PHY_ADDR 0 +#define CONFIG_ETH_PRIME +#define CONFIG_RMII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_IPADDR 192.168.1.103 +#define CONFIG_SERVERIP 192.168.1.101 +#define CONFIG_NETMASK 255.255.255.0 + +/* + * OCOTP Configs + */ +#ifdef CONFIG_CMD_IMXOTP + #define CONFIG_IMX_OTP + #define IMX_OTP_BASE OCOTP_BASE_ADDR + #define IMX_OTP_ADDR_MAX 0x7F + #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#endif + +/* + * I2C Configs + */ +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0x1f +#endif + +/* + * SPI Configs + */ +#ifdef CONFIG_CMD_SF + #define CONFIG_FSL_SF 1 + #define CONFIG_SPI_FLASH_IMX_M25PXX 1 + #define CONFIG_SPI_FLASH_CS 1 + #define CONFIG_IMX_ECSPI + #define IMX_CSPI_VER_2_3 1 + #define MAX_SPI_BYTES (64 * 4) +#endif + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_USDHC_NUM 4 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 2 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether SD1, 2, 3, or 4 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + /* SD3 and SD4 are 8 bit */ + #define CONFIG_MMC_8BIT_PORTS 0xC + /* Setup target delay in DDR mode for each SD port */ + #define CONFIG_GET_DDR_TARGET_DELAY +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/* + * GPMI Nand Configs + */ +/* #define CONFIG_CMD_NAND */ + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* NAND is the unique module invoke APBH-DMA */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +/* #define CONFIG_FSL_ENV_IN_MMC */ +/* #define CONFIG_FSL_ENV_IN_NAND */ +/* #define CONFIG_FSL_ENV_IN_SATA */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_NOWHERE 1 + +#ifdef CONFIG_SPLASH_SCREEN + /* + * Framebuffer and LCD + */ + #define CONFIG_LCD + #define CONFIG_IPU_V3H + #define CONFIG_VIDEO_MX5 + #define CONFIG_IPU_CLKRATE 260000000 + #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define LCD_BPP LCD_COLOR16 + #define CONFIG_CMD_BMP + #define CONFIG_BMP_8BPP + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SPLASH_SCREEN_ALIGN + #define CONFIG_SYS_WHITE_ON_BLACK +#endif +#endif /* __CONFIG_H */ |