diff options
| -rw-r--r-- | Makefile | 11 | ||||
| -rw-r--r-- | board/ads5121/Makefile | 4 | ||||
| -rw-r--r-- | board/ads5121/ads5121.c | 1 | ||||
| -rw-r--r-- | board/ads5121/pci.c | 213 | ||||
| -rw-r--r-- | cpu/mpc512x/speed.c | 21 | ||||
| -rw-r--r-- | include/asm-ppc/global_data.h | 1 | ||||
| -rw-r--r-- | include/asm-ppc/immap_512x.h | 61 | ||||
| -rw-r--r-- | include/configs/ads5121.h | 30 | ||||
| -rw-r--r-- | include/mpc512x.h | 84 |
9 files changed, 411 insertions, 15 deletions
@@ -733,8 +733,15 @@ motionpro_config: unconfig ######################################################################### ## MPC512x Systems ######################################################################### -ads5121_config: unconfig - @$(MKCONFIG) ads5121 ppc mpc512x ads5121 +ads5121_config \ +ads5121_PCI_config \ + : unconfig + @echo "" >$(obj)include/config.h + @if [ "$(findstring _PCI_,$@)" ] ; then \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + $(XECHO) "... with PCI enabled" ; \ + fi + @$(MKCONFIG) -a ads5121 ppc mpc512x ads5121 ######################################################################### diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index cd8148c..b93bee1 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 462f41d..8629b03 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -34,6 +34,7 @@ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_PCI_EN | \ CLOCK_SCCR1_TPR_EN) #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ diff --git a/board/ads5121/pci.c b/board/ads5121/pci.c new file mode 100644 index 0000000..a338604 --- /dev/null +++ b/board/ads5121/pci.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/mmu.h> +#include <asm/global_data.h> +#include <pci.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <fdt_support.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +static struct pci_controller pci_hose; + + +/************************************************************************** + * pci_init_board() + * + */ +void +pci_init_board(void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile law512x_t *pci_law; + volatile pot512x_t *pci_pot; + volatile pcictrl512x_t *pci_ctrl; + volatile pciconf512x_t *pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller *hose; + + /* Set PCI divider for 33MHz */ + reg32 = immr->clk.scfr[0]; + reg32 &= ~(SCFR1_PCI_DIV_MASK); + reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT; + immr->clk.scfr[0] = reg32; + + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = &immr->pci_ctrl; + pci_conf = &immr->pci_conf; + + hose = &pci_hose; + + /* + * Release PCI RST Output signal + */ + pci_ctrl->gcr = 0; + udelay(2000); + pci_ctrl->gcr = 1; + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; i++) + udelay(1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M; + + /* PCI IO space */ + pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; + + /* PCI mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEM_BASE, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_PHYS, + CFG_PCI_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI_IO_BASE, + CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR + 0x8300), + (CFG_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} + +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int tmp[2]; + const char *path; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { + path = fdt_getprop(blob, nodeoffset, "pci", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose.first_busno); + tmp[1] = cpu_to_be32(pci_hose.last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } + } +} +#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 99e3495..cfaffb5 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -67,12 +67,14 @@ int get_clocks (void) u8 cpmf; u8 sys_div; u8 ips_div; + u8 pci_div; u32 ref_clk = CFG_MPC512X_CLKIN; u32 spll; u32 sys_clk; u32 core_clk; u32 csb_clk; u32 ips_clk; + u32 pci_clk; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -95,8 +97,16 @@ int get_clocks (void) /* in case we cannot get a sane IPS divisor, fail gracefully */ ips_clk = 0; } + pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT; + if (pci_div != 0) { + pci_clk = csb_clk / pci_div; + } else { + /* in case we cannot get a sane IPS divisor, fail gracefully */ + pci_clk = 333333; + } gd->ips_clk = ips_clk; + gd->pci_clk = pci_clk; gd->csb_clk = csb_clk; gd->cpu_clk = core_clk; gd->bus_clk = csb_clk; @@ -115,11 +125,12 @@ ulong get_bus_freq (ulong dummy) int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - printf ("Clock configuration:\n"); - printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000); - printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); - printf (" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000); - printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); + printf("Clock configuration:\n"); + printf(" CPU: %4d MHz\n", gd->cpu_clk / 1000000); + printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000); + printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000); + printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); return 0; } diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index f9a3d92..205f7ed 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -103,6 +103,7 @@ typedef struct global_data { #if defined(CONFIG_MPC512X) u32 ips_clk; u32 csb_clk; + u32 pci_clk; #endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC8220) unsigned long bExtUart; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 23d10d4..cd90945 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -29,7 +29,7 @@ typedef struct law512x { u32 bar; /* Base Addr Register */ u32 ar; /* Attributes Register */ -} law521x_t; +} law512x_t; /* * System configuration registers @@ -47,9 +47,9 @@ typedef struct sysconf512x { u32 lpcs6aw; /* LP CS6 Access Window */ u32 lpcs7aw; /* LP CS7 Access Window */ u8 res1[0x1c]; - law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ + law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ u8 res2[0x28]; - law521x_t ddrlaw; /* DDR Local Access Window */ + law512x_t ddrlaw; /* DDR Local Access Window */ u8 res3[0x18]; u32 mbxbar; /* MBX Base Address */ u32 srambar; /* SRAM Base Address */ @@ -241,21 +241,70 @@ typedef struct dma512x { * PCI Software Configuration Registers */ typedef struct pciconf512x { - u8 fixme[0x80]; + u32 config_address; + u32 config_data; + u32 int_ack; + u8 res[116]; } pciconf512x_t; /* + * PCI Outbound Translation Register + */ +typedef struct pci_outbound_window { + u32 potar; + u8 res0[4]; + u32 pobar; + u8 res1[4]; + u32 pocmr; + u8 res2[4]; +} pot512x_t; + +/* * Sequencer */ typedef struct ios512x { - u8 fixme[0x100]; + pot512x_t pot[6]; + u8 res0[0x60]; + u32 pmcr; + u8 res1[4]; + u32 dtcr; + u8 res2[4]; } ios512x_t; /* * PCI Controller */ typedef struct pcictrl512x { - u8 fixme[0x100]; + u32 esr; + u32 ecdr; + u32 eer; + u32 eatcr; + u32 eacr; + u32 eeacr; + u32 edlcr; + u32 edhcr; + u32 gcr; + u32 ecr; + u32 gsr; + u8 res0[12]; + u32 pitar2; + u8 res1[4]; + u32 pibar2; + u32 piebar2; + u32 piwar2; + u8 res2[4]; + u32 pitar1; + u8 res3[4]; + u32 pibar1; + u32 piebar1; + u32 piwar1; + u8 res4[4]; + u32 pitar0; + u8 res5[4]; + u32 pibar0; + u8 res6[4]; + u32 piwar0; + u8 res7[132]; } pcictrl512x_t; diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 09c3140..65dc97e 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -34,6 +34,9 @@ * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) + * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) + * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) */ @@ -43,7 +46,7 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ -#undef CONFIG_PCI +/* CONFIG_PCI is defined at config time */ #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ @@ -217,6 +220,31 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* + * PCI + */ +#ifdef CONFIG_PCI + +/* + * General PCI + */ +#define CFG_PCI_MEM_BASE 0xA0000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE) +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0x00000000 +#define CFG_PCI_IO_PHYS 0x84000000 +#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */ + + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#endif + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ diff --git a/include/mpc512x.h b/include/mpc512x.h index b51cf78..b4cc2b9 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -46,6 +46,7 @@ #define LPCS6AW 0x003C #define LPCA7AW 0x0040 #define SRAMBAR 0x00C4 +#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ #define LPC_OFFSET 0x10000 @@ -189,6 +190,10 @@ #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 +#define SCFR1_PCI_DIV 0x6 +#define SCFR1_PCI_DIV_MASK 0x00700000 +#define SCFR1_PCI_DIV_SHIFT 20 + /* SCFR2 System Clock Frequency Register 2 */ #define SCFR2_SYS_DIV 0xFC000000 @@ -404,4 +409,83 @@ #define I2C_IF 0x02 #define I2C_RXAK 0x01 +/* POTAR - PCI Outbound Translation Address Register + */ +#define POTAR_TA_MASK 0x000fffff + +/* POBAR - PCI Outbound Base Address Register + */ +#define POBAR_BA_MASK 0x000fffff + +/* POCMR - PCI Outbound Comparision Mask Register + */ +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ +#define POCMR_PRE 0x20000000 /* prefetch enable */ +#define POCMR_SBS 0x00100000 /* special byte swap enable */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + +/* PITAR - PCI Inbound Translation Address Register + */ +#define PITAR_TA_MASK 0x000fffff + +/* PIBAR - PCI Inbound Base/Extended Address Register + */ +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff + +/* PIWAR - PCI Inbound Windows Attributes Register + */ +#define PIWAR_EN 0x80000000 +#define PIWAR_SBS 0x40000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E + #endif /* __MPC512X_H__ */ |