diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 169 | ||||
| -rw-r--r-- | include/configs/mx6q_sabreauto_lpddr2.h | 282 |
3 files changed, 452 insertions, 0 deletions
@@ -3307,6 +3307,7 @@ mx53_evk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53 mx6q_sabreauto_config \ +mx6q_sabreauto_lpddr2_config \ mx6q_sabreauto_iram_config : unconfig @[ -z "$(findstring iram_,$@)" ] || \ { echo "TEXT_BASE = 0x00910000" >$(obj)board/freescale/mx6q_sabreauto/config.tmp ; \ diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index d18ab74..4a20fb4 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -53,6 +53,174 @@ boot_data: .word TEXT_BASE image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET plugin: .word 0x0 +#ifdef CONFIG_LPDDR2 + +dcd_hdr: .word 0x40e803D2 /* Tag=0xD2, Len=124*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04e403CC /* Tag=0xCC, Len=124*8 + 4, Param=0x04 */ + +/* DCD */ +MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324) + +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038) + +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038) + +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038) + +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038) + +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038) + +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038) +MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000) + +MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038) +MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038) +MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038) +MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038) + +MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038) +MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038) +MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038) +MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038) + +MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038) +MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038) +MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038) +MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000) + +MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000) +MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000) +MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038) +MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000) + +MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) +MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000) + +MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff) +MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff) + +MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000) +MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000) + +MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000) +MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000) + +MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555) + +MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) +MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) + +MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) +MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) +MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) +MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) +MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333) +MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333) +MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333) +MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333) + +MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333) +MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333) +MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333) +MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333) +MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333) +MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333) +MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333) +MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333) + +MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39) +MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738) +MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846) +MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35) + +MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000) +MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0) +MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000) +MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0) + +MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00) +MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00) + +MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800) +MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800) + +MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5) +MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036) +MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83) +MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd) +MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c) +MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2) +MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e) +MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac) +MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0) + +MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f) + +MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000) + +MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5) +MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036) +MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83) +MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd) +MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c) +MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2) +MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e) +MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac) +MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0) + +MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f) +MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000) + +MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030) +MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030) +MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030) +MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030) +MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030) + +MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030) +MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030) +MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030) +MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030) +MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030) + +MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003) +MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003) + +MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800) +MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800) + +MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0) +MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0) + +MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003) +MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003) + +MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800) +MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800) + +MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0) +MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0) + +#else + dcd_hdr: .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */ @@ -175,5 +343,6 @@ MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) /* set IPU Qos=0x7 */ MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x00070007) MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) +#endif #endif diff --git a/include/configs/mx6q_sabreauto_lpddr2.h b/include/configs/mx6q_sabreauto_lpddr2.h new file mode 100644 index 0000000..bcc9dcb --- /dev/null +++ b/include/configs/mx6q_sabreauto_lpddr2.h @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX6Q SABRE Automotive + * Infotainment Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx6.h> + +#define CONFIG_LPDDR2 + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX6Q +#define CONFIG_MX6Q_SABREAUTO +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_MX6_CLK32 32768 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_ARCH_MMU /* disable MMU first */ +#define CONFIG_L2_OFF /* disable L2 cache first*/ + +#define CONFIG_MX6_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_UART_BASE_ADDR UART4_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_I2C + +/* Enable below configure when supporting nand */ + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ + +#define CONFIG_CMD_SATA +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p1 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; " \ + "mmc dev 3; " \ + "mmc read ${loadaddr} 0x800 0x1800; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX6Q SABREAUTO U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10010000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_MIIBASE -1 +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_MXC_FEC +#define CONFIG_FEC0_PHY_ADDR 0 +#define CONFIG_ETH_PRIME +#define CONFIG_RMII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_IPADDR 192.168.1.103 +#define CONFIG_SERVERIP 192.168.1.101 +#define CONFIG_NETMASK 255.255.255.0 + +/* + * I2C Configs + */ +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0x1f +#endif + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_USDHC_NUM 4 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 2 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether SD1, 2, 3, or 4 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + /* SD3 and SD4 are 8 bit */ + #define CONFIG_MMC_8BIT_PORTS 0xC + /* Setup target delay in DDR mode for each SD port */ + #define CONFIG_GET_DDR_TARGET_DELAY +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_SATA */ + +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SATA) + #define CONFIG_ENV_IS_IN_SATA 1 + #define CONFIG_SATA_ENV_DEV 0 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_SPLASH_SCREEN + /* + * Framebuffer and LCD + */ + #define CONFIG_LCD + #define CONFIG_IPU_V3H + #define CONFIG_VIDEO_MX5 + #define CONFIG_IPU_CLKRATE 260000000 + #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define LCD_BPP LCD_COLOR16 + #define CONFIG_CMD_BMP + #define CONFIG_BMP_8BPP + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SPLASH_SCREEN_ALIGN + #define CONFIG_SYS_WHITE_ON_BLACK +#endif +#endif /* __CONFIG_H */ |