diff options
| -rw-r--r-- | CHANGELOG | 7 | ||||
| -rw-r--r-- | MAINTAINERS | 1 | ||||
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | README | 4 | ||||
| -rw-r--r-- | board/csb226/csb226.c | 81 | ||||
| -rw-r--r-- | board/csb226/flash.c | 149 | ||||
| -rw-r--r-- | cpu/xscale/start.S | 168 | ||||
| -rw-r--r-- | include/commproc.h | 8 | ||||
| -rw-r--r-- | include/configs/FPS860L.h | 331 | ||||
| -rw-r--r-- | include/configs/csb226.h | 11 | ||||
| -rw-r--r-- | lib_arm/armlinux.c | 23 |
11 files changed, 626 insertions, 158 deletions
@@ -2,6 +2,13 @@ Changes since for U-Boot 0.1.0: ====================================================================== +* Patch by Robert Schwebel, 04 Nov 2002: + - use watchdog to reset PXA250 systems + - added progress callbacks to (some of the) ARM code + - update for Cogent CSB226 board + +* Add support for FPS860 board + * Patch by Guillaume Alexandre,, 04 Nov 2002: Improve PCI access on 32-bits Compact PCI bus diff --git a/MAINTAINERS b/MAINTAINERS index de37086..1bf1810 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -49,6 +49,7 @@ Wolfgang Denk <wd@denx.de> AMX860 MPC860 ETX094 MPC850 FPS850L MPC850 + FPS860L MPC860 ICU862 MPC862 IP860 MPC860 IVML24 MPC860 @@ -322,6 +322,7 @@ SXNI855T_config: unconfig xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _LCD,,$(subst _FEC,,$(subst _config,,$1))))) FPS850L_config \ +FPS860L_config \ TQM823L_config \ TQM823L_66MHz_config \ TQM823L_80MHz_config \ @@ -320,7 +320,7 @@ The following options need to be configured: CONFIG_GENIETV, CONFIG_PM826, CONFIG_ppmc8260, CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto, CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, - CONFIG_EBONY, CONFIG_sacsng + CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L ARM based boards: ----------------- @@ -1665,7 +1665,7 @@ configurations; the following names are supported: FADS860T_config SXNI855T_config rsdproto_config FPS850L_config Sandpoint8240_config sbc8260_config GENIETV_config TQM823L_config PIP405_config - GEN860T_config EBONY_config + GEN860T_config EBONY_config FPS860L_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c index 1ed4034..0d99aa8 100644 --- a/board/csb226/csb226.c +++ b/board/csb226/csb226.c @@ -24,14 +24,25 @@ */ #include <common.h> +#include <asm/arch/pxa-regs.h> -/* ------------------------------------------------------------------------- */ - +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif /* * Miscelaneous platform dependent initialisations */ + +/** + * board_init: - setup some data structures + * + * @return: 0 in case of success + */ + int board_init (void) { DECLARE_GLOBAL_DATA_PTR; @@ -48,6 +59,13 @@ int board_init (void) return 0; } + +/** + * dram_init: - setup dynamic RAM + * + * @return: 0 in case of success + */ + int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; @@ -57,3 +75,62 @@ int dram_init (void) return 0; } + + +/** + * csb226_set_led: - switch LEDs on or off + * + * @param led: LED to switch (0,1,2) + * @param state: switch on (1) or off (0) + */ + +void csb226_set_led(int led, int state) +{ + switch(led) { + + case 0: if (state==1) { + GPCR0 |= CSB226_USER_LED0; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED0; + } + break; + + case 1: if (state==1) { + GPCR0 |= CSB226_USER_LED1; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED1; + } + break; + + case 2: if (state==1) { + GPCR0 |= CSB226_USER_LED2; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED2; + } + break; + } + + return; +} + + +/** + * show_boot_progress: - indicate state of the boot process + * + * @param status: Status number - see README for details. + * + * The CSB226 does only have 3 LEDs, so we switch them on at the most + * important states (1, 5, 15). + */ + +void show_boot_progress (int status) +{ + switch(status) { + case 1: csb226_set_led(0,1); break; + case 5: csb226_set_led(1,1); break; + case 15: csb226_set_led(2,1); break; + } + + return; +} + diff --git a/board/csb226/flash.c b/board/csb226/flash.c index 0b95648..0b4e2f6 100644 --- a/board/csb226/flash.c +++ b/board/csb226/flash.c @@ -6,6 +6,9 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> + * * See file CREDITS for list of people who contributed to this * project. * @@ -26,6 +29,7 @@ */ #include <common.h> +#include <asm/arch/pxa-regs.h> #define FLASH_BANK_SIZE 0x02000000 #define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ @@ -33,7 +37,10 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -/*----------------------------------------------------------------------- +/** + * flash_init: - initialize data structures for flash chips + * + * @return: size of the flash */ ulong flash_init(void) @@ -41,8 +48,7 @@ ulong flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | @@ -51,8 +57,7 @@ ulong flash_init(void) flash_info[i].sector_count = CFG_MAX_FLASH_SECT; memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) - { + switch (i) { case 0: flashbase = PHYS_FLASH_1; break; @@ -60,15 +65,13 @@ ulong flash_init(void) panic("configured to many flash banks!\n"); break; } - for (j = 0; j < flash_info[i].sector_count; j++) - { + for (j = 0; j < flash_info[i].sector_count; j++) { flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; } size += flash_info[i].size; } - /* Protect monitor and environment sectors - */ + /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + _armboot_end_data - _armboot_start, @@ -82,16 +85,21 @@ ulong flash_init(void) return size; } -/*----------------------------------------------------------------------- + +/** + * flash_print_info: - print information about the flash situation + * + * @param info: */ + void flash_print_info (flash_info_t *info) { int i, j; - for (j=0; j<CFG_MAX_FLASH_BANKS; j++) - { - switch (info->flash_id & FLASH_VENDMASK) - { + for (j=0; j<CFG_MAX_FLASH_BANKS; j++) { + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): printf("Intel: "); break; @@ -100,38 +108,35 @@ void flash_print_info (flash_info_t *info) break; } - switch (info->flash_id & FLASH_TYPEMASK) - { + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): printf("28F128J3 (128Mbit)\n"); break; default: printf("Unknown Chip Type\n"); - goto Done; - break; + return; } printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) - { - if ((i % 5) == 0) - { - printf ("\n "); - } + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) printf ("\n "); + printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); } printf ("\n"); info++; } - -Done: } -/*----------------------------------------------------------------------- + +/** + * flash_erase: - erase flash sectors + * */ int flash_erase (flash_info_t *info, int s_first, int s_last) @@ -146,19 +151,15 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) return ERR_INVAL; } - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) return ERR_UNKNOWN_FLASH_VENDOR; - } prot = 0; for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; + if (info->protect[sect]) prot++; } - } - if (prot) - return ERR_PROTECTED; + + if (prot) return ERR_PROTECTED; /* * Disable interrupts which might cause a timeout @@ -178,57 +179,63 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) reset_timer_masked(); if (info->protect[sect] == 0) { /* not protected */ - /* vushort *addr = (vushort *)(info->start[sect]); */ - ushort *addr = (ushort *)(info->start[sect]); + u32 * volatile addr = (u32 * volatile)(info->start[sect]); + + /* erase sector: */ + /* The strata flashs are aligned side by side on */ + /* the data bus, so we have to write the commands */ + /* to both chips here: */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ - while ((*addr & 0x80) != 0x80) { + while ((*addr & 0x00800080) != 0x00800080) { if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ + *addr = 0x00B000B0; /* suspend erase*/ + *addr = 0x00FF00FF; /* read mode */ rc = ERR_TIMOUT; goto outahere; } } - /* clear status register command */ - *addr = 0x50; - /* reset to read mode */ - *addr = 0xFF; + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + } + printf("ok.\n"); } - if (ctrlc()) - printf("User Interrupt!\n"); + + if (ctrlc()) printf("User Interrupt!\n"); outahere: /* allow flash to settle - wait 10 ms */ udelay_masked(10000); - if (flag) - enable_interrupts(); + if (flag) enable_interrupts(); return rc; } -/*----------------------------------------------------------------------- - * Copy memory to flash + +/** + * write_word: - copy memory to flash + * + * @param info: + * @param dest: + * @param data: + * @return: */ static int write_word (flash_info_t *info, ulong dest, ushort data) { - /* vushort *addr = (vushort *)dest, val; */ ushort *addr = (ushort *)dest, val; int rc = ERR_OK; int flag; - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) return ERR_NOT_ERASED; /* * Disable interrupts which might cause a timeout @@ -252,12 +259,10 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) reset_timer_masked(); /* wait while polling the status register */ - while(((val = *addr) & 0x80) != 0x80) - { + while(((val = *addr) & 0x80) != 0x80) { if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0xB0; + *addr = 0xB0; /* suspend program command */ goto outahere; } } @@ -285,17 +290,23 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) } outahere: - /* read array command */ - *addr = 0xFF; - if (flag) - enable_interrupts(); + *addr = 0xFF; /* read array command */ + if (flag) enable_interrupts(); return rc; } -/*----------------------------------------------------------------------- - * Copy memory to flash. + +/** + * write_buf: - Copy memory to flash. + * + * @param info: + * @param src: source of copy transaction + * @param addr: where to copy to + * @param cnt: number of bytes to copy + * + * @return error code */ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) @@ -344,9 +355,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) cnt -= 2; } - if (cnt == 0) { - return ERR_OK; - } + if (cnt == 0) return ERR_OK; /* * handle unaligned tail bytes diff --git a/cpu/xscale/start.S b/cpu/xscale/start.S index 6cc7c43..cc24c30 100644 --- a/cpu/xscale/start.S +++ b/cpu/xscale/start.S @@ -17,7 +17,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -32,7 +32,7 @@ #include <version.h> .globl _start -_start: b reset +_start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -41,7 +41,7 @@ _start: b reset ldr pc, _irq ldr pc, _fiq -_undefined_instruction: .word undefined_instruction +_undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort _data_abort: .word data_abort @@ -112,20 +112,20 @@ FIQ_STACK_START: /****************************************************************************/ -/* */ -/* the actual reset code */ -/* */ +/* */ +/* the actual reset code */ +/* */ /****************************************************************************/ reset: - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ + mrs r0,cpsr /* set the cpu to SVC32 mode */ + bic r0,r0,#0x1f /* (superviser mode, M=10011) */ orr r0,r0,#0x13 msr cpsr,r0 - bl cpu_init_crit /* we do sys-critical inits */ + bl cpu_init_crit /* we do sys-critical inits */ -relocate: /* relocate U-Boot to RAM */ +relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r2, _armboot_start ldr r3, _armboot_end @@ -139,41 +139,47 @@ copy_loop: cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop - /* Set up the stack */ + /* Set up the stack */ ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - /* FIXME: bdinfo should be here */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + /* FIXME: bdinfo should be here */ sub sp, r0, #12 /* leave 3 words for abort-stack */ ldr pc, _start_armboot -_start_armboot: .word start_armboot +_start_armboot: .word start_armboot /****************************************************************************/ -/* */ -/* CPU_init_critical registers */ -/* */ -/* - setup important registers */ -/* - setup memory timing */ -/* */ +/* */ +/* CPU_init_critical registers */ +/* */ +/* - setup important registers */ +/* - setup memory timing */ +/* */ /****************************************************************************/ - /* Interrupt-Controller base address */ + /* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 #define ICMR 0x04 /* Reset-Controller */ -RST_BASE: .word 0x40f00030 +RST_BASE: .word 0x40f00030 #define RCSR 0x00 + /* Operating System Timer */ +OSTIMER_BASE: .word 0x40a00000 +#define OSMR3 0x0C +#define OSCR 0x10 +#define OWER 0x18 +#define OIER 0x1C - /* Clock Manager Registers */ -CC_BASE: .word 0x41300000 -#define CCCR 0x00 -cpuspeed: .word CFG_CPUSPEED + /* Clock Manager Registers */ +CC_BASE: .word 0x41300000 +#define CCCR 0x00 +cpuspeed: .word CFG_CPUSPEED - /* RS: ??? */ + /* RS: ??? */ .macro CPWAIT mrc p15,0,r0,c2,c0,0 mov r0,r0 @@ -183,7 +189,7 @@ cpuspeed: .word CFG_CPUSPEED cpu_init_crit: - /* mask all IRQs */ + /* mask all IRQs */ ldr r0, IC_BASE mov r1, #0x00 str r1, [r0, #ICMR] @@ -204,20 +210,20 @@ cpu_init_crit: /* Memory interfaces are working. Disable MMU and enable I-cache. */ - ldr r0, =0x2001 /* enable access to all coproc. */ + ldr r0, =0x2001 /* enable access to all coproc. */ mcr p15, 0, r0, c15, c1, 0 CPWAIT mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ CPWAIT - mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ + mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ CPWAIT mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ CPWAIT - /* Enable the Icache */ + /* Enable the Icache */ /* mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x1800 @@ -228,12 +234,12 @@ cpu_init_crit: /****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ +/* */ +/* Interrupt handling */ +/* */ /****************************************************************************/ -/* IRQ stack frame */ +/* IRQ stack frame */ #define S_FRAME_SIZE 72 @@ -259,38 +265,38 @@ cpu_init_crit: #define MODE_SVC 0x13 - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ + /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC ldr r2, _armboot_end add r2, r2, #CONFIG_STACKSIZE sub r2, r2, #8 - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ + ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ + add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ add r5, sp, #S_SP mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ + stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ mov r0, sp .endm - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ + /* use irq_save_user_regs / irq_restore_user_regs for */ + /* IRQ/FIQ handling */ .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ /* Calling SP, LR */ + str lr, [r8, #0] /* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] /* Save CPSR */ + str r0, [r8, #8] /* Save OLD_R0 */ mov r0, sp .endm @@ -309,7 +315,7 @@ cpu_init_crit: str lr, [r13] @ save caller lr / spsr mrs lr, spsr - str lr, [r13, #4] + str lr, [r13, #4] mov r13, #MODE_SVC @ prepare SVC-Mode msr spsr_c, r13 @@ -327,40 +333,40 @@ cpu_init_crit: /****************************************************************************/ -/* */ -/* exception handlers */ -/* */ +/* */ +/* exception handlers */ +/* */ /****************************************************************************/ - .align 5 + .align 5 undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -368,14 +374,14 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 fiq: get_fiq_stack irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ + bl do_fiq /* effiction fiq_save_user_regs */ irq_restore_user_regs #else @@ -384,28 +390,40 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif -/* - * FIXME How do we reset??? Watchdog timeout?? - */ +/************************************************************************/ +/* */ +/* Reset function: the PXA250 has no reset function, so we have to */ +/* perform a watchdog timeout to cause a reset. */ +/* */ +/************************************************************************/ .align 5 .globl reset_cpu reset_cpu: - /* - ldr r0, RST_BASE - mov r1, #0x0 @ set bit 3-0 ... - str r1, [r0, #RCSR] @ ... to clear in RCSR - mov r1, #0x1 - str r1, [r0, #RCSR] @ and perform reset - */ - b reset_cpu @ silly, but repeat endlessly + /* We set OWE:WME (watchdog enable) and wait until timeout happens */ + + ldr r0, OSTIMER_BASE + ldr r1, [r0, #OWER] + orr r1, r1, #0x0001 /* bit0: WME */ + str r1, [r0, #OWER] + + /* OS timer does only wrap every 1165 seconds, so we have to set */ + /* the match register as well. */ + + ldr r1, [r0, #OSCR] /* read OS timer */ + add r1, r1, #0x800 /* let OSMR3 match after */ + add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ + str r1, [r0, #OSMR3] + +reset_endless: + b reset_endless diff --git a/include/commproc.h b/include/commproc.h index 410b96d..fb6ec00 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -709,11 +709,11 @@ typedef struct scc_enet { #endif /* CONFIG_FADS860T */ -/*** FPS850L *********************************************************/ +/*** FPS850L, FPS860L ************************************************/ -#ifdef CONFIG_FPS850L +#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) /* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. + * to configure the pins for SCC2 use. */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 @@ -732,7 +732,7 @@ typedef struct scc_enet { */ #define SICR_ENET_MASK ((uint)0x0000ff00) #define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_FPS850L */ +#endif /* CONFIG_FPS850L, CONFIG_FPS860L */ /*** GEN860T **********************************************************/ #if defined(CONFIG_GEN860T) diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h new file mode 100644 index 0000000..d2ac9d2 --- /dev/null +++ b/include/configs/FPS860L.h @@ -0,0 +1,331 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index d38e9db..b6c7302 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -74,6 +74,7 @@ #define CONFIG_IPADDR 192.168.1.56 #define CONFIG_SERVERIP 192.168.1.2 #define CONFIG_BOOTCOMMAND "bootm 0x40000" +#define CONFIG_SHOW_BOOT_PROGRESS #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ @@ -156,7 +157,7 @@ #define CFG_GPCR0_VAL 0x08022080 #define CFG_GPCR1_VAL 0x00000000 #define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0xCD82A858 +#define CFG_GPDR0_VAL 0xCD82A878 #define CFG_GPDR1_VAL 0xFCFFAB80 #define CFG_GPDR2_VAL 0x0001FFFF #define CFG_GAFR0_L_VAL 0x80000000 @@ -191,10 +192,10 @@ #define CFG_MCIO0_VAL 0x00000000 #define CFG_MCIO1_VAL 0x00000000 -/* -#define _LED 0x08000010 -#define LED_BLANK (0x08000040) -*/ +#define CSB226_USER_LED0 0x00000008 +#define CSB226_USER_LED1 0x00000010 +#define CSB226_USER_LED2 0x00000020 + /* * FLASH and environment organization diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index 33f86e9..2fb8db8 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -56,6 +56,13 @@ static void setup_videolfb_tag(gd_t *gd); static struct tag *params; #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include <status_led.h> +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + extern image_header_t header; /* from cmd_bootm.c */ @@ -80,6 +87,8 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { + SHOW_BOOT_PROGRESS (9); + addr = simple_strtoul(argv[2], NULL, 16); printf ("## Loading Ramdisk Image at %08lx ...\n", addr); @@ -89,6 +98,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-10); do_reset (cmdtp, flag, argc, argv); } @@ -100,9 +110,12 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (char *)data, len) != checksum) { printf ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-11); do_reset (cmdtp, flag, argc, argv); } + SHOW_BOOT_PROGRESS (10); + print_image_hdr (hdr); data = addr + sizeof(image_header_t); @@ -115,15 +128,19 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (char *)data, len); if (csum != ntohl(hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } + SHOW_BOOT_PROGRESS (11); + if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_ARM) || (hdr->ih_type != IH_TYPE_RAMDISK) ) { printf ("No Linux ARM Ramdisk Image\n"); + SHOW_BOOT_PROGRESS (-13); do_reset (cmdtp, flag, argc, argv); } @@ -134,6 +151,8 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl(len_ptr[0]) % 4; int i; + SHOW_BOOT_PROGRESS (13); + /* skip kernel length and terminator */ data = (ulong)(&len_ptr[2]); /* skip any additional image length fields */ @@ -151,6 +170,8 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ + SHOW_BOOT_PROGRESS (14); + data = 0; } @@ -168,6 +189,8 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } + SHOW_BOOT_PROGRESS (15); + #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", (ulong)theKernel); |