diff options
| -rw-r--r-- | CHANGELOG | 3 | ||||
| -rw-r--r-- | MAKEALL | 29 | ||||
| -rw-r--r-- | Makefile | 3 | ||||
| -rw-r--r-- | board/adderII/Makefile | 40 | ||||
| -rw-r--r-- | board/adderII/adderII.c | 189 | ||||
| -rw-r--r-- | board/adderII/adderII.h | 45 | ||||
| -rw-r--r-- | board/adderII/config.mk | 29 | ||||
| -rw-r--r-- | board/adderII/flash.c | 501 | ||||
| -rw-r--r-- | board/adderII/u-boot.lds | 147 | ||||
| -rw-r--r-- | board/tqm8xx/Makefile | 2 | ||||
| -rw-r--r-- | cpu/mpc8xx/cpu.c | 1 | ||||
| -rw-r--r-- | cpu/mpc8xx/cpu_init.c | 3 | ||||
| -rw-r--r-- | include/configs/AdderII.h | 226 | ||||
| -rw-r--r-- | lib_ppc/board.c | 16 |
14 files changed, 1210 insertions, 24 deletions
@@ -2,6 +2,9 @@ Changes for U-Boot 0.4.7: ====================================================================== +* Patch by Raghu Krishnaprasad, 7 Aug 2003: + add support for Adder II MPC852T module + * Patch by George G. Davis, 19 Aug 2003: fix TI Innovator/OMAP1510 pin configs @@ -31,20 +31,21 @@ LIST_5xxx=" \ ######################################################################### LIST_8xx=" \ - ADS860 AMX860 c2mon CCM \ - cogent_mpc8xx ESTEEM192E ETX094 ELPT860 \ - FADS823 FADS850SAR FADS860T FLAGADM \ - FPS850L GEN860T GEN860T_SC GENIETV \ - GTH hermes IAD210 ICU862_100MHz \ - IP860 IVML24 IVML24_128 IVML24_256 \ - IVMS8 IVMS8_128 IVMS8_256 KUP4K \ - LANTEC lwmon MBX MBX860T \ - MHPC MPC86xADS MVS1 NETVIA \ - NETVIA_V2 NX823 pcu_e R360MPI \ - RBC823 rmu RPXClassic RPXlite \ - RRvision SM850 SPD823TS svm_sc8xx \ - SXNI855T TOP860 TQM823L TQM823L_LCD \ - TQM850L TQM855L TQM860L v37 \ + AdderII ADS860 AMX860 c2mon \ + CCM cogent_mpc8xx ESTEEM192E ETX094 \ + ELPT860 FADS823 FADS850SAR FADS860T \ + FLAGADM FPS850L GEN860T GEN860T_SC \ + GENIETV GTH hermes IAD210 \ + ICU862_100MHz IP860 IVML24 IVML24_128 \ + IVML24_256 IVMS8 IVMS8_128 IVMS8_256 \ + KUP4K LANTEC lwmon MBX \ + MBX860T MHPC MPC86xADS MVS1 \ + NETVIA NETVIA_V2 NX823 pcu_e \ + R360MPI RBC823 rmu RPXClassic \ + RPXlite RRvision SM850 SPD823TS \ + svm_sc8xx SXNI855T TOP860 TQM823L \ + TQM823L_LCD TQM850L TQM855L TQM860L \ + v37 \ " ######################################################################### @@ -210,6 +210,9 @@ IceCube_5100_config: unconfig ## MPC8xx Systems ######################################################################### +AdderII_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx adderII + ADS860_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx fads diff --git a/board/adderII/Makefile b/board/adderII/Makefile new file mode 100644 index 0000000..e5d8446 --- /dev/null +++ b/board/adderII/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/adderII/adderII.c b/board/adderII/adderII.c new file mode 100644 index 0000000..d398e54 --- /dev/null +++ b/board/adderII/adderII.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <mpc8xx.h> + +/* + * Check Board Identity: + */ + +int checkboard( void ) +{ + puts("Board: "); + puts("AdderII(MPC852T)\n" ); + + return 0; +} + +#if defined( CONFIG_SDRAM_50MHZ ) + +/****************************************************************************** +** for chip Samsung K4S643232F - T70 +** this table is for 32-50MHz operation +*******************************************************************************/ + +#define SDRAM_MPTPRVALUE 0x0200 + +#define SDRAM_MAMRVALUE0 0x00802114 /* refresh at 32MHz */ +#define SDRAM_MAMRVALUE1 0x00802118 + +#define SDRAM_OR1VALUE 0xff800e00 +#define SDRAM_BR1VALUE 0x00000081 + +#define SDRAM_MARVALUE 94 + +#define SDRAM_MCRVALUE0 0x80808105 +#define SDRAM_MCRVALUE1 0x80808130 + +const uint sdram_table[] = { + + /* single read (offset 0x00 in upm ram) */ + 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, + 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, + + /* burst read (offset 0x08 in upm ram) */ + 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, + 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, + 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, + + /* single write (offset 0x18 in upm ram) */ + 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, + 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* burst write (offset 0x20 in upm ram) */ + 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* refresh (offset 0x30 in upm ram) */ + 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* exception (offset 0x3C in upm ram) */ + 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04, +}; + +#else +#error SDRAM not correctly configured +#endif + +int _initsdram (uint base, uint noMbytes) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + if (noMbytes != 8) { + return -1; + } + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + memctl->memc_mptpr = SDRAM_MPTPRVALUE; + + /* Configure the refresh (mostly). This needs to be + * based upon processor clock speed and optimized to provide + * the highest level of performance. For multiple banks, + * this time has to be divided by the number of banks. + * Although it is not clear anywhere, it appears the + * refresh steps through the chip selects for this UPM + * on each refresh cycle. + * We have to be careful changing + * UPM registers after we ask it to run these commands. + */ + + memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24)); + memctl->memc_mar = 0x0; + udelay (200); + + /* Now run the precharge/nop/mrs commands. + */ + memctl->memc_mcr = 0x80002115; + udelay (200); + + /* Run 8 refresh cycles */ + memctl->memc_mcr = 0x80002380; + udelay (200); + + memctl->memc_mar = 0x88; + udelay (200); + + memctl->memc_mcr = 0x80002116; + udelay (200); + + memctl->memc_or1 = SDRAM_OR1VALUE; + memctl->memc_br1 = SDRAM_BR1VALUE | base; + + return 0; +} + +void _sdramdisable( void ) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_br1 = 0x00000000; + + /* maybe we should turn off upma here or something */ +} + +int initsdram (uint base, uint * noMbytes) +{ + uint m = 8; + + *noMbytes = m; + + if (!_initsdram (base, m)) { + return 0; + } else { + _sdramdisable (); + return -1; + } +} + +long int initdram (int board_type) +{ + /* AdderII: has 8MB SDRAM */ + uint sdramsz; + uint m = 0; + + if (!initsdram (0x00000000, &sdramsz)) { + m += sdramsz; + } else { + return -1; + } + return (m << 20); +} + +int testdram (void) +{ + /* TODO: XXX XXX XXX not an actual SDRAM test */ + printf ("Test: 8MB SDRAM\n"); + + return (0); +} diff --git a/board/adderII/adderII.h b/board/adderII/adderII.h new file mode 100644 index 0000000..24e2d93 --- /dev/null +++ b/board/adderII/adderII.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by FADS Monitor: + * + * Start Address Length + * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- + * | MON8xx code | 0xFE00_0100 Reset Vector + * +-----------------------+ 0xFE0?_???? + * | (unused) | + * +-----------------------+ + * | | + * +-----------------------+ + * | | + * +-----------------------+ + * | | + * +-----------------------+ + * | | + * +=======================+ + * | | + * | ... | + *****************************************************************************/ + + diff --git a/board/adderII/config.mk b/board/adderII/config.mk new file mode 100644 index 0000000..c23d942 --- /dev/null +++ b/board/adderII/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AdderII board ( Analogue-Micro ) +# + +TEXT_BASE = 0xFE000000 + diff --git a/board/adderII/flash.c b/board/adderII/flash.c new file mode 100644 index 0000000..77ab4f1 --- /dev/null +++ b/board/adderII/flash.c @@ -0,0 +1,501 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/****************************************************************************** +** Notes: AM29LV320DB - 90EI ( 32 Mbit device ) +** Sectors - Eight 8 Kb sector +** - Sixty three 64 Kb sector +** Bottom boot sector +******************************************************************************/ +#include <common.h> +#include <mpc8xx.h> + + +/****************************************************************************** +** Defines +******************************************************************************/ +#ifdef CONFIG_ADDERII + +#define ADDR0 0x0555 +#define ADDR1 0x02AA +#define FLASH_WORD_SIZE unsigned short + +#endif + +#if defined( CFG_ENV_IS_IN_FLASH ) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR ( CFG_FLASH_BASE + CFG_ENV_OFFSET ) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/****************************************************************************** +** Global Parameters +******************************************************************************/ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/****************************************************************************** +** Function Prototypes +******************************************************************************/ +static ulong flash_get_size( vu_long *addr, flash_info_t *info ); + +static int write_word( flash_info_t *info, ulong dest, ulong data ); + +static void flash_get_offsets( ulong base, flash_info_t *info ); + +int wait_for_DQ7( flash_info_t *info, int sect ); + +/****************************************************************************** +** Function : flash_init +** Param : void +** Notes : Initializes the Flash Chip +******************************************************************************/ +ulong flash_init (void) +{ + ulong size_b0 = -1; + int i; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* Set Flash to unknown */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Get the Flash Bank Size */ + + size_b0 = flash_get_size ((vu_long *) (CFG_FLASH_BASE), + &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## UNKNOWN Flash on Bank 0 - Size = 0x%08lx = %ldMB\n", + size_b0, size_b0 >> 20); + } + + /* Remap Flash according to size detected */ + memctl->memc_or0 = 0xFF800774; + memctl->memc_br0 = CFG_BR0_PRELIM; + + /* Setup Flash Sector Offsets */ + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* Monitor Protection ON - default */ + +#if ( CFG_MONITOR_BASE >= CFG_FLASH_BASE ) + flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, + (CFG_MONITOR_BASE + monitor_flash_len - 1), + &flash_info[0]); +#endif + + /* Protect Environment Variables */ +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, + (CFG_ENV_ADDR + CFG_ENV_SIZE - 1), &flash_info[0]); +#endif + + return size_b0; +} + +/****************************************************************************** +** Function : flash_get_offsets +** Param : ulong base, flash_into_t *info +** Notes : +******************************************************************************/ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + return; +} + + +/****************************************************************************** +** Function : flash_print_info +** Param : flash_info_t +** Notes : +******************************************************************************/ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Missing or unknown flash type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_BM: + printf ("BRIGHT MICRO "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + + } + + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, + info->sector_count); + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/****************************************************************************** +** Function : flash_get_size +** Param : vu_long *addr, flash_info_t *info +** Notes : +******************************************************************************/ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE manu_id, dev_id; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write Auto Select Command and read Manufacturer's ID and Dev ID */ + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090; + + manu_id = addr2[0]; + + switch (manu_id) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Read Device Id */ + dev_id = addr2[1]; + + switch (dev_id) { + case (FLASH_WORD_SIZE) AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; /* 8 - boot sec + 63 normal */ + info->size = 0x400000; /* 4MByte */ + break; + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + /* Set up sector start Addresses */ + + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block + ** Eight 8 Kb Boot sectors + ** Sixty Three 64Kb sectors + */ + for (i = 0; i < 8; i++) { + info->start[i] = base + (i * 0x00002000); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } + } + + /* Reset To read mode */ + + if (info->flash_id != FLASH_UNKNOWN) { + addr = (ulong *) info->start[0]; + *addr = 0xF0F0F0F0; + } + return (info->size); +} + +/******************************************************************************* +** Function : flash_erase +** Param : flash_info_t *info, int s_first, int s_last +** Notes : +******************************************************************************/ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay (1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { + putc ('.'); + last = now; + } + } + return 0; +} + + +/****************************************************************************** +** Function : write_buff +** Param : flash_info_t *info, uchar *src, ulong addr, ulong cnt +** Notes : +******************************************************************************/ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + /* get lower word aligned address */ + wp = (addr & ~3); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + + +/****************************************************************************** +** Function : write_word +** Param : flash_info_t *info, ulong dest, ulong data +** Notes : +******************************************************************************/ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/adderII/u-boot.lds b/board/adderII/u-boot.lds new file mode 100644 index 0000000..666e843 --- /dev/null +++ b/board/adderII/u-boot.lds @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) +*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + . = ALIGN(256 * 1024); + .ppcenv : + { + common/environment.o (.ppcenv) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/tqm8xx/Makefile b/board/tqm8xx/Makefile index a01fd86..2ff9b4d 100644 --- a/board/tqm8xx/Makefile +++ b/board/tqm8xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index b95e06f..c4b3938 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -98,6 +98,7 @@ static int check_CPU (long clock, uint pvr, uint immr) case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; case 0x05010000: suf = "D3"; m = 1; break; case 0x05020000: suf = "D4"; m = 1; break; + case 0x08000003: suf = ""; m = 1; break; /* this value is not documented anywhere */ case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; #endif diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 80f763d..dbf5db0 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -132,7 +132,8 @@ void cpu_init_f (volatile immap_t * immr) * I owe him a free beer. - wd] */ -#if defined(CONFIG_GTH) || \ +#if defined(CONFIG_ADDERII) || \ + defined(CONFIG_GTH) || \ defined(CONFIG_HERMES) || \ defined(CONFIG_ICU862) || \ defined(CONFIG_IP860) || \ diff --git a/include/configs/AdderII.h b/include/configs/AdderII.h new file mode 100644 index 0000000..c2cff23 --- /dev/null +++ b/include/configs/AdderII.h @@ -0,0 +1,226 @@ +/****************************************************************************** +* A collection of structures, addresses, and values associated with +* the Motorola 850T AdderIIF board. Copied from the FADS stuff. +* Magnus Damm added defines for 8xxrom and extended bd_info. +* Helmut Buchsbaum added bitvalues for BCSRx +* +* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) +******************************************************************************* +* 2003-JUL: The AdderII is using the following physical memorymap: +******************************************************************************* +* FA200000 -> FA20FFFF : IMAP internal in the cpu +* FE000000 -> FE400000 : flash connected to CS0, setup by 8xxrom +* 00000000 -> 00800000 : sdram setup by 8xxrom +*******************************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <mpc8xx_irq.h> + +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_ADDERII 1 + +/* CPU Clock speed */ +#define MPC8XX_FACT 12 /* Multilpy by 12 */ +#define MPC8XX_XIN 4000000 /* 4MHz */ +#define MPC8XX_HZ ( MPC8XX_FACT * MPC8XX_XIN ) + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ +#define CONFIG_SDRAM_50MHZ 1 + + +/* Default Serial Console, baudrate */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_LOADS_ECHO 1 + +/* FEC Ethernet controller configurations */ +#define CONFIG_FEC_ETH 1 +#define CONFIG_NET_MULTI 1 +#define FEC_ENET 1 + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL3 /* FEC interrupt */ + +/* Older kernels need clock in MHz newer in Hz */ +#define CONFIG_CLOCKS_IN_MHZ 1 + +/* Monitor Functions */ +#define CONFIG_COMMANDS ( CFG_CMD_FLASH | \ + CFG_CMD_MEMORY| \ + CFG_CMD_NET | \ + CFG_CMD_ENV | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* Configuration Settings */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ + +#if ( CONFIG_COMMANDS & CFG_CMD_KGDB ) +#define CFG_CBSIZE 1024 /* Console I/P buffer size */ +#else +#define CFG_CBSIZE 256 +#endif + +#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 ) + /* Print buffer size */ + +#define CFG_MAXARGS 16 /* Max number of cmd args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot args buffer size */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MEMTEST_START 0x00100000 /* Mem test works on */ +#define CFG_MEMTEST_END 0x00800000 /* 1 ... 8MB in SDRAM */ + +#define CFG_LOAD_ADDR 0x00100000 +#define CFG_HZ 1000 + +/****************************************************************************** +** Low level configuration settings. +** ( adderss mappings, register init values, etc. ) +** You should know what you are doing if you make changes here. +******************************************************************************/ +/* Start address for the final memory configuration set up by startup code +** Please note that CFG_SDRAM_BASE must start at 0 +*/ + +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE (( uint ) ( 4 * 1024 * 1024 )) /* 4MB */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN ( 256 << 10 ) /* 256 KByte */ +#define CFG_MALLOC_LEN ( 384 << 10 ) /* 384 KByte SDRAM rsvd */ + /* malloc() usage */ +/** +** For booting Linux, the board info and command line data +** have to be in the first 8 MB of memory, since this is +** the maximum mapped by the Linux kernel during initialization. +**/ +#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */ + +/****************************************************************************** +** Flash Organization +******************************************************************************/ + +#define CFG_MAX_FLASH_BANKS 1 /* Max no of flash mem banks */ +#define CFG_MAX_FLASH_SECT 71 /* Max no of sec on 1 chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Erase flash timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Write flash timeout (ms) */ + +/****************************************************************************** +** U-BOOT Environment variables in Flash +******************************************************************************/ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00040000 +#define CFG_ENV_SIZE 0x10000 /* 64KBytes env space */ +#define CFG_ENV_SECT_SIZE 0x10000 + +/****************************************************************************** +** Cache Configuration +******************************************************************************/ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if ( CONFIG_COMMANDS & CFG_CMD_KGDB ) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/****************************************************************************** +** Internal memory mapped register +******************************************************************************/ +#define CFG_IMMR 0xFA200000 +#define CFG_IMMR_SIZE (( uint) ( 62 * 1024 )) /* 64 KByte res */ + +/* Definitions for initial stack pointer and data area ( in DPRAM ) */ + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* end of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 +#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE ) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + + +/* SIU Module Configuration Register */ +#define CFG_SIUMCR ( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 ) + +/****************************************************************************** +** SYPCR - System protection and control +** SYPCR - can be written only once after reset +******************************************************************************/ +#if defined( CONFIG_WATCHDOG ) +#define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ + SYPCR_SWP ) +#else +#define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWP ) +#endif + +/* TBSCR - Time Base Status and Control Register */ +#define CFG_TBSCR ( TBSCR_REFA | TBSCR_REFB | TBSCR_TBE ) + +/* PISCR - Periodic Interrupt Status and Control */ +#define CFG_PISCR ( PISCR_PS | PISCR_PITF ) + +/* PLPRCR - PLL, Low-Power, and Reset Control Register */ +#define CFG_PLPRCR ((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST ) + +/* SCCR - System Clock and reset Control Register */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR ( SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000| SCCR_DFNH000 | \ + SCCR_DFLCD000 | SCCR_DFALCD00 ) +#define CFG_DER 0 + +/****************************************************************************** +** Because of the way the 860 starts up and assigns CS0 the +** entire address space, we have to set the memory controller +** differently. Normally, you write the option register +** first, and then enable the chip select by writing the +** base register. For CS0, you must write the base register +** first, followed by the option register. +******************************************************************************/ +/** + ** Memory Controller Definitions + ** BR0/1/2... and OR0/1/2... +*/ +/* For AdderII BR0 FLASH */ + +#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +/* Flash Timings: ACS = 11, TRLX = 1, CSNT = 0, SCY = 7 */ +#define CFG_OR_TIMING_FLASH ( OR_ACS_DIV2 | OR_BI | OR_SCY_7_CLK | OR_TRLX ) + +#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH ) + +#define CFG_OR0_PRELIM CFG_OR0_REMAP +#define CFG_BR0_PRELIM (( CFG_FLASH_BASE & BR_BA_MSK ) | \ + BR_PS_16 | BR_V ) + +/* For AdderII BR1 SDRAM */ + +#define CFG_PRELIM_OR1_AM 0xFF800000 +#define CFG_OR1_REMAP ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 ) +#define CFG_OR1_PRELIM ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 ) +#define CFG_BR1_PRELIM ( CFG_SDRAM_BASE | BR_MS_UPMA | BR_V ) + + +/******************************************************************************* +* Internal Definitions Boot Flags +*******************************************************************************/ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif +/* __CONFIG_H */ + diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 977d03e..8308969 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -632,7 +632,7 @@ void board_init_r (gd_t *id, ulong dest_addr) puts ("FLASH: "); if ((flash_size = flash_init ()) > 0) { -#ifdef CFG_FLASH_CHECKSUM +# ifdef CFG_FLASH_CHECKSUM print_size (flash_size, ""); /* * Compute and print flash CRC if flashchecksum is set to 'y' @@ -648,9 +648,9 @@ void board_init_r (gd_t *id, ulong dest_addr) ); } putc ('\n'); -#else +# else /* !CFG_FLASH_CHECKSUM */ print_size (flash_size, "\n"); -#endif /* CFG_FLASH_CHECKSUM */ +# endif /* CFG_FLASH_CHECKSUM */ } else { puts (failed); hang (); @@ -658,14 +658,14 @@ void board_init_r (gd_t *id, ulong dest_addr) bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */ bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ -#if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) +# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) bd->bi_flashoffset = 0; -#elif CFG_MONITOR_BASE == CFG_FLASH_BASE +# elif CFG_MONITOR_BASE == CFG_FLASH_BASE bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */ -#else +# else bd->bi_flashoffset = 0; -#endif -#else +# endif +#else /* CFG_NO_FLASH */ bd->bi_flashsize = 0; bd->bi_flashstart = 0; |