diff options
| -rw-r--r-- | drivers/spi/imx_spi_cpld.c | 28 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx25/imx_spi_cpld.h | 21 |
2 files changed, 45 insertions, 4 deletions
diff --git a/drivers/spi/imx_spi_cpld.c b/drivers/spi/imx_spi_cpld.c index 2e20b9c..6e1e556 100644 --- a/drivers/spi/imx_spi_cpld.c +++ b/drivers/spi/imx_spi_cpld.c @@ -27,9 +27,22 @@ #include <linux/types.h> #include <imx_spi.h> +#include <asm/arch/imx_spi_cpld.h> static struct spi_slave *cpld_slave; +void cpld_reg_write(u32 offset, u32 val) +{ + cpld_reg_xfer(offset, val, 0); + cpld_reg_xfer(offset + 0x2, (val >> 16), 0); +} + +u32 cpld_reg_read(u32 offset) +{ + return cpld_reg_xfer(offset, 0x0, 1) | \ + (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16); +} + /*! * To read/write to a CPLD register. * @@ -74,7 +87,22 @@ unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, struct spi_slave *spi_cpld_probe() { + u32 reg; cpld_slave = spi_setup_slave(0, 0, 25000000, 0); + + udelay(1000); + + /* Reset interrupt status reg */ + cpld_reg_write(PBC_INT_REST, 0x1F); + cpld_reg_write(PBC_INT_REST, 0); + cpld_reg_write(PBC_INT_MASK, 0xFFFF); + /* Reset the XUART and Ethernet controllers */ + reg = cpld_reg_read(PBC_SW_RESET); + reg |= 0x9; + cpld_reg_write(PBC_SW_RESET, reg); + reg &= ~0x9; + cpld_reg_write(PBC_SW_RESET, reg); + return cpld_slave; } diff --git a/include/asm-arm/arch-mx25/imx_spi_cpld.h b/include/asm-arm/arch-mx25/imx_spi_cpld.h index f0fa00c..4bf1388 100644 --- a/include/asm-arm/arch-mx25/imx_spi_cpld.h +++ b/include/asm-arm/arch-mx25/imx_spi_cpld.h @@ -25,9 +25,22 @@ #include <linux/types.h> -extern struct spi_slave *spi_cpld_probe(); -extern void spi_cpld_free(struct spi_slave *slave); -extern unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, - unsigned int read); +#define PBC_LED_CTRL 0x20000 +#define PBC_SB_STAT 0x20008 +#define PBC_ID_AAAA 0x20040 +#define PBC_ID_5555 0x20048 +#define PBC_VERSION 0x20050 +#define PBC_ID_CAFE 0x20058 +#define PBC_INT_STAT 0x20010 +#define PBC_INT_MASK 0x20038 +#define PBC_INT_REST 0x20020 +#define PBC_SW_RESET 0x20060 + +void cpld_reg_write(u32 offset, u32 val); +u32 cpld_reg_read(u32 offset); +struct spi_slave *spi_cpld_probe(); +void spi_cpld_free(struct spi_slave *slave); +unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, + unsigned int read); #endif /* _IMX_SPI_CPLD_H_ */ |