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-rw-r--r--board/mvblm7/mvblm7.c14
-rw-r--r--board/sh7763rdp/lowlevel_init.S1
-rw-r--r--board/sh7763rdp/u-boot.lds1
-rw-r--r--board/socrates/upm_table.h32
-rw-r--r--board/tqc/tqm85xx/nand.c18
-rw-r--r--common/env_nand.c2
-rw-r--r--cpu/mpc85xx/cpu.c2
-rw-r--r--doc/README.mvblm75
-rw-r--r--include/configs/MVBLM7.h2
9 files changed, 37 insertions, 40 deletions
diff --git a/board/mvblm7/mvblm7.c b/board/mvblm7/mvblm7.c
index 41cb39d..69fd785 100644
--- a/board/mvblm7/mvblm7.c
+++ b/board/mvblm7/mvblm7.c
@@ -45,8 +45,8 @@ int fixed_sdram(void)
msize = CFG_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ (ddr_size > 1);
+ ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
@@ -127,21 +127,21 @@ u8 *dhcp_vendorex_proc(u8 *popt)
#ifdef CONFIG_HARD_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- return bus == 0 && cs == 0;
+ return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
- volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
- iopd->dat &= ~MVBLM7_MMC_CS;
+ iopd->dat &= ~MVBLM7_MMC_CS;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
- iopd->dat |= ~MVBLM7_MMC_CS;
+ iopd->dat |= ~MVBLM7_MMC_CS;
}
#endif
diff --git a/board/sh7763rdp/lowlevel_init.S b/board/sh7763rdp/lowlevel_init.S
index 1942892..2a44eee 100644
--- a/board/sh7763rdp/lowlevel_init.S
+++ b/board/sh7763rdp/lowlevel_init.S
@@ -348,4 +348,3 @@ SR_MASK_D: .long 0xEFFFFF0F
WDTST_D: .long 0x5A000FFF
WDTCSR_D: .long 0xA5000000
WDTBST_D: .long 0x55000000
-
diff --git a/board/sh7763rdp/u-boot.lds b/board/sh7763rdp/u-boot.lds
index 8f8229b..c07f0d8 100644
--- a/board/sh7763rdp/u-boot.lds
+++ b/board/sh7763rdp/u-boot.lds
@@ -103,4 +103,3 @@ SECTIONS
PROVIDE (_end = .);
}
-
diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h
index f26d8a7..ea64a59 100644
--- a/board/socrates/upm_table.h
+++ b/board/socrates/upm_table.h
@@ -34,22 +34,22 @@
/* UPM Table Configuration Code for FPGA access */
static const unsigned int UPMTableA[] =
{
- 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, //Words 0 to 3
- 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, //Words 4 to 7
- 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, //Words 8 to 11
- 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, //Words 12 to 15
- 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, //Words 16 to 19
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
- 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, //Words 24 to 27
- 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, //Words 28 to 31
- 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 32 to 35
- 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 36 to 39
- 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
- 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 48 to 51
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 //Words 60 to 63
+ 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */
+ 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */
+ 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */
+ 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */
+ 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
+ 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */
+ 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */
+ 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */
+ 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */
+ 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
+ 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */
};
#endif
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index fe3b31f..9c5c12c 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -59,7 +59,7 @@ struct upm_freq {
/* UPM pattern for bus clock = 25 MHz */
static const u32 upm_patt_25[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -92,7 +92,7 @@ static const u32 upm_patt_25[] = {
/* UPM pattern for bus clock = 33.3 MHz */
static const u32 upm_patt_33[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -125,7 +125,7 @@ static const u32 upm_patt_33[] = {
/* UPM pattern for bus clock = 41.7 MHz */
static const u32 upm_patt_42[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -158,7 +158,7 @@ static const u32 upm_patt_42[] = {
/* UPM pattern for bus clock = 50 MHz */
static const u32 upm_patt_50[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -191,7 +191,7 @@ static const u32 upm_patt_50[] = {
/* UPM pattern for bus clock = 66.7 MHz */
static const u32 upm_patt_67[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -224,7 +224,7 @@ static const u32 upm_patt_67[] = {
/* UPM pattern for bus clock = 83.3 MHz */
static const u32 upm_patt_83[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -257,7 +257,7 @@ static const u32 upm_patt_83[] = {
/* UPM pattern for bus clock = 100 MHz */
static const u32 upm_patt_100[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
@@ -290,7 +290,7 @@ static const u32 upm_patt_100[] = {
/* UPM pattern for bus clock = 133.3 MHz */
static const u32 upm_patt_133[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
@@ -323,7 +323,7 @@ static const u32 upm_patt_133[] = {
/* UPM pattern for bus clock = 166.7 MHz */
static const u32 upm_patt_167[] = {
- /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
+ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
diff --git a/common/env_nand.c b/common/env_nand.c
index e21d2a3..8954017 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -231,7 +231,7 @@ int saveenv(void)
size_t total;
int ret = 0;
nand_erase_options_t nand_erase_options;
-
+
nand_erase_options.length = CFG_ENV_RANGE;
nand_erase_options.quiet = 0;
nand_erase_options.jffs2 = 0;
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index baf8b81..0f72051 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -323,7 +323,7 @@ void upmconfig (uint upm, uint * table, uint size)
/* Find the address for the dummy write transaction */
for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
i++, brp += 2, orp += 2) {
-
+
/* Look for a valid BR with selected UPM */
if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
diff --git a/doc/README.mvblm7 b/doc/README.mvblm7
index 6a40888..3ee9396 100644
--- a/doc/README.mvblm7
+++ b/doc/README.mvblm7
@@ -11,7 +11,7 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2 System Components
-2.1 CPU
+2.1 CPU
Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
512MByte DDR-II memory @ 133MHz.
8 MByte Nor Flash on local bus.
@@ -23,7 +23,7 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2.2 PCI
A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
-
+
2.3 FPGA
Altera Cyclone-II EP2C20/35 with PCI DMA engines.
Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
@@ -82,4 +82,3 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2. Initrd - name is stored in "initrd_name"
3. device tree blob - name is stored in "dtb_name"
Fallback files are the flash versions.
-
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 349ca14..0b238bd 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -262,7 +262,7 @@
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
-#define CONFIG_LOADS_ECHO
+#define CONFIG_LOADS_ECHO
#define CFG_LOADS_BAUD_CHANGE
/*
generated by cgit v1.1 at 2024-11-10 15:44:49 +0000