diff options
| -rw-r--r-- | cpu/arm_cortexa8/cpu.c | 4 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/omap3/clock.c | 5 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/omap3/sys_info.c | 29 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap3/omap3.h | 14 |
4 files changed, 36 insertions, 16 deletions
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 5e7b935..3e1780b 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -101,7 +101,7 @@ void l2cache_enable() volatile unsigned int j; /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() == CPU_3430_ES2) { + if (get_cpu_rev() >= CPU_3XX_ES20) { __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); @@ -131,7 +131,7 @@ void l2cache_disable() volatile unsigned int j; /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() == CPU_3430_ES2) { + if (get_cpu_rev() >= CPU_3XX_ES20) { __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index 8ac31be..d035677 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -132,7 +132,7 @@ void prcm_init(void) void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; - u32 clk_index, sil_index; + u32 clk_index, sil_index = 0; prm_t *prm_base = (prm_t *)PRM_BASE; prcm_t *prcm_base = (prcm_t *)PRCM_BASE; dpll_param *dpll_param_p; @@ -170,7 +170,8 @@ void prcm_init(void) * and sil_index will get the values for that SysClk for the * appropriate silicon rev. */ - sil_index = get_cpu_rev() - 1; + if (get_cpu_rev()) + sil_index = 1; /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index fb240df..2f04cd6 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo; static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; +static char *rev_s[CPU_3XX_MAX_REV] = { + "1.0", + "2.0", + "2.1", + "3.0", + "3.1"}; /***************************************************************** * dieid_num_r(void) - read and set die ID @@ -76,18 +82,27 @@ u32 get_cpu_type(void) u32 get_cpu_rev(void) { u32 cpuid = 0; + ctrl_id_t *id_base; /* * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. + * so using CPU ID to differentiate between ES1.0 and > ES1.0. */ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); if ((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; + return CPU_3XX_ES10; + else { + /* Decode the IDs on > ES1.0 */ + id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE; + cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf; + + /* Some early ES2.0 seem to report ID 0, fix this */ + if(cpuid == 0) + cpuid = CPU_3XX_ES20; + + return cpuid; + } } /**************************************************** @@ -277,8 +292,8 @@ int print_cpuinfo (void) sec_s = "?"; } - printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s, - sec_s, get_cpu_rev()); + printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n", + cpu_s, sec_s, rev_s[get_cpu_rev()]); return 0; } diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index d0d2737..7c11019 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -167,12 +167,16 @@ typedef struct gpio { * 343x real hardware: * ES1 = rev 0 * - * 343x code defines: - * ES1 = 0+1 = 1 - * ES1 = 1+1 = 1 + * ES2 onwards, the value maps to contents of IDCODE register [31:28]. */ -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 2 +#define CPU_3XX_ES10 0 +#define CPU_3XX_ES20 1 +#define CPU_3XX_ES21 2 +#define CPU_3XX_ES30 3 +#define CPU_3XX_ES31 4 +#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) + +#define CPU_3XX_ID_SHIFT 28 #define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ |